Chip verification method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a chip verification method and device, electronic equipment and a storage medium, which can save verification time and improve verification efficiency. The method comprises the steps that a verification environment and a first verification instruction are obtained, the verification environment is constructed based on a hardware description language, the first verification instruction is constructed based on a script language, and a script interpreter is arranged in the verification environment; the first verification instruction is explained and executed through the script interpreter and an intermediate language, and the intermediate language is used for interacting with the script language and the hardware description language; and in response to execution of the first verification instruction, triggering the verification environment to verify the to-be-verified design. The chip verification method can be used for chip verification.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a chip verification method, apparatus, electronic device, and storage medium. Background Technology

[0002] With the development of semiconductor technology, rapid iteration of chip verification has become a crucial part of integrated circuit design. The current verification process involves first setting up the corresponding verification environment, then compiling, running, and simulating, and finally checking the simulation results. Unlike IP (Intellectual Property) verification, SOC (System-on-a-Chip) verification focuses more on the overall verification of features across multiple IPs, typically requiring the merging of verification sequences from multiple IPs into a single SOC verification sequence. However, modifying the verification sequence, recompiling it into an executable file, and simulating it on a subsystem or SOC requires significant time. For example, SOC compilation usually takes several hours, and SOC initialization, which includes the initialization of each IP, takes even longer. Moreover, any errors in the verification sequence necessitate a complete re-iteration, resulting in substantial repetitive work and significant manpower and time costs. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a chip verification method, apparatus, electronic device, and storage medium, which can save verification time and improve verification efficiency.

[0004] In a first aspect, embodiments of the present invention provide a chip verification method, comprising: acquiring a verification environment and a first verification instruction, wherein the verification environment is constructed based on a hardware description language, the first verification instruction is constructed based on a scripting language, and a script interpreter is provided in the verification environment; interpreting and executing the first verification instruction through the script interpreter and an intermediate language, wherein the intermediate language is used to interact with the scripting language and the hardware description language respectively; and triggering the verification environment to verify the design to be verified in response to the execution of the first verification instruction.

[0005] In one implementation, interpreting and executing the first verification instruction via the script interpreter and intermediate language includes: interpreting the first verification instruction via the script interpreter and converting the first verification instruction into a second verification instruction via the intermediate language, wherein the second verification instruction is constructed based on the hardware description language; executing the second verification instruction; and triggering the verification environment to verify the design to be verified in response to the execution of the first verification instruction includes: triggering the verification environment to verify the design to be verified in response to the execution of the second verification instruction.

[0006] In one implementation, converting the first verification instruction into a second verification instruction via the intermediate language includes: converting the first verification instruction into the second verification instruction by calling a dynamic link library built based on the intermediate language.

[0007] In one embodiment, obtaining the verification environment and the first verification instruction includes: obtaining the target verification environment and receiving the first verification instruction through a preset interface, wherein the target verification environment is a compiled and initialized verification environment, and the preset interface includes a local interface and / or a network interface.

[0008] In one embodiment, the number of preset interfaces is at least one, wherein each preset interface is used to connect to at least one client.

[0009] In one embodiment, the first verification instruction includes a verification sequence, which includes at least one of the following: a verification control command, an excitation signal, and an expected result.

[0010] In one implementation, the design to be verified includes a system-level design to be verified, which includes a first intellectual property core and a second intellectual property core. The verification sequence of the first verification instruction is used in the verification test of the first intellectual property core. Acquiring the verification environment and the first verification instruction includes: acquiring the verification environment and the first verification instruction of the second intellectual property core, wherein the verification environment of the second intellectual property core is the same as the verification environment of the first intellectual property core, and the verification sequence in the first verification instruction of the first intellectual property core is the same as the verification sequence in the first verification instruction of the second intellectual property core. Interpreting and executing the first verification instruction through the script interpreter and intermediate language includes: interpreting and executing the first verification instruction of the second intellectual property core through the script interpreter and intermediate language. Triggering the verification environment to verify the design to be verified in response to the execution of the first verification instruction includes: triggering the verification environment to verify the design to be verified in the second intellectual property core in response to the execution of the first verification instruction of the second intellectual property core.

[0011] In one embodiment, obtaining the verification environment and the first verification instruction of the second intellectual property core includes: obtaining the verification environment corresponding to the first intellectual property core, using the verification environment corresponding to the first intellectual property core as the verification environment corresponding to the second intellectual property core; reusing the first verification instruction corresponding to the first intellectual property core to obtain the first verification instruction corresponding to the second intellectual property core.

[0012] In one embodiment, the verification control command includes at least one of the following: verification sequence creation instruction, verification sequence start instruction, register status query instruction, checkpoint setting instruction, and waveform data storage instruction.

[0013] In one implementation, after the verification environment is triggered to verify the design to be verified in response to the execution of the first verification instruction, the method further includes: converting the first verification result obtained from the verification into a second verification result through the intermediate language, wherein the first verification result is written based on the hardware description language and the second verification result is written based on the scripting language; and outputting the second verification result through a preset interface, wherein the preset interface includes a local interface and / or a network interface.

[0014] In one embodiment, after outputting the second verification result through a preset interface, the method further includes: receiving a third verification instruction, the third verification instruction being an instruction obtained by adjusting the first verification instruction based on the second verification result; using the third verification instruction as the new first verification instruction, jumping to the step of interpreting and executing the first verification instruction through the script interpreter and intermediate language to continue execution, iterating in a loop until the verification ends.

[0015] Secondly, embodiments of the present invention also provide a chip verification apparatus, comprising: an acquisition unit, configured to acquire a verification environment and a first verification instruction, wherein the verification environment is constructed based on a hardware description language, the first verification instruction is constructed based on a scripting language, and a script interpreter is provided in the verification environment; an execution unit, configured to interpret and execute the first verification instruction through the script interpreter and an intermediate language, wherein the intermediate language is used to interact with the scripting language and the hardware description language respectively; and a verification unit, configured to trigger the verification environment to verify the design to be verified in response to the execution of the first verification instruction.

[0016] In one embodiment, the execution unit includes: a conversion module, configured to interpret the first verification instruction through the script interpreter and convert the first verification instruction into a second verification instruction through the intermediate language, wherein the second verification instruction is constructed based on the hardware description language; an execution module, configured to execute the second verification instruction; the verification unit is specifically configured to: in response to the execution of the second verification instruction, trigger the verification environment to verify the design to be verified.

[0017] In one implementation, the conversion module includes: converting the first verification instruction into the second verification instruction by calling a dynamic link library built based on the intermediate language.

[0018] In one embodiment, the acquisition unit includes: acquiring a target verification environment and receiving the first verification instruction through a preset interface, wherein the target verification environment is a compiled and initialized verification environment, and the preset interface includes a local interface and / or a network interface.

[0019] In one embodiment, the number of preset interfaces is at least one, wherein each preset interface is used to connect to at least one client.

[0020] In one embodiment, the first verification instruction includes a verification sequence, which includes at least one of the following: a verification control command, an excitation signal, and an expected result.

[0021] In one embodiment, the design to be verified includes a system-level design to be verified, which includes a first intellectual property core and a second intellectual property core. The verification sequence of the first verification instruction is used in the verification test of the first intellectual property core. The acquisition unit is further configured to acquire the verification environment and the first verification instruction of the second intellectual property core, wherein the verification environment of the second intellectual property core is the same as the verification environment of the first intellectual property core, and the verification sequence in the first verification instruction of the first intellectual property core is the same as the verification sequence in the first verification instruction of the second intellectual property core. The execution unit is further configured to interpret and execute the first verification instruction of the second intellectual property core through the script interpreter and the intermediate language. The verification unit is further configured to trigger the verification environment to verify the design to be verified in the second intellectual property core in response to the execution of the first verification instruction of the second intellectual property core.

[0022] In one embodiment, the acquisition unit includes: acquiring the verification environment corresponding to the first intellectual property core, using the verification environment corresponding to the first intellectual property core as the verification environment corresponding to the second intellectual property core; reusing the first verification instruction corresponding to the first intellectual property core to obtain the first verification instruction corresponding to the second intellectual property core.

[0023] In one embodiment, the verification control command includes at least one of the following: verification sequence creation instruction, verification sequence start instruction, register status query instruction, checkpoint setting instruction, and waveform data storage instruction.

[0024] In one embodiment, the apparatus further includes: a conversion unit, configured to, after triggering the verification environment to verify the design to be verified in response to the execution of the first verification instruction, convert the first verification result obtained from the verification into a second verification result through the intermediate language, wherein the first verification result is written based on the hardware description language and the second verification result is written based on the scripting language; and an output unit, configured to output the second verification result through a preset interface, the preset interface including a local interface and / or a network interface.

[0025] In one embodiment, the device further includes: a receiving unit, configured to receive a third verification instruction after outputting the second verification result through a preset interface, wherein the third verification instruction is an instruction obtained by adjusting the first verification instruction based on the second verification result; and a jumping unit, configured to jump to the execution unit to continue execution with the third verification instruction as the new first verification instruction, and iterate in a loop until the verification ends.

[0026] Thirdly, embodiments of the present invention also provide an electronic device, the electronic device comprising: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed within the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing any chip verification method provided by embodiments of the present invention.

[0027] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement any of the chip verification methods provided in the embodiments of the present invention.

[0028] The chip verification method, apparatus, electronic device, and storage medium provided in this invention can acquire a verification environment and a first verification instruction. The verification environment is built based on a hardware description language, and the first verification instruction is built based on a scripting language. A script interpreter is provided in the verification environment. The first verification instruction is interpreted and executed through the script interpreter and an intermediate language, wherein the intermediate language interacts with both the scripting language and the hardware description language. In response to the execution of the first verification instruction, the verification environment is triggered to verify the design to be verified. Since the first verification instruction is built based on a scripting language, it is interpreted and executed in the runtime environment. Furthermore, since the intermediate language can interact with both the scripting language and the hardware description language, it can convert the first verification instruction into a hardware description language. In response to the execution of the first verification instruction, the verification environment is triggered to verify the design to be verified. Thus, the verification environment can verify the design to be verified without compiling it into an executable file, supports hot code updates, and is ready to use immediately, making verification more flexible, thereby saving verification time and improving verification efficiency. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A flowchart of a chip verification method provided in an embodiment of the present invention; Figure 2 A schematic diagram of communication provided for a chip verification method according to an embodiment of the present invention; Figure 3 A schematic diagram of the intermediate language mapping of the chip verification method provided in the embodiments of the present invention; Figure 4 A schematic code diagram of a chip verification method provided in an embodiment of the present invention; Figure 5 Another flowchart of a chip verification method provided for an embodiment of the present invention; Figure 6 A schematic diagram of a chip verification device provided for an embodiment of the present invention; Figure 7 A schematic diagram of an electronic device provided as an embodiment of the present invention. Detailed Implementation

[0031] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0032] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0033] In a first aspect, embodiments of the present invention provide a chip verification method that can save verification time and improve verification efficiency.

[0034] like Figure 1 As shown, an embodiment of the present invention provides a chip verification method, including: S11, Obtain the verification environment and the first verification instruction, wherein the verification environment is built based on a hardware description language, the first verification instruction is built based on a scripting language, and a script interpreter is provided in the verification environment; In this step, the verification environment and the first verification instruction can be obtained. The verification environment refers to the verification platform development framework, which verification engineers can use to build functional verification environments with standardized hierarchical structures and interfaces using its reusable components. Hardware description languages ​​(HDLs) are specialized programming languages ​​used for digital circuit design and simulation. Currently, the mainstream HDLs include Verilog and VHDL, two IEEE standard languages. For example, UVM (Universal Verification Methodology) is a verification environment based on the SystemVerilog class library. SystemVerilog is a hardware description language built on top of Verilog, combining hardware description languages ​​(HDLs) with modern high-level verification languages ​​(HVLs).

[0035] Verification instructions refer to instructions used to verify the design to be verified. In this invention, the first verification instruction can be constructed based on a scripting language, that is, the first verification instruction is described using a scripting language. For example, the description language of the first verification instruction can be Ruby (an object-oriented scripting language). A script interpreter is set up in the verification environment to interpret and execute the first verification instruction. Scripting languages ​​only require an interpreter to interpret and do not need to be compiled into an executable file, so they can be interpreted and executed simultaneously. In this step, the verification environment and the first verification instruction can be obtained. Since the first verification instruction is constructed based on a scripting language, it cannot perform verification functions. For example, the first verification instruction "uvm_ruby_seq.new" (Ruby pseudocode) can be used to represent the creation of a verification sequence.

[0036] S12, the first verification instruction is interpreted and executed through the script interpreter and intermediate language, wherein the intermediate language is used to interact with the script language and the hardware description language respectively; After obtaining the first verification instruction in step S11, the first verification instruction can be interpreted and executed. In this step, the first verification instruction is interpreted by a script interpreter, and is interpreted and executed through interaction between an intermediate language and the scripting language and the hardware description language. The intermediate language can be a language that can connect the scripting language and the hardware description language; that is, the intermediate language acts as a bridge or a translation, interacting with both the scripting language and the hardware description language. Due to the special role of the intermediate language, the first verification instruction achieves communication between the scripting language and the hardware description language through this bridge, thereby ensuring the interpretation and execution of the first verification instruction.

[0037] S13, in response to the execution of the first verification instruction, the verification environment is triggered to verify the design to be verified.

[0038] In this step, the verification environment verifies the design to be verified. Specifically, when the first verification instruction is executed, the verification environment is triggered to verify the verification requirements contained in the first verification instruction.

[0039] The chip verification method provided in this invention can acquire a verification environment and a first verification instruction. The verification environment is built based on a hardware description language, and the first verification instruction is built based on a scripting language. A script interpreter is provided in the verification environment. The first verification instruction is interpreted and executed through the script interpreter and an intermediate language, wherein the intermediate language interacts with both the scripting language and the hardware description language. In response to the execution of the first verification instruction, the verification environment is triggered to verify the design to be verified. Since the first verification instruction is built based on a scripting language, it is interpreted and executed in the runtime environment. Furthermore, since the intermediate language can interact with both the scripting language and the hardware description language, it can convert the first verification instruction into a hardware description language. In response to the execution of the first verification instruction, the verification environment is triggered to verify the design to be verified. Thus, the verification environment can verify the design to be verified without compiling it into an executable file, supports hot code updates, and is ready to use immediately, making verification more flexible, saving verification time, and improving verification efficiency.

[0040] Specifically, in step S11, obtaining the verification environment and the first verification instruction can, in one embodiment, include: obtaining the target verification environment and receiving the first verification instruction through a preset interface, wherein the target verification environment is a compiled and initialized verification environment, and the preset interface includes a local interface and / or a network interface.

[0041] The following explanation uses the scripting language Ruby as an example.

[0042] When the preset interface is a local interface, the target verification environment and the input device for the first verification command are located on the same computer or device. When the preset interface is a network interface, the target verification environment and the input device for the first verification command belong to different computers or devices. For example, such as Figure 2 As shown, the client and server are connected via a network interface. The client receives the input of the first verification command, and the server obtains the first verification command through a network interface, such as a socket.

[0043] In this embodiment, a first verification command is received through a preset interface. The preset interface may include a local interface and / or a network interface.

[0044] When the preset interface is a network interface or a combination of network and local interfaces, there can be multiple preset interfaces. In one embodiment, there is at least one preset interface, where each preset interface is used to connect to at least one client. For example, there can be multiple clients, each using relatively independent shell input / output, such as using Xterm (a terminal emulator on the X Window System) to receive user input and return output results. In this way, the server can receive the respective first verification commands from each client, thereby enabling multiple clients to share the server platform, and the server platform to receive verification from multiple clients, thus achieving cross-platform multi-user collaborative debugging using a socket communication mechanism.

[0045] The first verification instruction input by the client can take various forms, combining to form complex verification functions. In one implementation, the first verification instruction may include a verification sequence, which includes at least one of the following: a verification control command, an excitation signal, and an expected result. Specifically, the verification instruction can be a basic command that drives and manages the hardware or system-level verification process, including a verification control command or a verification sequence. The verification control command can be a core command set used to manage the verification process, covering operations such as creating and starting verification sequences, status queries, checkpoint settings, and waveform storage. The verification sequence can be a verification control command or an executable test scenario consisting of a specific sequence of excitation signals and corresponding expected results.

[0046] In one implementation, the verification control commands may include at least one of the following: a verification sequence creation command, a verification sequence activation command, a register status query command, a checkpoint setting command, and a waveform data storage command. Specifically, the verification control commands cover key configuration, execution, and monitoring stages in the verification lifecycle. The verification control commands may include a verification sequence creation command, specifically used to define and configure the test scenario or stimulus sequence to be executed. The verification control commands may also include a verification sequence activation command, specifically used to start the execution of a created verification sequence; a register status query command, specifically used to read the values ​​of target hardware registers or storage units in real time for status checks; a checkpoint setting command, specifically used to set specific breakpoints or markers during the verification process for pausing execution, checking status, or control flow; and a waveform data storage command, specifically used to control the recording and storage behavior of signal waveform data (such as starting / stopping capture, setting trigger conditions, selecting stored signals, etc.).

[0047] In the above embodiments, the verification environment and the first verification instruction are obtained. The verification process of the first verification instruction is described in detail in the following embodiments. In one embodiment, interpreting and executing the first verification instruction through the script interpreter and the intermediate language may include: interpreting the first verification instruction through the script interpreter, and converting the first verification instruction into a second verification instruction through the intermediate language, wherein the second verification instruction is constructed based on the hardware description language; and executing the second verification instruction.

[0048] In this implementation, the first verification instruction can be interpreted by a script interpreter and converted into a second verification instruction via an intermediate language. Since the intermediate language can interact with both the scripting language and the hardware description language, the first verification instruction can be converted into a hardware description language that the verification environment can understand, resulting in the second verification instruction. For example, the second verification instruction "seq = my_sequence::type_id::create("seq", this);" can use the hardware description language to indicate the creation of a verification sequence in the run_phase task of the test class. The intermediate language can include C and / or C++. Upon execution of the second verification instruction, the verification environment is triggered to verify the design to be verified. For example, Ruby and SystemVerilog cannot communicate directly, but both are compatible with C / C++ extensions. Thus, C / C++ can be used as a bridge to convert the first verification instruction described in Ruby into the second verification instruction described in SystemVerilog.

[0049] In the above embodiments, the first verification instruction is converted into a second verification instruction using an intermediate language. In one embodiment, converting the first verification instruction into the second verification instruction using the intermediate language may include: converting the first verification instruction into the second verification instruction by calling a dynamic link library built based on the intermediate language. For example, such as Figure 3 As shown, C / C++ can be used as middleware to achieve the mapping from Ruby to SystemVerilog. The SystemVerilog standard itself provides the DPI (direct program interface) mechanism to enable C / C++ to call SystemVerilog components, while Ruby can directly call C / C++ functions, ultimately achieving cross-language calls.

[0050] Specifically, setting up a UVM verification sequence typically involves steps such as sequence creation, sequence initiation, waiting for a period of time, and querying specific status registers using the register model. Therefore, verification sequences implemented in Ruby must also follow these steps. For SystemVerilog, the mainstream verification methodology is UVM. In practice, the functions exported using DPI must include the basic functions capable of constructing these steps. Due to UVM's excellent encapsulation, all basic UVM components can be exported as C / C++ functions that can be called by Ruby, making it very flexible and convenient. The Ruby server can be used to execute Ruby scripts to complete the execution of the verification sequence.

[0051] It should be noted that the verification system built on a scripting language in this invention is compatible with the UVM verification scheme and can be implemented without modifying the original verification components. This allows for the reuse of the UVM verification scheme, achieving efficient verification iteration and convergence without altering the original verification components. Scripting languages ​​only require an interpreter and do not need to be compiled into executable files, making them more flexible and significantly saving time in SOC verification iteration and convergence, thus improving the quality of chip verification.

[0052] In the above embodiments, verification can be performed by the verification environment upon execution of the first verification instruction. Furthermore, in some embodiments, the present invention can convert the verification result and output it through a preset interface. In one implementation, after the verification environment is triggered to verify the design to be verified in response to the execution of the first verification instruction, the verification method may further include: converting the first verification result obtained through the intermediate language into a second verification result, wherein the first verification result is written based on the hardware description language and the second verification result is written based on the scripting language; and outputting the second verification result through a preset interface, the preset interface including a local interface and / or a network interface.

[0053] To address more complex verification requirements during the verification process, embodiments of the present invention can implement the function of an online debugger to adjust the verification results and further verify them. In one embodiment, after outputting the second verification result through a preset interface, the method further includes: receiving a third verification instruction, wherein the third verification instruction is an instruction obtained by adjusting the first verification instruction based on the second verification result; using the third verification instruction as the new first verification instruction, jumping to the step of interpreting and executing the first verification instruction through the script interpreter and intermediate language to continue execution, iterating in a loop until the verification ends.

[0054] This invention also enables the reuse of verification sequences in system-level testing scenarios. In one embodiment, the design to be verified includes a system-level design to be verified, which includes a first intellectual property core and a second intellectual property core. The verification sequence of the first verification instruction is used in the verification test of the first intellectual property core. Acquiring the verification environment and the first verification instruction includes: acquiring the verification environment and the first verification instruction of the second intellectual property core, wherein the verification environment of the second intellectual property core is the same as the verification environment of the first intellectual property core, and the verification sequence in the first verification instruction of the first intellectual property core is the same as the verification sequence in the first verification instruction of the second intellectual property core. Interpreting and executing the first verification instruction through the script interpreter and intermediate language includes: interpreting and executing the first verification instruction of the second intellectual property core through the script interpreter and intermediate language. In response to the execution of the first verification instruction, triggering the verification environment to verify the design to be verified includes: in response to the execution of the first verification instruction of the second intellectual property core, triggering the verification environment to verify the design to be verified in the second intellectual property core.

[0055] In one embodiment, obtaining the verification environment and the first verification instruction of the second intellectual property core includes: obtaining the verification environment corresponding to the first intellectual property core, using the verification environment corresponding to the first intellectual property core as the verification environment corresponding to the second intellectual property core; reusing the first verification instruction corresponding to the first intellectual property core to obtain the first verification instruction corresponding to the second intellectual property core.

[0056] For example, such as Figure 4 As shown, using Ruby and UVM together makes it easy to reuse verification sequences. In SOC verification, building a verification sequence from scratch is extremely costly; generally, it's necessary to reuse verification sequences from various IPs to complete such a system-level test scenario. For example... Figure 4The Ruby pseudocode example shown integrates three IP authentication sequences. `uvm_ruby_seq` is a Ruby script that looks up `uvm_Sequence`s using the UVM mechanism. `ip1_seq`, `ip2_seq`, and `ip3_seq` are the IP authentication sequences retrieved by `uvm_ruby_seq` using their names (`ip_seqeuence_name`). Finally, the IP authentication sequences are invoked via `send`. In this process, `send` also acts as a glue function similar to `uvm_ruby_seq`. This allows for the reuse of existing IP authentication sequences through invocation, significantly improving SOC authentication efficiency.

[0057] The chip verification method provided by the embodiments of the present invention will be described in detail below through specific examples.

[0058] like Figure 5 As shown, the chip verification method provided by the embodiments of the present invention may include: S801, The client inputs a first verification command; the first verification command is constructed based on a scripting language; Optionally, the number of clients can be at least one; Optionally, the first verification instruction includes: a verification sequence, wherein the verification sequence includes at least one of the following: a verification control command, an excitation signal, and an expected result; Optionally, the verification control command includes at least one of the following: verification sequence creation command, verification sequence start command, register status query command, checkpoint setting command, and waveform data storage command; S802. Receive the first verification command through a preset interface; wherein, the preset interface includes a local interface and / or a network interface; S803. Obtain the target verification environment; wherein, the target verification environment is a compiled and initialized verification environment, the verification environment is built based on a hardware description language, and a script interpreter is set in the verification environment; S804. The first verification instruction is interpreted by the script interpreter; S805. By calling the dynamic link library built based on the intermediate language, the first verification instruction is converted into a second verification instruction; The intermediate language is used to interact with both the scripting language and the hardware description language; the second verification instruction is constructed based on the hardware description language. Optionally, the intermediate language includes C and / or C++. S806. Execute the second verification instruction; S807. In response to the execution of the second verification instruction, the verification environment is triggered to verify the design to be verified; S808. The first verification result obtained from the verification is converted into a second verification result through the intermediate language, wherein the first verification result is written based on the hardware description language and the second verification result is written based on the scripting language; S809. Output the second verification result through a preset interface, wherein the preset interface includes a local interface and / or a network interface; S810. Receive a third verification instruction, wherein the third verification instruction is an instruction obtained by adjusting the first verification instruction based on the second verification result; S811. Using the third verification instruction as the new first verification instruction, jump to the step of interpreting and executing the first verification instruction through the script interpreter and intermediate language and continue execution, iterating until the verification ends.

[0059] Secondly, embodiments of the present invention also provide a chip verification device that can save verification time and improve verification efficiency.

[0060] like Figure 6 As shown, an embodiment of the present invention provides a chip verification apparatus, comprising: The acquisition unit 61 is used to acquire a verification environment and a first verification instruction, wherein the verification environment is built based on a hardware description language, the first verification instruction is built based on a scripting language, and a script interpreter is provided in the verification environment; The execution unit 62 is used to interpret and execute the first verification instruction through the script interpreter and the intermediate language, wherein the intermediate language is used to interact with the script language and the hardware description language respectively; Verification unit 63 is used to trigger the verification environment to verify the design to be verified in response to the execution of the first verification instruction.

[0061] The chip verification device provided in this embodiment of the invention can acquire a verification environment and a first verification instruction. The verification environment is built based on a hardware description language, and the first verification instruction is built based on a scripting language. A script interpreter is provided in the verification environment. The first verification instruction is interpreted and executed through the script interpreter and an intermediate language, wherein the intermediate language is used to interact with both the scripting language and the hardware description language. In response to the execution of the first verification instruction, the verification environment is triggered to verify the design to be verified. Since the first verification instruction is built based on a scripting language, it is interpreted and executed in the runtime environment. Furthermore, since the intermediate language can interact with both the scripting language and the hardware description language, it can convert the first verification instruction into a hardware description language. In response to the execution of the first verification instruction, the verification environment is triggered to verify the design to be verified. Thus, the verification environment can verify the design to be verified without compiling it into an executable file, supports hot code updates, and is ready to use immediately after writing, making verification more flexible, thereby saving verification time and improving verification efficiency.

[0062] In one embodiment, the execution unit 62 includes: a conversion module, configured to interpret the first verification instruction through the script interpreter and convert the first verification instruction into a second verification instruction through the intermediate language, wherein the second verification instruction is constructed based on the hardware description language; an execution module, configured to execute the second verification instruction; and the verification unit 63 is specifically configured to: in response to the execution of the second verification instruction, trigger the verification environment to verify the design to be verified.

[0063] In one implementation, the conversion module includes: converting the first verification instruction into the second verification instruction by calling a dynamic link library built based on the intermediate language.

[0064] In one embodiment, the acquisition unit 61 includes: acquiring a target verification environment and receiving the first verification instruction through a preset interface, wherein the target verification environment is a compiled and initialized verification environment, and the preset interface includes a local interface and / or a network interface.

[0065] In one embodiment, the number of preset interfaces is at least one, wherein each preset interface is used to connect to at least one client.

[0066] In one embodiment, the first verification instruction includes a verification sequence, which includes at least one of the following: a verification control command, an excitation signal, and an expected result.

[0067] In one embodiment, the design to be verified includes a system-level design to be verified, which includes a first intellectual property core and a second intellectual property core. The verification sequence of the first verification instruction is used in the verification test of the first intellectual property core. The acquisition unit 61 is further configured to acquire the verification environment and the first verification instruction of the second intellectual property core, wherein the verification environment of the second intellectual property core is the same as the verification environment of the first intellectual property core, and the verification sequence in the first verification instruction of the first intellectual property core is the same as the verification sequence in the first verification instruction of the second intellectual property core. The execution unit 62 is further configured to interpret and execute the first verification instruction of the second intellectual property core through the script interpreter and the intermediate language. The verification unit 63 is further configured to trigger the verification environment to verify the design to be verified in the second intellectual property core in response to the execution of the first verification instruction of the second intellectual property core.

[0068] In one embodiment, the acquisition unit 61 includes: acquiring the verification environment corresponding to the first intellectual property core, using the verification environment corresponding to the first intellectual property core as the verification environment corresponding to the second intellectual property core; reusing the first verification instruction corresponding to the first intellectual property core to obtain the first verification instruction corresponding to the second intellectual property core.

[0069] In one embodiment, the verification control command includes at least one of the following: verification sequence creation instruction, verification sequence start instruction, register status query instruction, checkpoint setting instruction, and waveform data storage instruction.

[0070] In one embodiment, the apparatus further includes: a conversion unit, configured to, after triggering the verification environment to verify the design to be verified in response to the execution of the first verification instruction, convert the first verification result obtained from the verification into a second verification result through the intermediate language, wherein the first verification result is written based on the hardware description language and the second verification result is written based on the scripting language; and an output unit, configured to output the second verification result through a preset interface, the preset interface including a local interface and / or a network interface.

[0071] In one embodiment, the device further includes: a receiving unit, configured to receive a third verification instruction after outputting the second verification result through a preset interface, wherein the third verification instruction is an instruction obtained by adjusting the first verification instruction based on the second verification result; and a jump unit, configured to jump to the execution unit 62 to continue execution with the third verification instruction as the new first verification instruction, and iterate in a loop until the verification ends.

[0072] Thirdly, embodiments of the present invention also provide an electronic device that can save verification time and improve verification efficiency.

[0073] like Figure 7 As shown, the electronic device provided in the embodiments of the present invention may include: a housing 71, a processor 72, a memory 73, a circuit board 74, and a power supply circuit 75, wherein the circuit board 74 is disposed inside the space enclosed by the housing 71, and the processor 72 and the memory 73 are disposed on the circuit board 74; the power supply circuit 75 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 73 is used to store executable program code; the processor 72 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 73, for executing the chip verification method provided in any of the foregoing embodiments.

[0074] The specific execution process of the above steps by the processor 72, as well as the steps further executed by the processor 72 by running executable program code, can be found in the description of the foregoing embodiments, and will not be repeated here.

[0075] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the chip verification methods provided in the embodiments of the present invention, thus achieving the corresponding technical effects. This has been described in detail above and will not be repeated here.

[0076] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0077] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0078] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0079] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0080] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0081] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip verification method, characterized in that, include: Obtain a verification environment and a first verification instruction, wherein the verification environment is built based on a hardware description language, the first verification instruction is built based on a scripting language, and a script interpreter is provided in the verification environment; The first verification instruction is interpreted and executed through the script interpreter and intermediate language, wherein the intermediate language is used to interact with the script language and the hardware description language respectively; In response to the execution of the first verification instruction, the verification environment is triggered to verify the design to be verified.

2. The chip verification method according to claim 1, characterized in that, The step of interpreting and executing the first verification instruction through the script interpreter and intermediate language includes: The script interpreter interprets the first verification instruction and the intermediate language converts the first verification instruction into a second verification instruction, wherein the second verification instruction is constructed based on the hardware description language. Execute the second verification instruction; The step of triggering the verification environment to verify the design to be verified in response to the execution of the first verification instruction includes: In response to the execution of the second verification instruction, the verification environment is triggered to verify the design to be verified.

3. The chip verification method according to claim 2, characterized in that, The step of converting the first verification instruction into the second verification instruction through the intermediate language includes: The first verification instruction is converted into the second verification instruction by calling a dynamic link library built on the intermediate language.

4. The chip verification method according to claim 1, characterized in that, The acquisition of the verification environment and the first verification command include: The target verification environment is obtained and the first verification instruction is received through a preset interface. The target verification environment is a verification environment that has been compiled and initialized. The preset interface includes a local interface and / or a network interface.

5. The chip verification method according to claim 4, characterized in that, The number of preset interfaces is at least one, wherein each preset interface is used to connect to at least one client.

6. The chip verification method according to claim 1, characterized in that, The first verification instruction includes a verification sequence, which includes at least one of the following: a verification control command, an excitation signal, and an expected result.

7. The chip verification method according to claim 6, characterized in that, The design to be verified includes a system-level design to be verified, which includes a first intellectual property core and a second intellectual property core. The verification sequence of the first verification instruction is used in the verification test of the first intellectual property core. The acquisition of the verification environment and the first verification command include: Obtain the verification environment and first verification instruction of the second intellectual property core, wherein the verification environment of the second intellectual property core is the same as the verification environment of the first intellectual property core, and the verification sequence in the first verification instruction of the first intellectual property core is the same as the verification sequence in the first verification instruction of the second intellectual property core; The step of interpreting and executing the first verification instruction through the script interpreter and intermediate language includes: The script interpreter and intermediate language interpret and execute the first verification instruction of the second intellectual property core; The step of triggering the verification environment to verify the design to be verified in response to the execution of the first verification instruction includes: In response to the execution of the first verification instruction of the second intellectual property core, the verification environment is triggered to verify the design to be verified in the second intellectual property core.

8. The chip verification method according to claim 7, characterized in that, The verification environment and first verification command for obtaining the second intellectual property core include: Obtain the verification environment corresponding to the first intellectual property core, and use the verification environment corresponding to the first intellectual property core as the verification environment corresponding to the second intellectual property core; The first verification instruction corresponding to the first intellectual property core is reused to obtain the first verification instruction corresponding to the second intellectual property core.

9. The chip verification method according to claim 6, characterized in that, The verification control commands include at least one of the following: verification sequence creation command, verification sequence start command, register status query command, checkpoint setting command, and waveform data storage command.

10. The chip verification method according to claim 1, characterized in that, After the verification environment is triggered to verify the design to be verified in response to the execution of the first verification instruction, the method further includes: The first verification result obtained through the intermediate language is converted into a second verification result, wherein the first verification result is written based on the hardware description language and the second verification result is written based on the scripting language; The second verification result is output through a preset interface, which includes a local interface and / or a network interface.

11. The chip verification method according to claim 10, characterized in that, After outputting the second verification result through a preset interface, the method further includes: Receive a third verification instruction, wherein the third verification instruction is an instruction obtained by adjusting the first verification instruction based on the second verification result; The third verification instruction is used as the new first verification instruction. The process jumps to the step of interpreting and executing the first verification instruction through the script interpreter and intermediate language and continues to iterate until the verification ends.

12. A chip verification device, characterized in that, include: An acquisition unit is used to acquire a verification environment and a first verification instruction, wherein the verification environment is built based on a hardware description language, the first verification instruction is built based on a scripting language, and a script interpreter is provided in the verification environment; An execution unit is configured to interpret and execute the first verification instruction through the script interpreter and the intermediate language, wherein the intermediate language is configured to interact with the script language and the hardware description language respectively; The verification unit is used to trigger the verification environment to verify the design to be verified in response to the execution of the first verification instruction.

13. The chip verification apparatus according to claim 12, characterized in that, The execution unit includes: A conversion module is used to interpret the first verification instruction through the script interpreter and convert the first verification instruction into a second verification instruction through the intermediate language, wherein the second verification instruction is constructed based on the hardware description language; The execution module is used to execute the second verification instruction; The verification unit is specifically used for: In response to the execution of the second verification instruction, the verification environment is triggered to verify the design to be verified.

14. The chip verification apparatus according to claim 13, characterized in that, The conversion module includes: The first verification instruction is converted into the second verification instruction by calling a dynamic link library built on the intermediate language.

15. The chip verification apparatus according to claim 12, characterized in that, The acquisition unit includes: The target verification environment is obtained and the first verification instruction is received through a preset interface. The target verification environment is a verification environment that has been compiled and initialized. The preset interface includes a local interface and / or a network interface.

16. The chip verification apparatus according to claim 15, characterized in that, The number of preset interfaces is at least one, wherein each preset interface is used to connect to at least one client.

17. The chip verification apparatus according to claim 12, characterized in that, The first verification instruction includes a verification sequence, which includes at least one of the following: a verification control command, an excitation signal, and an expected result.

18. The chip verification apparatus according to claim 17, characterized in that, The design to be verified includes a system-level design to be verified, which includes a first intellectual property core and a second intellectual property core. The verification sequence of the first verification instruction is used in the verification test of the first intellectual property core. The acquisition unit is further configured to acquire the verification environment and the first verification instruction of the second intellectual property core, wherein the verification environment of the second intellectual property core is the same as the verification environment of the first intellectual property core, and the verification sequence in the first verification instruction of the first intellectual property core is the same as the verification sequence in the first verification instruction of the second intellectual property core. The execution unit is further configured to interpret and execute the first verification instruction of the second intellectual property core through the script interpreter and intermediate language; The verification unit is further configured to trigger the verification environment to verify the design to be verified in the second intellectual property core in response to the execution of the first verification instruction of the second intellectual property core.

19. The chip verification apparatus according to claim 18, characterized in that, The acquisition unit includes: Obtain the verification environment corresponding to the first intellectual property core, and use the verification environment corresponding to the first intellectual property core as the verification environment corresponding to the second intellectual property core; The first verification instruction corresponding to the first intellectual property core is reused to obtain the first verification instruction corresponding to the second intellectual property core.

20. The chip verification apparatus according to claim 17, characterized in that, The verification control commands include at least one of the following: verification sequence creation command, verification sequence start command, register status query command, checkpoint setting command, and waveform data storage command.

21. The chip verification apparatus according to claim 12, characterized in that, The device further includes: The conversion unit is used to convert the first verification result obtained from the verification into a second verification result through the intermediate language after the verification environment is triggered to verify the design to be verified in response to the execution of the first verification instruction. The first verification result is written based on the hardware description language, and the second verification result is written based on the scripting language. An output unit is used to output the second verification result through a preset interface, the preset interface including a local interface and / or a network interface.

22. The chip verification apparatus according to claim 21, characterized in that, The device further includes: The receiving unit is configured to receive a third verification instruction after the second verification result is output through a preset interface, wherein the third verification instruction is an instruction obtained by adjusting the first verification instruction based on the second verification result; The jump unit is used to jump to the execution unit to continue execution, taking the third verification instruction as the new first verification instruction, and iterates in a loop until the verification ends.

23. An electronic device, the electronic device comprising: The device includes a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed within the space enclosed by the housing, and the processor and memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the chip verification method as described in any one of claims 1-11.

24. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the chip verification method as described in any one of claims 1-11.

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