FPGA (Field Programmable Gate Array)-based multi-mode multi-channel cascading signal synchronous acquisition method

Abstract

The invention discloses a multi-mode multi-channel cascading signal synchronous acquisition method based on an FPGA (Field Programmable Gate Array). The multi-mode multi-channel cascading signal synchronous acquisition method comprises the following steps: constructing a topological structure of a signal synchronous acquisition system; the upper computer sends a signal acquisition instruction to the FPGA; the FPGA analyzes the signal acquisition instruction; the signal synchronous acquisition system completes parameter configuration of each channel signal synchronous acquisition module according to the analysis parameters; the detection time compensation module acquires channel data and performs time compensation on the channel signal according to the trigger mode and the time compensation value; the signal detection module acquires channel data, performs signal detection on the channel data, and outputs a trigger signal to the trigger selection module after detecting a signal meeting a detection condition; the trigger selection module selects a trigger signal meeting a condition according to the trigger mode and forwards the trigger signal to the data acquisition module; and the data acquisition module collects channel signals subjected to time compensation and transmits the channel signals to the upper computer. The method has the advantages that multiple channel signals can be synchronously collected and processed, and needed calculation and storage resources are few.

Description

Technical Field

[0001] This invention relates to the field of comprehensive testing instrument technology, and in particular to a method for synchronous acquisition of multi-mode, multi-channel cascaded signals based on FPGA. Background Technology

[0002] The main function of the comprehensive tester is to collect signals for subsequent analysis and processing to obtain various indicators of the signals.

[0003] The comprehensive tester receives a variety of signals and needs to be adapted to various test scenarios such as Bluetooth, GPS / BDS, WIFI SISO / MIMO testing, and power calibration. This requires the equipment to have the ability to detect, acquire, transmit, and process signals of various bandwidths, and to have different signal detection and acquisition functions for different test items.

[0004] In most existing technologies, signal detection involves cross-correlation between the input signal and a local sequence code, and the presence of a peak in the cross-correlation result is used to determine the presence of the target frame signal. This approach requires significant computational and storage resources for real-time processing of high-bandwidth signals; different signal types require different auxiliary data, which presents a significant limitation for comprehensive testing instruments that need to process multiple signals.

[0005] Disadvantages of existing technologies: Existing signal synchronous acquisition methods require a lot of computing and storage resources and are difficult to process multiple channel signals simultaneously. Summary of the Invention

[0006] This invention provides a multi-mode, multi-channel, cascaded signal synchronous acquisition method based on FPGA, which can synchronously acquire and process signals from multiple channels with relatively low computational and storage resources.

[0007] To achieve the above objectives, this invention provides a multi-mode, multi-channel cascadeable signal synchronous acquisition method based on FPGA, which, as a key feature, includes the following steps:

[0008] Step 1: Build the topology of the signal synchronous acquisition system in the FPGA of the comprehensive test instrument through the host computer. The signal synchronous acquisition system is equipped with M channel signal synchronous acquisition modules with identical structure.

[0009] The channel signal synchronous acquisition module is equipped with a signal detection module and a detection time compensation module. The input terminals of the signal detection module and the detection time compensation module acquire the AD channel data of the corresponding channel. The output terminal of the signal detection module is connected to the input terminal of the trigger selection module. The output terminal of the trigger selection module is connected to the first input terminal of the data acquisition module. The output terminal of the detection time compensation module is connected to the second input terminal of the data acquisition module.

[0010] Step 2: The host computer sends a signal acquisition command to the FPGA;

[0011] Step 3: The parsing unit in the FPGA parses the signal acquisition command and transfers the parsed control parameters to the signal synchronization acquisition system;

[0012] Step 4: The signal synchronization acquisition system completes the parameter configuration of each channel signal synchronization acquisition module according to the control parameters;

[0013] Step 5: The detection time compensation module in the channel signal synchronization acquisition module acquires the AD channel data of the corresponding channel, and performs time compensation on the AD channel signal according to the set triggering method and its corresponding time compensation value to obtain the time-compensated signal;

[0014] Step 6: After starting the data acquisition task, the signal detection module acquires the AD channel data of the corresponding channel and performs signal detection on the AD channel data. When a signal that meets the detection conditions is detected, a trigger signal is output to the trigger selection module.

[0015] Step 7: When the trigger selection module receives a trigger signal corresponding to the set trigger mode, the trigger selection module forwards the trigger signal to the data acquisition module; otherwise, the trigger selection module continues to wait for a trigger signal.

[0016] Step 8: After receiving the trigger signal, the data acquisition module begins to collect the time-compensated channel signals and transmits the collected channel signals to the host computer.

[0017] The topology of the signal synchronous acquisition system is built into the FPGA of the comprehensive test instrument.

[0018] Through the above design, the time overhead generated during signal transmission is compensated by the detection time compensation module, the signal start position is accurately located, the signal time synchronization accuracy between receiving channels is high, the time synchronization of receiving channels of the same or different devices can be precisely controlled by FPGA, and independent or synchronous acquisition of multi-channel data can also be realized, and the working mode of receiving channels is flexible.

[0019] Preferably, the control parameters include, but are not limited to, the time parameters for the signal acquisition module to start or stop working, the triggering method and length of the acquired signals for each channel, the time offset of the acquired signals, the input / output direction of the external BNC port, and the trigger voltage level of the input signals.

[0020] Preferably, the triggering methods include local triggering, external triggering, rising edge triggering, power triggering, transmit triggering, receive triggering, and free operation.

[0021] This invention supports multiple triggering methods, quantitative or non-quantitative data acquisition, and various testing scenarios.

[0022] Preferably, in step 6, the signal detection is either power detection or edge detection.

[0023] Preferably, the edge detection uses the delayed dual-window energy ratio method to detect the rising edge of the signal energy; the power detection uses real-time detection of the full-scale power change of the AD within the dual window to achieve power triggering.

[0024] As a preferred option: when the signal detection is power detection, the detection condition is that the full-scale power of the signal reaches the set power range;

[0025] When signal detection is edge detection, the detection condition is that the rising edge of the signal energy reaches the set rising edge threshold range.

[0026] Preferably, in step 1, the external trigger interface control module is connected to the trigger selection module and is used to set the BNC interface to input or output mode according to the external triggering method.

[0027] When the comprehensive tester is used as the master device, the external trigger interface control module sets the BNC interface to output mode; when the comprehensive tester is used as the slave device, the BNC interface is set to input mode.

[0028] As a preferred method: when N integrated testing instruments are cascaded, the N integrated testing instruments perform synchronous signal acquisition, including the following steps:

[0029] Step 1: Designate one of the N integrated testers as the master device, configure the triggering method according to the signal detection requirements, set the BNC interface to output mode, set the channel time compensation value to T1, and forward the trigger signal to other devices through the BNC interface;

[0030] Step 2: Set other devices as slave devices, set the triggering method to external triggering, set the BNC interface to input mode, and set the channel time compensation value to T1+T2; where T1 is the set master device time compensation value and T2 is the set slave device time compensation value.

[0031] Step 3: Each device operates according to the signal acquisition process in Steps 5-8 to complete the synchronous acquisition of signals from N devices.

[0032] This invention enables the cascading of N devices via a BNC interface, allowing the N devices to synchronously acquire signals.

[0033] Preferably, the master device is provided with X BNC interfaces. When X≥N-1, each BNC interface is correspondingly connected to a slave device; when X<N-1, the master device is connected to the slave device through a BNC power divider according to the usage requirements.

[0034] The beneficial effects of the present invention are as follows:

[0035] 1): The receiving channel working mode is flexible. A single device has M data channels, which can work independently, or the working time and working mode of multiple channels can be synchronized to support the M*M multi-input multi-output communication technology; multiple devices can also be cascaded to complete the required tests.

[0036] 2): The time synchronization accuracy between receiving channels is high. The time synchronization of the receiving channels of the same device or different devices can be accurately controlled through the FPGA, and the time error accuracy can reach 4.17 ns.

[0037] 3): The receiving channels support multiple triggering methods and multiple acquisition modes. It supports triggering methods such as external trigger / native trigger / rising edge trigger / power trigger / transmission trigger / reception trigger / free running, etc.; it supports quantitative acquisition or non-quantitative acquisition of data, etc., and supports multiple test scenarios.

[0038] 4): The output interfaces are rich. The overflow situation, acquisition frame length, acquisition frame timestamp, frame sequence number, etc. of the acquired signals are counted, which is convenient for subsequent signal processing and analysis.

[0039] 5): It can synchronously acquire and process multiple channel signals, and requires less computing and storage resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a flow chart of the present invention;

[0041] Figure 2 is a block diagram of the signal synchronous acquisition system structure in the embodiment;

[0042] Figure 3 is a schematic diagram of the cascaded structure of the main device and the slave device of the comprehensive tester in the embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] The present invention will be further described in detail below with reference to the drawings and specific examples. The following embodiments or drawings are used to illustrate the present invention, but are not used to limit the scope of the present invention.

[0044] As Figure 1 shown, a multi-mode multi-channel cascaded signal synchronous acquisition method based on FPGA includes the following steps:

[0045] Step 1: Build the topology of the signal synchronization acquisition system 1 in the FPGA of the comprehensive test instrument through the host computer. The signal synchronization acquisition system 1 is equipped with M channel signal synchronization acquisition modules 1a with identical structure.

[0046] The channel signal synchronization acquisition module 1a is equipped with a signal detection module and a detection time compensation module. The input terminals of the signal detection module and the detection time compensation module acquire the AD channel data of the corresponding channel. The output terminal of the signal detection module is connected to the input terminal of a trigger selection module. The output terminal of the trigger selection module is connected to the first input terminal of the data acquisition module. The output terminal of the detection time compensation module is connected to the second input terminal of the data acquisition module. Figure 2 As shown.

[0047] Figure 2 The system is equipped with two channel signal synchronous acquisition modules 1a, which can perform independent acquisition of channel 1 and channel 2 signals, or synchronous acquisition of channel 1 and channel 2 signals.

[0048] Step 2: The host computer sends a signal acquisition command to the FPGA;

[0049] Step 3: The parsing unit in the FPGA parses the signal acquisition command and transfers the parsed control parameters to the signal synchronization acquisition system 1;

[0050] Step 4: The signal synchronization acquisition system 1 completes the parameter configuration of each channel signal synchronization acquisition module 1a according to the control parameters;

[0051] Step 5: The detection time compensation module in the channel signal synchronization acquisition module 1a acquires the AD channel data of the corresponding channel, and performs time compensation on the AD channel signal according to the preset triggering method and its corresponding time compensation value to obtain the time-compensated signal;

[0052] Step 6: After starting the data acquisition task, the signal detection module acquires the AD channel data of the corresponding channel and performs signal detection on the AD channel data. When a signal that meets the detection conditions is detected, a trigger signal is output to the trigger selection module.

[0053] Step 7: When the trigger selection module receives a trigger signal corresponding to the preset trigger mode, the trigger selection module forwards the trigger signal to the data acquisition module; otherwise, the trigger selection module continues to wait for a trigger signal.

[0054] Step 8: After receiving the trigger signal, the data acquisition module begins to collect the time-compensated channel signals and transmits the collected channel signals to the host computer.

[0055] The control parameters include, but are not limited to, the start and end times of the signal acquisition module, the triggering method and length of the acquired signals for each channel, the time offset of the acquired signals, the input and output directions of the external BNC port, and the trigger voltage level of the input signals.

[0056] The triggering methods include local triggering, external triggering, rising edge triggering, power triggering, transmit triggering, receive triggering, and free operation.

[0057] In step 6, the signal detection is either power detection or edge detection.

[0058] The edge detection uses the delayed dual-window energy ratio method to detect the rising edge of the signal energy; the power detection uses real-time detection of the full-scale power change of the AD within the dual window to achieve power triggering.

[0059] When the signal detection is power detection, the detection condition is that the full-scale power of the signal reaches the set power range.

[0060] When signal detection is edge detection, the detection condition is that the rising edge of the signal energy reaches the set rising edge threshold range.

[0061] The external trigger interface control module is connected to the trigger selection module and is used to set the BNC interface to input or output mode according to the external triggering method.

[0062] When N integrated testing instruments are cascaded, they perform synchronous signal acquisition, including the following steps:

[0063] Step 1: Designate one of the N integrated testers as the master device, configure the triggering method according to the signal detection requirements, set the BNC interface to output mode, set the channel time compensation value to T1, and forward the trigger signal to other devices through the BNC interface;

[0064] Step 2: Set other devices as slave devices, set the triggering method to external triggering, set the BNC interface to input mode, and set the channel time compensation value to T1+T2; where T1 is the set master device time compensation value and T2 is the set slave device time compensation value.

[0065] Step 3: Each device operates according to the signal acquisition process in Steps 5-8 to complete the synchronous acquisition of signals from N devices.

[0066] like Figure 3 As shown in Figure a, the master device has 4 BNC interfaces and connects to 4 slave devices. Each BNC interface of the master device corresponds to one slave device.

[0067] like Figure 3As shown in b, the master device has one BNC interface and connects to four slave devices. The master device connects to all slave devices through a bus, i.e., a BNC power divider.

[0068] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for synchronous acquisition of multi-mode, multi-channel cascaded signals based on FPGA, characterized in that, Includes the following steps: Step 1: The topology of the signal synchronous acquisition system (1) is built in the FPGA of the comprehensive tester by the host computer. The signal synchronous acquisition system (1) is equipped with M channel signal synchronous acquisition modules (1a) with the same structure. The channel signal synchronous acquisition module (1a) is equipped with a signal detection module and a detection time compensation module. The input terminals of the signal detection module and the detection time compensation module acquire the AD channel data of the corresponding channel. The output terminal of the signal detection module is connected to the input terminal of the trigger selection module. The output terminal of the trigger selection module is connected to the first input terminal of the data acquisition module. The output terminal of the detection time compensation module is connected to the second input terminal of the data acquisition module. Step 2: The host computer sends a signal acquisition command to the FPGA; Step 3: The parsing unit in the FPGA parses the signal acquisition command and transfers the parsed control parameters to the signal synchronous acquisition system (1); Step 4: The signal synchronization acquisition system (1) completes the parameter configuration of each channel signal synchronization acquisition module (1a) according to the control parameters; Step 5: The detection time compensation module in the channel signal synchronization acquisition module (1a) acquires the AD channel data of the corresponding channel, and performs time compensation on the AD channel signal according to the set triggering method and its corresponding time compensation value to obtain the time-compensated signal; Step 6: After starting the data acquisition task, the signal detection module acquires the AD channel data of the corresponding channel and performs signal detection on the AD channel data. When a signal that meets the detection conditions is detected, a trigger signal is output to the trigger selection module. Step 7: When the trigger selection module receives a trigger signal corresponding to the set trigger mode, the trigger selection module forwards the trigger signal to the data acquisition module; otherwise, the trigger selection module continues to wait for a trigger signal. Step 8: After receiving the trigger signal, the data acquisition module begins to collect the time-compensated channel signals and transmits the collected channel signals to the host computer.

2. The FPGA-based multi-mode, multi-channel, cascadeable signal synchronous acquisition method according to claim 1, characterized in that: The control parameters include, but are not limited to, the start and end times of the signal acquisition module, the triggering method and length of the acquired signals for each channel, the time offset of the acquired signals, the input and output directions of the external BNC port, and the trigger voltage level of the input signals.

3. The FPGA-based multi-mode, multi-channel cascadeable signal synchronous acquisition method according to claim 1 or 2, characterized in that: The triggering methods include local triggering, external triggering, rising edge triggering, power triggering, transmit triggering, receive triggering, and free operation.

4. The FPGA-based multi-mode, multi-channel cascadeable signal synchronous acquisition method according to claim 1, characterized in that: In step 6, the signal detection is either power detection or edge detection.

5. The FPGA-based multi-mode, multi-channel cascadeable signal synchronous acquisition method according to claim 4, characterized in that: The edge detection uses the delayed dual-window energy ratio method to detect the rising edge of the signal energy; the power detection uses real-time detection of the full-scale power change of the AD within the dual window to achieve power triggering.

6. The FPGA-based multi-mode, multi-channel cascadeable signal synchronous acquisition method according to claim 5, characterized in that: When the signal detection is power detection, the detection condition is that the full-scale power of the signal reaches the set power range. When signal detection is edge detection, the detection condition is that the rising edge of the signal energy reaches the set rising edge threshold range.

7. The FPGA-based multi-mode, multi-channel cascadeable signal synchronous acquisition method according to claim 3, characterized in that: In the step 1, the external trigger interface control module is connected to the trigger selection module and is used to set the BNC interface to the input or output mode according to the external trigger method.

8. The FPGA-based multi-mode, multi-channel cascadeable signal synchronous acquisition method according to claim 7, characterized in that: When N synthesizers are cascaded, the N synthesizers perform signal synchronous acquisition, including the following steps: Step 1: Use one device among the N synthesizers as the master device, configure the trigger method according to the signal detection requirements, set the BNC interface to the output mode, set the channel time compensation value to T1, and forward the trigger signal to other devices through the BNC interface; Step 2: Use the other devices as slave devices, set the trigger method to external trigger, set the BNC interface to the input mode, and set the channel time compensation value to T1 + T2; where T1 is the time compensation value set for the master device, and T2 is the time compensation value set for the slave device; Step 3: Each device operates according to the signal acquisition process in steps 5 - step 8 to complete the signal synchronous acquisition of N devices.

9. The FPGA-based multi-mode, multi-channel cascadeable signal synchronous acquisition method according to claim 8, characterized in that: The master device is provided with X BNC interfaces. When X ≥ N - 1, each BNC interface is correspondingly connected to one slave device; when X < N - 1, the master device is connected to the slave device through a BNC power divider according to the usage requirements.

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