Low power consumption communication circuit based on dpd algorithm

Abstract

The present application relates to the technical field of communication circuit, specifically relates to low-power consumption communication circuit based on DPD algorithm, including main control module, power amplifier, DPD processing module, power detection module, signal acquisition module, power management module.Main control module is responsible for switching the working mode of DPD processing module;Power amplifier is used for amplifying signal power, so that it can be sent to a long distance;The power detection module is used for real-time detection of the output power of power amplifier;The DPD processing is used for pre-distortion processing to input signal;Signal acquisition module is used for collecting the output power data detected by power detection module;Power management module is used for power supply for each module.The present application solves the technical problems of high power consumption, poor adaptability, transient distortion of working mode switching and other technical problems in the prior art.

Description

Technical Field

[0001] This invention relates to the field of communication circuit technology, and more specifically, to a low-power communication circuit based on the DPD algorithm. Background Technology

[0002] In wireless communication systems, power amplifiers are key components that determine communication distance and signal quality. However, the nonlinear characteristics of power amplifiers can cause signal distortion, affecting the performance of communication circuits and communication quality. Digital predistortion (DPD) technology improves communication performance by adding a predistortion circuit before the power amplifier to predistort the input signal, thus canceling the nonlinear distortion of the power amplifier.

[0003] Existing DPD communication circuits operate in a constant-time mode, with the DPD module running at a fixed frequency regardless of whether the power amplifier's output power is high or low. This generates unnecessary power consumption in low-power communication scenarios. Furthermore, the update cycle of the predistortion parameters in existing DPD algorithms is fixed, failing to dynamically adjust according to the real-time nonlinearity of the power amplifier. This results in poor predistortion performance in scenarios with significant fluctuations in power amplifier characteristics. Therefore, the proposed solution in this invention sets three different operating modes for the DPD module: high-power, medium-power, and low-power modes, depending on the power amplifier's output power. However, when the DPD module switches between different operating modes, the abrupt changes in the DPD model order and operating frequency cause discontinuities in the predistortion parameters, resulting in signal distortion at the moment of mode switching. This signal distortion can lead to data transmission errors in practical wireless communication applications.

[0004] In summary, existing DPD communication circuits suffer from high power consumption, poor adaptability, and instantaneous distortion during operating mode switching. Summary of the Invention

[0005] The purpose of this application is to provide a low-power communication circuit based on the DPD algorithm, which solves the technical problems of high power consumption, poor adaptability, and instantaneous distortion during working mode switching in the prior art.

[0006] To solve the above-mentioned technical problems, the solution adopted in this application is as follows:

[0007] The low-power communication circuit based on the DPD algorithm includes: a main control module, a power amplifier, a DPD processing module, and a power detection module.

[0008] The main control module is responsible for switching the working mode of the DPD processing module;

[0009] The power amplifier is used to amplify the signal power, enabling it to be transmitted over a longer distance;

[0010] The power detection module is used to detect the output power of the power amplifier in real time.

[0011] The DPD processing module is used to perform predistortion processing on the input signal, including a hardware platform FPGA and software modules running on the FPGA: a predistorter, a nonlinearity evaluation unit, and a predistortion adaptive algorithm unit; the DPD processing module also includes a predistortion parameter storage unit, which uses a high-speed flash memory chip. The high-speed flash memory chip is connected to the FPGA via an SPI bus and is used to store the data generated during the predistortion processing.

[0012] The main control module is connected to the signal input terminal of the DPD processing module via the SPI interface, and sends working mode switching commands to the DPD processing module; the signal output terminal of the DPD processing module is also connected to the main control module via the SPI interface, and the main control module receives the status feedback signals from the DPD processing module.

[0013] The signal receiving end of the DPD processing module receives signals from the upstream device. The signals are pre-distorted by the DPD processing module to obtain a pre-distorted signal. The signal output end of the DPD processing module is connected to the signal input end of the power amplifier, and the pre-distorted signal is transmitted to the power amplifier for power amplification to give the signal sufficient energy to be sent to the downstream device. The power signal output end of the power amplifier is connected to the power signal input end of the power detection module, which is used to detect the output signal of the power amplifier.

[0014] Preferably, the predistorter operates on an FPGA platform and is used to predistort the input signal; the predistorter employs a polynomial model, fitting the nonlinear characteristics of the power amplifier through a polynomial function; the polynomial function is:

[0015]

[0016] Where x(n) is the input signal, y(n) is the predistorted signal, and c k Here, K represents the polynomial coefficients, and K is the polynomial order.

[0017] The nonlinearity evaluation unit is used to calculate the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) of the signal, and to calculate the real-time nonlinearity of the power amplifier based on these two parameters.

[0018] The predistortion adaptive algorithm unit is used to adjust the predistortion parameters according to the real-time power of the power amplifier;

[0019] The predistortion parameter storage unit is used to store predistortion parameters.

[0020] Preferably, the low-power communication circuit based on the DPD algorithm further includes a signal acquisition module;

[0021] The signal acquisition module is used to acquire the real-time power of the power amplifier detected by the power detection module;

[0022] The signal acquisition module includes a high-speed ADC and a low-pass filter;

[0023] The signal receiving end of the low-pass filter is connected to the power signal output end of the power detection module. The low-pass filter is a Butterworth filter with a cutoff frequency of 50MHz, used to filter out high-frequency noise in the analog power signal output by the power detection module. The analog signal input end of the high-speed ADC is connected to the signal output end of the low-pass filter. The high-speed ADC converts the analog power signal into a digital power signal and feeds it back to the main control module.

[0024] Preferably, the low-power communication circuit based on the DPD algorithm further includes a power management module;

[0025] The power management module provides adjustable operating voltage to each module, ensuring the normal operation of the entire circuit. Preferably, the DPD processing module has three operating modes: high power mode, medium power mode, and low power mode.

[0026] The high-power mode is when the power amplifier output power is ≥27dBm, the DPD processing module runs at the highest frequency of 100MHz, and the predistorter adopts a 16th-order polynomial model to ensure the predistortion accuracy under high power.

[0027] The medium power mode is when 15dBm < power amplifier output power < 27dBm, the DPD processing module operates at a frequency of 50MHz, and the predistorter switches to an 8th-order polynomial model to reduce the amount of computation.

[0028] The low-power mode is when the power amplifier output power is ≤15dBm, the DPD processing module enters intermittent working mode, wakes up once every 10ms to perform predistortion processing, and enters sleep state at other times. At this time, the predistorter adopts a fourth-order polynomial model.

[0029] Preferably, the low-power communication circuit based on the DPD algorithm further includes a transition mode for the DPD processing module;

[0030] The transition mode is to set a transition power range between high power mode, medium power mode and low power mode. When the output power of the power amplifier is in the transition power range, the transition mode is activated.

[0031] The transition modes include high-power transition modes and low-power transition modes;

[0032] The transition power range of the high-power transition mode is 27±1dBm, and the transition power range of the medium-low power transition mode is 15±1dBm.

[0033] Preferably, the low-power communication circuit based on the DPD algorithm further includes a parameter interpolation algorithm for the DPD processing module;

[0034] The parameter interpolation algorithm is a linear interpolation of the current predistortion parameters and target parameters by the DPD processing module before switching to the transition mode, generating 10 intermediate parameter sets;

[0035] When the DPD processing module switches from high power mode to medium power mode, it inserts 10 high-medium intermediate parameter sets between the 16th-order predistorter model parameters in high power mode and the 8th-order predistorter model parameters in medium power mode, with an interval of 0.2μs between each high-medium intermediate parameter set.

[0036] When the DPD processing module switches from medium power mode to low power mode, it inserts 10 medium-low intermediate parameter sets between the 8th-order predistorter model parameters in medium power mode and the 4th-order predistorter model parameters in low power mode, with an interval of 0.2μs between each medium-low intermediate parameter set.

[0037] Preferably, the DPD processing module's operating mode switching is performed according to the following steps:

[0038] Step S1: Power on the circuit, initialize each module of the circuit, and the DPD processing module enters the initial working mode. The initial working mode of the DPD processing module is the medium power mode; proceed to step S2.

[0039] Step S2: The main control module determines whether the output power of the power amplifier is greater than or equal to 27dBm. If the output power of the power amplifier is greater than or equal to 27dBm, it outputs a command to switch to high power mode and returns to step S2 to continue to determine the output power of the power amplifier; otherwise, it executes step S3.

[0040] Step S3: The main control module determines whether the output power of the power amplifier is less than 27dBm and greater than 15dBm. If the output power of the power amplifier is less than 27dBm and greater than 15dBm, it outputs a command to switch to medium power mode and returns to step S2 to continue to determine the output power of the power amplifier; otherwise, it executes step S4.

[0041] Step S4: The main control module determines whether the output power of the power amplifier is less than or equal to 15dBm. If the output power of the power amplifier is less than or equal to 15dBm, it outputs a command to switch to low power mode and returns to step S2 to continue to determine the output power of the power amplifier; otherwise, it executes step S5.

[0042] Step S5: Return to step S2 and continue to determine the output power of the power amplifier.

[0043] Preferably, when the DPD processing module switches working modes, it loads the intermediate parameter set sequentially in chronological order, so that the predistorter model parameters and operating frequency change gradually in a step-like manner.

[0044] When the DPD processing module switches from high power mode to medium power mode, it loads the high-medium intermediate parameter set in time sequence, so that the predistorter model can achieve a gradual transition from 16th order to 12th order to 8th order, and finally achieve an error vector amplitude (EVM) fluctuation of ≤0.5% within 0.2μs.

[0045] When the DPD processing module switches from medium power mode to low power mode, it loads the medium-low intermediate parameter set sequentially in time order, so that the predistorter model can achieve a gradual transition from 8th order to 6th order to 4th order, and finally achieve an error vector amplitude (EVM) fluctuation of ≤0.5% within 0.2μs.

[0046] Preferably, the power amplifier is model ADL5320;

[0047] The main control module uses a low-power MCU of model STM32L432KBU6;

[0048] The power detection module uses the AD8361 power detector from Analog Devices.

[0049] The FPGA used is a Xilinx Artix-7 series FPGA.

[0050] The technical solution of this application has at least the following advantages and beneficial effects:

[0051] 1. This invention sets three operating modes for the DPD processing module based on the different output power of the power amplifier: high power mode, medium power mode, and low power mode. When the power amplifier output power is ≥27dBm, the DPD processing module operates in high power mode; when 15dBm < power amplifier output power < 27dBm, the DPD processing module operates in medium power mode; and when the power amplifier output power is ≤15dBm, the DPD processing module operates in low power mode. This method solves the problem of unnecessary power consumption in low-power communication scenarios caused by the DPD processing module operating at a fixed frequency.

[0052] 2. After setting three working modes for the DPD processing module, it was found that when the DPD processing module switches between working modes, the sudden change in the model order and operating frequency of the predistorter will cause the predistortion parameters to be discontinuous, resulting in signal distortion at the moment of working mode switching. In actual wireless communication applications, signal distortion will lead to data transmission errors.

[0053] Therefore, this invention introduces a transition mode and parameter interpolation algorithm for the DPD processing module.

[0054] The transition modes include two types: high-power transition mode and low-power transition mode. The parameter interpolation algorithm generates an intermediate parameter set between the current predistortion parameters and the target predistortion parameters. For example, when the DPD processing module switches from high-power mode to low-power mode, 10 high-to-low-power intermediate parameter sets are inserted between the 16th-order predistorter model parameters in high-power mode and the 8th-order predistorter model parameters in low-power mode. The interval between each high-to-low-power intermediate parameter set is 0.2μs. Thus, when the DPD processing module switches from high-power mode to low-power mode, the high-to-low-power intermediate parameter sets are loaded sequentially in time, enabling the predistorter model to achieve a gradual transition from 16th order to 12th order to 8th order. Attached Figure Description

[0055] Figure 1 This is a diagram showing the connection relationship of the circuit modules of the present invention;

[0056] Figure 2 This is a flowchart of the working mode switching process of the DPD processing module of the present invention. Detailed Implementation

[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] It should be noted that similar reference numerals and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. The terms "center," "upper," "lower," "inner," and "outer," indicating orientation or positional relationships based on the orientation or positional relationships shown in the figures, or the orientation or positional relationships commonly used when the product is in use, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed or operated in a specific orientation, and therefore should not be construed as a limitation on this application. It should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," and "connect" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0059] This invention provides a low-power communication circuit based on the DPD algorithm.

[0060] The low-power communication circuit based on the DPD algorithm in this invention is suitable for wireless communication systems. It processes the output signal from an upstream device (signal source) and transmits it to a downstream device (signal receiver). The upstream device generates baseband or intermediate frequency signals for wireless transmission. These signals have not undergone power amplification or nonlinear compensation. These signals are input into the low-power communication circuit based on the DPD algorithm for processing, and the processed signals are output to the downstream device. The upstream device transmitting the signal can be a baseband processing unit, a modem, or a signal generator; the downstream device receiving the signal can be a base station, a gateway, or a data logger. For example, in a communication link where a signal is transmitted from a mobile phone to a base station, the upstream device is the mobile phone, and the downstream device is the base station.

[0061] This invention focuses on the hardware composition and driving method of a low-power communication circuit based on the DPD algorithm, without elaborating on the detailed process and principle of signal reception and transmission, as the reception and transmission of wireless signals are existing technologies.

[0062] Figure 1 This is a connection diagram of a low-power communication circuit module based on the DPD algorithm, as shown in some embodiments of this specification.

[0063] The low-power communication circuit of the DPD algorithm includes a main control module, a power amplifier, a DPD processing module, a power detection module, a signal acquisition module, and a power management module.

[0064] Combination Figure 1The connection relationships between the main control module, power amplifier, DPD processing module, power detection module, signal acquisition module, and power management module of the low-power communication circuit based on the DPD algorithm in this invention are described below:

[0065] Furthermore, the main control module is connected to the signal input terminal of the DPD processing module via the SPI interface, and sends working mode switching commands to the DPD processing module; the signal output terminal of the DPD processing module is also connected to the main control module via the SPI interface, and the main control module receives the status feedback signals from the DPD processing module.

[0066] Specifically, the signal receiver of the DPD processing module receives signals from the upstream device. The signals undergo pre-distortion processing by the DPD processing module to obtain a pre-distorted signal. The signal output of the DPD processing module is connected to the signal input of the power amplifier, transmitting the pre-distorted signal to the power amplifier for further power amplification to ensure the signal has sufficient energy to be sent to the downstream device.

[0067] Specifically, the power signal output terminal of the power amplifier is connected to the power signal input terminal of the power detection module, which is used to detect the output signal of the power amplifier.

[0068] Specifically, the power signal output terminal of the power detection module is connected to the signal input terminal of the signal acquisition module, and the signal output terminal of the signal acquisition module is connected to the power feedback signal receiving terminal of the main control module. The signal acquisition module feeds back the real-time power of the power amplifier to the main controller. The main controller outputs a working mode switching command to the DPD processing module based on the real-time power of the power amplifier to control the switching of its working mode.

[0069] Specifically, the power output terminal of the power management module is electrically connected to the power input terminals of the main control module, the power amplifier, the DPD processing module, the power detection module, and the signal acquisition module, respectively, to provide them with a stable operating voltage.

[0070] The following provides further details on the specific functions and model numbers of each module:

[0071] Furthermore, the main control module is responsible for switching the working mode of the DPD processing module.

[0072] Furthermore, the main control module uses a low-power MCU, model STM32L432KBU6, which has multiple low-power modes that can be flexibly switched according to different working scenarios and requirements.

[0073] Furthermore, power amplifiers are used to amplify signal power, enabling it to be transmitted over longer distances.

[0074] Furthermore, the power amplifier model is ADL5320.

[0075] Furthermore, the power detection module is used to detect the output power of the power amplifier in real time. The power detection module converts the detected output power of the power amplifier into an electrical signal and transmits this electrical signal to the signal acquisition module. The signal output by the power amplifier is an analog signal, which contains high-frequency noise, harmonics, or spurious signals.

[0076] It should be noted that the power detection module uses the AD8361 power detector from Analog Devices, which operates in a frequency range of 1MHz to 8GHz, meeting the frequency requirements of most wireless communication systems.

[0077] Furthermore, the signal acquisition module includes a high-speed ADC and a low-pass filter for acquiring the real-time power of the power amplifier detected by the power detection module. More specifically, the signal receiving end of the low-pass filter is connected to the power signal output end of the power detection module. The low-pass filter is a Butterworth filter with a cutoff frequency of 50MHz, used to filter out high-frequency noise in the analog power signal output by the power detection module. The analog signal input end of the high-speed ADC is connected to the signal output end of the low-pass filter. The high-speed ADC converts the analog power signal into a digital power signal and feeds it back to the main control module. In some embodiments, the sampling rate of the high-speed ADC is 12bit / 100MSPS, which can accurately acquire the real-time power of the power amplifier detected by the power detection module.

[0078] It should be noted that the low-pass filter is model LT1568 and the high-speed ADC is model AD9634.

[0079] Specifically, the DPD processing module is used to perform predistortion processing on the input signal, including the hardware platform FPGA and the software modules running on the FPGA: predistorter, nonlinearity evaluation unit, and predistortion adaptive algorithm unit.

[0080] Specifically, the DPD processing module also includes a predistortion parameter storage unit, which employs a high-speed flash memory chip. This high-speed flash memory chip is connected to the FPGA via an SPI bus and is used to store data generated during the predistortion processing. In some embodiments, the high-speed flash memory chip is model MT25QL256.

[0081] Specifically, the predistorter runs on an FPGA platform to predistort the input signal to compensate for the nonlinear distortion of the power amplifier; the nonlinearity evaluation unit also runs on an FPGA platform to calculate the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) of the signal, and to determine the real-time nonlinearity of the power amplifier based on these two calculated parameters; the predistortion adaptive algorithm unit is used to adjust the predistortion parameters according to the real-time power magnitude signal of the power amplifier.

[0082] It should be noted that the FPGA used is a Xilinx Artix-7 series FPGA.

[0083] Specifically, the power management module provides adjustable operating voltage to each module, ensuring the normal operation of the entire circuit.

[0084] Specifically, the power management module uses Dialog's DA9063 power management module, which can adjust the output voltage and output different voltages as needed.

[0085] Another aspect of the present invention provides a software driving method for low-power communication circuits based on the DPD algorithm.

[0086] Figure 2 This is a flowchart illustrating the working mode switching process of the DPD processing module in some embodiments of this specification.

[0087] Furthermore, the predistorter employs a polynomial model, fitting the nonlinear characteristics of the power amplifier using a polynomial function. The polynomial function is:

[0088]

[0089] Where x(n) is the input signal, y(n) is the predistorted signal, and c k These are the polynomial coefficients, and K is the polynomial order. Specifically, based on the output power of the power amplifier, the DPD processing module is configured with the following three operating modes:

[0090] High power mode: When the power amplifier output power is ≥27dBm, the DPD processing module operates at a maximum frequency of 100MHz, and the predistorter adopts a 16th-order polynomial model to ensure the predistortion accuracy under high power.

[0091] Medium power mode: When 15dBm < power amplifier output power < 27dBm, the DPD processing module operates at a frequency of 50MHz, and the predistorter switches to an 8th-order polynomial model to reduce computation.

[0092] Low power mode: When the power amplifier output power is ≤15dBm, the DPD processing module enters intermittent working mode, wakes up once every 10ms to perform predistortion processing, and enters sleep mode at other times. At this time, the predistorter adopts a 4th order polynomial model.

[0093] Specifically, the nonlinearity evaluation unit calculates the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) of the signal by transmitting the real-time power of the power amplifier through the signal acquisition module, and evaluates the real-time nonlinearity of the power amplifier based on these two parameters.

[0094] It should be noted that the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) of the signal are existing technologies and methods, and their principles and calculation processes will not be elaborated in this invention.

[0095] Specifically, the predistortion adaptive algorithm unit is used to adjust the predistortion parameters based on the real-time power signal of the power amplifier. The predistortion parameters are used to compensate for the nonlinear characteristics of the power amplifier, making the output signal linearized after power amplification.

[0096] It should be noted that the predistortion adaptive algorithm is existing technology. This invention uses this algorithm to adjust the predistortion parameters, but will not introduce its implementation principle again.

[0097] Furthermore, the threshold for Adjacent Channel Power Ratio (ACPR) is set to -45dBc, and the threshold for Error Vector Magnitude (EVM) is set to 5%. When the Adjacent Channel Power Ratio > -45dBc or the EVM > 5%, the predistortion parameter update period is shortened to 1ms; when the Adjacent Channel Power Ratio ≤ -45dBc and the EVM ≤ 5%, the predistortion parameter update period is extended to 10ms; when the power amplifier output power ≤ 15dBm, the predistortion parameter update period is fixed at 100ms.

[0098] Specifically, after the circuit is powered on, the main control module initializes each module, sets the initial working mode to medium power mode, the DPD processing module runs at a frequency of 50MHz, and the predistorter adopts an 8th-order polynomial model.

[0099] Specifically, the main controller module sets the power thresholds for the power amplifier, with thresholds of 27dBm and 15dBm. More specifically, the signal acquisition module transmits the real-time detected output power of the power amplifier to the main control module. The main control module compares the real-time output power with the power thresholds. When the power amplifier output power is ≥27dBm, the main control module sends a high-power mode switching command to the DPD processing module; when 15dBm < power amplifier output power < 27dBm, the main control module sends a medium-power mode switching command to the DPD processing module; and when the power amplifier output power is ≤15dBm, the main control module sends a low-power mode switching command to the DPD processing module.

[0100] Furthermore, the DPD processing module's operating mode switching is performed according to the following steps:

[0101] Step S1: Power on the circuit, initialize each module of the circuit, and the DPD processing module enters the initial working mode. The initial working mode of the DPD processing module is the medium power mode; proceed to step S2.

[0102] Step S2: The main control module determines whether the output power of the power amplifier is greater than or equal to 27dBm. If the output power of the power amplifier is greater than or equal to 27dBm, it outputs a command to switch to high power mode and returns to step S2 to continue to determine the output power of the power amplifier; otherwise, it executes step S3.

[0103] Step S3: The main control module determines whether the output power of the power amplifier is less than 27dBm and greater than 15dBm. If the output power of the power amplifier is less than 27dBm and greater than 15dBm, it outputs a command to switch to medium power mode and returns to step S2 to continue to determine the output power of the power amplifier; otherwise, it executes step S4.

[0104] Step S4: The main control module determines whether the output power of the power amplifier is less than or equal to 15dBm. If the output power of the power amplifier is less than or equal to 15dBm, it outputs a command to switch to low power mode and returns to step S2 to continue to determine the output power of the power amplifier; otherwise, it executes step S5.

[0105] Step S5: Return to step S2 and continue to determine the output power of the power amplifier.

[0106] Thus, this invention sets three different operating modes for the DPD processing module, which operate in high-power, medium-power, and low-power modes depending on the output power of the power amplifier. However, when the DPD processing module switches between different operating modes, the abrupt changes in the model order and operating frequency of the predistorter cause discontinuities in the predistortion parameters, resulting in signal distortion at the moment of mode switching. This signal distortion can lead to data transmission errors in practical wireless communication applications. Therefore, this invention introduces a transition mode and parameter interpolation algorithm for the DPD processing module.

[0107] Furthermore, a 256KB cache is added to the DPD processing module to store intermediate parameter sets, ensuring the real-time performance of parameter interpolation calculations.

[0108] Specifically, the 256KB cache is an IS61WV51216 SRAM chip.

[0109] Specifically, the transition mode sets a transition power range between high power mode, medium power mode, and low power mode. When the power amplifier output power is in the transition power range, the transition mode is activated.

[0110] Specifically, the transition modes include a high-power transition mode and a low-power transition mode. In some embodiments, the transition power range of the high-power transition mode is 27±1dBm, and the transition power range of the low-power transition mode is 15±1dBm.

[0111] Specifically, the parameter interpolation algorithm performs linear interpolation on the current predistortion parameters and the target predistortion parameters before switching to the transition mode, generating 10 intermediate parameter sets. For example, when the DPD processing module switches from high-power mode to medium-power mode, 10 high-medium intermediate parameter sets are inserted between the 16th-order predistorter model parameters of the high-power mode and the 8th-order predistorter model parameters of the medium-power mode, with an interval of 0.2 μs between each high-medium intermediate parameter set. As another example, when the DPD processing module switches from medium-power mode to low-power mode, 10 medium-low intermediate parameter sets are inserted between the 8th-order predistorter model parameters of the medium-power mode and the 4th-order predistorter model parameters of the low-power mode, with an interval of 0.2 μs between each medium-low intermediate parameter set.

[0112] Specifically, when the DPD processing module switches operating modes, it loads intermediate parameter sets sequentially over time, causing the predistorter model parameters and operating frequency to change gradually in a stepwise manner. For example, when the DPD processing module switches from high-power mode to medium-power mode, it loads high-to-medium intermediate parameter sets sequentially over time, enabling the predistorter model to gradually transition from order 16 to order 12 to order 8, ultimately achieving an error vector amplitude (EVM) fluctuation of ≤0.5% within 0.2μs. As another example, when the DPD processing module switches from medium-power mode to low-power mode, it loads medium-to-low intermediate parameter sets sequentially over time, enabling the predistorter model to gradually transition from order 8 to order 6 to order 4, ultimately achieving an error vector amplitude (EVM) fluctuation of ≤0.5% within 0.2μs.

[0113] The various embodiments of the present invention have now been described in detail. To avoid obscuring the concept of the invention, some details known in the art have not been described. Those skilled in the art will fully understand how to implement the technical solutions of this invention based on the above description, and the scope of the invention is defined by the appended claims.

Claims

1. A low power consumption communication circuit based on DPD algorithm, characterized in that, include: Main control module, power amplifier, DPD processing module, power detection module; The main control module is responsible for switching the working mode of the DPD processing module; The power amplifier is used to amplify the signal power, enabling it to be transmitted over a longer distance; The power detection module is used to detect the output power of the power amplifier in real time. The DPD processing module is used to perform predistortion processing on the input signal, including a hardware platform FPGA and software modules running on the FPGA: a predistorter, a nonlinearity evaluation unit, and a predistortion adaptive algorithm unit; the DPD processing module also includes a predistortion parameter storage unit, which uses a high-speed flash memory chip. The high-speed flash memory chip is connected to the FPGA via an SPI bus and is used to store the data generated during the predistortion processing. The main control module is connected to the signal input terminal of the DPD processing module via the SPI interface, and sends working mode switching commands to the DPD processing module; the signal output terminal of the DPD processing module is also connected to the main control module via the SPI interface, and the main control module receives the status feedback signals from the DPD processing module. The signal receiving end of the DPD processing module receives signals from the upstream device. The signals are pre-distorted by the DPD processing module to obtain a pre-distorted signal. The signal output end of the DPD processing module is connected to the signal input end of the power amplifier, and the pre-distorted signal is transmitted to the power amplifier for power amplification to give the signal sufficient energy to be sent to the downstream device. The power signal output end of the power amplifier is connected to the power signal input end of the power detection module, which is used to detect the output signal of the power amplifier. The DPD processing module has three operating modes: high power mode, medium power mode, and low power mode. The DPD processing module has different operating frequencies in different modes. The DPD processing module includes a predistorter. The predistorter is used to predistort the input signal. The DPD processing module adopts a transition mode when switching operating modes. The transition mode sets a transition power range between high power mode, medium power mode and low power mode. When the power amplifier output power is in the transition power range, the transition mode is activated. When the DPD processing module switches to the transition mode, it uses a parameter interpolation algorithm to interpolate the current predistortion parameters and the target predistortion parameters to generate several intermediate parameter sets. When the DPD processing module switches working modes, it loads the intermediate parameter set sequentially in chronological order, so that the model parameters of the predistorter and the operating frequency of the DPD processing module change gradually in a step-like manner.

2. The DPD algorithm based low power communication circuit according to claim 1, characterized in that, The predistorter operates on an FPGA platform and is used to predistort the input signal. The predistorter employs a polynomial model, fitting the nonlinear characteristics of the power amplifier using a polynomial function. The polynomial function is: ； wherein, is an input signal, is a pre-distorted signal, is a polynomial coefficient, is a polynomial order; The nonlinearity evaluation unit is used to calculate the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) of the signal, and to calculate the real-time nonlinearity of the power amplifier based on these two parameters. The predistortion adaptive algorithm unit is used to adjust the predistortion parameters according to the real-time power of the power amplifier; The predistortion parameter storage unit is used to store predistortion parameters.

3. The DPD algorithm based low power consumption communication circuit according to claim 1, wherein, The low-power communication circuit based on the DPD algorithm also includes a signal acquisition module; The signal acquisition module is used to acquire the real-time power of the power amplifier detected by the power detection module; The signal acquisition module includes a high-speed ADC and a low-pass filter; The signal receiving end of the low-pass filter is connected to the power signal output end of the power detection module. The low-pass filter is a Butterworth filter with a cutoff frequency of 50MHz, used to filter out high-frequency noise in the analog power signal output by the power detection module. The analog signal input end of the high-speed ADC is connected to the signal output end of the low-pass filter. The high-speed ADC converts the analog power signal into a digital power signal and feeds it back to the main control module.

4. The DPD algorithm based low power consumption communication circuit according to claim 1, wherein, The low-power communication circuit based on the DPD algorithm also includes a power management module; The power management module provides adjustable operating voltage to each module, ensuring the normal operation of the entire circuit.

5. The DPD algorithm based low power consumption communication circuit according to claim 1, wherein, The high-power mode is when the power amplifier output power is ≥27dBm, the DPD processing module runs at the highest frequency of 100MHz, and the predistorter adopts a 16th-order polynomial model to ensure the predistortion accuracy under high power. The medium power mode is when 15dBm < power amplifier output power < 27dBm, the DPD processing module operates at a frequency of 50MHz, and the predistorter switches to an 8th-order polynomial model to reduce the amount of computation. The low-power mode is when the power amplifier output power is ≤15dBm, the DPD processing module enters intermittent working mode, wakes up once every 10ms to perform predistortion processing, and enters sleep state at other times. At this time, the predistorter adopts a fourth-order polynomial model.

6. The DPD algorithm based low power consumption communication circuit according to claim 1, wherein, The transition mode is to set a transition power range between high power mode, medium power mode and low power mode. When the output power of the power amplifier is in the transition power range, the transition mode is activated. The transition modes include high-power transition modes and low-power transition modes; The transition power range of the high-power transition mode is 27±1dBm, and the transition power range of the medium-low power transition mode is 15±1dBm.

7. The DPD algorithm based low power consumption communication circuit according to claim 1, wherein, The parameter interpolation algorithm is a linear interpolation of the current predistortion parameters and target parameters by the DPD processing module before switching to the transition mode, generating 10 intermediate parameter sets; When the DPD processing module switches from high power mode to medium power mode, it inserts 10 high-medium intermediate parameter sets between the 16th-order predistorter model parameters in high power mode and the 8th-order predistorter model parameters in medium power mode, with an interval of 0.2μs between each high-medium intermediate parameter set. When the DPD processing module switches from medium power mode to low power mode, it inserts 10 medium-low intermediate parameter sets between the 8th-order predistorter model parameters in medium power mode and the 4th-order predistorter model parameters in low power mode, with an interval of 0.2μs between each medium-low intermediate parameter set.

8. The DPD algorithm based low power consumption communication circuit according to claim 1, wherein, The switching of the working mode of the DPD processing module is performed according to the following steps: Step S1: Power on the circuit, initialize each module of the circuit, and the DPD processing module enters the initial working mode. The initial working mode of the DPD processing module is the medium power mode; proceed to step S2. Step S2: The main control module determines whether the output power of the power amplifier is greater than or equal to 27dBm. If the output power of the power amplifier is greater than or equal to 27dBm, it outputs a command to switch to high power mode and returns to step S2 to continue to determine the output power of the power amplifier; otherwise, it executes step S3. Step S3: The main control module determines whether the output power of the power amplifier is less than 27dBm and greater than 15dBm. If the output power of the power amplifier is less than 27dBm and greater than 15dBm, it outputs a command to switch to medium power mode and returns to step S2 to continue to determine the output power of the power amplifier; otherwise, it executes step S4. Step S4: The main control module determines whether the output power of the power amplifier is less than or equal to 15dBm. If the output power of the power amplifier is less than or equal to 15dBm, it outputs a command to switch to low power mode and returns to step S2 to continue to determine the output power of the power amplifier; otherwise, it executes step S5. Step S5: Return to step S2 and continue to determine the output power of the power amplifier.

9. The DPD algorithm based low power consumption communication circuit according to claim 1, wherein, When the DPD processing module switches working modes, it loads intermediate parameter sets sequentially according to time, so that the predistorter model parameters and operating frequency change gradually in a step-like manner. Specifically: When the DPD processing module switches from high-power mode to medium-power mode, it loads the high-medium intermediate parameter set sequentially in time, enabling the predistorter model to gradually transition from order 16 to order 12 to order 8, ultimately achieving an error vector amplitude (EVM) fluctuation of ≤0.5% within 0.2μs. When the DPD processing module switches from medium power mode to low power mode, it loads the medium-low intermediate parameter set in chronological order, so that the predistorter model can gradually transition from 8th order to 6th order to 4th order, and finally achieve an error vector amplitude (EVM) fluctuation of ≤0.5% within 0.2μs.

10. The DPD algorithm based low power consumption communication circuit according to claim 1, wherein, The power amplifier is model ADL5320; The main control module uses a low-power MCU of model STM32L432KBU6; The power detection module uses the AD8361 power detector from Analog Devices. The FPGA used is a Xilinx Artix-7 series FPGA.

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