A fully digital in-memory computing device based on a lookup table structure

Abstract

This invention discloses a fully digital in-memory computing device based on a lookup table structure, comprising: a first SRAM unit and a second SRAM unit, and a lookup table structure; the lookup table structure is connected to the first SRAM unit and the second SRAM unit respectively; the input and output of the first SRAM unit are both first weights of a neural network; the input and output of the second SRAM unit are both second weights of a neural network; the lookup table structure directly uses the outputs of the first SRAM unit and the second SRAM unit as inputs, and also receives a first input stimulus and a second input stimulus; the output of the lookup table structure includes: carry output and bit output; before inputting the first input stimulus and the second input stimulus, the lookup table structure receives weights from the first SRAM unit and the second SRAM unit respectively for pre-calculation; when inputting the first input stimulus and the second input stimulus, the lookup table structure selects the output based on the data obtained from the pre-calculation.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a fully digital in-memory computing device based on a lookup table structure. Background Technology

[0002] With the proliferation of edge computing circuits, in-memory computing circuits have effectively solved the data transmission problem of the von Neumann architecture. Therefore, academia and industry are increasingly focusing on the field of in-memory computing.

[0003] Currently, mainstream in-memory computing circuits employ analog domain computation, performing multiplication and accumulation operations by quantizing voltage. However, this method has low accuracy and is unsuitable for high-precision applications. Digital domain in-memory computing architectures can solve the accuracy problem, but the power consumption of the addition tree circuits in its computation process is too high, resulting in power consumption issues.

[0004] Therefore, how to solve the power consumption problem of digital domain in-memory computing architecture is currently a key research focus. Summary of the Invention

[0005] To address the power consumption issues of current digital domain in-memory computing architectures, this invention provides a fully digital in-memory computing device based on a lookup table structure. Since the lookup table can perform bitwise multiplication and first-level addition, it can replace the computation in the addition tree circuit of the digital domain in-memory computing architecture, eliminating the need for multipliers in the SRAM basic cells. Furthermore, because the lookup table structure can pre-calculate based on weights, it can selectively output results directly upon input stimulus, converting dynamic power consumption into static power consumption, thereby solving the power consumption problem caused by the original computation using the addition tree circuit.

[0006] To address the aforementioned technical problems, a first aspect of the present invention discloses an all-digital in-memory computing device based on a lookup table structure, comprising: two basic SRAM units in an SRAM: a first SRAM unit and a second SRAM unit, and a lookup table structure; wherein the lookup table structure is respectively connected to the first SRAM unit and the second SRAM unit;

[0007] The input and output of the first SRAM unit are both the first weights of the neural network;

[0008] The input and output of the second SRAM unit are both the second weights of the neural network;

[0009] The lookup table structure directly uses the outputs of the first SRAM unit and the second SRAM unit as inputs, and connects to the first input stimulus and the second input stimulus;

[0010] The output of the lookup table structure includes: carry output and bit output;

[0011] Before inputting the first input stimulus and the second input stimulus, the lookup table structure receives the first weight and the second weight from the first SRAM cell and the second SRAM cell respectively for pre-budgeting; when inputting the first input stimulus and the second input stimulus, the lookup table structure selects and outputs based on the data obtained from the pre-budgeting.

[0012] Preferably, the lookup table structure includes: an arithmetic unit, a first multiplexer, and a second multiplexer; the input terminals of the first multiplexer and the second multiplexer are respectively connected to the arithmetic unit; wherein,

[0013] The computing unit serves to pre-calculate the first weight and the second weight;

[0014] The input of the first multiplexer includes: the data obtained from the budget; the selection signal of the first multiplexer includes: the first input stimulus and the second input stimulus; the output of the first multiplexer includes: the sum bit output;

[0015] The input of the second multiplexer includes: the data obtained from the budget; the selection signal of the second multiplexer includes: the first input stimulus and the second input stimulus; the output of the second multiplexer includes: the carry output.

[0016] Preferably, both the first multiplexer and the second multiplexer are 4-to-1 multiplexers.

[0017] Preferably, the arithmetic unit includes: a first inverter and a second inverter;

[0018] The first inverter has its input terminal connected to the first SRAM cell, and serves to invert the first weight.

[0019] The second inverter has its input connected to the second SRAM cell, and serves to invert the second weight.

[0020] Preferably, the arithmetic unit further includes:

[0021] A first AND gate has one input terminal connected to both the input terminal of the first SRAM cell and the input terminal of the first inverter, and the other input terminal connected to both the input terminal of the second SRAM cell and the input terminal of the second inverter; the inputs of the first AND gate include: the first weight and the second weight; the output terminal of the first AND gate is connected to the input terminal of the second multiplexer.

[0022] The second AND gate has one input connected to the output of the first inverter, and the other input connected to both the second SRAM cell and the input of the second inverter; the inputs of the second AND gate include: the inverted signal of the first weight and the second weight; the output of the second AND gate is connected to the input of the second multiplexer.

[0023] A third AND gate has one input terminal connected to both the first SRAM cell and the input terminal of the first inverter, and the other input terminal connected to the output terminal of the second inverter; the input of the third AND gate includes the inverted signals of the first weight and the second weight; the output terminal of the third AND gate is connected to the input terminal of the second multiplexer.

[0024] The fourth AND gate has one input connected to the output of the first inverter and the other input connected to the output of the second inverter; the inputs of the fourth AND gate include: the inverted signal of the first weight and the inverted signal of the second weight; the output of the fourth AND gate is connected to the input of the second multiplexer.

[0025] A first XOR gate has one input terminal connected to both the input terminal of the first SRAM cell and the input terminal of the first inverter, and the other input terminal connected to both the input terminal of the second SRAM cell and the input terminal of the second inverter; the input of the first XOR gate includes: the first weight and the second weight; the output terminal of the first XOR gate is connected to the input terminal of the first multiplexer.

[0026] The second XOR gate has one input connected to the output of the first inverter, and the other input connected to both the second SRAM cell and the input of the second inverter; the inputs of the second XOR gate include: the inverted signal of the first weight and the second weight; the output of the second XOR gate is connected to the input of the first multiplexer.

[0027] The third XOR gate has one input terminal connected to both the first SRAM cell and the input terminal of the first inverter, and the other input terminal connected to the output terminal of the second inverter; the input of the third XOR gate includes the inverted signals of the first weight and the second weight; the output terminal of the third XOR gate is connected to the input terminal of the first multiplexer.

[0028] The fourth XOR gate has one input connected to the output of the first inverter and the other input connected to the output of the second inverter; the inputs of the fourth XOR gate include: the inverted signal of the first weight and the inverted signal of the second weight; the output of the fourth XOR gate is connected to the input of the first multiplexer.

[0029] A second aspect of the present invention discloses an all-digital in-memory computing architecture, comprising an all-digital in-memory computing device based on a lookup table structure as described in any of the foregoing technical solutions.

[0030] A third aspect of the present invention discloses a computer device comprising a fully digital in-memory computing device based on a lookup table structure as described in any of the foregoing technical solutions.

[0031] Through one or more technical solutions of the present invention, the present invention has the following beneficial effects or advantages:

[0032] This invention discloses a fully digital in-memory computing device based on a lookup table structure. It combines SRAM and a lookup table structure to replace the calculations of the addition tree circuit and the multiplier units of the basic SRAM cells used in the original architecture. The lookup table structure is used to pre-calculate the weights stored in the SRAM cells. When the first and second input stimuli are input, the selected output is directly selected based on the data obtained from the budget. The power consumption generated during the calculation process is converted into static power consumption, thereby solving the power consumption problem caused by the addition tree circuit used in the original calculation. It can achieve the effect of reducing power consumption and improving energy efficiency.

[0033] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0034] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings.

[0035] In the attached diagram:

[0036] Figure 1 A schematic diagram of the structure of an all-digital in-memory computing device based on a lookup table structure according to an embodiment of the present invention is shown.

[0037] Figure 2 A schematic diagram of a lookup table structure according to an embodiment of the present invention is shown. Detailed Implementation

[0038] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0039] This invention discloses a fully digital in-memory computing device based on a lookup table structure. This device can be used in fully digital in-memory computing architectures, combining SRAM and a lookup table structure to replace the computation of the addition tree circuit and the multiplier units of the basic SRAM cells used in the original architecture. This reduces the use of one level of addition tree and multiplier units, thereby reducing power consumption. Taking a signed binary neural network in-memory computing architecture as an example, it supports single-bit signed number operations, where voltage VDD represents "1" and voltage VSS represents "0". The lookup table structure in this device converts the computational power consumption originally generated by the addition tree circuit into static power consumption, thereby reducing power consumption and improving energy efficiency.

[0040] See Figure 1 This is a schematic diagram of a fully digital in-memory computing device based on a lookup table structure, including: two basic SRAM cells in SRAM: a first SRAM cell 101 and a second SRAM cell 102, and a lookup table structure 103. The device is implemented by combining the two basic SRAM cells and the lookup table structure 103, which together constitute the basic structure of the device.

[0041] The first SRAM cell 101 and the second SRAM cell 102 are the most basic units in SRAM, each composed of 6 transistors. The first weight W0 and the second weight W1 in the neural network are stored in the first SRAM cell 101 and the second SRAM cell 102 respectively through the SRAM storage process. The input and output of the first SRAM cell 101 are both the first weight W0 of the neural network; the input and output of the second SRAM cell 102 are both the second weight W1 of the neural network. That is, the weights stored inside the SRAM are directly output and entered into the lookup table structure 103 as input to the lookup table structure 103. In this embodiment, the weight values ​​are also replaced by "0" and "1" in binary, representing -1 and +1 respectively.

[0042] The lookup table structure 103 is connected to the first SRAM cell 101 and the second SRAM cell 102 respectively.

[0043] The lookup table structure 103 receives two types of inputs: weight inputs and stimulus inputs. Specifically, the lookup table structure 103 directly uses the weight outputs of the first SRAM cell 101 and the second SRAM cell 102 as weight inputs. Additionally, the lookup table structure 103 connects to the first stimulus input IN0 and the second stimulus input IN1 as stimulus inputs. The stimulus inputs are the parts multiplied by the weight inputs.

[0044] The output of lookup table structure 103 includes: carry output COUT and bit output SUM.

[0045] The reason why the device in this embodiment can reduce power consumption is that before inputting the first input stimulus IN0 and the second input stimulus IN1, the device stores the first weight W0 and the second weight W1 in their respective SRAM cells. At this time, the lookup table structure 103 receives the first weight W0 and the second weight W1 from the first SRAM cell 101 and the second SRAM cell 102 respectively, performs a pre-calculation, and obtains the calculated data. When the first input stimulus IN0 and the second input stimulus IN1 are input, the lookup table structure 103 can directly select the output based on the calculated data without participating in the calculation. This avoids the dynamic consumption generated during dynamic calculation and only generates static power consumption.

[0046] See Figure 2 This is a structural diagram of lookup table structure 103, including: an operation unit, a first multiplexer MUX1, and a second multiplexer MUX2.

[0047] The inputs of the first multiplexer MUX1 and the second multiplexer MUX2 are connected to the arithmetic unit, respectively. The output of the first multiplexer MUX1 is used as the sum output SUM, and the output of the second multiplexer MUX2 is used as the carry output COUT.

[0048] The calculation unit serves to pre-calculate the first weight W0 and the second weight W1.

[0049] Continue reading Figure 2 The arithmetic unit includes: four AND gates, four XOR gates, a first inverter, and a second inverter. The four AND gates are: first AND gate A1, second AND gate A2, third AND gate A3, and fourth AND gate A4; the four XOR gates are: first XOR gate X1, second XOR gate X2, third XOR gate X3, and fourth XOR gate X4.

[0050] The first inverter l1 has its input terminal connected to the first SRAM unit 101, which inverts the first weight W0 to obtain the inverted signal W0' of the first weight W0.

[0051] The second inverter l2 has its input connected to the second SRAM cell 102, and it inverts the second weight W1 to obtain the inverted signal W1' of the second weight W1.

[0052] The first AND gate A1 has one input terminal connected to the input terminals of the first SRAM cell 101 and the first inverter 11, and the other input terminal connected to the input terminals of the second SRAM cell 102 and the second inverter 12; the input of the first AND gate A1 includes: a first weight W0 and a second weight W1; the output terminal of the first AND gate A1 is connected to the input terminal of the second multiplexer MUX2.

[0053] The second AND gate A2 has one input connected to the output of the first inverter l1, and the other input connected to the input of the second SRAM cell 102 and the second inverter l2. The input of the second AND gate A2 includes: the inverted signal W0' of the first weight W0 and the second weight W1. The output of the second AND gate A2 is connected to the input of the second multiplexer MUX2.

[0054] The third AND gate A3 has one input terminal connected to the input terminals of the first SRAM cell 101 and the first inverter l1, and the other input terminal connected to the output terminal of the second inverter l2; the input of the third AND gate A3 includes: the inverted signal W1' of the first weight W0 and the second weight W1; the output terminal of the third AND gate A3 is connected to the input terminal of the second multiplexer MUX2;

[0055] The fourth AND gate A4 has one input connected to the output of the first inverter l1 and the other input connected to the output of the second inverter l2; the input of the fourth AND gate A4 includes: the inverted signal W0' of the first weight W0 and the inverted signal W1' of the second weight W1; the output of the fourth AND gate A4 is connected to the input of the second multiplexer MUX2.

[0056] The first XOR gate X1 has one input terminal connected to the input terminals of the first SRAM cell 101 and the first inverter 11, and the other input terminal connected to the input terminals of the second SRAM cell 102 and the second inverter 12; the input of the first XOR gate X1 includes: a first weight W0 and a second weight W1; the output terminal of the first XOR gate X1 is connected to the input terminal of the first multiplexer MUX1.

[0057] The second XOR gate X2 has one input connected to the output of the first inverter l1, and the other input connected to the input of the second SRAM cell 102 and the second inverter l2. The input of the second XOR gate X2 includes: the inverted signal W0' of the first weight W0 and the second weight W1. The output of the second XOR gate X2 is connected to the input of the first multiplexer MUX1.

[0058] The third XOR gate X3 has one input terminal connected to the input terminals of the first SRAM cell 101 and the first inverter l1, and the other input terminal connected to the output terminal of the second inverter l2; the input of the third XOR gate X3 includes: the inverted signal W1' of the first weight W0 and the second weight W1; the output terminal of the third XOR gate X3 is connected to the input terminal of the first multiplexer MUX1.

[0059] The fourth XOR gate X4 has one input connected to the output of the first inverter l1 and the other input connected to the output of the second inverter l2. The inputs of the fourth XOR gate X4 include the inverted signal W0' of the first weight W0 and the inverted signal W1' of the second weight W1. The output of the fourth XOR gate X4 is connected to the input of the first multiplexer MUX1.

[0060] The above describes the specific structure of the arithmetic unit. The following section introduces two multiplexers. Both multiplexers are 4-to-1 multiplexers.

[0061] The inputs of the first multiplexer MUX1 include the calculated data, specifically the outputs of the first XOR gate X1, the second XOR gate X2, the third XOR gate X3, and the fourth XOR gate X4.

[0062] The selection signals of the first multiplexer MUX1 include: the first input stimulus IN0 and the second input stimulus IN1.

[0063] The output of the first multiplexer MUX1 includes: the bit output SUM.

[0064] The inputs of the second multiplexer MUX2 include the calculated data, specifically the outputs of the first AND gate A1, the second AND gate A2, the third AND gate A3, and the fourth AND gate A4.

[0065] The selection signals of the second multiplexer MUX2 include: the first input stimulus IN0 and the second input stimulus IN1.

[0066] The output of the second multiplexer MUX2 includes: carry output COUT.

[0067] In this embodiment, both the first multiplexer MUX1 and the second multiplexer MUX2 use the first input stimulus IN0 and the second input stimulus IN1 as selection signals. Their corresponding outputs are described below:

[0068] When the first input stimulus IN0 is 0 and the second input stimulus IN1 is 0, the first multiplexer MUX1 and the second input stimulus IN1 output: the output of the fourth XOR gate X4 and the output of the fourth AND gate A4, respectively.

[0069] When the first input stimulus IN0 is 0 and the second input stimulus IN1 is 1, the first multiplexer MUX1 and the second input stimulus IN1 output: the output of the third XOR gate X3 and the output of the third AND gate A3, respectively.

[0070] When the first input stimulus IN0 is 1 and the second input stimulus IN1 is 0, the first multiplexer MUX1 and the second input stimulus IN1 output: the output of the second XOR gate X2 and the output of the second AND gate A2, respectively.

[0071] When the first input stimulus IN0 is 1 and the second input stimulus IN1 is 1, the first multiplexer MUX1 and the second input stimulus IN1 output: the output of the first XOR gate X1 and the output of the first AND gate A1, respectively.

[0072] When designing the lookup table structure 103, considering the in-memory computation units of the binary neural network, the output of the first stage can be represented using Boolean logic as follows:

[0073] (COUT, SUM)=IN0⊙W0+IN1⊙W1

[0074] To eliminate the influence of the two input stimuli, a truth table is created for (COUT, SUM) with respect to all values ​​of the first input stimulus IN0 and the second input stimulus IN1. The truth table is shown in Table 1 below:

[0075] Table 1

[0076] IN1 IN0 (COUT, SUM) 0 0 W0'+W1' 0 1 W0'+W1 1 0 W0+W1' 1 1 W0+W1

[0077] In Table 1, each "+" represents a half adder, and the Boolean logic for the half adder is as follows:

[0078] COUT = A·B represents the logical relationship of the AND gate.

[0079] SUM = A⊕B represents the logical relationship of an XOR gate.

[0080] Based on this, the aforementioned lookup table structure 103 is constructed. The lookup table structure 103 does not need to wait for input stimulus and can perform calculations directly. Therefore, there is only static power consumption during the calculation process.

[0081] The above is a detailed structural introduction of a fully digital in-memory computing device based on a lookup table structure. Since lookup tables can perform bitwise multiplication and first-level addition, they can replace the computations of the addition tree circuit in the digital domain in-memory computing architecture, such as the first-level computation in the addition tree circuit and the multiplier units corresponding to each SRAM basic unit. Therefore, while eliminating the first-level addition, the multiplier unit equipped in each basic SRAM unit is also eliminated; both are replaced by a lookup table structure, thus simplifying the overall structure of the fully digital in-memory architecture. Furthermore, by adopting the implementation principle of pre-calculating neural network weights using a lookup table structure, the computational power consumption in the original calculation process is transformed into static power consumption while simplifying the structure, achieving the goal of reducing power consumption and improving energy efficiency. In addition, as digital logic, compared with mainstream analog domain in-memory computing structures, the circuit has better robustness, and the PVT (process, voltage, temperature) effect has a relatively small impact on the circuit's function.

[0082] Based on the same inventive concept as the foregoing embodiments, the following embodiments disclose an all-digital in-memory computing architecture, including the all-digital in-memory computing device based on a lookup table structure described in any of the foregoing embodiments.

[0083] Based on the same inventive concept as the foregoing embodiments, the following embodiments disclose a computer device comprising a fully digital in-memory computing device based on a lookup table structure as described in any of the foregoing embodiments.

[0084] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0085] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A fully digital in-memory computing device based on a lookup table structure, characterized in that, include: The SRAM consists of two basic SRAM cells: a first SRAM cell and a second SRAM cell, and a lookup table structure; wherein the lookup table structure connects the first SRAM cell and the second SRAM cell respectively; The input and output of the first SRAM unit are both the first weights of the neural network; The input and output of the second SRAM unit are both the second weights of the neural network; The lookup table structure directly uses the outputs of the first SRAM unit and the second SRAM unit as inputs, and connects to the first input stimulus and the second input stimulus; The output of the lookup table structure includes: carry output and bit output; Before inputting the first input stimulus and the second input stimulus, the lookup table structure receives the first weight and the second weight from the first SRAM cell and the second SRAM cell, respectively, and performs pre-calculation. When the first input stimulus and the second input stimulus are input, the lookup table structure combines the data obtained from the pre-calculation to select the output. The lookup table structure includes: an arithmetic unit, a first multiplexer, and a second multiplexer; the input terminals of the first multiplexer and the second multiplexer are respectively connected to the arithmetic unit. The computing unit serves to pre-calculate the first weight and the second weight; The input of the first multiplexer includes: the data obtained from the budget; the selection signal of the first multiplexer includes: the first input stimulus and the second input stimulus; the output of the first multiplexer includes: the sum bit output; The input of the second multiplexer includes: the data obtained from the budget; the selection signal of the second multiplexer includes: the first input stimulus and the second input stimulus; the output of the second multiplexer includes: the carry output.

2. The apparatus as claimed in claim 1, characterized in that, Both the first multiplexer and the second multiplexer are 4-to-1 multiplexers.

3. The apparatus as described in claim 2, characterized in that, The arithmetic unit includes: a first inverter and a second inverter; The first inverter has its input terminal connected to the first SRAM cell, and serves to invert the first weight. The second inverter has its input connected to the second SRAM cell, and serves to invert the second weight.

4. The apparatus as described in claim 3, characterized in that, The arithmetic unit further includes: A first AND gate has one input terminal connected to both the input terminal of the first SRAM cell and the input terminal of the first inverter, and the other input terminal connected to both the input terminal of the second SRAM cell and the input terminal of the second inverter; the inputs of the first AND gate include: the first weight and the second weight; the output terminal of the first AND gate is connected to the input terminal of the second multiplexer. The second AND gate has one input connected to the output of the first inverter, and the other input connected to both the second SRAM cell and the input of the second inverter; the inputs of the second AND gate include: the inverted signal of the first weight and the second weight; the output of the second AND gate is connected to the input of the second multiplexer. A third AND gate has one input terminal connected to both the first SRAM cell and the input terminal of the first inverter, and the other input terminal connected to the output terminal of the second inverter; the input of the third AND gate includes the inverted signals of the first weight and the second weight; the output terminal of the third AND gate is connected to the input terminal of the second multiplexer. The fourth AND gate has one input connected to the output of the first inverter and the other input connected to the output of the second inverter; the inputs of the fourth AND gate include: the inverted signal of the first weight and the inverted signal of the second weight; the output of the fourth AND gate is connected to the input of the second multiplexer. A first XOR gate has one input terminal connected to both the input terminal of the first SRAM cell and the input terminal of the first inverter, and the other input terminal connected to both the input terminal of the second SRAM cell and the input terminal of the second inverter; the input of the first XOR gate includes: the first weight and the second weight; the output terminal of the first XOR gate is connected to the input terminal of the first multiplexer. The second XOR gate has one input connected to the output of the first inverter, and the other input connected to both the second SRAM cell and the input of the second inverter; the inputs of the second XOR gate include: the inverted signal of the first weight and the second weight; the output of the second XOR gate is connected to the input of the first multiplexer. The third XOR gate has one input terminal connected to both the first SRAM cell and the input terminal of the first inverter, and the other input terminal connected to the output terminal of the second inverter; the input of the third XOR gate includes the inverted signals of the first weight and the second weight; the output terminal of the third XOR gate is connected to the input terminal of the first multiplexer. The fourth XOR gate has one input connected to the output of the first inverter and the other input connected to the output of the second inverter; the inputs of the fourth XOR gate include: the inverted signal of the first weight and the inverted signal of the second weight; the output of the fourth XOR gate is connected to the input of the first multiplexer.

5. A fully digital in-memory computing architecture, characterized in that, The invention includes a fully digital in-memory computing device based on a lookup table structure as described in any one of claims 1-4.

6. A computer device, characterized in that, The invention includes a fully digital in-memory computing device based on a lookup table structure as described in any one of claims 1-4.

Images