Display device and electronic device including the same

Abstract

The invention provides a display device and an electronic device including the same. The display device includes: a substrate; a first active pattern disposed on the substrate and extending in a first direction; a first conductive pattern disposed on the first active pattern and overlapping a portion of the first active pattern in a plan view; a second conductive pattern disposed on the first conductive pattern and extending in a second direction intersecting the first direction; and a second active pattern disposed on the second conductive pattern and defining a storage capacitor together with the first conductive pattern and the second conductive pattern.

Description

Technical Field

[0001] The embodiments relate to display devices. More specifically, the embodiments relate to display devices that provide visual information. Background Technology

[0002] A display device is a device that displays images to provide visual information to a user. Types of display devices include liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays. Display devices can operate using thin-film transistors (TFTs), capacitors, and multi-line circuits with complex interconnections.

[0003] Recently, with the increasing demand for compact and high-resolution display devices, there is a growing need for efficient spatial arrangement, interconnection structures, driving methods, and improved image quality among thin-film transistors, capacitors, and lines included in display devices. Summary of the Invention

[0004] The embodiments provide a display device with improved display quality.

[0005] The display device according to an embodiment includes: a substrate; a first active pattern disposed on the substrate and extending in a first direction; a first conductive pattern disposed on the first active pattern and partially overlapping the first active pattern in a plan view; a second conductive pattern disposed on the first conductive pattern and extending in a second direction intersecting the first direction; and a second active pattern disposed on the second conductive pattern and defining a storage capacitor together with the first conductive pattern and the second conductive pattern.

[0006] In an embodiment, the storage capacitor may include a first storage capacitor defined by overlapping a portion of a first conductive pattern with a portion of a second conductive pattern and a second storage capacitor defined by overlapping a portion of a second conductive pattern with a portion of a second active pattern.

[0007] In an embodiment, the display device may further include: a gate voltage line disposed on a second active pattern, extending in a second direction and configured to be subjected to a gate write signal; a horizontal power supply voltage line disposed on the gate voltage line and extending in the second direction; a third conductive pattern disposed on the gate voltage line and spaced apart from the horizontal power supply voltage line in a first direction; and a fourth conductive pattern disposed on the gate voltage line and spaced apart from the third conductive pattern and the horizontal power supply voltage line.

[0008] In an embodiment, the second conductive pattern may be electrically connected to the first active pattern, and the third conductive pattern may be spaced apart from the second conductive pattern in a first direction in a planar view and electrically connected to the first active pattern.

[0009] In an embodiment, the first active pattern, the first conductive pattern, the second conductive pattern, and the third conductive pattern may together define a driving transistor.

[0010] In an embodiment, the second conductive pattern may be the source electrode of the driving transistor, the third conductive pattern may be the drain electrode of the driving transistor, and the portion of the first conductive pattern that overlaps with the first active pattern in the planar view may be the gate electrode of the driving transistor.

[0011] In an embodiment, the first conductive pattern may be electrically connected to the second active pattern, and the fourth conductive pattern may be spaced apart from the first conductive pattern in a first direction in a planar view and may be electrically connected to the second active pattern.

[0012] In an embodiment, the second active pattern, the gate voltage line, the first conductive pattern, and the fourth conductive pattern may together define the switching transistor.

[0013] In an embodiment, the first conductive pattern may be the drain electrode of the switching transistor, the fourth conductive pattern may be the source electrode of the switching transistor, and the portion of the gate voltage line that overlaps with the second active pattern in the plan view may be the gate electrode of the switching transistor.

[0014] In one embodiment, the horizontal power supply voltage line can be configured to be applied a power supply voltage, and the horizontal power supply voltage line can be electrically connected to the second conductive pattern.

[0015] In an embodiment, the second conductive pattern and the first active pattern can be connected through a first contact hole, the second active pattern and the first conductive pattern can be connected through a second contact hole, the horizontal power supply voltage line and the second conductive pattern can be connected through a third contact hole, the third conductive pattern and the first active pattern can be connected through a fourth contact hole, and the fourth conductive pattern and the second active pattern can be connected through a fifth contact hole.

[0016] In an embodiment, in a plan view, the first contact hole, the third contact hole, and the fourth contact hole may be arranged along a first imaginary vertical line parallel to the first direction, and in a plan view, the second contact hole and the fifth contact hole may be arranged along a second imaginary vertical line parallel to the first direction and spaced apart from the first imaginary vertical line.

[0017] In an embodiment, the display device may further include: a data voltage line disposed on a horizontal power supply voltage line and extending in a first direction; and a fifth conductive pattern disposed on the data voltage line and spaced apart from the horizontal power supply voltage line in the first direction in a plan view.

[0018] In one embodiment, the data voltage line can be connected to the fourth conductive pattern through the sixth contact hole, and in a plan view, the sixth contact hole can overlap with the fifth contact hole.

[0019] In an embodiment, the fifth conductive pattern can be electrically connected to the third conductive pattern through the seventh contact hole, and in a plan view, the seventh contact hole can overlap with the fourth contact hole.

[0020] In an embodiment, in a plan view, the fifth conductive pattern and the data voltage line may be adjacent to each other.

[0021] In an embodiment, the display device may further include a vertical power voltage line disposed between the horizontal power voltage line and the data voltage line and extending in a first direction.

[0022] In an embodiment, in a planar view, the second active pattern may partially overlap with the first active pattern.

[0023] A display device according to an embodiment includes: a substrate; a first active pattern disposed on the substrate and extending in a first direction; a first conductive pattern disposed on the first active pattern and partially overlapping the first active pattern in a plan view; a second conductive pattern disposed on the first conductive pattern, extending in a second direction intersecting the first direction, and partially contacting the first active pattern through a first contact hole; a second active pattern disposed on the second conductive pattern, partially overlapping each of the first and second conductive patterns in a plan view, and partially contacting the first conductive pattern through a second contact hole; a gate voltage line disposed on the second active pattern, extending in a second direction, and configured to be applied a gate write signal; a horizontal power supply voltage line disposed on the gate voltage line, configured to be applied a power supply voltage, and partially contacting the second conductive pattern through a third contact hole; a third conductive pattern disposed in the same layer as the horizontal power supply voltage line and partially contacting the first active pattern through a fourth contact hole; and a fourth conductive pattern disposed in the same layer as the horizontal power supply voltage line and partially contacting the second active pattern through a fifth contact hole.

[0024] In an embodiment, in a plan view, the first contact hole, the third contact hole, and the fourth contact hole may be arranged along a first imaginary vertical line parallel to the first direction, and in a plan view, the second contact hole and the fifth contact hole may be arranged along a second imaginary vertical line parallel to the first direction and spaced apart from the first imaginary vertical line.

[0025] In a display device according to embodiments of the present disclosure, the display device may include a first active pattern disposed on a substrate and extending in a first direction, a first conductive pattern partially overlapping the first active pattern in a planar view, a second conductive pattern disposed on the first conductive pattern and extending in a second direction intersecting the first direction, and a second active pattern defining a storage capacitor together with the first and second conductive patterns. A pixel included in the display device may include two transistors. Therefore, the number of pixels included in the display device can be increased, thus enabling the display device to be implemented at a high resolution. Furthermore, since the display device may include sensing circuitry for external compensation, transistor degradation can be prevented. Attached Figure Description

[0026] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 It is shown that it includes Figure 1 The circuit diagram of the pixels in the display device.

[0029] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 It is shown that it includes Figure 1 A plan view of an example of pixels in a display device.

[0030] Figure 16 It is shown Figure 1 The pixels of the display device along Figure 15 A cross-sectional view of the section cut by line I-I'.

[0031] Figure 17 It is shown Figure 1 The pixels of the display device along Figure 15 A cross-sectional view of the section cut by line II-II'.

[0032] Figure 18 and Figure 19 It is shown that it includes Figure 1 A plan view of another example of pixels in a display device.

[0033] Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 It is shown that it includes Figure 1 A plan view of yet another example of pixels in a display device.

[0034] Figure 25 It is shown by Figure 1 The display device realizes the view of the electronic device. Detailed Implementation

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” is not to be construed as a limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” or “including” and / or “comprising” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0036] It will be understood that although the terms “first,” “second,” “third,” etc., may be used in this document to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings of this document, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0037] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element, or there can be an intervening element between them. Conversely, when an element is referred to as being "directly on another element," there is no intervening element.

[0038] In the following description, the display device according to the embodiment will be described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same parts, and redundant descriptions of the same parts will be omitted.

[0039] Figure 1This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0040] refer to Figure 1 The display device DD may include a display panel PN, a timing controller CON, a gate driver GDV, a data driver DDV, and a sensing circuit SSC.

[0041] The display panel PN may include a display area defined as the region for displaying an image and a peripheral area adjacent to the display area. Multiple pixels PX, multiple gate lines GL1, GL2, ... GLn, multiple data lines DL1, DL2, ... DLm, and sensing connection lines SCL may be disposed in the display area. Here, m and n are positive integers. Gate driver GDV, data driver DDV, and sensing circuitry SSC may be disposed in the peripheral area.

[0042] In this specification, the plane may be defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the second direction DR2 may be perpendicular to the first direction DR1. Furthermore, a third direction DR3 may be perpendicular to the plane.

[0043] Multiple pixels PX can be arranged in a matrix form comprising multiple matrix rows and multiple matrix columns. For example, multiple pixels PX can be arranged along a first direction DR1 and a second direction DR2. Each of the multiple pixels PX can be electrically connected to a gate line in multiple gate lines GL1, GL2, ... GLn, a data line in multiple data lines DL1, DL2, ... DLm, and a sensing connection line SCL.

[0044] Each of the multiple gate lines GL1, GL2, ... GLn can extend along the second direction DR2. Furthermore, the multiple gate lines GL1, GL2, ... GLn can be arranged along the first direction DR1. Each of the multiple data lines DL1, DL2, ... DLm can extend along the first direction DR1. Furthermore, the multiple data lines DL1, DL2, ... DLm can be arranged along the second direction DR2.

[0045] The timing controller CON can receive input image data IDAT and input control signal CTRL from the main processor (e.g., graphics processing unit, GPU, etc.). In one embodiment, the input image data IDAT may include red image data, green image data, and blue image data. In another embodiment, the input image data IDAT may also include white image data. In yet another embodiment, the input image data IDAT may include magenta image data, yellow image data, and cyan image data. The input control signal CTRL may include a master clock signal and a data enable signal. The input control signal CTRL may also include a vertical synchronization signal and a horizontal synchronization signal.

[0046] The timing controller CON can generate gate control signal GCTRL, data control signal DCTRL, and output image data ODAT based on the input image data IDAT and the input control signal CTRL.

[0047] The timing controller CON can generate a gate control signal GCTRL based on the input control signal CTRL to control the operation of the gate driver GDV, and output the gate control signal GCTRL to the gate driver GDV. The gate control signal GCTRL may include a vertical start signal and a gate clock signal.

[0048] The timing controller CON can generate a data control signal DCTRL for controlling the operation of the data driver DDV based on the input control signal CTRL, and output the data control signal DCTRL to the data driver DDV. The data control signal DCTRL can include a horizontal start signal and a load signal.

[0049] The timing controller CON can receive input image data IDAT and input control signal CTRL, and generate output image data ODAT. The timing controller CON can output the output image data ODAT to the data driver DDV.

[0050] The gate driver GDV can generate a gate signal GS for driving multiple gate lines GL1, GL2, ... GLn in response to a gate control signal GCTRL input from the timing controller CON. For example, the gate signal GS may include a gate write signal (e.g., Figure 2 The gate write signal GW). The gate driver GDV can output the gate signal GS to each of multiple gate lines GL1, GL2, ... GLn. For example, the gate driver GDV can sequentially output the gate signal GS to multiple gate lines GL1, GL2, ... GLn.

[0051] The data driver DDV can receive data control signals DCTRL and output image data ODAT from the timing controller CON. The data driver DDV can generate a data voltage VD that converts the output image data ODAT into an analog voltage. The data driver DDV can output the data voltage VD to multiple data lines DL1, DL2, ... DLm. In one embodiment, the data driver DDV can be mounted on the display panel PN or integrated into the periphery of the display panel PN. In another embodiment, the data driver DDV can be implemented as one or more integrated circuits (“ICs”).

[0052] The sensing circuit SSC can be electrically connected to the sensing connection line SCL. Furthermore, the sensing connection line SCL can be connected to a power supply voltage line that applies power supply voltages to the multiple pixels PX. Therefore, when the display device DD is driven in sensing mode, the sensing circuit SSC can sample the voltage corresponding to the first power supply voltage (e.g., ...) from the sensing connection line SCL. Figure 2 The sensing circuit SSC measures the first power supply voltage (ELVDD) and its sensing current, and can use the sensing current to calculate a threshold voltage value for measuring the degradation of transistors located in the display area. The sensing circuit SSC can provide compensation data CDAT, including the calculated threshold voltage value, to the timing controller CON. In other words, the sensing circuit SSC can be an external compensation circuit for applying a compensation voltage to each of the multiple pixels PX and preventing transistor degradation.

[0053] Figure 2 It is shown that it includes Figure 1 The circuit diagram of the pixels in the display device.

[0054] refer to Figure 2 A pixel PX may include a pixel circuit PXC and a light-emitting element EE. The pixel circuit PXC may include a first transistor TR1, a second transistor TR2, and a storage capacitor CST. The pixel circuit PXC can provide a drive current to the light-emitting element EE, and the light-emitting element EE can generate light based on the drive current.

[0055] The first terminal of the first transistor TR1 can be connected to the first power supply voltage line. For example, the first transistor TR1 can receive the first power supply voltage ELVDD from the first power supply voltage line through the first terminal, and can generate a drive current corresponding to the first power supply voltage ELVDD.

[0056] The second terminal of the first transistor TR1 can be connected to the light-emitting element EE. For example, the first transistor TR1 can provide drive current to the light-emitting element EE through its second terminal. The gate terminal of the first transistor TR1 can be connected to the first terminal of the storage capacitor CST. In this specification, the first transistor TR1 may be referred to as the "drive transistor".

[0057] In one embodiment, the first transistor TR1 may be a p-channel metal-oxide-semiconductor (“PMOS”) transistor. In another embodiment, the first transistor TR1 may be an n-channel metal-oxide-semiconductor (“NMOS”) transistor.

[0058] The first terminal of the second transistor TR2 can be connected to the data voltage line (e.g., Figure 12The data voltage line VDL). A data voltage VD can be applied to the data voltage line VDL. The second terminal of the second transistor TR2 can be connected to the gate terminal of the first transistor TR1. Furthermore, the second terminal of the second transistor TR2 can be connected to the first terminal of the storage capacitor CST. The gate terminal of the second transistor TR2 can be connected to the gate voltage line (e.g., Figure 9 Gate voltage line GL).

[0059] The second transistor TR2 can be turned on by the gate write signal GW provided by the gate voltage line GL. When the second transistor TR2 is turned on, it can provide the data voltage VD to the first transistor TR1. In this specification, the second transistor TR2 may be referred to as a switching transistor.

[0060] In one embodiment, the second transistor TR2 may be a PMOS transistor. In another embodiment, the second transistor TR2 may be an NMOS transistor.

[0061] The first terminal of the storage capacitor CST can be connected to the gate terminal of the first transistor TR1 and the second terminal of the second transistor TR2. Furthermore, the second terminal of the storage capacitor CST can be connected to the first power supply voltage line. The storage capacitor CST can maintain the voltage level of the gate terminal of the first transistor TR1 during the inactive period of the gate write signal GW provided by the gate voltage line GL.

[0062] A driving current can be applied to one end of the light-emitting element EE, and a second power supply voltage ELVSS can be applied to the other end of the light-emitting element EE.

[0063] Further reference Figure 1 The sensing connection line SCL can be connected to the first power supply voltage line. The threshold voltage of the first transistor TR1 can be compensated by connecting the sensing connection line SCL to the sensing circuit SSC.

[0064] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 It is shown that it includes Figure 1 A plan view of an example of pixels in a display device. Figure 16 It is shown Figure 1 The pixels of the display device along Figure 15A cross-sectional view of the section cut by line I-I'. Figure 17 It is shown Figure 1 The pixels of the display device along Figure 15 A cross-sectional view of the section taken from line II-II'. As used herein, a "planar view" is taken on the substrate SUB (see [reference]). Figure 16 The view in the thickness direction (i.e., the third direction DR3).

[0065] For example, Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 It is shown that it includes Figure 1 This is a plan view of one of a plurality of pixels PX in a display device DD. Parts of the plurality of pixels PX can emit different colors of light. For example, the plurality of pixels PX may include a first pixel emitting red light, a second pixel emitting green light, and a third pixel emitting blue light. The first, second, and third pixels adjacent to each other along the second direction DR2 can constitute a unit pixel. Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 This is a planar view showing one of the first, second, and third pixels. However, the pixels PX and unit pixels of this disclosure are not limited to this, and the unit pixel may include four or more pixels PX, and the light emitted by the pixels PX may include various colors other than red, green, and blue.

[0066] refer to Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 Display devices (e.g., Figure 1 The display device (DD) may include a substrate SUB, a first active layer ATV1, a first insulating layer IL1, a first conductive layer CL1, a second insulating layer IL2, a second conductive layer CL2, a third insulating layer IL3, a second active layer ATV2, a fourth insulating layer IL4, a third conductive layer CL3, a fifth insulating layer IL5, a fourth conductive layer CL4, an interlayer insulating layer ISL, a fifth conductive layer CL5, a first via insulating layer VIA1, a sixth conductive layer CL6, a second via insulating layer VIA2, a pixel defining layer PDL, a pixel electrode PXE, a light emitting layer EML, and a common electrode CME.

[0067] A first active pattern ATP1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1 can define a first transistor TR1. A second active pattern ATP2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2 can define a second transistor TR2. A pixel electrode PXE, an emissive layer EML, and a common electrode CME can define a light-emitting element EE.

[0068] The substrate SUB can comprise transparent or opaque materials. The substrate SUB can be made of a transparent resin substrate. Examples of transparent resin substrates include polyimide substrates. In this case, the substrate SUB, as a polyimide substrate, can comprise a first organic layer, a first barrier layer, a second organic layer, etc. Alternatively, the substrate SUB can comprise a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, an alkali-free glass substrate, etc. These can be used individually or in combination with each other.

[0069] The first active layer ATV1, the first conductive layer CL1, the second conductive layer CL2, the second active layer ATV2, the third conductive layer CL3, the fourth conductive layer CL4, the fifth conductive layer CL5, and the sixth conductive layer CL6 can be stacked sequentially on the substrate SUB.

[0070] The first active layer ATV1 may be disposed on the substrate SUB. In an embodiment, the first active layer ATV1 may include polycrystalline silicon. However, the materials included in the first active layer ATV1 according to embodiments of the present disclosure are not limited to this, and the first active layer ATV1 may include metal oxide semiconductor, amorphous silicon, etc.

[0071] The first active layer ATV1 may include a first active pattern ATP1. A pixel PX may include one first active pattern ATP1. The first active pattern ATP1 may extend along a first direction DR1. The first active pattern ATP1 may be arranged along the first direction DR1 and a second direction DR2. For example, the first active pattern ATP1 included in a pixel PX and the first active pattern ATP1 included in another pixel adjacent to that pixel PX may be spaced apart along the first direction DR1 or the second direction DR2.

[0072] The first active pattern ATP1 may include a first active region AR1, a second active region AR2, and a third active region AR3. The first active region AR1 and the second active region AR2 may be adjacent to each other in a first direction DR1. The second active region AR2 and the third active region AR3 may be adjacent to each other in the first direction DR1. The second active region AR2 may be located between the first active region AR1 and the third active region AR3.

[0073] The first conductive layer CL1 can be disposed on the first active pattern ATP1. Specifically, the first insulating layer IL1 can be disposed on the first active pattern ATP1, and the first conductive layer CL1 can be disposed on the first insulating layer IL1.

[0074] In this embodiment, the first insulating layer IL1 may include an inorganic insulating material. This inorganic insulating material may include silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination. In an embodiment, the first insulating layer IL1 may cover the first active layer ATV1. For example, the first insulating layer IL1 may have a substantially uniform thickness and cover the first active layer ATV1. However, the first insulating layer IL1 according to embodiments of the present disclosure may not be limited to this, and the first insulating layer IL1 may have a substantially flat upper surface and cover the first active layer ATV1.

[0075] In this embodiment, the first conductive layer CL1 may include a conductive material. For example, the conductive material may include silver (Ag), molybdenum (Mo), aluminum (Al), or aluminum nitride (Al). x N y ), tungsten (W), tungsten nitride (W) x N y Indium tin oxide (ITO), indium zinc oxide (IZO), etc. These can be used alone or in combination.

[0076] The first conductive layer CL1 may include a first conductive pattern CP1. In an embodiment, in a planar view, the first conductive pattern CP1 may overlap with a first active pattern ATP1. For example, in a planar view, the first conductive pattern CP1 may partially overlap with the first active pattern ATP1. Specifically, in a planar view, the first conductive pattern CP1 may overlap with a second active region AR2 of the first active pattern ATP1. The portion of the first conductive pattern CP1 that overlaps with the first active pattern ATP1 in the planar view may be the first gate electrode GE1 of the first transistor TR1. Furthermore, the portion of the first active pattern ATP1 that overlaps with the first conductive pattern CP1 in the planar view may be the channel region of the first transistor TR1. In other words, the second active region AR2 may be the channel region of the first transistor TR1.

[0077] The second conductive layer CL2 can be disposed on the first conductive layer CL1. Specifically, the second insulating layer IL2 can be disposed on the first conductive layer CL1, and the second conductive layer CL2 can be disposed on the second insulating layer IL2.

[0078] In an embodiment, the second insulating layer IL2 may comprise an inorganic insulating material. In an embodiment, the second insulating layer IL2 may cover the first conductive layer CL1. For example, the second insulating layer IL2 may have a substantially uniform thickness and cover the first conductive layer CL1. However, the second insulating layer IL2 according to embodiments of this disclosure is not limited to this, and the second insulating layer IL2 may have a substantially flat upper surface and cover the first conductive layer CL1.

[0079] In an embodiment, the second conductive layer CL2 may include a conductive material. The second conductive layer CL2 may include a second conductive pattern CP2. The second conductive pattern CP2 may extend in a second direction DR2. The second conductive pattern CP2 may be arranged along a first direction DR1. In an embodiment, in a plan view, the second conductive pattern CP2 may overlap with a first active pattern ATP1. For example, in a plan view, the second conductive pattern CP2 may overlap with each of the first active region AR1 and the second active region AR2.

[0080] A first contact hole CNT1 can be defined between the second conductive pattern CP2 and the first active pattern ATP1 to electrically connect the second conductive pattern CP2 and the first active pattern ATP1 to each other. For example, the first contact hole CNT1 can penetrate the first insulating layer IL1 and the second insulating layer IL2 in the thickness direction (e.g., the third direction DR3). Therefore, a portion of the second conductive pattern CP2 can contact the first active region AR1 of the first active pattern ATP1 through the first contact hole CNT1. In an embodiment, the second conductive pattern CP2 can be the first source electrode SE1, which is the source electrode of the first transistor TR1. However, this disclosure is not limited to this, and the second conductive pattern CP2 can also be the drain electrode of the first transistor TR1.

[0081] In a plan view, the second conductive pattern CP2 may overlap with the first conductive pattern CP1. The storage capacitor CST may include a first storage capacitor CST1 and a second storage capacitor CST2. The second conductive pattern CP2 and the first conductive pattern CP1 may overlap each other in the plan view to define the first storage capacitor CST1. Specifically, the portion of the first conductive pattern CP1 that overlaps with the second conductive pattern CP2 in the plan view may define the first terminal of the first storage capacitor CST1, and the portion of the second conductive pattern CP2 that overlaps with the first conductive pattern CP1 in the plan view may define the second terminal of the first storage capacitor CST1.

[0082] The second active layer ATV2 can be disposed on the second conductive layer CL2. Specifically, the third insulating layer IL3 can be disposed on the second conductive layer CL2, and the second active layer ATV2 can be disposed on the third insulating layer IL3.

[0083] In an embodiment, the third insulating layer IL3 may comprise an inorganic insulating material. In an embodiment, the third insulating layer IL3 may cover the second conductive layer CL2. For example, the third insulating layer IL3 may have a substantially uniform thickness and cover the second conductive layer CL2. However, the third insulating layer IL3 according to embodiments of the present disclosure is not limited to this, and the third insulating layer IL3 may have a substantially flat upper surface and cover the second conductive layer CL2.

[0084] In an embodiment, the second active layer ATV2 may include polycrystalline silicon. Furthermore, in an embodiment, the second active layer ATV2 may include a material substantially the same as the first active layer ATV1. For example, the first active layer ATV1 may include polycrystalline silicon, and the second active layer ATV2 may also include polycrystalline silicon. However, the materials included in the second active layer ATV2 according to embodiments of this disclosure are not limited to this, and the second active layer ATV2 may include metal-oxide-semiconductor, amorphous silicon, etc.

[0085] The second active layer ATV2 may include a second active pattern ATP2. The second active pattern ATP2 may extend along a first direction DR1. The second active pattern ATP2 may be arranged along the first direction DR1 and the second direction DR2. For example, the second active pattern ATP2 included in a pixel PX and the second active pattern ATP2 included in another pixel adjacent to that pixel PX may be spaced apart from each other along the first direction DR1 or the second direction DR2.

[0086] The second active pattern ATP2 may include a fourth active region AR4, a fifth active region AR5, and a sixth active region AR6. The fourth active region AR4 and the fifth active region AR5 may be adjacent to each other in the first direction DR1. The fifth active region AR5 may be located between the fourth active region AR4 and the sixth active region AR6.

[0087] In the plan view, the second active pattern ATP2 may overlap with the first conductive pattern CP1. The second contact hole CNT2, which electrically connects the second active pattern ATP2 and the first conductive pattern CP1 to each other, may be defined between the second active pattern ATP2 and the first conductive pattern CP1.

[0088] For example, the second contact hole CNT2 can penetrate the second insulating layer IL2 and the third insulating layer IL3 in the thickness direction. Therefore, the fourth active region AR4 of the second active pattern ATP2 can partially contact the first conductive pattern CP1 through the second contact hole CNT2. In an embodiment, the portion of the first conductive pattern CP1 that contacts the fourth active region AR4 can be the second drain electrode DE2, which is the drain electrode of the second transistor TR2. However, this disclosure is not limited to this, and the portion of the first conductive pattern CP1 that contacts the fourth active region AR4 can be the source electrode of the second transistor TR2.

[0089] In the planar view, the second active pattern ATP2 can overlap with the second conductive pattern CP2. For example, in the planar view, the fourth active region AR4 of the second active pattern ATP2 can overlap with the second conductive pattern CP2. The second active pattern ATP2 and the second conductive pattern CP2 can overlap each other in the planar view to define the second storage capacitor CST2. Specifically, the portion of the second conductive pattern CP2 that overlaps with the second active pattern ATP2 in the planar view can define the first terminal of the second storage capacitor CST2, and the portion of the second active pattern ATP2 that overlaps with the second conductive pattern CP2 in the planar view can define the second terminal of the second storage capacitor CST2. The first conductive pattern CP1, the second conductive pattern CP2, and the second active pattern ATP2 can together define the storage capacitor CST. In other words, the storage capacitor CST can have a dual-capacitor structure in which two capacitors overlap in the planar view. Therefore, the storage capacity of the storage capacitor CST can be increased.

[0090] In one embodiment, the second active pattern ATP2 may partially overlap with the first active pattern ATP1 in a planar view. Therefore, the area of ​​the pixel PX, which includes the first transistor TR1 and the second transistor TR2, can be reduced.

[0091] The third conductive layer CL3 can be disposed on the second active layer ATV2. The fourth conductive layer CL4 can be disposed on the third conductive layer CL3. Specifically, the fourth insulating layer IL4 can be disposed on the second active layer ATV2, and the third conductive layer CL3 can be disposed on the fourth insulating layer IL4. Furthermore, the fifth insulating layer IL5 can be disposed on the third conductive layer CL3, and the fourth conductive layer CL4 can be disposed on the fifth insulating layer IL5.

[0092] In an embodiment, the fourth insulating layer IL4 and the fifth insulating layer IL5 may comprise inorganic insulating materials. In an embodiment, the fourth insulating layer IL4 may cover the second active layer ATV2. For example, the fourth insulating layer IL4 may have a substantially uniform thickness and cover the second active layer ATV2. However, the fourth insulating layer IL4 according to embodiments of this disclosure is not limited to this, and the fourth insulating layer IL4 may have a substantially flat upper surface and cover the second active layer ATV2.

[0093] In an embodiment, the fifth insulating layer IL5 may cover the third conductive layer CL3. For example, the fifth insulating layer IL5 may have a substantially uniform thickness and cover the third conductive layer CL3. However, the fifth insulating layer IL5 according to embodiments of the present disclosure may not be limited to this, and the fifth insulating layer IL5 may have a substantially flat upper surface and cover the third conductive layer CL3.

[0094] In this embodiment, each of the third conductive layer CL3 and the fourth conductive layer CL4 may include a conductive material. The third conductive layer CL3 may include a gate voltage line GL. A gate write signal GW may be applied to the gate voltage line GL. The gate voltage line GL may extend along the second direction DR2. Furthermore, the gate voltage line GL may be arranged along the first direction DR1. In a plan view, the gate voltage line GL may overlap with the fifth active region AR5 of the second active pattern ATP2. The portion of the gate voltage line GL that overlaps with the fifth active region AR5 in the plan view may be the second gate electrode GE2, which is the gate electrode of the second transistor TR2. Furthermore, the portion of the fifth active region AR5 that overlaps with the gate voltage line GL in the plan view may be the channel region of the second transistor TR2.

[0095] The fourth conductive layer CL4 may include a third conductive pattern CP3, a fourth conductive pattern CP4, and a horizontal power supply voltage line HVL. In a plan view, the third conductive pattern CP3, the fourth conductive pattern CP4, and the horizontal power supply voltage line HVL may be spaced apart from each other. For example, in a pixel PX, the third conductive pattern CP3 may be spaced apart from the horizontal power supply voltage line HVL in a first direction DR1. In a pixel PX, the fourth conductive pattern CP4 may be spaced apart from the horizontal power supply voltage line HVL in the first direction DR1. A first power supply voltage (e.g., ...) may be applied to the horizontal power supply voltage line HVL. Figure 2 The first power supply voltage is ELVDD).

[0096] A horizontal power supply voltage line HVL can extend along the second direction DR2. The horizontal power supply voltage line HVL can be arranged along the first direction DR1. In a plan view, the horizontal power supply voltage line HVL can overlap with the second conductive pattern CP2. A third contact hole CNT3 can be defined between the horizontal power supply voltage line HVL and the second conductive pattern CP2 to electrically connect the horizontal power supply voltage line HVL and the second conductive pattern CP2. Specifically, the third contact hole CNT3 can penetrate the third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5 in the thickness direction. Therefore, the horizontal power supply voltage line HVL can contact the second conductive pattern CP2 through the third contact hole CNT3. Therefore, the first power supply voltage ELVDD can be transmitted to the first active region AR1 along the horizontal power supply voltage line HVL and the second conductive pattern CP2.

[0097] In the plan view, the third conductive pattern CP3 may overlap with the third active region AR3 of the first active pattern ATP1. A fourth contact hole CNT4 may be defined between the third conductive pattern CP3 and the first active pattern ATP1 to electrically connect them. Specifically, the fourth contact hole CNT4 may penetrate the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5 in the thickness direction. Therefore, the third conductive pattern CP3 can contact the third active region AR3 of the first active pattern ATP1 through the fourth contact hole CNT4. The third conductive pattern CP3 may be the first drain electrode DE1, which is the drain electrode of the first transistor TR1. However, this disclosure is not limited to this, and the third conductive pattern CP3 may also be the source electrode of the first transistor TR1.

[0098] In one embodiment, in a plan view, the third conductive pattern CP3 and the gate voltage line GL may be adjacent to each other. In another embodiment, in a plan view, the third conductive pattern CP3 and the gate voltage line GL may overlap each other. In yet another embodiment, in a plan view, the third conductive pattern CP3 and the gate voltage line GL may be spaced apart from each other.

[0099] In the plan view, the fourth conductive pattern CP4 may overlap with the sixth active region AR6 of the second active pattern ATP2. A fifth contact hole CNT5 may be defined between the fourth conductive pattern CP4 and the second active pattern ATP2 to electrically connect the fourth conductive pattern CP4 and the second active pattern ATP2. Specifically, the fifth contact hole CNT5 may penetrate the fourth insulating layer IL4 and the fifth insulating layer IL5 in the thickness direction. Therefore, the fourth conductive pattern CP4 can contact the sixth active region AR6 of the second active pattern ATP2 through the fifth contact hole CNT5. The fourth conductive pattern CP4 may be the second source electrode SE2, which is the source electrode of the second transistor TR2. However, this disclosure is not limited to this, and the fourth conductive pattern CP4 may also be the drain electrode of the second transistor TR2.

[0100] In one embodiment, in a plan view, the fourth conductive pattern CP4 and the gate voltage line GL may be adjacent to each other. In another embodiment, in a plan view, the fourth conductive pattern CP4 and the gate voltage line GL may overlap each other. In yet another embodiment, in a plan view, the fourth conductive pattern CP4 and the gate voltage line GL may be spaced apart from each other.

[0101] In one embodiment, in a plan view, the fourth conductive pattern CP4 and the second conductive pattern CP2 may be adjacent to each other. In another embodiment, in a plan view, the fourth conductive pattern CP4 and the second conductive pattern CP2 may overlap each other. In yet another embodiment, in a plan view, the fourth conductive pattern CP4 and the second conductive pattern CP2 may be spaced apart from each other.

[0102] The fifth conductive layer CL5 can be disposed on the fourth conductive layer CL4. Specifically, the interlayer insulating layer ISL can be disposed on the fourth conductive layer CL4, and the fifth conductive layer CL5 can be disposed on the interlayer insulating layer ISL.

[0103] In an embodiment, the interlayer insulating layer (ISL) may comprise an inorganic insulating material. In an embodiment, the ISL may cover the fourth conductive layer (CL4). For example, the ISL may have a substantially uniform thickness and cover the fourth conductive layer (CL4). However, the ISL according to embodiments of this disclosure is not limited to this, and the ISL may have a substantially flat upper surface and cover the fourth conductive layer (CL4).

[0104] In this embodiment, the fifth conductive layer CL5 may include a conductive material. The data voltage line VDL may extend along a first direction DR1. The data voltage line VDL may be arranged along a second direction DR2. A data voltage (e.g., ...) may be applied to the data voltage line VDL. Figure 2 The data voltage VDL is defined. A sixth contact hole CNT6 can be positioned between the data voltage line VDL and the fourth conductive pattern CP4 to electrically connect the data voltage line VDL and the fourth conductive pattern CP4. Specifically, the sixth contact hole CNT6 can penetrate the interlayer insulating layer ISL in the thickness direction. Therefore, the data voltage line VDL can contact the fourth conductive pattern CP4 through the sixth contact hole CNT6.

[0105] In an embodiment, in a plan view, the fifth contact hole CNT5 and the sixth contact hole CNT6 may overlap each other. The data voltage line VDL can be electrically connected to the sixth active region AR6 of the second active pattern ATP2 through the fifth contact hole CNT5 and the sixth contact hole CNT6.

[0106] The sixth conductive layer CL6 can be disposed on the fifth conductive layer CL5. Specifically, the first through-hole insulating layer VIA1 can be disposed on the fifth conductive layer CL5, and the sixth conductive layer CL6 can be disposed on the first through-hole insulating layer VIA1.

[0107] In an embodiment, the first through-hole insulating layer VIA1 may include an organic insulating material, such as polyimide (PI). In an embodiment, the first through-hole insulating layer VIA1 may have a substantially flat upper surface and may cover a fifth conductive layer CL5.

[0108] In one embodiment, the sixth conductive layer CL6 may include a conductive material. The sixth conductive layer CL6 may include a fifth conductive pattern CP5. In one embodiment, in a planar view, the fifth conductive pattern CP5 may be spaced apart from the horizontal power supply voltage line HVL in a first direction DR1. In one embodiment, in a planar view, the fifth conductive pattern CP5 may be adjacent to the data voltage line VDL. In another embodiment, in a planar view, the fifth conductive pattern CP5 may overlap with the data voltage line VDL. In yet another embodiment, in a planar view, the fifth conductive pattern CP5 may be spaced apart from the data voltage line VDL.

[0109] In an embodiment, in a plan view, the fifth conductive pattern CP5 may overlap with the third conductive pattern CP3. A seventh contact hole CNT7 may be defined between the fifth conductive pattern CP5 and the third conductive pattern CP3 to electrically connect them to each other. Specifically, the seventh contact hole CNT7 may penetrate the interlayer insulating layer ISL and the first through-hole insulating layer VIA1 in the thickness direction. Therefore, the fifth conductive pattern CP5 can contact the third conductive pattern CP3 through the seventh contact hole CNT7.

[0110] In an embodiment, in a plan view, the seventh contact hole CNT7 may overlap with the fourth contact hole CNT4. In an embodiment, the first contact hole CNT1, the third contact hole CNT3, the fourth contact hole CNT4, and the seventh contact hole CNT7 may be arranged along a first direction DR1.

[0111] In this embodiment, the resolution of the display device DD can be from 1500 pixels per inch (ppi) to 2000 ppi. More preferably, the resolution of the display device DD can be from about 1750 ppi to about 2000 ppi. For example, the length of a pixel PX in the first direction DR1 can be from 12.7 micrometers (μm) to 16.93 μm. More preferably, the length of a pixel PX in the first direction DR1 can be from 14.56 μm to 16.93 μm. Furthermore, the length of a pixel PX in the second direction DR2 can be from 4.23 μm to 5.64 μm. More preferably, the length of a pixel PX in the second direction DR2 can be from 4.85 μm to 5.64 μm.

[0112] A second via insulating layer VIA2 may be disposed on the sixth conductive layer CL6. In an embodiment, the second via insulating layer VIA2 may comprise an organic insulating material, such as polyimide. The second via insulating layer VIA2 may have a substantially flat upper surface and may cover the sixth conductive layer CL6.

[0113] The pixel electrode PXE can be disposed on the second via insulating layer VIA2. The pixel electrode PXE can be electrically connected to the sixth conductive layer CL6 through a contact hole that penetrates the second via insulating layer VIA2 in the thickness direction. Specifically, the pixel electrode PXE can contact the fifth conductive pattern CP5 through the contact hole.

[0114] In embodiments, the pixel electrode (PXE) may include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. These can be used individually or in combination with each other.

[0115] A pixel defining layer (PDL) may be disposed on a pixel electrode (PXE). The PDL may partially cover the pixel electrode (PXE). Furthermore, contact holes exposing at least a portion of the pixel electrode (PXE) may be defined in the PDL. For example, the contact holes in the PDL may expose the central portion of the pixel electrode (PXE), and the PDL may cover the edges of the pixel electrode (PXE). The PDL may comprise an organic insulating material, such as polyimide.

[0116] The emissive layer (EML) can be disposed on the pixel electrode (PXE). The EML can be disposed on the pixel electrode (PXE) exposed by contact holes in the pixel limiting layer (PDL). The EML can include organic light-emitting materials, quantum dots, etc.

[0117] The common electrode (CME) can be disposed on the emissive layer (EML) and the pixel confinement layer (PDL). The common electrode (CME) can include materials such as aluminum, platinum (Pt), silver, magnesium (Mg), gold (Au), chromium (Cr), tungsten, and titanium (Ti). These can be used individually or in combination.

[0118] As described above, the display device DD may include a first active pattern ATP1 disposed on a substrate SUB and extending along a first direction DR1, a first conductive pattern CP1 disposed on the first active pattern ATP1 and partially overlapping the first active pattern ATP1 in a planar view, a second conductive pattern CP2 disposed on the first conductive pattern CP1 and extending along a second direction DR2, and a second active pattern ATP2 disposed on the second conductive pattern CP2 and defining a storage capacitor CST together with the first conductive pattern CP1 and the second conductive pattern CP2. A pixel PX included in the display device DD may include two transistors. Therefore, the number of pixels PX included in the display device DD increases, making it possible to implement the display device DD at a high resolution. Furthermore, since the display device DD includes sensing circuitry for external compensation (e.g., ...), ... Figure 1 The sensing circuit (SSC) can prevent transistor degradation.

[0119] Figure 18 and Figure 19 It is shown that it includes Figure 1 A plan view of another example of pixels in a display device.

[0120] In the plan view, refer to Figure 18 and Figure 19 The described display device DD, except for the location of the second contact hole CNT2' that electrically connects the second active pattern ATP2 and the first conductive pattern CP1 of the second active layer ATV2' to each other, is similar to the reference. Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 The described display device DD is essentially the same.

[0121] In the following text, omissions or simplifications may be made in conjunction with references. Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 The content described overlaps with the content described.

[0122] refer to Figure 18 and Figure 19 In the plan view, the first contact hole CNT1, the third contact hole CNT3, and the fourth contact hole CNT4 can be arranged along a first imaginary vertical line LN1. The first imaginary vertical line LN1 can be a straight line parallel to the first direction DR1. In other words, the first contact hole CNT1, the third contact hole CNT3, and the fourth contact hole CNT4 can be arranged as a line along the first direction DR1. Furthermore, since the seventh contact hole CNT7 overlaps with the fourth contact hole CNT4 in the plan view, the seventh contact hole CNT7 can also be arranged along the first imaginary vertical line LN1.

[0123] In this embodiment, in a plan view, the second contact hole CNT2' and the fifth contact hole CNT5 can be arranged along a second imaginary vertical line LN2. The second imaginary vertical line LN2 can be a straight line parallel to the first direction DR1. Furthermore, the second imaginary vertical line LN2 can be spaced apart from the first imaginary vertical line LN1 in a direction opposite to the second direction DR2. In other words, the second contact hole CNT2' and the fifth contact hole CNT5 can be arranged in a line along the first direction DR1. Furthermore, since the sixth contact hole CNT6 overlaps with the fifth contact hole CNT5 in the plan view, the sixth contact hole CNT6 can also be arranged along the second imaginary vertical line LN2 in the plan view.

[0124] Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 It is shown that it includes Figure 1 A plan view of yet another example of pixels in a display device.

[0125] refer to Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 The described display device DD, except for the vertical power supply voltage line VVL, is similar to the reference. Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 The described display device DD is essentially the same.

[0126] In the following text, omissions or simplifications may be made in conjunction with references. Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 The content described overlaps with the content described.

[0127] refer to Figures 20 to 24 The display device DD may include a fifth conductive layer CL5 comprising a vertical power supply voltage line VVL. The fifth conductive layer CL5 may include the vertical power supply voltage line VVL. The sixth conductive layer CL6 and the seventh conductive layer CL7 may respectively include a data voltage line VDL and a fifth conductive pattern CP5.

[0128] A first power supply voltage, ELVDD, can be applied to the vertical power supply voltage line VVL. The vertical power supply voltage line VVL can extend in a first direction DR1. Furthermore, the vertical power supply voltage line VVL can be arranged in a second direction DR2. In a plan view, the vertical power supply voltage line VVL can overlap with the horizontal power supply voltage line HVL. Additionally, in a plan view, the vertical power supply voltage line VVL can overlap with the data voltage line VDL.

[0129] The sixth conductive layer CL6 and the seventh conductive layer CL7 can be sequentially disposed on the fifth conductive layer CL5. The fifth conductive layer CL5 can be disposed on the fourth conductive layer CL4. For example, the vertical power supply voltage line VVL can be disposed on the horizontal power supply voltage line HVL. Furthermore, the vertical power supply voltage line VVL can be disposed below the data voltage line VDL. That is, in the cross-sectional view, the vertical power supply voltage line VVL can be disposed between the horizontal power supply voltage line HVL and the data voltage line VDL.

[0130] A power supply voltage contact hole CNT_P can be defined between the vertical power supply voltage line VVL and the horizontal power supply voltage line HVL to electrically connect them to each other. Specifically, the power supply voltage contact hole CNT_P can penetrate the insulating layer disposed between the fourth conductive layer CL4 and the fifth conductive layer CL5 in the thickness direction. Therefore, the vertical power supply voltage line VVL can contact the horizontal power supply voltage line HVL through the power supply voltage contact hole CNT_P. Therefore, the drive current generated by the first power supply voltage ELVDD applied to the vertical power supply voltage line VVL and the horizontal power supply voltage line HVL can be transmitted to the first active region AR1. In other words, the first power supply voltage ELVDD can be applied to the first power supply voltage line having a mesh structure formed by the vertical power supply voltage line VVL and the horizontal power supply voltage line HVL.

[0131] Figure 25 It is shown by Figure 1 The display device realizes the view of the electronic device.

[0132] refer to Figure 25 , Figure 1The display device DD can be applied to an electronic device ED for virtual reality (VR), including a head-mounted display. Virtual reality images can be viewed through the display device DD included in the electronic device ED. However, the electronic device ED according to embodiments of the present invention is not limited thereto, and the electronic device ED can have various forms besides head-mounted displays.

[0133] Electronic devices (EDs) may include processors, memory devices, storage devices, input / output devices, power supplies, and display devices. In such embodiments, the display device may be... Figure 1 The display device DD. In addition, the electronic device ED may also include multiple ports for communication with graphics cards, sound cards, memory cards, universal serial bus (USB) devices, and other electronic devices.

[0134] A processor can perform various computational functions or tasks. A processor can be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. A processor can be connected to other components via address buses, control buses, data buses, etc. Furthermore, a processor can be connected to expansion buses, such as the Peripheral Component Interconnect (PCI) bus.

[0135] The memory device can store data for the operation of the electronic device ED. In embodiments, for example, the memory device may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, or the like, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, or the like.

[0136] Storage devices may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, CD-ROM devices, or the like. I / O devices may include input devices such as a keyboard, keypad, mouse, touchpad, touchscreen, or the like, and output devices such as a printer, speaker, or the like. In some embodiments, a display device DD may be included in the I / O devices. A power supply may provide power for the operation of the electronic device ED. The display device DD may be connected to other components via a bus or other communication link.

[0137] The display device DD according to the embodiment can be applied to display devices including computers, laptops, mobile phones, smartphones, smart tablets, PMPs, PDAs, MP3 players, etc.

[0138] Although methods and systems according to embodiments have been described with reference to the accompanying drawings, the embodiments shown are examples and can be modified and altered by those skilled in the art without departing from the spirit of the technology described in the claims.

Claims

1. A display device, comprising: Substrate; A first active pattern is disposed on the substrate and extends in a first direction; A first conductive pattern is disposed on the first active pattern and partially overlaps with the first active pattern in a planar view; The second conductive pattern is disposed on the first conductive pattern and extends in a second direction intersecting the first direction; as well as A second active pattern is disposed on the second conductive pattern and together with the first conductive pattern and the second conductive pattern defines a storage capacitor.

2. The display device according to claim 1, wherein, The storage capacitor includes: A first storage capacitor is defined by overlapping portions of the first conductive pattern and portions of the second conductive pattern; and The second storage capacitor is defined by overlapping a portion of the second conductive pattern and a portion of the second active pattern.

3. The display device according to claim 1, further comprising: A gate voltage line is disposed on the second active pattern, extends in the second direction, and is configured to be applied with a gate write signal; A horizontal power supply voltage line is disposed on the gate voltage line and extends in the second direction; A third conductive pattern is disposed on the gate voltage line and spaced apart from the horizontal power supply voltage line in the first direction; as well as A fourth conductive pattern is disposed on the gate voltage line and spaced apart from the third conductive pattern and the horizontal power supply voltage line.

4. The display device according to claim 3, wherein, The second conductive pattern is electrically connected to the first active pattern, and The third conductive pattern is spaced apart from the second conductive pattern in the first direction in the plan view and is electrically connected to the first active pattern.

5. The display device according to claim 4, wherein, The first active pattern, the first conductive pattern, the second conductive pattern, and the third conductive pattern together define a driving transistor.

6. The display device according to claim 5, wherein, The second conductive pattern is the source electrode of the driving transistor. The third conductive pattern is the drain electrode of the driving transistor, and The portion of the first conductive pattern that overlaps with the first active pattern in the planar view is the gate electrode of the driving transistor.

7. The display device according to claim 4, wherein, The first conductive pattern is electrically connected to the second active pattern, and The fourth conductive pattern is spaced apart from the first conductive pattern in the first direction in the plan view and is electrically connected to the second active pattern.

8. The display device according to claim 7, wherein, The second active pattern, the gate voltage line, the first conductive pattern, and the fourth conductive pattern together define the switching transistor.

9. The display device according to claim 8, wherein, The first conductive pattern is the drain electrode of the switching transistor. The fourth conductive pattern is the source electrode of the switching transistor, and The portion of the gate voltage line that overlaps with the second active pattern in the planar view is the gate electrode of the switching transistor.

10. The display device according to claim 7, wherein, The horizontal power supply voltage line is configured to be applied with a power supply voltage, and The horizontal power supply voltage line is electrically connected to the second conductive pattern.

11. The display device according to claim 10, wherein, The second conductive pattern and the first active pattern are connected through the first contact hole. The second active pattern and the first conductive pattern are connected through a second contact hole. The horizontal power supply voltage line and the second conductive pattern are connected through a third contact hole. The third conductive pattern and the first active pattern are connected through a fourth contact hole, and The fourth conductive pattern and the second active pattern are connected through a fifth contact hole.

12. The display device according to claim 11, wherein, In the plan view, the first contact hole, the third contact hole, and the fourth contact hole are arranged along a first imaginary vertical line parallel to the first direction, and In the plan view, the second contact hole and the fifth contact hole are arranged along a second imaginary vertical line that is parallel to the first direction and spaced apart from the first imaginary vertical line.

13. The display device according to claim 11, further comprising: A data voltage line is provided on the horizontal power supply voltage line and extends in the first direction; as well as A fifth conductive pattern is disposed on the data voltage line and is spaced apart from the horizontal power supply voltage line in the first direction in the plan view.

14. The display device according to claim 13, wherein, The data voltage line is connected to the fourth conductive pattern through the sixth contact hole, and In the plan view, the sixth contact hole overlaps with the fifth contact hole.

15. The display device according to claim 13, wherein, The fifth conductive pattern is electrically connected to the third conductive pattern through the seventh contact hole, and In the plan view, the seventh contact hole overlaps with the fourth contact hole.

16. The display device according to claim 13, wherein, In the plan view, the fifth conductive pattern and the data voltage line are adjacent to each other.

17. The display device according to claim 13, further comprising: A vertical power supply voltage line is positioned between the horizontal power supply voltage line and the data voltage line, and extends in the first direction.

18. A display device, comprising: Substrate; A first active pattern is disposed on the substrate and extends in a first direction; A first conductive pattern is disposed on the first active pattern and partially overlaps with the first active pattern in a planar view; The second conductive pattern is disposed on the first conductive pattern, extends in a second direction intersecting the first direction, and partially contacts the first active pattern through the first contact hole; A second active pattern is disposed on the second conductive pattern, overlapping a portion of each of the first conductive pattern and the second conductive pattern in the plan view, and contacting a portion of the first conductive pattern through a second contact hole; A gate voltage line is disposed on the second active pattern, extends in the second direction, and is configured to be applied with a gate write signal; A horizontal power supply voltage line is disposed on the gate voltage line, configured to be supplied with a power supply voltage, and in contact with a portion of the second conductive pattern through a third contact hole; The third conductive pattern is disposed in the same layer as the horizontal power supply voltage line and is in partial contact with the first active pattern through the fourth contact hole; as well as The fourth conductive pattern is disposed in the same layer as the horizontal power supply voltage line and is in partial contact with the second active pattern through the fifth contact hole.

19. The display device according to claim 18, wherein, In the plan view, the first contact hole, the third contact hole, and the fourth contact hole are arranged along a first imaginary vertical line parallel to the first direction, and In the plan view, the second contact hole and the fifth contact hole are arranged along a second imaginary vertical line that is parallel to the first direction and spaced apart from the first imaginary vertical line.

20. Electronic devices, including: The display device is configured to display images; as well as The processor is configured to drive the display device. The display device includes: Substrate; A first active pattern is disposed on the substrate and extends in a first direction; A first conductive pattern is disposed on the first active pattern and partially overlaps with the first active pattern in a planar view; A second conductive pattern is disposed on the first conductive pattern and extends in a second direction intersecting the first direction; and A second active pattern is disposed on the second conductive pattern and together with the first conductive pattern and the second conductive pattern defines a storage capacitor.

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