Display panel and display device

Abstract

The invention provides a display panel and a display device. According to the invention, the output module is provided with the second shading part, the second shading part and the constant-voltage signal line are arranged in a non-overlapping manner, one part of the plurality of first through holes in the first shading part is overlapped with the second shading part, and the other part of the plurality of first through holes is overlapped with the constant-voltage signal line. Therefore, external light entering the output module through the first through hole is shielded by the constant-voltage signal line and the second shading part, and the technical problem that the device performance of the oxidation transistor is affected is avoided under the condition that a release channel of the organic flat layer is met.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] The gate drive circuit of an OLED (Organic Light-Emitting Diode) display panel includes an output transistor. When it is made of oxide semiconductor material, it needs to be equipped with a light-shielding structure to avoid the influence of light on the device effect of oxide semiconductor.

[0003] In related technologies, a light-shielding structure covering the oxide semiconductor is usually set using the material of the anode layer. Since an organic planarization layer is set below the anode layer, a certain number of holes need to be set on the light-shielding structure to provide a channel for the release of gas in the organic planarization layer. Light can enter the oxide transistor through the holes, which will damage the device performance of the oxide transistor. Summary of the Invention

[0004] This application provides a display panel and display device to solve the technical problem of impaired device performance of oxide transistors in existing gate drive circuits.

[0005] This application provides a display panel, which includes a substrate and a gate driving circuit disposed on one side of the substrate. The gate driving circuit includes a plurality of first gate circuits; wherein, the first gate circuit includes:

[0006] Signal generation module;

[0007] An output module is electrically connected to the signal generation module, and the output module includes a first type of oxide transistor;

[0008] A clock signal line is electrically connected to the output module and is not overlapped with the output module.

[0009] A constant voltage signal line is electrically connected to the output module and has an overlapping portion with the output module;

[0010] A first light-shielding portion is disposed on the side of the output module away from the substrate, and the first light-shielding portion has a plurality of first through holes; and

[0011] The second light-shielding part is disposed between the output module and the first light-shielding part. The second light-shielding part and the output module have an overlapping portion, and the second light-shielding part and the constant voltage signal line are not overlapped.

[0012] Among them, a portion of the plurality of first through holes overlaps with the second light-shielding portion, and another portion of the plurality of first through holes overlaps with the constant voltage signal line.

[0013] Meanwhile, embodiments of this application provide a display device, which includes the display panel as described above.

[0014] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0017] Figure 1 This is a first structural diagram of the display panel of this application.

[0018] Figure 2 This is a structural diagram of the pixel driving circuit in the display panel of this application.

[0019] Figure 3 This is a second structural diagram of the display panel in this application.

[0020] Figure 4 This is a structural diagram of the gate driving circuit in the display panel of this application.

[0021] Figure 5 This is a diagram of the film structure in the display panel of this application.

[0022] Figure 6 This is a diagram showing the film stacking of the first gate circuit in the first gate circuit of this application.

[0023] Figure 7 This is a film diagram of the first active layer in the first gate circuit of this application.

[0024] Figure 8 This is a film diagram of the second active layer in the first gate circuit of this application.

[0025] Figure 9 This is a stacked diagram of the first active layer, the second active layer, and the first gate layer in the first gate circuit of this application.

[0026] Figure 10This is a film layer diagram of the third gate layer in the first gate circuit of this application.

[0027] Figure 11 This is a film layer diagram of the fourth gate layer in the first gate circuit of this application.

[0028] Figure 12 This is a stacked diagram of the first active layer, second active layer, first gate layer, third gate layer and fourth gate layer in the first gate circuit of this application.

[0029] Figure 13 This is a film diagram of the first source-drain layer in the first gate circuit of this application.

[0030] Figure 14 This is a stacked diagram of the first active layer, second active layer, first gate layer, third gate layer, fourth gate layer and first source / drain layer in the first gate circuit of this application.

[0031] Figure 15 This is a first type of film layer diagram of the second source / drain layer in the first gate circuit of this application.

[0032] Figure 16 This is a first type of film layer stack diagram of the first active layer, second active layer, first gate layer, third gate layer, fourth gate layer, first source-drain layer and second source-drain layer in the first gate circuit of this application.

[0033] Figure 17 This is a first type of film layer diagram of the anode layer in the first gate circuit of this application.

[0034] Figure 18 This is a first type of film layer stack diagram of the first active layer, second active layer, first gate layer, third gate layer, fourth gate layer, first source-drain layer, second source-drain layer and anode layer in the first gate circuit of this application.

[0035] Figure 19 This is a second type of film layer diagram of the second source-drain layer in the first gate circuit of this application.

[0036] Figure 20 This is a third type of film layer diagram of the second source / drain layer in the first gate circuit of this application.

[0037] Figure 21 This is a fourth type of film layer diagram of the second source-drain layer in the first gate circuit of this application.

[0038] Figure 22 This is a second type of film layer diagram of the anode layer in the first gate circuit of this application.

[0039] Figure 23This is a second type of film layer stack diagram of the first active layer, second active layer, first gate layer, third gate layer, fourth gate layer, first source-drain layer, second source-drain layer and anode layer in the first gate circuit of this application. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0041] Please see Figures 1 to 23 This application proposes a display panel 100, which includes a substrate 110 and a gate driving circuit 300 disposed on one side of the substrate 110. The gate driving circuit 300 includes a plurality of first gate circuits 310.

[0042] In this embodiment, the first gate circuit 310 includes a signal generation module 310a and an output module 310b. The output module 310b is electrically connected to the signal generation module 310a, and the output module 310b includes a first type of oxide transistor.

[0043] In this embodiment, the first gate circuit 310 further includes a clock signal line and a constant voltage signal line. The clock signal line is electrically connected to the output module 310b, and the clock signal line and the output module 310b are not overlapped. The constant voltage signal line is electrically connected to the output module 310b, and the constant voltage signal line and the output module 310b have an overlapping portion.

[0044] In this embodiment, the first gate circuit 310 further includes a first light-shielding portion 510 disposed on the side of the output module 310b away from the substrate 110, and the first light-shielding portion 510 is provided with a plurality of first through holes HL1.

[0045] In this embodiment, the first gate circuit 310 further includes a second light-shielding part 520 disposed between the output module 310b and the first light-shielding part 510. The second light-shielding part 520 and the output module 310b have an overlapping portion, and the second light-shielding part 520 and the constant voltage signal line are not overlapped.

[0046] In this embodiment, a portion of the plurality of first through holes HL1 overlaps with the second light-shielding portion 520, and another portion of the plurality of first through holes HL1 overlaps with the constant voltage signal line.

[0047] In related technologies, when the output transistor in the gate drive circuit 300 is made of oxide semiconductor material, only one constant voltage signal line electrically connected to the transistor is typically provided on the output transistor. To avoid light affecting the device effect of the oxide semiconductor, a light-shielding structure covering the oxide semiconductor can be provided using the material of the anode layer 141. Since an organic planarization layer is provided below the anode layer 141, a certain number of perforations need to be provided on the light-shielding structure to provide gas release channels in the organic planarization layer. However, a single constant voltage signal line cannot block all the perforations, causing light to enter the oxide semiconductor through some of the perforations. The first light-shielding part 520 is provided on the output module 310b. The second light-shielding part 520 and the constant voltage signal line are not overlapped. A portion of the plurality of first through holes HL1 on the first light-shielding part 510 overlaps with the second light-shielding part 520, and another portion of the plurality of first through holes HL1 overlaps with the constant voltage signal line. This allows external light entering the output module 310b through the first through holes HL1 to be blocked by the constant voltage signal line and the second light-shielding part 520. While satisfying the release channel of the organic planarization layer, the technical problem of the device performance being affected by the oxide transistor is avoided.

[0048] It should be noted that the material of the first light-shielding part 510 in this application can be made from the material of the anode layer 141.

[0049] The technical solution of this application will now be described in conjunction with specific embodiments.

[0050] Please see Figure 1 The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA has multiple rows of sub-pixels PL. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains multiple display units that implement its display functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the display units within the display area AA in displaying information.

[0051] Please see Figure 1 A bonding terminal 400 is provided on the lower side of the display area AA. The bonding terminal 400 can be connected to an external circuit and transmits the signal input from the external circuit to the data trace, thereby driving the display panel 100 to display the image. For example, the bonding terminal 400 can be bonded to a chip or a flip-chip film to provide power and drive signals to the display panel 100.

[0052] In this embodiment, multiple light-emitting devices (LEDs) and pixel driving circuits (PCs) for driving the LEDs can be arrayed within the display area AA. The pixel driving circuit PC can be aTbC, where a is greater than or equal to 2 and b is greater than or equal to 1. The following description uses a 6T1C pixel driving circuit PC as an example.

[0053] Please see Figure 2 The pixel driving circuit PC may include a switching transistor T2A, a driving transistor T1A, a compensation transistor T3A, a reset transistor T4A, a first light-emitting transistor T5A, a second light-emitting transistor T6A, and a storage capacitor Cst.

[0054] Please see Figure 2 The first electrode of switching transistor T2A is connected to the data signal line Data, and the second electrode of switching transistor T2A is connected to the control node Ba. The gate of switching transistor T2A receives the switching control signal Nscan1. The first electrode of driving transistor T1A is connected to the control node Aa, the second electrode of driving transistor T1A is connected to the control node Ba, and the gate of driving transistor T1A is connected to the control node Qa. The first electrode of compensation transistor T3A is connected to the control node Aa, the second electrode of compensation transistor T3A is connected to the control node Qa, and the gate of compensation transistor T3A receives the compensation control signal Nscan2. The first electrode of reset transistor T4A receives the reset signal Vi, and the second electrode of reset transistor T4A is connected to the control node Ca. The gate of reset transistor T4A receives the second light-emitting control signal EM2; the first electrode of the first light-emitting transistor T5A is connected to the high-level source VDD, the second electrode of the first light-emitting transistor T5A is connected to the control node Aa, and the gate of the first light-emitting transistor T5A receives the first light-emitting control signal EM1; the first electrode of the second light-emitting transistor T6A is connected to the control node Ba, the second electrode of the second light-emitting transistor T6A is connected to the control node Ca, and the gate of the second light-emitting transistor T6A receives the second light-emitting control signal EM2; one end of the storage capacitor Cst is connected to the control node Qa, and the other end of the storage capacitor Cst is connected to the control node Ca; the anode of the light-emitting device LED is connected to the control node Ca, and the cathode of the light-emitting device LED is connected to the low-level source VSS.

[0055] In this embodiment, the high-level source VDD is used to provide a constant high voltage to the pixel driving circuit PC, and the low-level source VSS is used to provide a constant low voltage to the pixel driving circuit PC.

[0056] In this embodiment, the switching transistor T2A, driving transistor T1A, compensation transistor T3A, and reset transistor T4A can be either P-type or N-type transistors, and the first light-emitting transistor T5A and the second light-emitting transistor T6A can be either P-type or N-type transistors. For example, in this application, the switching transistor T2A, driving transistor T1A, compensation transistor T3A, and reset transistor T4A are N-type transistors, and the first light-emitting transistor T5A and the second light-emitting transistor T6A are P-type transistors. That is, the effective level of the switching transistor T2A, driving transistor T1A, compensation transistor T3A, and reset transistor T4A is high, and the effective level of the first light-emitting transistor T5A and the second light-emitting transistor T6A is low.

[0057] In this embodiment, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain.

[0058] In this embodiment, the first light-emitting transistor T5A and the second light-emitting transistor T6A can be composed of at least two transistors connected in series to reduce the leakage current of the first light-emitting transistor T5A and the second light-emitting transistor T6A.

[0059] In this embodiment, the second direction Y is parallel to the scan line of the display panel 100, and the angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°.

[0060] Please see Figure 3 The gate driving circuit 300 is disposed within the non-display area NA, and the gate driving circuit 300 can also be disposed on both sides of the display area AA; the gate driving circuit 300 may include N cascaded gate driving units 300a, and the multiple gate driving units 300a can be arranged along the first direction X. The structure of the gate driving unit 300a can be various, for example in... Figure 3 In the structure, the gate driving unit 300a may include a plurality of first gate circuits 310 arranged and cascaded along the first direction X, a plurality of second gate circuits 320 arranged and cascaded along the first direction X, and a plurality of third gate circuits 330 arranged and cascaded along the first direction X.

[0061] Please see Figure 3 The first gate circuit 310 is located on one side of the display area AA. The first gate circuit 310 is used to output a switch control signal Nscan1 to a row of sub-pixels PL, that is, the row of pixel driving circuit PC needs a first gate circuit 310.

[0062] Please see Figure 3The second gate circuit 320 is located on the side of the first gate circuit 310 away from the display area AA. The second gate circuit 320 is used to output the compensation control signal Nscan2 to the two rows of sub-pixels PL, that is, the two rows of pixel driving circuits PC need one stage of the second gate circuit 320.

[0063] Please see Figure 3 The third gate circuit 330 is located on the side of the second gate circuit 320 away from the display area AA. The third gate circuit 330 is used to output the first light emission control signal EM1 or the second light emission control signal EM2 to the two rows of sub-pixels PL. That is, the two rows of pixel driving circuits PC require one third gate circuit 330. For example, the third gate circuit 330 located on one side of the display area AA is used to output the first light emission control signal EM1, and the third gate circuit 330 located on the other side of the display area AA is used to output the second light emission control signal EM2.

[0064] It should be noted that the reset signal Vi is a constant voltage, which does not require the corresponding gate drive circuit 300 to control it, and can be directly connected to the corresponding constant voltage source.

[0065] It should be noted that the positions of the first gate circuit 310, the second gate circuit 320, and the third gate circuit 330 in this application can be changed. For example, the second gate circuit 320, the third gate circuit 330, and the first gate circuit 310 can be arranged along the second direction Y, the third gate circuit 330, the second gate circuit 320, and the first gate circuit 310 can be arranged along the second direction Y, and the third gate circuit 330, the first gate circuit 310, and the second gate circuit 320 can be arranged along the second direction Y.

[0066] In this embodiment, the first gate circuit 310, the second gate circuit 320, and the third gate circuit 330 of this application can be mTnC gate circuits. In the following embodiment, the structure of the gate driving unit 300a of this application will be described using an 8T1C first gate circuit as an example.

[0067] Please see Figure 4 The first gate circuit 310 includes a signal generation module 310a and an output module 310b. The signal generation module 310a may include a pull-up control module 311, a pull-down control module 313 and a voltage stabilization module 315. The output module 310b may include a pull-up module 312 and a pull-down module 314. The clock signal line is connected to the pull-up module 312 and the constant voltage signal line is connected to the pull-down module 314.

[0068] Please see Figure 4 The control terminal of the pull-up control module 311 is electrically connected to the corresponding first-type clock line XCK for transmitting pull-up control signals, and the output terminal of the pull-up control module 311 is electrically connected to the corresponding pull-up node Q.

[0069] Please see Figure 4 The input terminal of the pull-up module 312 is electrically connected to the corresponding clock signal line (hereinafter referred to as the second type clock line CK) for transmitting the pull-up signal. The control terminal of the pull-up module 312 is electrically connected to the corresponding pull-up node Q. The output terminal of the pull-up module 312 is electrically connected to the output terminal OUT of the first gate circuit 310, and the output terminal OUT of the first gate circuit 310 is connected to the gate of the switching transistor T2A, which is equivalent to the output module 310b and the gate of the switching transistor T2A being connected.

[0070] Please see Figure 4 The control terminal of the pull-down control module 313 is electrically connected to the output terminal of the pull-up control module 311 (i.e., the pre-pull-up node K), and the output terminal of the pull-down control module 313 is electrically connected to the corresponding pull-down node P.

[0071] Please see Figure 4 The input terminal of the pull-down module 314 is electrically connected to the corresponding constant voltage signal line for transmitting the pull-down signal. The constant voltage signal line can be, but is not limited to, the low potential line VGL. The control terminal of the pull-down module 314 is electrically connected to the corresponding pull-down node P. The output terminal of the pull-down module 314 is electrically connected to the output terminal OUT of the first gate circuit 310.

[0072] Please see Figure 4 The control terminal of the voltage stabilization module 315 is electrically connected to the corresponding pull-down node P, and the output terminal of the voltage stabilization module 315 is electrically connected to the corresponding pull-up node Q.

[0073] The following is about Figure 4 The specific structure of the transistor is described.

[0074] Please see Figure 4 The pull-up control module 311 includes a first transistor T1. The drain of the first transistor T1 is connected to the initial signal line or the output terminal OUT of the previous stage first gate circuit 310, and the source of the first transistor T1 is connected to the pre-pull-up node K. The first transistor T1 can be a single-gate or dual-gate structure, for example... Figure 4 The gate of the first transistor T1 includes a first gate of the first transistor T1 and a second gate of the first transistor T1, and both gates of the first transistor T1 are connected to the first type of clock line XCK.

[0075] Please see Figure 4 The pull-up module 312 includes a fifth transistor T5 and a first capacitor C1. The drain of the fifth transistor T5 is connected to a second type of signal line, and the source of the fifth transistor T5 is connected to the output terminal OUT of the first gate circuit 310. The fifth transistor T5 can be a single-gate or dual-gate structure, for example... Figure 4The gate of the fifth transistor T5 includes the first gate of the fifth transistor T5 and the second gate of the first transistor T1. Both gates of the fifth transistor T5 are connected to the pull-up node Q. The first plate C1a of the first capacitor C1 is connected to the pull-up node Q, and the second plate C1b of the first capacitor C1 is connected to the output terminal OUT of the first gate circuit 310.

[0076] Please see Figure 4 The pull-down control module 313 includes a second transistor T2 and a third transistor T3. The gate of the second transistor T2 is connected to the pre-pull-up node K, the drain of the second transistor T2 is connected to the high-level source VGH, and the source of the second transistor T2 is connected to the pull-down node P. The drain of the third transistor T3 is connected to the low-level source VGL, and the source of the third transistor T3 is connected to the pull-down node P. The third transistor T3 can be a single-gate or dual-gate structure, for example... Figure 4 The gate of the third transistor T3 includes the first gate and the second gate of the third transistor T3, and both gates of the third transistor T3 can be connected to the pre-pull-up node K.

[0077] Please see Figure 4 The pull-down module 314 includes a sixth transistor T6. The drain of the sixth transistor T6 is connected to a low-level source VGL, and the source of the sixth transistor T6 is connected to the output terminal OUT of the first gate circuit 310. The sixth transistor T6 can be a single-gate or dual-gate structure, for example... Figure 4 The gate of the sixth transistor T6 includes a first gate and a second gate of the sixth transistor T6. The first gate of the sixth transistor T6 is connected to the pull-down node P, and the second gate of the sixth transistor T6 is connected to the low-level source VGL.

[0078] Please see Figure 4 The voltage stabilization module 315 includes a fourth transistor T4, a seventh transistor T7, and an eighth transistor T8. The drain of the fourth transistor T4 is connected to a high-level source VGH, the source of the fourth transistor T4 is connected to a pre-pull-up node K, and the gate of the fourth transistor T4 is connected to a pull-down node P. The gate of the seventh transistor T7 is connected to a high-level source VGH, the drain of the seventh transistor T7 is connected to a pre-pull-up node K, and the source of the seventh transistor T7 is connected to a pull-up node Q. The drain of the eighth transistor T8 is connected to a low-level source VGL, and the source of the eighth transistor T8 is connected to a pull-up node Q. The eighth transistor T8 can be a single-gate or dual-gate structure, for example... Figure 4 The gate of the eighth transistor T8 includes a first gate and a second gate of the eighth transistor T8. The first gate of the eighth transistor T8 is connected to the pull-down node P, and the second gate of the eighth transistor T8 is connected to the low-level source VGL.

[0079] Specifically, the transistor types of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be either silicon semiconductor transistors or oxide semiconductor transistors. For example, the second transistor T2 and the fourth transistor T4 can be silicon semiconductor transistors, the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be oxide semiconductor transistors, the fifth transistor T5 and the sixth transistor T6 can be type 1 oxide transistors, and the first transistor T1, the third transistor T3, the seventh transistor T7, and the eighth transistor T8 can be type 2 oxide transistors.

[0080] Specifically, oxide semiconductor transistors can be metal oxide transistors, and silicon semiconductor transistors can be low-temperature polycrystalline silicon transistors.

[0081] In this embodiment, the first type of clock line XCK and the second type of clock line CK can be one of the following: the first control clock line NCK1, the second control clock line NCK2, the third control clock line NCK3, and the fourth control clock line NCK4.

[0082] For example, in the (n-3)th stage first gate circuit 310, the first type of clock line XCK is the fourth control clock line NCK4, and the second type of clock line CK is the first control clock line NCK1; in the (n-2)th stage first gate circuit 310, the first type of clock line XCK is the first control clock line NCK1, and the second type of clock line CK is the second control clock line NCK2; in the (n-1)th stage first gate circuit 310, the first type of clock line XCK is the second control clock line NCK2, and the second type of clock line CK is the third control clock line NCK3; in the nth stage first gate circuit 310, the first type of clock line XCK is the third control clock line NCK3, and the second type of clock line CK is the fourth control clock line NCK4.

[0083] It should be noted that some transistors in this application adopt a single-gate design and some adopt a dual-gate design. For transistors with a single-gate design, the gate is its only gate. For transistors with a dual-gate design, the gate refers to the bottom gate and the top gate. For example, the first transistor T1 is a dual-gate design. The gate of the first transistor T1 refers to the first gate and the second gate of the first transistor T1. Similarly, the description of the gate of other transistors can be found in the description of the transistors above, and will not be repeated in the following embodiments.

[0084] The following is about Figure 4 The structure of the film layer of the display panel 100 of this application is described.

[0085] Please see Figure 5The display panel 100 may have a substrate 110 and an array driving layer 120 disposed on the substrate 110 in the display area AA and the non-display area NA. In the display area AA, the display panel 100 may also have a pixel definition layer disposed on the array driving layer 120, a light-emitting device layer disposed on the same layer as the pixel definition layer, and an encapsulation layer disposed on the pixel definition layer. The following mainly describes the film layer structure in the non-display area NA.

[0086] In this embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent substrate 110 is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque substrate 110 and a transparent substrate 110 can be used.

[0087] In this embodiment, the substrate 110 is used to support the various film layers disposed on the substrate 110. The substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials used for flexible substrates include, but are not limited to, polyimide (PI).

[0088] In this embodiment, the substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 stacked together. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0089] In this embodiment, the first flexible substrate 111 is formed by coating a polymeric material onto a support substrate (not shown) and then curing the polymeric material. The second flexible substrate 113 is formed by coating the first flexible substrate 111 with the same material and then curing the material. The second flexible substrate 113 is formed by the same method as that used to form the first flexible substrate 111. Each of the first flexible substrate 111 and the second flexible substrate 113 may be formed to have a thickness of about 8 μm to about 12 μm. Furthermore, when the substrate 110 is formed from the first flexible substrate 111 and the second flexible substrate 113, pinholes, cracks, etc., formed during the manufacturing of the first flexible substrate 111 are covered by the second flexible substrate 113, thereby removing the aforementioned defects.

[0090] Please see Figure 5The array driving layer 120 may include multiple thin-film transistors (TFTs). These TFTs may be etch-block type, back-channel etch type, or classified according to the position of the gate and active layer as bottom-gate TFTs, top-gate TFTs, etc., or according to their performance as N-type TFTs, P-type TFTs; among them, Figure 5 The thin-film transistor in the text does not represent Figure 2 The structural diagram of any transistor is merely a schematic diagram of each film layer of the display panel 100 of this application.

[0091] Please see Figure 5 The array driving layer 120 may include a light-shielding layer 121 disposed on the substrate 110, a buffer layer 122 disposed on the light-shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, a first inter-insulator 128 disposed on the second gate layer 127, a second active layer 129 disposed on the first inter-insulator 128, and a third gate insulating layer 130 disposed on the second active layer 129. A third gate layer 131 disposed on the third gate insulating layer 130, a fourth gate insulating layer 132 disposed on the third gate insulating layer 131, a fourth gate layer 133 disposed on the fourth gate insulating layer 132, a second inter-insulating layer 134 disposed on the fourth gate layer 133, a first source-drain layer 135 disposed on the second inter-insulating layer 134, a first planarization layer 136 disposed on the first source-drain layer 135, a second source-drain layer 137 disposed on the first planarization layer 136, a second planarization layer 138 disposed on the second source-drain layer 137, a third source-drain layer 139 disposed on the second planarization layer 138, and a third planarization layer 140 disposed on the third source-drain layer 139.

[0092] Please see Figure 5 The light-shielding layer 121 is disposed on or inside the second barrier layer 114. The light-shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light-shielding layer 121 can be a black light-shielding material, such as black light-shielding metal or black organic material.

[0093] Please see Figure 5 The buffer layer 122 is disposed on the light-shielding layer 121. The material of the buffer layer 122 may be a compound composed of nitrogen, silicon and oxygen elements, such as a single layer of silicon oxide film or a stacked structure of silicon oxide and silicon nitride.

[0094] Please see Figure 5The first active layer 123 is disposed on the buffer layer 122, and the second active layer 129 can be disposed on the first insulating layer 128. The materials of the first active layer 123 and the second active layer 129 can be one of silicon semiconductor transistors or oxide semiconductor transistors, such as metal oxide semiconductor, amorphous silicon or low temperature polycrystalline silicon. In this application, the material of the first active layer 123 can be low temperature polycrystalline silicon, and the material of the second active layer 129 can be indium gallium zinc oxide semiconductor.

[0095] Please see Figure 5 The first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 130, the fourth gate insulating layer 132, the first interlayer insulating layer 128, and the second interlayer insulating layer 134 are respectively disposed on the corresponding metal layer or semiconductor layer, so that the metal layer or semiconductor layer of different layers is disposed separately; the materials of the first gate insulating layer 124, the second gate insulating layer 126, the first interlayer insulating layer 128, the third gate insulating layer 130, the fourth gate insulating layer 132, and the second interlayer insulating layer 134 can be inorganic materials composed of silicon oxynitride or organic materials with planarity, or stacked structures such as silicon oxide, silicon nitride, and aluminum oxide.

[0096] Please see Figure 5 The first gate layer 125, the second gate layer 127, the third gate layer 131 and the fourth gate layer 133 are respectively disposed on the corresponding insulating layer. The materials of the first gate layer 125, the second gate layer 127, the third gate layer 131 and the fourth gate layer 133 may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu or single-layer or multi-layer metal structures composed of at least two of the above metals. For example, the materials may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0097] Please see Figure 5 The materials of the first source-drain layer 135, the second source-drain layer 137, and the third source-drain layer 139 may include metals such as Cr, W, Ti, Ta, Mo, Al, and Cu, or single-layer or multi-layer metal structures composed of at least two of the above metals. For example, the materials may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0098] Please see Figure 5The first planarization layer 136, the second planarization layer 138, and the third planarization layer 140 can be laid as a whole or only in the display area AA and part of the non-display area NA to ensure the flatness of the film layer of the array driving layer 120. The materials of the first planarization layer 136, the second planarization layer 138, and the third planarization layer 140 can be inorganic materials composed of silicon oxynitride or organic materials with flatness, such as flexible materials such as polytetrafluoroethylene.

[0099] It should be noted that, Figure 5 The document lists the structures of two oxide transistors and one silicon semiconductor transistor. Figure 5 The three types of transistors shown are only schematic diagrams of the film layers of different types of transistors in the non-display area NA, and do not represent the specific structure of the transistors in the non-display area NA.

[0100] It should be noted that, since the material of the second gate layer 127 in this application is typically made of titanium to shield the influence of the bottom charge in the display area AA, and the spacing between the second gate layer 127 and the second active layer 129 is small, in order to improve the bias temperature stress (BTS) characteristics of the oxide transistor, this application uses the first gate layer 125 as the bottom gate of the oxide transistor. Figure 5 The second gate layer 127 is not shown in the structure.

[0101] The following is about Figure 4 The specific structure of the circuit in the description describes the technical solution of this application.

[0102] Please see Figure 6 The first gate layer 125 includes the gate T1G of the first transistor T1, the gate T2G of the second transistor T2, the gate T3G of the third transistor T3, the gate T4G of the fourth transistor T4, the gate T5G of the fifth transistor T5, the gate T6G of the sixth transistor T6, the gate T7G of the seventh transistor T7, and the gate T8G of the eighth transistor T8.

[0103] Please see Figure 6 Since the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all oxide transistors, in order to improve the mobility of the above transistors, this application sets the above transistors as dual-gate transistors, and the first gate layer 125 includes the bottom gate of the above transistors; for example, the first gate layer 125 includes the first gate T1Ga of the first transistor T1, the first gate T3Ga of the third transistor T3, the first gate T5Ga of the fifth transistor T5, the first gate T6Ga of the sixth transistor T6, the first gate T7Ga of the seventh transistor T7, and the first gate T8Ga of the eighth transistor T8.

[0104] Please see Figure 6 The first gate T3Ga of the third transistor T3 and the first gate T1Ga of the first transistor T1 are arranged along the first direction X. The first gate T6Ga of the sixth transistor T6 and the first gate T5Ga of the fifth transistor T5 are arranged along the first direction X. The gate T4G of the fourth transistor T4 and the first gate T7Ga of the seventh transistor T7 are arranged along the first direction X. The first gate T3Ga of the third transistor T3, the gate T2G of the second transistor T2, the gate T4G of the fourth transistor T4 and the first gate T8Ga of the eighth transistor T8 are arranged along the second direction Y. The first gate T8Ga of the eighth transistor T8 is arranged adjacent to the first gate T6Ga of the sixth transistor T6 and the first gate T5Ga of the fifth transistor T5.

[0105] Please see Figure 6 The first gate T6Ga of the sixth transistor T6 and the first gate T5Ga of the fifth transistor T5 both include branch gates extending along the second direction Y; for example, the first gate T6Ga of the sixth transistor T6 includes one branch gate, and the first gate T5Ga of the fifth transistor T5 includes a main gate and three branch gates connected to the main gate and arranged and spaced apart along the first direction X.

[0106] Please see Figure 6 The spacing between the first gate T6Ga of the sixth transistor T6 and the first gate T5Ga of the fifth transistor T5 can be equal to the spacing between two adjacent branch gates in the first gate T5Ga of the fifth transistor T5.

[0107] Please see Figure 6 The first gate layer 125 also includes a first transmission segment ET1, a second transmission segment ET2, a third transmission segment ET3, a fourth transmission segment ET4 and a fifth transmission segment ET5. The first transmission segment ET1, the second transmission segment ET2, the third transmission segment ET3 and the fourth transmission segment ET4 all extend along the second direction Y, and the fifth transmission segment ET5 is a broken line segment.

[0108] Please see Figure 6The first transmission segment ET1 is connected to the first gate T5Ga of the first transistor T1 at one end away from the first gate T5Ga of the fifth transistor T5. The middle position of the second transmission segment ET2 is connected to the first gate T7Ga of the fourth transistor T4 at one end away from the first gate T7Ga of the seventh transistor T7. The third transmission segment ET3 is connected to the main gate of the first gate T5Ga of the fifth transistor T5. The two ends of the fourth transmission segment ET4 are connected to the gate T2G of the second transistor T2 and the first gate T3Ga of the third transistor T3. The fifth transmission segment ET5 is located between the first gate T3Ga of the third transistor T3 and the first gate T1Ga of the first transistor T1, and the end of the fifth transmission segment ET5 away from the first gate T1Ga of the first transistor T1 and the fourth transmission segment ET4 are connected to the first gate T3Ga of the third transistor T3 at the same position.

[0109] Please see Figure 6 Since the fifth transistor T5 is used to output the compensation control signal Nscan2, the load of the fifth transistor T5 is greater than that of other non-output transistors. In order to ensure the output load of the fifth transistor T5, this application can make the area of ​​the fifth transistor T5 larger than the area of ​​other transistors not used for output load. At the same time, since the sixth transistor T6 is used to pull down the potential of the output point of the fifth transistor T5, the area of ​​the sixth transistor T6 can be smaller than the area of ​​the fifth transistor T5, but the area of ​​the sixth transistor T6 must be larger than the area of ​​other transistors not used for output load.

[0110] In this embodiment, the area of ​​the first gate T5Ga of the fifth transistor T5 is larger than the area of ​​the first gate T6Ga of the sixth transistor T6, and the area of ​​the first gate T6Ga of the sixth transistor T6 is larger than the area of ​​the gates of other transistors not used for the output load.

[0111] Please see Figure 7 The first active layer 123 includes an active pattern T2A of a second transistor T2 and an active pattern T4A of a fourth transistor T4. The active patterns T2A of the second transistor T2 and T4A of the fourth transistor T4 both extend along the second direction Y, and the active patterns T2A of the second transistor T2 and T4A of the fourth transistor T4 are connected along the second direction Y.

[0112] Please see Figure 9 The active pattern T2A of the second transistor T2 and the gate T2G of the second transistor T2 have an overlapping portion, and the overlapping portion is the channel of the second transistor T2; the active pattern T4A of the fourth transistor T4 and the gate T4G of the fourth transistor T4 have an overlapping portion, and the overlapping portion is the channel of the fourth transistor T4.

[0113] Please see Figure 8The second active layer 129 includes an active pattern T1A of the first transistor T1, an active pattern T3A of the third transistor T3, an active pattern T5A of the fifth transistor T5, an active pattern T6A of the sixth transistor T6, an active pattern T7A of the seventh transistor T7, and an active pattern T8A of the eighth transistor T8.

[0114] Please see Figure 8 The active pattern T6A of the sixth transistor T6 and the active pattern T5A of the fifth transistor T5 are connected. The active pattern T6A of the sixth transistor T6 and the active pattern T5A of the fifth transistor T5 both include at least two active sub-parts arranged at intervals along the second direction Y. The active sub-parts of the sixth transistor T6 and the fifth transistor T5 are connected in the first direction X.

[0115] Please see Figure 9 The active pattern T1A of the first transistor T1 and the first gate T1Ga of the first transistor T1 have overlapping portions; the active pattern T3A of the third transistor T3 and the first gate T3Ga of the third transistor T3 have overlapping portions; the active pattern T6A of the sixth transistor T6 and the first gate T6Ga of the sixth transistor T6 have overlapping portions; the active pattern T7A of the seventh transistor T7 and the first gate T7Ga of the seventh transistor T7 have overlapping portions; the active pattern T8A of the eighth transistor T8 and the first gate T8Ga of the eighth transistor T8 have overlapping portions; and the active pattern T5A of the fifth transistor T5 and the first gate T5Ga of the fifth transistor T5 have overlapping portions.

[0116] Please see Figure 9 The gate T6G of the sixth transistor T6 and the gate T5G of the fifth transistor T5 have relatively long lengths along the second direction Y. Since the sixth transistor T6 and the fifth transistor T5 are oxide transistors, they have the advantage of low leakage current, but the characteristic of low mobility. In order to improve the mobility of the sixth transistor T6 and the fifth transistor T5, this application can increase the channel width in the transistor. Therefore, in order to further increase the channel width of the transistor, the dimensions of the active pattern T6A of the sixth transistor T6 and the active pattern T5A of the fifth transistor T5 along the second direction Y can be increased as much as possible. However, since the active part will have the problem of electrostatic concentration when the semiconductor structure is too large in the second direction Y, causing the active part to be damaged by electrostatic discharge, this application can set the structure of the active pattern T6A of the sixth transistor T6 and the active pattern T5A of the fifth transistor T5 as multiple sub-active parts arranged at intervals.

[0117] In this embodiment, the widths of the active pattern T6A of the sixth transistor T6 and the active pattern T5A of the fifth transistor T5 can be the same; or, please refer to... Figure 8 and Figure 9The width of the active pattern T6A of the sixth transistor T6 can be smaller than the width of the active pattern T5A of the fifth transistor T5.

[0118] Please see Figure 8 and Figure 9 The channel width of the active pattern T1A of the first transistor T1 is greater than the channel width of the transistors not used for the output load (i.e., except for the sixth transistor T6, the seventh transistor T7, the tenth transistor T10, and the ninth transistor T9). Since the first transistor T1 is used to pull up the potential of node K, in order to ensure the accuracy of the potential of the pull-up node K, this application improves the mobility of the first transistor T1 by increasing the width of the active pattern T1A of the first transistor T1.

[0119] Please see Figure 10 The third gate layer 131 includes the second gate T1Gb of the first transistor T1, the second gate T3Gb of the third transistor T3, the second gate T5Gb of the fifth transistor T5, the second gate T6Gb of the sixth transistor T6, the second gate T7Gb of the seventh transistor T7, and the second gate T8Gb of the eighth transistor T8. The above gates can be used as the top gates of the corresponding transistors.

[0120] Please see Figure 10 The second gate T6Gb of the sixth transistor T6 and the second gate T5Gb of the fifth transistor T5 both include a branch gate extending along the second direction Y; for example, the second gate T6Gb of the sixth transistor T6 includes one branch gate, and the second gate T5Gb of the fifth transistor T5 includes a main gate and three branch gates connected to the main gate and arranged and spaced apart along the first direction X.

[0121] Please see Figure 10 and Figure 12 The spacing between the second gate T6Gb of the sixth transistor T6 and the second gate T5Gb of the fifth transistor T5 can be equal to the spacing between two adjacent branch gates in the second gate T5Gb of the fifth transistor T5; at the same time, the spacing between two adjacent branch gates in the second gate T5Gb of the fifth transistor T5 can be greater than the spacing between two adjacent branch gates in the first gate T5Ga of the fifth transistor T5.

[0122] Please see Figure 12The second gate T1Gb and the first gate T1Ga of the first transistor T1 overlap; the second gate T3Gb and the first gate T3Ga of the third transistor T3 overlap; the second gate T5Gb and the first gate T5Ga of the fifth transistor T5 overlap; the second gate T6Gb and the first gate T6Ga of the sixth transistor T6 overlap; the second gate T7Gb and the first gate T7Ga of the seventh transistor T7 overlap; and the second gate T8Gb and the first gate T8Ga of the eighth transistor T8 overlap. The width of the second gate of each of the above transistors is smaller than the width of the first gate.

[0123] Please see Figure 12 The active pattern T1A of the first transistor T1 and the second gate T1Gb of the second transistor T2T1 have overlapping portions; the active pattern T3A of the third transistor T3 and the second gate T3Gb of the third transistor T3 have overlapping portions; the active pattern T6A of the sixth transistor T6 and the second gate T6Gb of the sixth transistor T6 have overlapping portions; the active pattern T7A of the seventh transistor T7 and the second gate T7Gb of the seventh transistor T7 have overlapping portions; the active pattern T8A of the eighth transistor T8 and the second gate T8Gb of the eighth transistor T8 have overlapping portions; the active pattern T5A of the fifth transistor T5 and the second gate T5Gb of the fifth transistor T5 have overlapping portions, and the aforementioned overlapping portions are the channels of the corresponding transistors, and the channels of the aforementioned transistors completely fall within the first gate of the corresponding transistors.

[0124] Please see Figure 10 The third gate layer 131 also includes the first plate C1a of the first capacitor C1, the sixth transmission segment ET6, the seventh transmission segment ET7, the eighth transmission segment ET8, and the ninth transmission segment ET9. The sixth transmission segment ET6 is connected to the main gate of the first plate C1a and the second gate T5Gb of the fifth transistor T5. The seventh transmission segment ET7 is connected to the main gate of the second gate T5Gb of the fifth transistor T5. The eighth transmission segment ET8, the seventh transmission segment ET7, and the sixth transmission segment ET6 are arranged along the first direction X. The two ends of the eighth transmission segment ET8 are connected to the second gate T6Gb of the sixth transistor T6 and the second gate T8Gb of the eighth transistor T8. The ninth transmission segment ET9 is connected to the second gate T7Gb of the seventh transistor T7.

[0125] Please see Figure 11 and Figure 12 The fourth gate layer 133 includes a second electrode C1b of the first capacitor C1. The second electrode C1b is correspondingly disposed with the first electrode C1a, and the orthogonal projection of the first electrode C1a on the fourth gate layer 133 is located within the second electrode C1b, that is, the area of ​​the first electrode C1a can be smaller than the area of ​​the second electrode C1b.

[0126] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes the source T6S of the sixth transistor T6, the drain T6D of the sixth transistor T6, the source T5S of the fifth transistor T5, and the drain T5D of the fifth transistor T5.

[0127] Please see Figure 13 and Figure 14 The source T6S and drain T6D of the sixth transistor T6, the source T5S and drain T5D of the fifth transistor T5 all include branch electrodes extending along the second direction Y and spaced apart along the first direction X. For example, the source T5S and drain T5D of the fifth transistor T5 each include two branch electrodes extending along the second direction Y and arranged along the first direction X, and the source T5S and drain T5D of the fifth transistor T5 are arranged alternately along the first direction X.

[0128] Please see Figure 13 and Figure 14 The branch electrode of the source T6S of the sixth transistor T6, which is close to the drain T5D of the fifth transistor T5, is shared by the source T6S of the sixth transistor T6 and the source T5S of the fifth transistor T5. The end of the shared branch electrode that is close to the display area AA is the output terminal OUT of the first gate circuit 310.

[0129] Please see Figure 13 and Figure 14 The two gate branch electrodes of the sixth transistor T6 can be disposed between the branch electrodes of the source T6S and the drain T6D of the sixth transistor T6, which are arranged at intervals. The two gate branch electrodes of the fifth transistor T5 are disposed between the branch electrodes of the source T5S and the drain T5D of the fifth transistor T5, which are arranged at intervals.

[0130] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a first connection segment CT1. One end of the first connection segment CT1 is connected to the drain T5S of the fifth transistor T5, and the other end of the first connection segment CT1 is connected to the second type clock line CK through a via.

[0131] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a second connection segment CT2. One end of the second connection segment CT2 passes through a via and is connected to a first type clock line XCK. The other end of the second connection segment CT2 passes through a via and is connected to one end of the first transmission segment ET1.

[0132] Please see Figure 13and Figure 14 The first source-drain layer 135 includes a third connection segment CT3. One end of the third connection segment CT3 passes through a via and is connected to the other end of the first transmission segment ET1. The other end of the third connection segment CT3 passes through a via and is connected to the first gate T1Ga and the second gate T1Gb of the first transistor T1.

[0133] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a fourth connection segment CT4, which includes a lateral segment CT4a and a vertical segment CT4b connected to the middle of the lateral segment CT4a. One end of the lateral segment CT4a is connected to one end of the active pattern T7A of the seventh transistor T7, and the other end of the lateral segment CT4a is connected to the seventh transmission segment ET7. The end of the vertical segment CT4b away from the lateral segment CT4a is connected to one end of the active pattern T8A of the eighth transistor T8.

[0134] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a fifth connection segment CT5, which includes four connection points arranged along the second direction Y. The first connection point of the fifth connection segment CT5 is connected to the end of the fifth transmission segment ET5 away from the third transistor T3. The second connection point of the fifth connection segment CT5 is connected to the end of the active pattern T1A of the first transistor T1 away from the first transmission segment ET1. The third connection point of the fifth connection segment CT5 is connected to the end of the active pattern T7A of the seventh transistor T7 away from the fourth connection segment CT4. The fourth connection point of the fifth connection segment CT5 is connected to the end of the active pattern T4A of the fourth transistor T4 away from the second transistor T2.

[0135] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a sixth connection segment CT6. One end of the sixth connection segment CT6 is connected to the high potential line Nvgh of the second source-drain layer 137. The other end of the sixth connection segment CT6 is connected to the other end of the active pattern T4A of the fourth transistor T4. The middle section of the sixth connection segment CT6 is connected to the ninth transmission segment ET9.

[0136] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a seventh connection segment CT7. One end of the seventh connection segment CT7 is connected to the end of the active pattern T3A of the third transistor T3 away from the fifth transmission segment ET5. The other end of the seventh connection segment CT7 is connected to the end of the active pattern T2A of the second transistor T2 away from the fourth transistor T4. The middle segment of the seventh connection segment CT7 is connected to the end of the second transmission segment ET2 away from the eighth transmission segment ET8.

[0137] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes an eighth connection segment CT8. One end of the eighth connection segment CT8 passes through a via and is connected to the second gate T3Gb of the third transistor T3. The other end of the eighth connection segment CT8 passes through a via and is connected to the connection point of the fifth transmission segment ET5 and the fourth transmission segment ET4.

[0138] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a ninth connection segment CT9. One end of the ninth connection segment CT9 passes through a via and is connected away from the active pattern T3A of the third transistor T3. The other end of the ninth connection segment CT9 passes through a via and is connected to the first low potential line Nvgh1 of the second source-drain layer 137.

[0139] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a tenth connection segment CT10. One end of the tenth connection segment CT10 passes through a via and connects to the end of the second transmission segment ET2 away from the third transistor T3. The other end of the tenth connection segment CT10 passes through a via and connects to the connection point of the eighth transmission segment ET8 and the second gate T8Gb of the eighth transistor T8.

[0140] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes an eleventh connection segment CT11. One end of the eleventh connection segment CT11 passes through a via and is connected to the second low potential line Nvgh2 of the second source-drain layer 137. The other end of the eleventh connection segment CT11 passes through a via and is connected to one end of the active pattern T8A of the eighth transistor T8 near the sixth transistor T6. The middle section of the eleventh connection segment CT11 is connected to the bent section connected to the first gate T8Ga of the eighth transistor T8.

[0141] Please see Figure 13 and Figure 14 The first source-drain layer 135 includes a twelfth connection segment CT12. One end of the twelfth connection segment CT12 passes through a via and is connected to the source T5S of the fifth transistor T5 and the source T6S of the sixth transistor T6 of this stage. The other end of the twelfth connection segment CT12 passes through a via and is connected to the end of the active pattern T1A of the first transistor T1 of the next stage first gate circuit 310 away from the fifth connection segment CT5.

[0142] Please see Figure 15 and Figure 16The second source-drain layer 137 includes a first low potential line Nvgh1, a high potential line Nvgh, a first control clock line NCK1, a second control clock line NCK2, a third control clock line NCK3, a fourth control clock line NCK4, a first low potential line Nvgh1, a second low potential line Nvgh2, a third low potential line Nvgh3, and a start signal line STV, all extending along the first direction X and arranged along the second direction Y.

[0143] In this embodiment, the first low-potential line Nvgh1 is connected to the active pattern T3A of the third transistor T3 through the ninth connection segment CT9, the high-potential line Nvgh is connected to the sixth connection segment CT6 through a via, the second low-potential line Nvgh2 is connected to the active pattern T8A of the eighth transistor T8 and the second gate T8Gb of the eighth transistor T8 through the eleventh connection segment CT11, and the third low-potential line Nvgh3 is connected to the source T6S of the sixth transistor T6.

[0144] Please see Figure 16 The plurality of first gate circuits 310 arranged and cascaded along the first direction X may include a plurality of repeating units RU. Each repeating unit RU may include four first gate circuits 310 arranged sequentially along the first direction X. The following description will take the (n-3)th level first gate circuit 310, the (n-2)th level first gate circuit 310, the (n-1)th level first gate circuit 310 and the nth level first gate circuit 310 as examples.

[0145] In the (n-3)th stage first gate circuit 310, the first gate T1Ga of the first transistor T1 is connected through the first transmission segment ET1 and the fourth control clock line NCK4, and the drain T5D of the fifth transistor T5 is connected through the first connection segment CT1 and the first control clock line NCK1.

[0146] In the (n-2)th stage first gate circuit 310, the first gate T1Ga of the first transistor T1 is connected through the first transmission segment ET1 and the first control clock line NCK1, and the drain T5D of the fifth transistor T5 is connected through the first connection segment CT1 and the second control clock line NCK2.

[0147] In the (n-1)th stage first gate circuit 310, the first gate T1Ga of the first transistor T1 is connected through the first transmission segment ET1 and the second control clock line NCK2, and the drain T5D of the fifth transistor T5 is connected through the first connection segment CT1 and the third control clock line NCK3.

[0148] In the nth stage first gate circuit 310, the first gate T1Ga of the first transistor T1 is connected through the first transmission segment ET1 and the third control clock line NCK3, and the drain T5D of the fifth transistor T5 is connected through the first connection segment CT1 and the fourth control clock line NCK4.

[0149] exist Figure 16 In the structure, since the first gate circuits 310 of different stages are connected to different control clock lines, the lengths of the first transmission segment ET1 and the first connection segment CT1 in the first gate circuits 310 of different stages are different.

[0150] For example, please see Figure 6 and Figure 13 In the n-3rd stage first gate circuit 310 to the nth stage first gate circuit 310, the length of the first connection segment CT1 gradually decreases, that is, the length of the first connection segment CT1 in the n-3rd stage first gate circuit 310 is the longest, and the length of the first connection segment CT1 in the nth stage first gate circuit 310 is the shortest.

[0151] For example, please see Figure 6 and Figure 13 In the first gate circuit 310 of the (n-2)th stage to the first gate circuit 310 of the nth stage, the length of the first transmission segment ET1 gradually increases, and the length of the first transmission segment ET1 in the (n-3)th stage first gate circuit 310 is greater than the length of the first transmission segment ET1 in the nth stage first gate circuit 310. That is, the length of the first transmission segment ET1 in the (n-3)th stage first gate circuit 310 is the longest, and the length of the first transmission segment ET1 in the (n-2)th stage first gate circuit 310 is the shortest.

[0152] In this embodiment, since the third low potential line Nvgh3 and the sixth transistor T6 overlap and are connected, the first low potential line Nvgh1 and the third transistor T3 are connected, the second low potential line Nvgh2 and the eighth transistor T8 are connected, the third transistor T3 and the eighth transistor T8 are used for signal switching control, and the sixth transistor T6 is used to pull down the potential of the output terminal OUT of the first gate circuit 310. Therefore, the output load of the sixth transistor T6 is greater than the output load of the third transistor T3 and the eighth transistor T8.

[0153] Please see Figure 15 and Figure 16 The width of the third low potential line Nvgh3 is greater than that of the first low potential line Nvgh1 and the second low potential line Nvgh2, which improves the output load capacity of the third low potential line Nvgh3.

[0154] In the embodiments of this application, in order to ensure that the output signals of different output clock lines are the same, this application can make the line widths of the four output clock lines equal.

[0155] In this embodiment, the start signal line STV and the first transistor T1 in the signal generation module 310a are electrically connected, and the start signal line STV and the output module 310b have an overlapping portion.

[0156] Please see Figure 15 and Figure 16 The second source-drain layer 137 may also include a second light-shielding portion 520, and the second light-shielding portion 520 may be disposed between the third low potential line Nvgh3 and the start signal line STV; that is, the second light-shielding portion 520 may be disposed in the same layer as the constant voltage signal line, that is, the constant voltage signal line and the second light-shielding portion 520 are formed in the same process.

[0157] It should be noted that the constant voltage signal line in this application can be the third low potential line Nvgh3.

[0158] It should be noted that the second light-shielding part 520 can also be made using the material of the third source-drain layer 139. In the following embodiment, the second light-shielding part 520 is made using the material of the second source-drain layer 137 as an example for illustration.

[0159] Please see Figure 17 and Figure 18 The anode layer 141 may include a first light-shielding portion 510. Since a first planarization layer 136, a second planarization layer 138 and a third planarization layer 140 are provided between the first light-shielding portion 510 and the substrate 110, the arrangement of the first through-hole HL1 satisfies the gas release channel in the organic material. For example, each first gate circuit 310 may have 2*4 first through-holes HL1 arranged in an array, that is, each first light-shielding portion 510 has 4 rows and 2 columns of first through-holes HL1.

[0160] In this embodiment, although the width of the third low-potential line Nvgh3 is relatively large, it is still insufficient to completely block all eight first vias HL1. To prevent light from entering the oxide transistor in the output module 310b through the unblocked first vias HL1, this application provides a second light-shielding part 520 parallel to the first light-shielding part 510. That is, the four first vias HL1 in the first column of the first light-shielding part 510 are blocked by the third low-potential line Nvgh3, and the four first vias HL1 in the second column of the first light-shielding part 510 are blocked by the second light-shielding part 520. This avoids the technical problem of the oxide transistor's device performance being affected while satisfying the release channel of the organic planarization layer.

[0161] In this embodiment, since the second light-shielding part 520 only serves as a shielding element and does not need to transmit voltage or current signals, adjacent second light-shielding parts 520 are spaced apart in the gate driving circuit 300. See [link to documentation] for details. Figure 15 .

[0162] In this embodiment, at least two second light-shielding portions 520 are connected in the gate driving circuit 300; for example, please refer to... Figure 19In a repeating unit RU, two second light-shielding parts 520 can be connected to each other, and the two connected second light-shielding parts 520 can be spaced apart from two other connected second light-shielding parts 520.

[0163] In this embodiment, in the gate driving circuit 300, two adjacent second light-shielding portions 520 are connected, for example, see [reference needed]. Figure 20 In a repeating unit RU, four second light-shielding parts 520 can be connected together.

[0164] In this embodiment, the voltage signal transmitted by the second light-shielding part 520 is the same as the voltage signal transmitted by the constant voltage signal line, and the second light-shielding part 520 is electrically connected to the output module 310b; that is, the second light-shielding part 520 is equivalent to setting the second third low potential line Nvgh3, that is, the output module 310b reduces the load of a single third low potential line Nvgh3 by connecting to two low potential lines.

[0165] In this embodiment, the oxide transistor may include an oxide active portion, that is, the active pattern T5A of the fifth transistor T5 and the active pattern T6A of the sixth transistor T6 are both oxide active portions. The outer contour of the orthographic projection of the oxide active portion on the substrate 110 is located within the outer contour of the orthographic projection of the first light-shielding portion 510 on the substrate 110. That is, the first light-shielding portion 510 blocks the active pattern T5A of the fifth transistor T5 and the active pattern T6A of the sixth transistor T6 to prevent light from incident on the active pattern T5A of the fifth transistor T5 and the active pattern T6A of the sixth transistor T6.

[0166] Please see Figure 17 The first gate circuit 310 may also include a third light-shielding part 530 disposed on the side of the signal generation module 310a away from the substrate 110, and the third light-shielding part 530 covers the signal generation module 310a.

[0167] In this embodiment, the first transistor T1, the third transistor T3, the seventh transistor T7, and the eighth transistor T8 in the signal generation module 310a are all oxide semiconductor transistors. In order to avoid the oxide semiconductor transistors in the signal generation module 310a being affected by external light, this application can provide a third light-shielding part 530 in the inner area where the signal generation module 310a is located.

[0168] Meanwhile, since organic materials also form in the area where the signal generation module 310a is located, please refer to... Figure 17 and Figure 18The third light-shielding part 530 may have a second through hole HL2 to form a gas release channel for organic materials. In order to prevent light from entering the oxide semiconductor transistor through the second through hole HL2, the second through hole HL2 and the second type of oxide transistor are not overlapped.

[0169] For example, since the second transistor T2 and the fourth transistor T4 are silicon semiconductor transistors, the second via HL2 of this application can correspond to the active pattern T2A of the second transistor T2 and the active pattern T4A of the fourth transistor T4; at the same time, since no corresponding oxide semiconductor material is provided in the first capacitor C1, the second via HL2 of this application can also correspond to the first capacitor C1.

[0170] In this embodiment, in the gate driving circuit 300, the plurality of second vias HL2 include a plurality of first sub-vias HL2a and a plurality of second sub-vias HL2b spaced apart. A first sub-via HL2a overlaps with a signal generation module 310a, and a second sub-via HL2b overlaps with two adjacent signal generation modules 310a.

[0171] In one embodiment, a portion of the plurality of first sub-holes HL2a overlaps with the first capacitor C1, and another portion of the plurality of first sub-holes HL2a overlaps with the silicon semiconductor transistor.

[0172] For example, please see Figure 17 and Figure 18 In a repeating unit RU, the third light-shielding part 530 is provided with four first sub-holes HL2a and two second sub-holes HL2b. The four first sub-holes HL2a are arranged at intervals along the first direction X, and the two second sub-holes HL2b are arranged at intervals along the first direction X. The first sub-holes HL2a in the (n-3)th stage first gate circuit 310 and the (n-1)th stage first gate circuit 310 overlap with the end of the first capacitor C1 that is away from the output module 310b. The first sub-holes HL2a in the (n-2)th stage first gate circuit 310 and the nth stage first gate circuit 310 overlap with the active pattern T2A of the second transistor T2 and the active pattern T4A of the fourth transistor T4.

[0173] For example, a second sub-hole HL2b overlaps with the signal generation module 310a of the (n-3)th stage first gate circuit 310 and the (n-2)th stage first gate circuit 310. This second sub-hole HL2b also overlaps with the twelfth connecting segment CT12, the tenth connecting segment CT10, the eighth transmission segment ET8, and the second transmission segment ET2 of the (n-3)th stage first gate circuit 310. Furthermore, this second sub-hole HL2b overlaps with the end of the first capacitor C1 of the (n-2)th stage first gate circuit 310 closest to the output module 310b. Partially; another second sub-hole HL2b overlaps with the signal generation module 310a of the (n-1)th stage first gate circuit 310 and the nth stage first gate circuit 310. The second sub-hole HL2b overlaps with the twelfth connecting segment CT12, the tenth connecting segment CT10, the eighth transmission segment ET8 and the second transmission segment ET2 of the (n-1)th stage first gate circuit 310. The second sub-hole HL2b also overlaps with the end of the first capacitor C1 of the nth stage first gate circuit 310 that is closer to the output module 310b.

[0174] Please see Figure 17 and Figure 18 Since the sum of the areas of the active patterns in the first type of oxide semiconductor transistors in the output module 310b is greater than the sum of the areas of the active patterns in the second type of oxide semiconductor transistors in the signal generation module 310a, the area of ​​the first via HL1 in this application cannot be too large to prevent light from passing through the boundary of the first via HL1 and entering the output module 310b. At the same time, the first via HL1 cannot exceed the boundary of the second light-shielding part 520 and the third low-potential line Nvgh3. That is, the size of the first via HL1 is limited by the width of the second light-shielding part 520 and the third low-potential line Nvgh3. In other words, the area of ​​the first via HL1 can be smaller than the area of ​​the second via HL2.

[0175] In this embodiment, since the second sub-hole HL2b overlaps with two adjacent signal generation modules 310a, and no oxide semiconductor material is disposed in this area, the application can make the area of ​​the second sub-hole HL2b larger than the area of ​​the first sub-hole HL2a.

[0176] In this embodiment, the first through hole HL1 and the second through hole HL2 can be in the shape of a circle, a square, a rectangle, a triangle, etc.

[0177] In this embodiment, the third light-shielding part 530 and the first light-shielding part 510 can be disposed in the same layer and connected to each other; that is, the third light-shielding part 530 and the first light-shielding part 510 of this application can both be made of the material of the anode layer 141 at the same time, which simplifies the product manufacturing process.

[0178] It should be noted that the third source-drain layer 139 of this application can be provided with an anode connection line located in the display area AA and a fan-out line, and the corresponding structure is not required in the non-display area NA; or, the second light-shielding part 520 of this application can be made using the material of the third source-drain layer 139.

[0179] Please see Figures 21 to 23 The second source-drain layer 137 may not require the second light-shielding part 520, and the distance between the boundary of the oxide active part and the boundary of the first light-shielding part 510 on the side of the display area AA close to the display panel 100 is greater than the distance between the boundary of the oxide active part and the boundary of the first light-shielding part 510 on the side of the display area AA far from the display panel 100.

[0180] In this embodiment, since the boundaries of the first light-shielding part 510 are all exhaust channels of organic materials, this application can reduce the distance between the boundary of the oxide active part and the boundary of the first light-shielding part 510, which is equivalent to shrinking the boundary of the first light-shielding part 510 near the display area AA, so that the gas in the organic material under the first light-shielding part 510 can be exhausted through the boundary of the first light-shielding part 510 near the display area AA.

[0181] In this embodiment, on the side near the display area AA of the display panel 100, the distance between the boundary of the oxide active portion and the boundary of the first light-shielding portion 510 is less than or equal to 130 micrometers.

[0182] It should be noted that, Figure 21 and Figure 22 The structure in can be applied to Figures 6 to 20 In the structure, that is, this application can set the second light-shielding part 520 and shrink the boundary of the first light-shielding part 510.

[0183] It should be noted that this application also proposes a display device, which includes the aforementioned display panel, and the display device of this application can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0184] This application provides a display panel and display device. The first gate circuit of the display panel includes an output module, a first light-shielding part, a second light-shielding part disposed between the output module and the first light-shielding part, a clock signal line and a constant voltage signal line electrically connected to the output module. The output module includes a first type of oxide transistor. The clock signal line is not overlapped with the output module. The second light-shielding part and the constant voltage signal line overlap with the output module. The second light-shielding part and the constant voltage signal line are not overlapped. This application provides a second light-shielding part on the output module, and the second light-shielding part and the constant voltage signal line are not overlapped. A portion of the plurality of first through holes on the first light-shielding part overlaps with the second light-shielding part, and another portion of the plurality of first through holes overlaps with the constant voltage signal line. This allows external light entering the output module through the first through holes to be blocked by the constant voltage signal line and the second light-shielding part. This avoids the technical problem of the oxide transistor affecting the device performance while satisfying the release channel of the organic planarization layer.

[0185] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0186] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0187] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0188] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The system includes a substrate and a gate driving circuit disposed on one side of the substrate. The gate driving circuit includes a plurality of first gate circuits; wherein the first gate circuit includes: Signal generation module; An output module is electrically connected to the signal generation module, and the output module includes a first type of oxide transistor; A clock signal line is electrically connected to the output module and is not overlapped with the output module. A constant voltage signal line is electrically connected to the output module and has an overlapping portion with the output module; A first light-shielding portion is disposed on the side of the output module away from the substrate, and the first light-shielding portion has a plurality of first through holes; and The second light-shielding part is disposed between the output module and the first light-shielding part. The second light-shielding part and the output module have an overlapping portion, and the second light-shielding part and the constant voltage signal line are not overlapped. Among them, a portion of the plurality of first through holes overlaps with the second light-shielding portion, and another portion of the plurality of first through holes overlaps with the constant voltage signal line.

2. The display panel as described in claim 1, characterized in that, The second light-shielding part and the constant voltage signal line are arranged in the same layer.

3. The display panel as described in claim 1, characterized in that, In the gate driving circuit, two adjacent second light-shielding portions are spaced apart, or at least two second light-shielding portions are connected together.

4. The display panel as described in claim 1, characterized in that, In the gate driving circuit, two adjacent second light-shielding portions are connected together; The voltage signal transmitted by the second light-shielding part is the same as the voltage signal transmitted by the constant voltage signal line, and the second light-shielding part is electrically connected to the output module.

5. The display panel as described in claim 1, characterized in that, The first gate circuit further includes a start signal line electrically connected to the signal generation module, and the start signal line and the output module have an overlapping portion; The second light-shielding part is located between the constant voltage signal line and the starting signal line.

6. The display panel as described in any one of claims 1 to 5, characterized in that, The first gate circuit further includes a third light-shielding portion disposed on the side of the signal generation module away from the substrate, the third light-shielding portion covering the signal generation module; The third light-shielding part has a second through hole, and the signal generation module includes a second type of oxide transistor. The second through hole and the second type of oxide transistor do not overlap.

7. The display panel as described in claim 6, characterized in that, The third light-shielding part and the first light-shielding part are disposed on the same layer, and the third light-shielding part and the first light-shielding part are connected.

8. The display panel as described in claim 6, characterized in that, The area of ​​the second through hole is larger than the area of ​​the first through hole.

9. The display panel as described in claim 6, characterized in that, In the gate driving circuit, the plurality of second vias include a plurality of first sub-vias and a plurality of second sub-vias spaced apart; Wherein, one of the first sub-holes overlaps with one of the signal generation modules, and one of the second sub-holes overlaps with two adjacent signal generation modules.

10. The display panel as claimed in claim 9, characterized in that, The signal generation module includes a first capacitor and a silicon semiconductor transistor. A portion of the plurality of first sub-holes overlaps with the first capacitor, and another portion of the plurality of first sub-holes overlaps with the silicon semiconductor transistor.

11. The display panel as claimed in claim 9, characterized in that, The area of ​​the second sub-hole is larger than the area of ​​the first sub-hole.

12. The display panel according to any one of claims 1 to 5, 7 to 11, characterized in that, The first type of oxide transistor includes an oxide active portion, wherein the outer contour of the orthographic projection of the oxide active portion on the substrate is located within the outer contour of the orthographic projection of the first light-shielding portion on the substrate. Specifically, on the side closer to the display area of ​​the display panel, the distance between the boundary of the oxide active portion and the boundary of the first light-shielding portion is greater than the distance between the boundary of the oxide active portion and the boundary of the first light-shielding portion on the side farther from the display area of ​​the display panel.

13. The display panel as claimed in claim 12, characterized in that, On the side of the display area near the display panel, the distance between the boundary of the oxide active portion and the boundary of the first light-shielding portion is less than or equal to 130 micrometers.

14. The display panel as claimed in any one of claims 1 to 5, 7 to 11, characterized in that, The display panel further includes a pixel driving circuit, which includes a switching transistor, a driving transistor, and a compensation transistor. The output module and the gate of the switching transistor are connected, and the effective level of the switching transistor is high.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 14.

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