Display device and method for manufacturing display device

Abstract

Provided is a display device having a large aperture ratio. A transistor, a capacitor, and a liquid crystal element are provided in a pixel of the display device. A spacer is provided between a lower electrode that is one of a source electrode and a drain electrode of the transistor and an upper electrode that is the other of the source electrode and the drain electrode of the transistor. The upper electrode and the spacer include an opening that reaches the lower electrode, and the semiconductor layer, the gate insulating layer, and the gate electrode are provided in this order so as to have a region inside the opening. The lower electrode is used as a first wiring, the gate electrode is used as a second wiring, and the first wiring and the second wiring are orthogonal. The upper electrode, the gate insulating layer, and the third wiring constitute a capacitor. The third wiring is provided on the same surface to be formed as the second wiring, and extends in a direction parallel to the second wiring. A pixel electrode of the liquid crystal element has a region overlapping the third wiring.

Description

Technical Field

[0001] One aspect of the present invention relates to a display device, a semiconductor device, a display module, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a display device and a method for manufacturing a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields for one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] Note that in this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, and includes circuits that include semiconductor elements (transistors, diodes, or photodiodes, etc.) and devices that include such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. For example, as examples of semiconductor devices, there are integrated circuits, chips having integrated circuits, and electronic components that house chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and sometimes include semiconductor devices. Background Technology

[0004] Semiconductor devices, including transistors, are widely used in electronic devices. For example, by reducing the area occupied by transistors in display devices, pixel size can be reduced to achieve higher resolution. Furthermore, by reducing the area occupied by transistors, the aperture ratio of pixels can be increased. Therefore, there is a need for transistor miniaturization.

[0005] As a type of display device, there are liquid crystal display devices (LCDs) that incorporate liquid crystal elements (also called liquid crystal devices). For example, active matrix liquid crystal display devices, which arrange pixel electrodes in a matrix and use transistors as switching elements connected to each pixel electrode, have attracted attention.

[0006] For example, active matrix liquid crystal display devices (Patent Document 1 and Patent Document 2) are known to use transistors containing metal oxides in the channel forming region as switching elements connected to each pixel electrode. [Preliminary Technology Documents] [Patent Literature]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2007-123861 [Patent Document 2] Japanese Patent Application Publication No. 2007-96055 Summary of the Invention The technical problem that the invention aims to solve

[0008] One objective of this invention is to provide a display device with a high pixel aperture ratio and a method for manufacturing the same. Another objective of this invention is to provide a low-power display device and a method for manufacturing the same. Another objective of this invention is to provide a display device capable of displaying high-brightness images and a method for manufacturing the same. Another objective of this invention is to provide a high-speed driven display device and a method for manufacturing the same. Another objective of this invention is to provide a high-definition display device and a method for manufacturing the same. Another objective of this invention is to provide a small-sized display device and a method for manufacturing the same. Another objective of this invention is to provide a display device with a narrow bezel and a method for manufacturing the same. Another objective of this invention is to provide a display device including micro-transistors and a method for manufacturing the same. Another objective of this invention is to provide a display device including transistors with high on-state current and a method for manufacturing the same. Another objective of this invention is to provide a display device with transistors having good electrical characteristics and a method for manufacturing the same. Another objective of this invention is to provide a method for manufacturing a display device with a low number of steps. Finally, another objective of this invention is to provide a novel display device, a novel semiconductor device, and a method for manufacturing the same.

[0009] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Note that objectives other than those described above can be extracted from the description, drawings, claims, etc. means of solving technical problems

[0010] One aspect of the present invention is a display device comprising a transistor, a capacitor, and a first insulating layer. The transistor includes a first wiring, a second wiring, a conductive layer, a semiconductor layer, and a second insulating layer. The capacitor includes a third wiring, a conductive layer, and a second insulating layer. The first insulating layer is disposed on the first wiring and includes a first opening extending to the first wiring. The conductive layer is disposed on the first insulating layer and includes a second opening having a region overlapping the first opening. The semiconductor layer is disposed such that it has a region contacting the first wiring and a region contacting the conductive layer, and has regions located inside the first opening and regions located inside the second opening. The second insulating layer is disposed on the semiconductor layer and the conductive layer such that it has regions located inside the first opening and regions located inside the second opening. The second wiring is disposed on the second insulating layer such that it has regions located inside the first opening and regions located inside the second opening. The third wiring is disposed on the second insulating layer such that it has a region overlapping the conductive layer. The first wiring extends in a first direction, and the second and third wirings extend in a second direction perpendicular to the first direction when viewed from a plane.

[0011] In the above-described manner, the display device may include a liquid crystal element, the second insulating layer may include a third opening that reaches the conductive layer, the pixel electrode of the liquid crystal element may have a region that contacts the conductive layer inside the third opening, and the pixel electrode may have a region that overlaps with the third wiring.

[0012] In the above-described manner, the display device may include a third insulating layer, which may be disposed on the second wiring, the third wiring and the second insulating layer and have a region located between the third wiring and the pixel electrode, and the third insulating layer may include a third opening.

[0013] In the above-described manner, the semiconductor layer may also comprise a metal oxide.

[0014] One aspect of the present invention is a method for manufacturing a display device, comprising the steps of: forming a first wiring extending in a first direction; forming a first insulating layer on the first wiring; forming a conductive layer on the first insulating layer; forming a first opening in the conductive layer that overlaps with the first wiring; forming a second opening in the first insulating layer that reaches the first wiring in such a way that it has a region that overlaps with the first opening; forming a semiconductor layer in such a way that it has a region that contacts the first wiring and a region that contacts the conductive layer, and has a region located inside the first opening and a region located inside the second opening; forming a second insulating layer on the semiconductor layer and the conductive layer in such a way that it has a region located inside the first opening and a region located inside the second opening; forming a conductive film on the second insulating layer; and forming a second wiring having a region located inside the first opening and a region located inside the second opening, and a third wiring having a region that overlaps with the conductive layer by processing the conductive film, wherein the second wiring and the third wiring extend in a second direction perpendicular to the first direction when viewed from a plane.

[0015] In the above manufacturing method, a third insulating layer may be formed on the second wiring, the third wiring, and the second insulating layer. A third opening reaching the conductive layer may be formed in the third insulating layer and the second insulating layer. A pixel electrode may be formed in such a way that it has a region in contact with the conductive layer inside the third opening and a region overlapping with the third wiring. A liquid crystal element including a pixel electrode, a common electrode, and liquid crystal may be formed. Invention Effects

[0016] According to one aspect of the present invention, a display device with a high pixel aperture ratio and a method for manufacturing the same can be provided. According to one aspect of the present invention, a low-power display device and a method for manufacturing the same can be provided. According to one aspect of the present invention, a display device capable of displaying high-brightness images and a method for manufacturing the same can be provided. According to one aspect of the present invention, a high-speed driven display device and a method for manufacturing the same can be provided. According to one aspect of the present invention, a high-definition display device and a method for manufacturing the same can be provided. According to one aspect of the present invention, a small display device and a method for manufacturing the same can be provided. According to one aspect of the present invention, a display device with a narrow bezel and a method for manufacturing the same can be provided. According to one aspect of the present invention, a display device including microtransistors and a method for manufacturing the same can be provided. According to one aspect of the present invention, a display device including transistors with high on-state current and a method for manufacturing the same can be provided. According to one aspect of the present invention, a display device with transistors having good electrical characteristics and a method for manufacturing the same can be provided. According to one aspect of the present invention, a method for manufacturing a display device with a low number of steps can be provided. According to one aspect of the present invention, a novel display device, a novel semiconductor device, and a method for manufacturing the same can be provided.

[0017] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Effects other than those described above can be extracted from the specification, drawings, and claims. Brief description of the attached figures

[0018] Figure 1A This is a block diagram illustrating an example of the structure of a display device. Figure 1B This is a planar diagram showing an example of the structure of a pixel. Figure 1C This is a circuit diagram showing an example of the structure of a pixel. Figures 2A1 to 2A3 This is a plan view showing an example of the structure of a semiconductor device. Figure 2B This is a cross-sectional view showing an example of the structure of a semiconductor device. Figure 3A This is a plan view showing an example of the structure of a semiconductor device. Figure 3B This is a cross-sectional view showing an example of the structure of a semiconductor device. Figure 4A and Figure 4B This is a planar diagram showing an example of the structure of a pixel. Figure 5A and Figure 5B This is a cross-sectional view showing an example of the structure of a pixel. Figure 6A and Figure 6B This is a cross-sectional view showing an example of the structure of a pixel. Figure 7A and Figure 7B This is a planar diagram showing an example of the structure of a pixel. Figure 8A and Figure 8B This is a planar diagram showing an example of the structure of a pixel. Figure 9A This is a planar diagram showing an example of the structure of a pixel. Figure 9B It is a circuit diagram illustrating a transistor. Figure 10A and Figure 10B This is a planar diagram showing an example of the structure of a pixel. Figure 11A This is a cross-sectional view showing an example of the structure of a pixel. Figure 11B It is a circuit diagram illustrating a transistor. Figure 12A This is a planar diagram showing an example of the structure of a pixel. Figure 12B This is a cross-sectional view showing an example of the structure of a pixel. Figure 13A and Figure 13B This is a planar diagram showing an example of the structure of a pixel. Figure 14A and Figure 14B This is a planar diagram showing an example of the structure of a pixel. Figure 15A and Figure 15B This is a planar diagram showing an example of the structure of a pixel. Figure 16A This is a circuit diagram showing an example of the structure of a pixel. Figures 16B to 16D This is a planar diagram showing an example of the structure of a pixel. Figure 17A and Figure 17B This is a cross-sectional view showing an example of the structure of a pixel. Figure 18A1 , Figure 18A2 , Figure 18B1 and Figure 18B2 This is a planar diagram showing an example of the structure of a pixel. Figure 19 This is a cross-sectional view showing an example of the structure of a pixel. Figures 20A to 20D This is a plan view showing an example of a transistor structure. Figure 21A and Figure 21B This is a planar diagram showing an example of the structure of a pixel. Figures 22A to 22D This is a circuit diagram showing an example of the structure of a pixel. Figure 23 This is a circuit diagram showing an example of the structure of a pixel. Figure 24A and Figure 24B This is a planar diagram showing an example of the structure of a pixel. Figure 25 This is a cross-sectional view showing an example of the structure of a pixel. Figure 26 This is a cross-sectional view showing an example of the structure of a pixel. Figure 27A and Figure 27B This is a planar diagram showing an example of the structure of a pixel. Figure 28A and Figure 28B This is a planar diagram showing an example of the structure of a pixel. Figure 29A This is a block diagram illustrating an example of the structure of a drive circuit. Figure 29B and Figure 29C This is a circuit diagram showing an example of the structure of a drive circuit. Figure 30 This is a block diagram illustrating an example of the structure of a display device. Figure 31A This is a plan view showing an example of the structure of a display device. Figure 31B This is a cross-sectional view showing an example of the structure of a display device. Figure 32A This is a block diagram illustrating an example of the structure of a drive circuit. Figure 32BThis is a circuit diagram showing an example of the structure of a drive circuit. Figure 32C This is a timing diagram illustrating an example of a driving method for a driving circuit. Figure 33A This is a plan view showing an example of the structure of a display device. Figure 33B This is a cross-sectional view showing an example of the structure of a display device. Figure 34 This is a cross-sectional view showing an example of the structure of a display device. Figure 35 This is a cross-sectional view showing an example of the structure of a display device. Figure 36 This is a cross-sectional view showing an example of the structure of a display device. Figures 37A to 37D This is a cross-sectional view showing an example of the structure of a display device. Figures 38A to 38E This is a cross-sectional view illustrating an example of a manufacturing method for a display device. Figures 39A to 39D This is a cross-sectional view illustrating an example of a manufacturing method for a display device. Figures 40A to 40C This is a cross-sectional view illustrating an example of a manufacturing method for a display device. Figure 41A This is a plan view illustrating an example of a manufacturing method for a display device. Figure 41B and Figure 41C This is a cross-sectional view illustrating an example of a manufacturing method for a display device. Figures 42A to 42C This is a cross-sectional view illustrating an example of a manufacturing method for a display device. Figure 43A and Figure 43B This is a cross-sectional view illustrating an example of a manufacturing method for a display device. Figure 44A and Figure 44B This is a cross-sectional view illustrating an example of a manufacturing method for a display device. Figure 45A and Figure 45B This is a cross-sectional view illustrating an example of a manufacturing method for a display device. Figure 46A This is a plan view showing an example of the structure of a semiconductor device. Figures 46B1 to 46B3 This is a cross-sectional view showing an example of the structure of a semiconductor device. Figure 47A and Figure 47B This is a plan view showing an example of the structure of a semiconductor device. Figure 48A1 and Figure 48A2 This is a plan view showing an example of the structure of a semiconductor device. Figure 48B This is a cross-sectional view showing an example of the structure of a semiconductor device. Figure 49A This is a plan view showing an example of the structure of a semiconductor device. Figure 49B This is a cross-sectional view showing an example of the structure of a semiconductor device. Figure 50A This is a plan view showing an example of the structure of a semiconductor device. Figure 50B1 and Figure 50B2 This is a cross-sectional view showing an example of the structure of a semiconductor device. Figures 51A to 51G This is a planar diagram showing an example of the structure of a pixel. Figures 52A to 52I This is a planar diagram showing an example of the structure of a pixel. Figure 53 This is a perspective view showing an example of the structure of a display device. Figure 54 This is a cross-sectional view showing an example of the structure of a display device. Figure 55 This is a cross-sectional view showing an example of the structure of a display device. Figure 56 This is a cross-sectional view showing an example of the structure of a display device. Figure 57 This is a cross-sectional view showing an example of the structure of a display device. Figure 58 This is a cross-sectional view showing an example of the structure of a display device. Figure 59 This is a cross-sectional view showing an example of the structure of a display device. Figure 60 This is a cross-sectional view showing an example of the structure of a display device. Figure 61 This is a cross-sectional view showing an example of the structure of a display device. Figure 62 This is a cross-sectional view showing an example of the structure of a display device. Figures 63A to 63D This is a diagram illustrating an example of an electronic device. Figures 64A to 64E This is a diagram illustrating an example of an electronic device. Figures 65A to 65G This is a diagram illustrating an example of an electronic device. Methods of implementing the invention

[0019] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0020] Note that in the inventive structure described below, the same symbols are used in different figures to show the same parts or parts with the same function, and repeated descriptions are omitted. Furthermore, the same shading lines are sometimes used to indicate parts with the same function, without special additional symbols. Moreover, the same shading lines are sometimes used for multiple layers that can be formed by the same process.

[0021] For ease of understanding, the positions, sizes, and extents of structures shown in the accompanying drawings may not represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not limited to the positions, sizes, and extents disclosed in the accompanying drawings.

[0022] Furthermore, depending on the situation or state, the "film" and "layer" can be interchanged. For example, sometimes a "conductive layer" can be changed into a "conductive film." In addition, sometimes an "insulating film" can be changed into an "insulating layer." Or, sometimes a "semiconductor film" can be changed into a "semiconductor layer."

[0023] Furthermore, in this specification and other documents, "electrode" and "wiring" do not functionally limit their constituent elements. For example, sometimes an "electrode" is used as part of a "wiring," and vice versa. Moreover, "electrode" or "wiring" also includes cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0024] In this specification and other materials, the structure in which at least one light-emitting layer is fabricated in each light-emitting element with a different emission wavelength is sometimes referred to as an SBS (Side By Side) structure. Because the SBS structure allows for optimization of materials and structure for each light-emitting element, the freedom in material and structure selection is increased, making it easier to achieve improvements in brightness and reliability.

[0025] In this specification, the light-emitting element (also called a light-emitting device) includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Here, the layers included in the EL layer (also called functional layers) can be categorized as light-emitting layers, carrier injection layers (hole injection layers and electron injection layers), carrier transport layers (hole transport layers and electron transport layers), and carrier blocking layers (hole blocking layers and electron blocking layers). Note that the carrier injection layer, carrier transport layer, and carrier blocking layer may not always be clearly distinguishable based on their cross-sectional shape or characteristics. In addition, sometimes a single layer performs the functions of two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0026] In this specification and the like, the light-receiving element (also referred to as a light-receiving device) includes at least an active layer serving as a photoelectric conversion layer between a pair of electrodes.

[0027] In this specification, "generally consistent planar shapes" means that at least a portion of the edges of each layer in a stack overlaps. For example, it means that the upper and lower layers are processed using the same mask pattern or a portion thereof. However, there are actually cases where the edges do not overlap, and sometimes the upper layer is inside or outside the lower layer; in such cases, it can also be said that the planar shapes are "generally consistent." When the planar shapes are consistent or generally consistent, it can also be said that the ends are aligned or substantially aligned.

[0028] In this specification and the like, the planar shape of a constituent element refers to the edge shape of the constituent element when viewed from a plane. Furthermore, "viewed from a plane" means the view taken from the normal direction of the surface on which the constituent element is formed or the surface of the support (e.g., a substrate) on which the constituent element is formed.

[0029] In this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region where the angle (also called the cone angle) formed by the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side surface, substrate surface, and surface to be formed of the constituent element do not necessarily have to be completely flat; they may also be approximately planar with slight curvature or approximately planar with slight irregularities.

[0030] In this specification and the like, unless otherwise stated, when the side surface of a layer has a tapered shape, the outermost portion of that side surface is referred to as the end of the layer. For example, unless otherwise stated, when the bottom end of a layer is located outside the top end, the bottom end of the layer is simply referred to as the end.

[0031] Furthermore, in this specification and other materials, for convenience, terms such as "upper," "lower," "left," and "right" are used to indicate the arrangement and to illustrate the positional relationships of the constituent elements with reference to the accompanying drawings. Moreover, the positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to that described in the specification, and may be appropriately replaced as needed.

[0032] In this specification and other materials, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (or simply OS). For example, when a metal oxide is used as the semiconductor layer of a transistor, it is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can be interpreted as a transistor containing either a metal oxide or an oxide semiconductor. Note that sometimes nitrogen-containing metal oxides are collectively referred to as metal oxides. Furthermore, nitrogen-containing metal oxides can also be called metal oxynitrides.

[0033] (Implementation Method 1) In this embodiment, a display device and its manufacturing method according to one aspect of the present invention will be described with reference to the accompanying drawings.

[0034] One aspect of the present invention relates to a liquid crystal display device having pixels. Pixels include transistors, capacitors, and liquid crystal elements.

[0035] In the aforementioned transistor, the source and drain electrodes are located at different heights, therefore the current flowing through the semiconductor layer flows in the height direction. In other words, it can be said that the channel length direction includes a component in the height direction (vertical direction). Therefore, this transistor can also be called a longitudinal transistor or a longitudinal channel transistor, etc.

[0036] More specifically, an insulating layer serving as a spacer is provided between the lower electrode of one of the source and drain electrodes of the aforementioned transistor and the upper electrode of the other of the source and drain electrodes. Note that in the following description, the insulating layer serving as a spacer may sometimes be simply referred to as a spacer, or the spacer may be called an insulating layer.

[0037] The spacer has a first opening leading to the lower electrode, and the upper electrode has a second opening having a region overlapping the first opening. Furthermore, the semiconductor layer forming the channel has a region contacting the lower electrode and a region contacting the upper electrode, and also has regions located inside the first opening and regions located inside the second opening. A gate insulating layer and a gate electrode are disposed inside the first opening and the second opening, overlapping with the semiconductor layer. Because the source electrode, semiconductor layer, and drain electrode can be disposed in an overlapping manner, the occupied area can be significantly reduced compared to a so-called planar transistor where the semiconductor layer is disposed on a plane.

[0038] In one aspect of the display device of the present invention, a lower electrode is used as a first wiring and a gate electrode is used as a second wiring. The first wiring extends in a first direction. The second wiring extends in a second direction perpendicular to the first direction. Furthermore, a first opening, a second opening, and a semiconductor layer are provided in the region where the first wiring and the second wiring overlap, in other words, in the region where the first wiring and the second wiring intersect (intersection). Thus, a pixel transistor can be provided at the intersection of the first wiring and the second wiring.

[0039] In this specification, "perpendicular" means the angle formed by two straight lines is 80° or more and 100° or less. Therefore, it also includes angles of 85° or more and 95° or less. Furthermore, "approximately perpendicular" or "generally perpendicular" means the angle formed by two straight lines is 60° or more and 120° or less. In this specification, "parallel" means the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes angles of -5° or more and 5° or less. "Generally parallel" means the angle formed by two straight lines is -30° or more and 30° or less.

[0040] The upper electrode of the aforementioned transistor has a region that serves as one electrode of the aforementioned capacitor. That is, the other of the source and drain electrodes of the aforementioned transistor and one electrode of the aforementioned capacitor can use the same conductive layer. Furthermore, the other electrode of the aforementioned capacitor is disposed on the same surface as the gate electrode of the aforementioned transistor. In this case, by extending the gate insulating layer of the aforementioned transistor between one electrode and the other electrode of the aforementioned capacitor, a portion of this insulating layer can be used as the dielectric of the aforementioned capacitor. In other words, the gate insulating layer of the aforementioned transistor and the dielectric of the aforementioned capacitor can use the same insulating layer.

[0041] In one aspect of the display device of the present invention, the other electrode of the capacitor is used as a third wiring extending in a second direction. That is, the third wiring extends in a direction parallel to the second wiring, which is used as the gate electrode of the transistor. As described above, the second wiring and the third wiring are disposed on the same formed surface. Therefore, by making the second wiring and the third wiring parallel, short circuits caused by contact between the second wiring and the third wiring can be prevented.

[0042] As described above, compared to arranging the pixel transistors in a region outside the intersection of the first and second wirings and arranging the pixel capacitors in a region that does not overlap with the third wiring, the display device according to one aspect of the present invention can improve the pixel aperture ratio. Therefore, the power consumption of the display device can be reduced. Furthermore, high-brightness image display can be achieved without increasing power consumption.

[0043] An opening is provided in the insulating layer having a region that serves as the dielectric of the capacitor, leading to a conductive layer that serves as an electrode of the capacitor. Furthermore, a pixel electrode of the liquid crystal element is provided such that it has a region inside the opening that contacts the conductive layer. In a display device according to one aspect of the present invention, the pixel electrode may have a region overlapping with a third wiring. Therefore, in addition to the conductive layer, the pixel electrode can also be used as an electrode of the capacitor. Thus, compared to the case where the pixel electrode does not overlap with the third wiring, the capacitance value can be increased without increasing the capacitor's footprint. Furthermore, the capacitor's footprint can be reduced without decreasing the capacitance value. Therefore, the pixel aperture ratio can be improved.

[0044] <Example 1 of the structure of a display device> Figure 1A This is a block diagram illustrating a structural example of a display device 10 according to one aspect of the present invention. The display device 10 includes a display unit 20, a scan line driving circuit 11, a signal line driving circuit 13, and a circuit 15. The display unit 20 includes a plurality of pixels 21 arranged in a matrix of m rows and n columns. Here, the pixel 21 in the first row and first column is denoted as pixel 21[1, 1], and the pixel 21 in the m row and n column is denoted as pixel 21[m, n].

[0045] In this specification and accompanying drawings, when multiple constituent elements use the same symbol and it is necessary to distinguish them, sometimes the symbol is supplemented with, for example, "_1", "[1]", "[1,1]" or "...". <1> Identification symbols such as "". In addition, when describing the common content among multiple constituent elements with attached identification symbols, or when it is not necessary to distinguish them, sometimes identification symbols are not attached and the description is written without them.

[0046] The scan line driving circuit 11 is electrically connected to the pixel 21 via wiring 41. Wiring 41 extends in the row direction of the matrix described above. Here, wiring 41 electrically connected to the pixel 21 in the first row is denoted as wiring 41[1]. Furthermore, wiring 41 electrically connected to the pixel 21 in the second row is denoted as wiring 41[2]. Moreover, wiring 41 electrically connected to the pixel 21 in the m-th row is denoted as wiring 41[m].

[0047] The signal line driving circuit 13 is electrically connected to the pixel 21 via wiring 43. Wiring 43 extends in the column direction of the matrix described above. Here, wiring 43 electrically connected to the pixel 21 in the first column is referred to as wiring 43[1]. In addition, wiring 43 electrically connected to the pixel 21 in the second column is referred to as wiring 43[2]. In addition, wiring 43 electrically connected to the pixel 21 in the (n-1)th column is referred to as wiring 43[n-1]. Furthermore, wiring 43 electrically connected to the pixel 21 in the nth column is referred to as wiring 43[n]. Note that the row direction and the column direction can be perpendicular to each other.

[0048] Circuit 15 is electrically connected to pixel 21 via wiring 45. Wiring 45 extends in the row direction of the aforementioned matrix. Note that in Figure 1A The diagram shows an example where the wiring 45 in each row is not electrically connected to each other, but they can also be electrically connected to each other. For example, the wiring 45 in each row can be electrically connected to each other inside the circuit 15.

[0049] Pixel 21 includes a display element that can display an image on display unit 20. For example, a liquid crystal element can be used as the display element. Alternatively, a light-emitting element, such as an organic EL element, can be used as the display element.

[0050] The scan line driving circuit 11, for example, has the function of selecting pixels 21 for writing image data line by line. Specifically, the scan line driving circuit 11 can select pixels 21 for writing image data by outputting signals to the wiring 41. Here, the scan line driving circuit 11 outputs the above signal to the wiring 41[1] after outputting the above signal to the wiring 41[2], and outputs the above signal to the wiring 41[m] in sequence, thereby selecting all pixels 21. Thus, the signal output by the scan line driving circuit 11 to the wiring 41 is a scan signal, and the wiring 41 can be said to be a scan line.

[0051] The signal line driving circuit 13 has the function of writing image data. The image data is supplied to the pixels 21 through wiring 43. For example, image data can be written to all pixels 21 included in the row selected by the scan line driving circuit 11. Here, the image data can be represented as a signal (image signal). Thus, wiring 43 can be considered a signal line.

[0052] Circuit 15 has the function of generating a power supply potential and supplying it to wiring 45. Therefore, circuit 15 is also referred to as a power supply circuit. Circuit 15, for example, has the function of generating a low power supply potential (hereinafter also simply referred to as "low potential" or "VSS") and supplying it to wiring 45. In addition, circuit 15 may also have the function of generating a high power supply potential (hereinafter also simply referred to as "high potential" or "VDD"). Wiring 45 is supplied with a power supply potential, and thus wiring 45 can be referred to as a power supply line.

[0053] Figure 1B This is a plan view showing an example of the structure of pixel 21. Pixel 21 includes multiple sub-pixels 23. Figure 1B An example is shown where pixel 21 includes sub-pixels 23R, 23G, and 23B. Note that in... Figure 1BSub-pixels 23R, 23G, and 23B have the same or substantially the same planar shapes, but one aspect of the invention is not limited thereto. The planar shapes of sub-pixels 23R, 23G, and 23B can be suitably determined. The planar shapes of sub-pixels 23R, 23G, and 23B can be different from each other, or two or more of them can be the same or substantially the same.

[0054] In this specification, for example, when describing the common content among subpixels 23R, 23G, and 23B, the letter distinguishing them is sometimes omitted and they are simply referred to as subpixel 23. When describing the common content among other constituent elements distinguished by letters, symbols with omitted letters are sometimes used.

[0055] exist Figure 1B In the pixel 21 shown, the sub-pixels 23 are arranged in a stripe pattern. Alternatively, the sub-pixels 23 can be arranged in an S-stripe pattern, matrix pattern, Delta pattern, Bayer pattern, or Pentile pattern, etc. An example of the planar shape of the sub-pixels and the arrangement of the sub-pixels can be found in Embodiment 3.

[0056] Subpixels 23R, 23G, and 23B emit light of different colors. Examples of subpixels 23R, 23G, and 23B include subpixels of three colors: red (R), green (G), and blue (B), as well as subpixels of three colors: yellow (Y), cyan (C), and magenta (M). Furthermore, more than four subpixels 23 can be provided in pixel 21. For example, subpixels of four colors: R, G, B, and white (W) can be provided in pixel 21. Thus, by including multiple subpixels 23 that emit light of different colors in pixel 21, the display device 10 can display a full-color image on the display unit 20. Additionally, subpixels of R, G, B, and infrared (IR) light can also be provided in pixel 21.

[0057] Alternatively, the display unit 20 may also be equipped with a sensor, for example, a sensor may be provided in the pixel 21. For example, the display unit 20 may also have the function of a fingerprint sensor. For example, the display unit 20 may also have the function of an optical or ultrasonic fingerprint sensor.

[0058] Figure 1C This is a circuit diagram showing an example of the structure of sub-pixel 23. Figure 1C The sub-pixel 23 shown includes pixel circuit 40 and liquid crystal element 70.

[0059] Pixel circuit 40 includes transistor 51 and capacitor 57. That is, pixel circuit 40 is a 1Tr1C type pixel circuit. Note that in... Figure 1CTransistor 51 is an n-channel transistor, but it can also be a p-channel transistor. The same applies to other transistors shown in this specification.

[0060] In pixel circuit 40, one of the source and drain of transistor 51 is electrically connected to wiring 43. The other of the source and drain of transistor 51 is electrically connected to one electrode of capacitor 57. One electrode of capacitor 57 is electrically connected to one electrode of liquid crystal element 70. The gate of transistor 51 is electrically connected to wiring 41. The other electrode of capacitor 57 is electrically connected to wiring 45. The other electrode of liquid crystal element 70 is electrically connected to wiring 47. Wiring 47 is used as a power supply line. Here, one electrode of liquid crystal element 70 is also referred to as the pixel electrode. Alternatively, the other electrode of liquid crystal element 70 is sometimes referred to as the common electrode. In addition, in pixel circuit 40, wiring 45 and wiring 47 can be supplied with a low power supply potential, for example.

[0061] In the pixel circuit 40, transistor 51 is used as a switch, which controls the conduction and non-conductivity states between wiring 43 and one electrode of liquid crystal element 70 according to the potential of wiring 41. When transistor 51 is turned on, image data is written to pixel circuit 40, and when transistor 51 is turned off, the written image data is retained.

[0062] The capacitor 57 has the function of maintaining the potential of one electrode of the liquid crystal element 70. The orientation state of the liquid crystal element 70 is controlled according to the potential corresponding to the image data supplied to one electrode of the liquid crystal element 70.

[0063] The liquid crystal element 70 can be configured in the following modes, for example: TN (Twisted Nematic) mode; STN (Super-Twisted Nematic) mode; VA (Vertical Alignment) mode; ASM (Axially Symmetric Aligned Micro-cell) mode; OCB (Optically Compensated Birefringence) mode; FLC (Ferroelectric Liquid Crystal) mode; AFLC (Anti-Ferroelectric Liquid Crystal) mode; MVA (Multidomain Vertical Alignment) mode; PVA (Patterned Vertical Alignment) mode; IPS (In Plane Switching) mode; FFS (Fringe Field Switching) mode; or TBA (Transverse Bend Alignment) mode, etc. Other examples include ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, and guest-host mode. Note that this is not a limitation; various modes can be used.

[0064] An OS transistor is preferably used as transistor 51. The source-drain leakage current (also called off-state current) of an OS transistor in its off-state state is significantly small. Therefore, by using an OS transistor as transistor 51, the charge stored in capacitor 57 can be maintained for a longer period. Thus, image data written to sub-pixel 23 can be maintained for a longer period, thereby reducing the frequency of refresh operations (writing image data to sub-pixel 23 again). This reduces the power consumption of the display device 10.

[0065] <Example 1 of semiconductor device structure> Figure 2A1This is a plan view illustrating a structural example of a semiconductor device included in a display device according to one aspect of the present invention, specifically a plan view illustrating a structural example of a transistor 50 and its surrounding structure included in a display device according to one aspect of the present invention. Figure 2B yes Figure 2A1 The cross-sectional view shown is the dotted-dotted line A1-A2. Note that in... Figure 2A1 In the diagram, for example, some components of transistor 50, such as insulating layers, are omitted. Regarding the plan view of the transistor, the following figures also omit some components such as insulating layers.

[0066] For example, transistor 50 can be used as a transistor included in pixel 21. For example, transistor 50 can be used as transistor 51. In addition, transistor 50 can also be used as at least a portion of the transistors included in scan line drive circuit 11, signal line drive circuit 13, and circuit 15.

[0067] In a semiconductor device included in a display device according to one aspect of the present invention, an insulating layer 103 and a transistor 50 are disposed on a substrate 101. The insulating layer 103 serves as a spacer. Note that an insulating layer may also be disposed between the substrate 101 and the transistor 50 and the insulating layer 103. This insulating layer serves as a base insulating layer. Furthermore, at least one of electrodes, wiring, transistors, capacitors, and resistors may be disposed between the substrate 101 and the transistor 50 and the insulating layer 103. For example, a first base insulating layer may be disposed on the substrate 101, a layer with wiring (also called a wiring layer) may be disposed on the first base insulating layer, and a second base insulating layer may be disposed on the wiring layer. Note that... Figure 2B An example of a three-layer stacked structure is shown, comprising insulating layer 103a, insulating layer 103b on insulating layer 103a, and insulating layer 103c on insulating layer 103b. The insulating layer 103 also has a three-layer stacked structure in the cross-sectional view below. Details of insulating layers 103a, 103b, and 103c will be described later.

[0068] The transistor 50 includes a conductive layer 111, a conductive layer 112, a semiconductor layer 113, an insulating layer 105, and a conductive layer 115. Figure 2A1 An example is shown in which conductive layer 112 extends in a direction parallel to conductive layer 111 and in a direction perpendicular to conductive layer 115.

[0069] exist Figure 2A1 and Figure 2BIn the diagram, as shown on the coordinate axes, the direction in which the conductive layer 111 extends is the X direction. Additionally, the direction perpendicular to the X direction and, for example, parallel to the top surface of the substrate 101 is the Y direction, and the direction perpendicular to the top surface of the substrate 101 is the Z direction. In the following figures, the definitions of the X, Y, and Z directions may sometimes be the same and sometimes different. For example, sometimes the extension direction of the conductive layer 111 is set to the Y direction. The X, Y, and Z directions can be mutually perpendicular.

[0070] Conductive layer 111 is used as one of the source and drain electrodes of transistor 50. Conductive layer 112 is used as the other of the source and drain electrodes of transistor 50. Insulating layer 105 is used as the gate insulating layer of transistor 50. Conductive layer 115 is used as the gate electrode of transistor 50.

[0071] In semiconductor layer 113, the entire area between the source electrode and the drain electrode, where the gate insulating layer overlaps with the gate electrode, is used as the channel formation region. Furthermore, in semiconductor layer 113, the region in contact with the source electrode is used as the source region, and the region in contact with the drain electrode is used as the drain region.

[0072] A conductive layer 111 is disposed on a substrate 101, an insulating layer 103 is disposed on the substrate 101 and the conductive layer 111, and a conductive layer 112 is disposed on the insulating layer 103. The conductive layers 111 and 112 have regions that overlap each other through the insulating layer 103. Figure 2B As shown, conductive layer 111 is disposed below insulating layer 103, and conductive layer 112 is disposed above insulating layer 103. Therefore, conductive layer 111 can be considered as the lower electrode of transistor 50, and conductive layer 112 can be considered as the upper electrode of transistor 50. Here, the thickness of insulating layer 103, which is used as a spacer, can be made thicker than the thickness of insulating layer 105, which is used as the gate insulating layer of transistor 50.

[0073] The insulating layer 103 includes an opening 121 that extends into the conductive layer 111. The conductive layer 112 includes an opening 123 that extends into the opening 121. That is, the opening 123 has a region that overlaps with the opening 121.

[0074] exist Figure 2A1 In the diagram, conductive layer 111, conductive layer 112, semiconductor layer 113, conductive layer 115, opening 121, and opening 123 are shown as components of transistor 50. Here, Figure 2A2 It was omitted. Figure 2A1 The diagram shows a structural example of the conductive layer 115 among the constituent elements. That is, Figure 2A2 The diagram shows conductive layer 111, conductive layer 112, semiconductor layer 113, opening 121, and opening 123. Additionally, Figure 2A3 It was omitted. Figure 2A2The diagram shows a structural example of the semiconductor layer 113 among the constituent elements. That is, Figure 2A3 The conductive layer 111, conductive layer 112, opening 121, and opening 123 are shown.

[0075] like Figure 2A3 and Figure 2B As shown, conductive layer 112 includes an opening 123 in the region overlapping with conductive layer 111. For example... Figure 2A3 As shown, the conductive layer 112 may have a structure that covers the entire outer periphery of the opening 121 when viewed from a planar perspective. Preferably, the conductive layer 112 is not disposed inside the opening 121. That is, the conductive layer 112 preferably does not contact the side surface of the insulating layer 103 on the side of the opening 121.

[0076] Figure 2A1 , Figure 2A2 and Figure 2A3 An example is shown where both openings 121 and 123 are circular when viewed from a planar perspective. By making the planar shapes of openings 121 and 123 circular, the machining accuracy during their formation can be improved, allowing for the formation of finer openings 121 and 123. Note that in this specification, the circular shape is not limited to a perfect circle. Furthermore, the planar shapes of openings 121 and 123 may also be elliptical, for example.

[0077] Figure 2B An example is shown where the end of the conductive layer 112 at the opening 123 side is the same as or substantially the same as the end of the insulating layer 103 at the opening 121 side. The planar shape of the opening 123 can also be said to be the same as or substantially the same as the planar shape of the opening 121. Note that in this specification, the end of the conductive layer 112 at the opening 123 side refers to the bottom surface end of the conductive layer 112 at the opening 123 side. The bottom surface of the conductive layer 112 refers to the surface of the insulating layer 103 side. The end of the insulating layer 103 at the opening 121 side refers to the top surface end of the insulating layer 103 at the opening 121 side. The top surface of the insulating layer 103 refers to the surface of the conductive layer 112 side. Furthermore, the planar shape of the opening 123 refers to the planar shape of the bottom surface end of the conductive layer 112 at the opening 123 side. The planar shape of the opening 121 refers to the planar shape of the top end of the opening 121 on one side of the insulating layer 103.

[0078] Note that end alignment or approximate alignment can also be described as end-aligned or approximately aligned. In cases of end-aligned or approximate alignment, and in cases of consistent or approximate planar shapes, it can be said that, when viewed from the plane, at least a portion of its edges overlaps with each other between the stacked layers. For example, this includes cases where the upper and lower layers are processed from the same mask pattern or a portion thereof. However, strictly speaking, sometimes the edges do not overlap and the upper layer is inside or outside the lower layer; in such cases, it can also be said that the ends are approximately aligned or the planar shapes are approximately consistent.

[0079] The opening 121 can be formed, for example, using a photoresist mask used to form the opening 123. Specifically, first, a conductive layer 111 is formed on a substrate 101, and then an insulating layer 103, a conductive film that will become a conductive layer 112 on the insulating layer 103, and a photoresist mask on the conductive film are formed on the substrate 101 and the conductive layer 111. The opening 123 is formed in the conductive film using the photoresist mask, and then the opening 121 is formed in the insulating layer 103 using the photoresist mask, thereby making the end of the opening 121 coincide with or substantially coincide with the end of the opening 123. By adopting this structure, the process can be simplified.

[0080] Semiconductor layer 113 is disposed such that it covers openings 121 and 123 and has regions located inside openings 121 and 123. Semiconductor layer 113 has a shape that extends along the top and side surfaces of conductive layer 112, the side surface of insulating layer 103, and the top surface of conductive layer 111. Semiconductor layer 113, for example, has regions that contact the top and side surfaces of conductive layer 112, the side surface of insulating layer 103, and the top surface of conductive layer 111.

[0081] The semiconductor layer 113 preferably covers the end portion of the conductive layer 112 on one side of the opening 123. For example, Figure 2B This illustrates a structure where the end of the semiconductor layer 113 is located on the conductive layer 112. Alternatively, the end of the semiconductor layer 113 can be described as being in contact with the top surface of the conductive layer 112.

[0082] For example, in Figure 2B In this embodiment, semiconductor layer 113 has a single-layer structure, but this is not the only aspect of the invention. Semiconductor layer 113 may also have a stacked structure of two or more layers.

[0083] An insulating layer 105, serving as the gate insulating layer of transistor 50, is disposed such that it covers openings 121 and 123 and has regions located inside openings 121 and 123. The insulating layer 105 is disposed on semiconductor layer 113, conductive layer 112, and insulating layer 103. The insulating layer 105 may have regions that contact the top and side surfaces of semiconductor layer 113, conductive layer 112, and insulating layer 103. The insulating layer 105 has a shape that follows the shape of the top surface of insulating layer 103, the top and side surfaces of conductive layer 112, and the top and side surfaces of semiconductor layer 113.

[0084] A conductive layer 115, serving as the gate electrode of transistor 50, is disposed on insulating layer 105 and may have a region that contacts the top surface of insulating layer 105. The conductive layer 115 has a region that overlaps with semiconductor layer 113 across insulating layer 105.

[0085] For example, such as Figure 2B As shown, the conductive layer 115 is provided in such a manner that it has a region located inside the opening 121 and a region located inside the opening 123, and has a region sandwiching the insulating layer 105 and the semiconductor layer 113 opposite each other. Furthermore, in Figure 2B In the example shown, conductive layer 115 has a region that overlaps with conductive layers 111 and 112, separated by insulating layer 105 and semiconductor layer 113. Furthermore, conductive layer 115 covers the entire semiconductor layer 113. By employing this structure, a gate electric field can be applied to the entire semiconductor layer 113, thereby improving the electrical characteristics of transistor 50, for example, increasing the transistor's on-state current. Additionally, by providing an insulating layer 103 between conductive layers 111 and 115 in addition to the insulating layer 105 used as a gate insulating layer, the parasitic capacitance formed between conductive layers 111 and 115 is reduced, for example, compared to the case where only insulating layer 103 is provided between conductive layers 111 and 115.

[0086] Transistor 50 is a so-called top-gate transistor with a gate electrode above semiconductor layer 113. Furthermore, since the bottom surface of semiconductor layer 113 has a region that contacts the source electrode and the drain electrode, it can be described as a TGBC (Top Gate Bottom Contact) transistor.

[0087] Here, refer to Figure 3A and Figure 3B Explain the channel length and channel width of transistor 50. Figure 3A It is shown Figure 2A1 An enlarged plan view of the transistor 50 and its surrounding structure. Figure 3B yes Figure 3A The cross-sectional view shown is the dotted-dash line A3-A4.

[0088] In the semiconductor layer 113, the region in contact with the conductive layer 111 is used as one of the source region and the drain region, the region in contact with the conductive layer 112 is used as the other of the source region and the drain region, and the region between the source region and the drain region is used as the channel formation region.

[0089] The channel length of transistor 50 is the distance between the source and drain regions. Figure 3B The double arrows in the diagram represent the channel length L50 of transistor 50. The channel length L50, when viewed in cross-section, is the distance between the end of the region where semiconductor layer 113 contacts conductive layer 111 and the end of the region where semiconductor layer 113 contacts conductive layer 112.

[0090] Here, the channel length L50 of transistor 50 is equivalent to the length of the side surface of the insulating layer 103 on the side of the opening 121 when viewed from the XZ plane. That is, the channel length L50 is determined by the thickness T103 of the insulating layer 103 and the angle θ103 formed by the side surface of the insulating layer 103 on the side of the opening 121 and the surface of the insulating layer 103 to which it is formed (here, the top surface of the conductive layer 111), and is not affected by the performance of the exposure apparatus used for transistor fabrication. Therefore, the channel length L50 can be set to be smaller than the limiting resolution of the exposure apparatus, enabling the realization of miniature transistors. For example, the channel length L50 is preferably 0.01 μm or more and less than 3.0 μm, more preferably 0.05 μm or more and less than 3.0 μm, more preferably 0.10 μm or more and less than 3.0 μm, more preferably 0.15 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 2.5 μm, more preferably 0.20 μm or more and less than 2.0 μm, more preferably 0.20 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.2 μm, more preferably 0.40 μm or more and less than 1.2 μm, more preferably 0.40 μm or more and less than 1.0 μm, and more preferably 0.50 μm or more and less than 1.0 μm.

[0091] exist Figure 3B In the diagram, a double arrow indicates the thickness T103 of the insulating layer 103. Note that... Figure 3B An example is shown where the insulating layer 103 has a three-layer stacked structure comprising an insulating layer 103a, an insulating layer 103b on the insulating layer 103a, and an insulating layer 103c on the insulating layer 103b. Here, the thickness of the insulating layer 103a is denoted as thickness T103a, the thickness of the insulating layer 103b is denoted as thickness T103b, and the thickness of the insulating layer 103c is denoted as thickness T103c.

[0092] By reducing the channel length L50, the on-state current of transistor 50 can be increased. Therefore, by using transistor 50 as a transistor included in display device 10, such as the transistor included in pixel 21, display device 10 can be driven at high speed.

[0093] The channel length L50 can be controlled by adjusting the thickness T103 and angle θ103 of the insulating layer 103.

[0094] The thickness T103 of the insulating layer 103 is preferably 0.01 μm or more and less than 3.0 μm, more preferably 0.05 μm or more and less than 3.0 μm, more preferably 0.10 μm or more and less than 3.0 μm, more preferably 0.15 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 2.5 μm, more preferably 0.20 μm or more and less than 2.0 μm, more preferably 0.20 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.2 μm, more preferably 0.40 μm or more and less than 1.2 μm, more preferably 0.40 μm or more and less than 1.0 μm, and more preferably 0.50 μm or more and less than 1.0 μm.

[0095] The side surface of the insulating layer 103 with opening 121 preferably has a tapered shape. The angle θ103 formed between the side surface of the insulating layer 103 with opening 121 and the surface on which the insulating layer 103 is formed (here, the top surface of the conductive layer 111) is preferably less than 90 degrees. By reducing the angle θ103, the coverage of the layer (e.g., semiconductor layer 113) disposed on the insulating layer 103 can be improved. However, sometimes the contact area between the semiconductor layer 113 and the conductive layer 111 becomes smaller due to the reduction of the angle θ103, thus increasing the contact resistance between the semiconductor layer 113 and the conductive layer 111. The angle θ103 is preferably 45 degrees or more and less than 90 degrees, more preferably 50 degrees or more and less than 90 degrees, more preferably 55 degrees or more and less than 90 degrees, more preferably 60 degrees or more and less than 90 degrees, more preferably 60 degrees or more and less than 85 degrees, more preferably 65 degrees or more and less than 85 degrees, more preferably 65 degrees or more and less than 80 degrees, and more preferably 70 degrees or more and less than 80 degrees. By setting the angle θ103 within the above range, the coverage of the layer (e.g., semiconductor layer 113) formed on the conductive layer 111 and the insulating layer 103 can be improved while shortening the channel length of the transistor 50, thereby suppressing defects such as breaks or voids in the layer. In addition, the contact resistance between the semiconductor layer 113 and the conductive layer 111 can be reduced.

[0096] In this specification and the like, "disconnection" refers to the phenomenon where a layer, film, or electrode is broken due to the shape of the surface to which it is formed (e.g., a step).

[0097] Note, for example, in Figure 3B The diagram shows a structure in which the shape of the side surface of the insulating layer 103 on the side of the opening 121 is straight when viewed in cross-section, but one aspect of the invention is not limited to this. The shape of the side surface of the insulating layer 103 on the side of the opening 121 when viewed in cross-section may also be curved, and may include both a region with a straight side surface and a region with a curved side surface.

[0098] The channel width of transistor 50 is the width of the source region or the width of the drain region in a direction orthogonal to the channel length direction. That is, the channel width is the width of the region where semiconductor layer 113 contacts conductive layer 111 or the width of the region where semiconductor layer 113 contacts conductive layer 112 in a direction orthogonal to the channel length direction. Here, the channel width of transistor 50 will be described as the width of the region where semiconductor layer 113 contacts conductive layer 112 in a direction orthogonal to the channel length direction. Figure 3A and Figure 3B The solid double arrow in the middle represents the channel width W50 of transistor 50. The channel width W50, when viewed from the plane, is the length of the bottom end of the conductive layer 112 on the side of the opening 123.

[0099] The channel width W50 is determined by the planar shape of the opening 123. Figure 3A and Figure 3B The width D123 of the opening 123 is indicated by a double arrow. The width D123 refers to the shorter side of the smallest rectangle that is circumscribed by the opening 123 when viewed from a plane. When the opening 123 is formed by photolithography, the width D123 of the opening 123 is above the limit resolution of the exposure device. The width D123 is preferably 0.20 μm or more and less than 5.0 μm, more preferably 0.20 μm or more and less than 4.5 μm, more preferably 0.20 μm or more and less than 4.0 μm, more preferably 0.20 μm or more and less than 3.5 μm, more preferably 0.20 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 2.5 μm, more preferably 0.20 μm or more and less than 2.0 μm, more preferably 0.20 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.2 μm, more preferably 0.40 μm or more and less than 1.2 μm, more preferably 0.40 μm or more and less than 1.0 μm, and more preferably 0.50 μm or more and less than 1.0 μm. Note that when the planar shape of the opening 123 is circular, the width D123 is equivalent to the diameter of the opening 123, and the channel width W50 can be equal to the length of the outer perimeter of the opening 123 when viewed from the plane, which can be calculated as "D123×π".

[0100] <Example 1 of pixel structure> Figure 4A It is shown Figure 1C A plan view of an example structure of subpixel 23. Figure 4B It is represented by a dashed line. Figure 4A The pixel electrode of the liquid crystal element 70 in the sub-pixel 23 shown is a plan view with the shaded lines of the pixel electrode omitted. Figure 5A yes Figure 4A and Figure 4B The cross-sectional view shown by the dotted line B1-B2 illustrates an example of the structure of transistor 51, capacitor 57, and liquid crystal element 70. (See diagram below.) Figure 5A As shown, transistor 51, capacitor 57 and liquid crystal element 70 are disposed between substrate 101 and substrate 141.

[0101] Figure 4A , Figure 4B and Figure 5A In the example shown, the structure of transistor 51 is similar to... Figure 2A1 and Figure 2B The structure of the transistor 50 shown is the same. Here, the conductive layer 111, conductive layer 112, semiconductor layer 113, and conductive layer 115 included in the transistor 51 are conductive layer 111a, conductive layer 112a, semiconductor layer 113a, and conductive layer 115a, respectively. In addition, the opening 121 and opening 123 provided in the transistor 51 are opening 121a and opening 123a, respectively.

[0102] The capacitor 57 includes a conductive layer 112a on the insulating layer 103, an insulating layer 105 on the conductive layer 112a, and a conductive layer 116 disposed on the insulating layer 105 and having a region overlapping with the conductive layer 112a. The conductive layer 112a serves as one electrode of the capacitor 57. The insulating layer 105 serves as the dielectric of the capacitor 57. The conductive layer 116 serves as the other electrode of the capacitor 57. As described above, the same conductive layer 112a can be used for the other of the source and drain electrodes of the transistor 51 and one electrode of the capacitor 57. Furthermore, the same insulating layer 105 can be used for the gate insulating layer of the transistor 51 and the dielectric of the capacitor 57. Moreover, the conductive layer 116 can be formed on the same surface as the conductive layer 115a used as the gate electrode of the transistor 51. Therefore, the conductive layer 116 can contain the same material as the conductive layer 115a and can be formed by the same process. For example, the conductive layers 115a and 116 can be formed by processing the same conductive film.

[0103] At least a portion of the conductive layer 111a is used as wiring 43 with signal line function, and is Figure 1AThe signal line driving circuit 13 shown is electrically connected. At least a portion of the conductive layer 115a is used as wiring 41 with scan line function, and is connected to... Figure 1A The scan line drive circuit 11 shown is electrically connected. At least a portion of the conductive layer 116 is used as wiring 45, which functions as a power line, and is connected to... Figure 1A The circuit 15 shown is electrically connected.

[0104] Wiring 43 extends in the first direction. Furthermore, wiring 41 and wiring 45 extend in a second direction perpendicular to the first direction. In this specification, the region of conductive layer 111a extending in the first direction is used as wiring 43. Furthermore, the region of conductive layer 115a extending in the second direction is used as wiring 41. Moreover, the region of conductive layer 116 extending in the second direction is used as wiring 45. Figure 4A and Figure 4B In the diagram, the first direction is the Y direction, and the second direction is the X direction.

[0105] Sub-pixel 23 has an area where wiring 41 and wiring 43 overlap, and an area where wiring 45 and wiring 43 overlap. In other words, sub-pixel 23 has an area where wiring 41 and wiring 43 intersect, and an area where wiring 45 and wiring 43 intersect. Furthermore, sub-pixel 23 has a junction of wiring 41 and wiring 43, and a junction of wiring 45 and wiring 43.

[0106] Openings 121a and 123a, and a semiconductor layer 113a are disposed at the intersection of wiring 41 and wiring 43. Therefore, a transistor 51 is disposed at the intersection of wiring 41 and wiring 43. As described above, the transistor 51 includes wiring 41 used as a gate electrode, wiring 43 used as one of a source electrode and a drain electrode, a conductive layer 112a used as the other of the source electrode and drain electrode, a semiconductor layer 113a, and an insulating layer 105 used as a gate insulating layer.

[0107] The region of conductive layer 112a used as an electrode of capacitor 57 has a region that overlaps with wiring 45. That is, the region of conductive layer 112a used as an electrode of capacitor 57 has a region that overlaps with the region of conductive layer 116 used as wiring 45. As described above, capacitor 57 includes conductive layer 112a, insulating layer 105 on conductive layer 112a, and wiring 45 on insulating layer 105.

[0108] As described above, at least a portion of the conductive layer 116 used as wiring 45 is disposed on the same surface as the conductive layer 115a, which is at least a portion used as wiring 41. Thus, by arranging wiring 41 and wiring 45 in a direction parallel to each other, it is possible to prevent short circuits caused by contact between conductive layer 115a and conductive layer 116.

[0109] As described above, in the sub-pixels 23 included in the display device 10, transistors 51 are provided at the intersection of wiring 41 used as scan lines and wiring 43 used as signal lines. Furthermore, capacitors 57 are provided in the area overlapping with wiring 45 used as power lines. Therefore, compared to providing transistors 51 in areas other than the intersections of wiring 41 and 43 and providing capacitors 57 in areas not overlapping with wiring 45, the aperture ratio of the sub-pixels 23 can be increased. Thus, the aperture ratio of the pixel 21 including the sub-pixels 23 can be increased. Therefore, the display device 10 can be a low-power display device. Furthermore, the display device 10 displays high-brightness images without increasing power consumption.

[0110] An insulating layer 107 is provided on conductive layers 115a and 116 and insulating layer 105. That is, an insulating layer 107 is provided on wiring 41, wiring 45 and insulating layer 105. The insulating layer 107 serves as a barrier layer to suppress impurities from the outside, for example, diffusing into transistor 51. A liquid crystal element 70 is provided on the insulating layer 107.

[0111] The liquid crystal element 70 includes a pixel electrode 131 and a common electrode 139, and a liquid crystal 135 is disposed between the pixel electrode 131 and the common electrode 139. An insulating layer 133 is disposed between the pixel electrode 131 and the liquid crystal 135, and an insulating layer 137 is disposed between the liquid crystal 135 and the common electrode 139. The insulating layers 133 and 137 are used as alignment films.

[0112] Insulating layers 105 and 107 include an opening 125 reaching the conductive layer 112a. A pixel electrode 131 is disposed to cover the opening 125. The pixel electrode 131 has a shape along the top and side surfaces of the insulating layer 107, the side surfaces of the insulating layer 105, and the top surface of the conductive layer 112a. The pixel electrode 131 has a region that contacts the top surface of the conductive layer 112a inside the opening 125. The pixel electrode 131 may have a region that contacts the top surface of the insulating layer 107, a region that contacts the side surface of the insulating layer 107, a region that contacts the side surface of the insulating layer 105, and a region that contacts the top surface of the conductive layer 112a. Note that in Figure 4A and Figure 4B Although the opening 125 is a rectangle with rounded corners when viewed from a plane, one aspect of the invention is not limited to this and may have the same shape as the opening 121 or the opening 123.

[0113] Here, the pixel electrode 131 preferably has a region that overlaps with the conductive layer 116 across the insulating layer 107. Specifically, the pixel electrode 131 preferably has a region that overlaps with the region of the conductive layer 116 that is used as wiring 45. Thus, in addition to the conductive layer 112a, the pixel electrode 131 can also be used as an electrode of the capacitor 57. In this case, in addition to the insulating layer 105, the insulating layer 107 can also be used as the dielectric of the capacitor 57. In other words, the capacitor 57 can have a structure in which a capacitor composed of the conductive layer 112a, the insulating layer 105, and the conductive layer 116 is connected in parallel with a capacitor composed of the pixel electrode 131, the insulating layer 107, and the conductive layer 116. Note that when the pixel electrode 131 has a region that overlaps with the wiring 45 across the insulating layer 107, the insulating layer 107 can be said to be disposed on the wiring 41, the wiring 45, and the insulating layer 105 and has a region located between the wiring 45 and the pixel electrode 131.

[0114] As described above, compared to the case where the pixel electrode 131 does not overlap with the wiring 45, when the pixel electrode 131 has a region that overlaps with the wiring 45 through the insulating layer 107, the capacitance value can be increased without increasing the occupied area of ​​the capacitor 57. Furthermore, the occupied area of ​​the capacitor 57 can be reduced without decreasing the capacitance value. Therefore, the aperture ratio of the sub-pixel 23 and the aperture ratio of the pixel 21 can be improved. Note that the pixel electrode 131 may also not overlap with the wiring 45.

[0115] Furthermore, by providing the opening 125 in a manner that reaches the conductive layer 112a, for example, compared to providing the opening 125 in a manner that reaches the conductive layer 111a, the depth of the opening 125 can be shallower. Therefore, the depth of the recess formed in the layer overlapping the opening 125 can be shallower, improving the flatness of the layer. This makes it easier to manufacture the display device 10.

[0116] A light-shielding layer 145, a coloring layer 143, a protective layer 147, a common electrode 139, an insulating layer 149, and an insulating layer 137 are sequentially disposed on one side of the substrate 101 of the substrate 141. The coloring layer 143 is disposed in the area of ​​the display section 20 where the light-shielding layer 145 is not disposed. The end of the coloring layer 143 overlaps with the end of the light-shielding layer 145.

[0117] When the display device 10 is a transmissive liquid crystal display device, a backlight (not shown) is provided in the display device 10. The backlight can be provided on one side of the substrate 101, specifically, it can be provided on the outer side of the substrate 101 (on the side opposite to the formation surface of the transistor 51). Note that when the display device 10 is a reflective liquid crystal display device, the backlight may not be provided in the display device 10.

[0118] The common electrode 139 is made of a material with high transmittance to visible light. Furthermore, when the display device 10 is a transmissive liquid crystal display device, the pixel electrode 131 is made of a material with high transmittance to visible light. When the display device 10 is a reflective liquid crystal display device, the pixel electrode 131 is made of a material with high reflectivity to visible light.

[0119] The coloring layer 143 includes a region overlapping with the liquid crystal element 70, and the transmittance of a specific color of light is higher than that of other colors of light. Therefore, the light emitted by the liquid crystal element 70 having the region overlapping with the coloring layer 143 is extracted as light of that specific color and released to the outside of the display device 10. This specific color can be red, green, or blue. Alternatively, it can be yellow, cyan, or magenta.

[0120] The protective layer 147, for example, functions as a cover layer to suppress the diffusion of components contained in the coloring layer 143 into the liquid crystal element 70. Here, it is preferred that the protective layer 147 is planarized, for example, that an insulating layer 149 can be easily formed on the protective layer 147. Note that the protective layer 147 may also not be planarized.

[0121] Examples of materials that can be used for the coloring layer 143 include metallic materials, resin materials, and resin materials containing pigments or dyes. The coloring layer 143 can be formed, for example, using an inkjet printing method.

[0122] An insulating layer 149 may be provided in at least a portion of the area overlapping with the light-shielding layer 145. The insulating layer 149 is a columnar spacer obtained by selectively etching the insulating layer, which is provided to control the spacing (cell gap) between the pixel electrode 131 and the common electrode 139. Note that the insulating layer 149 may also be a spherical spacer.

[0123] Figure 5B yes Figure 4A and Figure 4B The cross-sectional view shown is along the dotted lines B3-B4, illustrating a structural example of the intersection of wiring 43 and wiring 45. (See diagram below.) Figure 5BAs shown, insulating layers 103 and 105 are provided between wiring 43, which is used as a signal line, and wiring 45, which is used as a power line. On the other hand, when wiring 43 is provided on the same surface as conductive layer 112a, i.e., between insulating layers 103 and 105, the insulating layer between wiring 43 and wiring 45 is, for example, only insulating layer 105. Therefore, by using conductive layer 111a as wiring 43, the parasitic capacitance formed between wiring 43 and wiring 45 is reduced, for example, compared to when conductive layer 112a is used as wiring 43. As a result, the charging time required for wiring 43 can be shortened. Therefore, display device 10 can be a high-speed driven display device. Note that conductive layer 112a can be used as wiring 43. In this case, opening 125 is provided in insulating layers 103, 105, and 107 to reach conductive layer 111a. Furthermore, pixel electrode 131 is electrically connected to conductive layer 111a.

[0124] Figure 6A and Figure 6B Show respectively Figure 5A and Figure 5B An example is shown where an insulating layer 109 is provided on an insulating layer 107. Figure 6A and Figure 6B In the example shown, insulating layer 133 is disposed on insulating layer 109.

[0125] In addition, Figure 6A In the example shown, in addition to insulating layers 105 and 107, insulating layer 109 also has an opening 125. Figure 6A In the example shown, the pixel electrode 131 has a shape along the top and side surfaces of the insulating layer 109, the side surface of the insulating layer 107, the side surface of the insulating layer 105, and the top surface of the conductive layer 112a. The pixel electrode 131 may have a region contacting the top surface of the insulating layer 109, a region contacting the side surface of the insulating layer 109, a region contacting the side surface of the insulating layer 107, a region contacting the side surface of the insulating layer 105, and a region contacting the top surface of the conductive layer 112a. Furthermore, the pixel electrode 131 may have a region overlapping the wiring 45 with the insulating layer 107 and the insulating layer 109. In this case, in addition to the insulating layers 105 and 107, the insulating layer 109 can also serve as the dielectric of the capacitor 57.

[0126] The insulating layer 109 functions as a planarization layer. By providing the insulating layer 109 on the insulating layer 107, unevenness caused by transistor 51, capacitor 57, etc., can be reduced. Therefore, for example, the liquid crystal element 70 can be easily manufactured. On the other hand, for example, by employing... Figure 5AThe structure shown without the insulating layer 109 can shorten the distance between the wiring 45 and the pixel electrode 131 in the area where the wiring 45 overlaps with the pixel electrode 131. This allows for an increase in the capacitance value of the capacitor 57.

[0127] Figure 7A It is shown Figure 1C A plan view of an example structure of subpixel 23. Figure 7B It is represented by a dashed line. Figure 7A The plan view of wiring 41, wiring 45 and pixel electrode 131 in sub-pixel 23, with their shaded lines omitted.

[0128] Figure 7A and Figure 7B The following example is shown: Figure 4A The conductive layer 111a shown has a region (protrusion) protruding in the X direction, and conductive layer 112a, semiconductor layer 113a, wiring 41, opening 121a, and opening 123a are disposed in a manner overlapping the protrusion. Figure 7A and Figure 7B In the example shown, a transistor 51 is disposed in the area where the protrusion of the conductive layer 111a overlaps with the wiring 41.

[0129] exist Figure 7A and Figure 7B In the example shown, for example with Figure 4A Compared to the example shown, the area of ​​the overlapping region between conductive layer 112a and conductive layer 115a can be reduced. Therefore, the parasitic capacitance formed between conductive layer 112a and conductive layer 115a can be reduced. Therefore, the charging time required for, for example, wiring 41 can be shortened. As described above, the display device 10 can be driven at high speed. On the other hand, for example... Figure 4A In the example shown, with Figure 7A and Figure 7B The example shown can be compared to miniaturizing subpixel 23 to allow for a high-density configuration of pixel 21 including subpixel 23.

[0130] Figure 8A It shows that, apart from Figure 7A A plan view of an example where a transistor is also provided at the intersection of wiring 41 and wiring 43, in addition to the protrusion of conductive layer 111a. Figure 8B It is represented by a dashed line. Figure 8A The plan view of wiring 41, wiring 45 and pixel electrode 131 in sub-pixel 23, with their shaded lines omitted. Figure 9A yes Figure 8A and Figure 8B The cross-sectional view shown is the dotted line B1-B2.

[0131] exist Figure 8A , Figure 8B and Figure 9A In the example shown, transistor 51_1 is disposed at the intersection of wiring 41 and wiring 43, and transistor 51_2 is disposed at the protrusion of conductive layer 111a. Conductive layer 111a serves as one of the source and drain electrodes of transistor 51_1 and one of the source and drain electrodes of transistor 51_2. Conductive layer 112a serves as the other of the source and drain electrodes of transistor 51_1 and the other of the source and drain electrodes of transistor 51_2. Conductive layer 115a serves as the gate electrode of both transistor 51_1 and transistor 51_2. Semiconductor layer 113a_1, opening 121a_1, and opening 123a_1 are disposed on transistor 51_1. Semiconductor layer 113a_2, opening 121a_2, and opening 123a_2 are disposed on transistor 51_1. Note that in Figure 9A The diagram shows a structural example where an insulating layer 109 is provided on the insulating layer 107, but the insulating layer 109 may not be provided.

[0132] Figure 9B This is a circuit diagram illustrating the transistor 51. (For example...) Figure 9B As shown, in Figure 8A , Figure 8B and Figure 9A In the example shown, transistor 51 can be considered as transistors 51_1 and 51_2 whose source, drain, and gate electrodes are connected in parallel. Figure 9B As shown, conductive layer 111a can be considered as one of the source and drain electrodes of transistor 51. Furthermore, conductive layer 112a can be considered as the other of the source and drain electrodes of transistor 51. Moreover, conductive layer 115a can be considered as the gate electrode of transistor 51.

[0133] In transistor 51, there is Figures 8A to 9BIn the structure shown, the sum of the channel widths of transistor 51_1 and 51_2 can be considered as the channel width of transistor 51. Therefore, compared to the case where one opening 121a and one opening 123 are provided in transistor 51, the channel width of transistor 51 can be increased. This increases the on-state current of transistor 51, allowing for high-speed writing of image data to sub-pixels 23. Thus, the display device 10 can be driven at high speed. On the other hand, when one opening 121a and one opening 123 are provided in transistor 51, for example, compared to the case where two openings 121a and two openings 123 are provided in transistor 51, the occupied area of ​​transistor 51 can be reduced. Therefore, sub-pixels 23 can be miniaturized, allowing for high-density configuration of pixels 21 including sub-pixels 23. Note that three or more semiconductor layers 113a, three or more openings 121a, and three or more openings 123a can also be provided in transistor 51. The channel width of transistor 51 can be further increased by increasing the number of openings 121a and 123a, etc.

[0134] Furthermore, a semiconductor layer 113a may be located inside a plurality of openings 121a and a plurality of openings 123a. For example, openings 121a_1 and 123a_1, and openings 121a_2 and 123a_2 may also share the semiconductor layer 113a.

[0135] Figure 10A It is shown Figure 8A A plan view of an example where the conductive layer 111a of transistor 51_1 is separated from the conductive layer 111a of transistor 51_2. Figure 10B It is represented by a dashed line. Figure 10A The plan view of wiring 41, wiring 45 and pixel electrode 131 in sub-pixel 23, with their shaded lines omitted. Figure 11A yes Figure 10A and Figure 10B The cross-sectional view shown is the dotted line B1-B2. Figure 10A , Figure 10B and Figure 11A In the example shown, the conductive layer 111a included in transistor 51_1 is designated as conductive layer 111a_1, and the conductive layer 111a included in transistor 51_2 is designated as conductive layer 111a_2. Note that... Figure 11A An example of a structure is shown where an insulating layer 109 is provided on the insulating layer 107, but the insulating layer 109 may not be provided.

[0136] At least a portion of the conductive layer 111a_1 is used as wiring 43. Furthermore, openings 125 leading to the conductive layer 111a_2 are provided in insulating layers 103, 105, 107, and 109. A pixel electrode 131 is disposed such that it has a region located inside the opening 125. The pixel electrode 131 has a region that contacts the conductive layer 111a_2 inside the opening 125.

[0137] Figure 11B This is a circuit diagram illustrating the transistor 51. (For example...) Figure 11B As shown, in Figure 10A , Figure 10B and Figure 11A In the example shown, transistor 51 can be considered as transistors 51_1 and 51_2 connected in series through conductive layer 112a. Figure 11B As shown, conductive layer 111a_1 can be considered as one of the source and drain electrodes of transistor 51. Furthermore, conductive layer 111a_2 can be considered as the other of the source and drain electrodes of transistor 51. Moreover, conductive layer 115a can be considered as the gate electrode of transistor 51.

[0138] In transistor 51, there is Figures 10A to 11B In the structure shown, the sum of the channel lengths of transistor 51_1 and transistor 51_2 can be considered as the channel length of transistor 51. Therefore, compared to the case where one opening 121a and one opening 123 are provided in transistor 51, the channel length of transistor 51 can be increased. This reduces the off-state current of transistor 51 and maintains the charge accumulated in capacitor 57 for a longer period. Therefore, the image data written to sub-pixel 23 can be maintained for a longer period, thus reducing the refresh frequency. This reduces the power consumption of display device 10. Note that three or more openings 121a and three or more openings 123a can also be provided in transistor 51. This further increases the channel length of transistor 51.

[0139] Furthermore, a single semiconductor layer 113a may be located inside a plurality of openings 121a and a plurality of openings 123a. For example, openings 121a_1 and 123a_1, and openings 121a_2 and 123a_2 may also share the semiconductor layer 113a.

[0140] Figures 8A to 11B The structure of transistor 51 shown can be applied to another transistor included in display device 10. For example, when sub-pixel 23 includes a transistor other than transistor 51, it can be... Figures 8A to 11B The structure of transistor 51 shown is applied to this transistor. Furthermore, it can be... Figures 8A to 11BThe structure of transistor 51 shown is applied to at least a portion of the transistors included in the scan line drive circuit 11, the transistors included in the signal line drive circuit 13, and the transistors included in the circuit 15.

[0141] Figures 4A to 6B An example is shown in which the conductive layer 112a does not overlap with the wiring 43 in the area outside the intersection of wiring 41 and wiring 43, but one aspect of the invention is not limited to this. Figure 12A It is shown Figure 4B The plan view shows an example of conductive layer 112a having an area overlapping with wiring 43 in the region between wiring 41 and wiring 45 and at the intersection of wiring 43 and wiring 45. Figure 12B yes Figure 12A The cross-sectional view shown by the dotted lines B5-B6, in addition to illustrating structural examples of transistor 51, capacitor 57, and liquid crystal element 70, also illustrates a structural example of the intersection of wiring 43 and wiring 45. Note that... Figure 12B An example of a structure is shown where an insulating layer 109 is provided on the insulating layer 107, but the insulating layer 109 may not be provided.

[0142] Figure 12A An example is shown where the conductive layer 112a does not overlap with the wiring 41 in the area outside the intersection of wiring 41 and wiring 43. On the other hand, Figure 4B An example is shown in which the conductive layer 112a has a region that overlaps with the wiring 41 in the area outside the intersection of wiring 41 and wiring 43.

[0143] and Figure 4B Compared to sub-pixel 23 shown, Figure 12A The sub-pixel 23 shown can increase the area of ​​the region where the pixel electrode 131 is disposed but where the conductive layers 111a, 112a, 115a, and 116 are not disposed, when viewed from a planar perspective. Therefore, the aperture ratio of the sub-pixel 23 can be increased. On the other hand, compared with... Figure 12A Compared to sub-pixel 23 shown, Figure 4B The sub-pixel 23 shown can reduce the area of ​​the region where the wiring 43 overlaps with the conductive layer 112a. Therefore, noise caused by the conductive layer 112a in the image data supplied to the sub-pixel 23 through the wiring 43 can be suppressed. As a result, the display device 10 can display high-quality images.

[0144] Figure 13A It is shown Figure 1C A plan view of an example structure of subpixel 23. Figure 13B It is shown by dashed lines. Figure 13A The pixel electrode 131 in the sub-pixel 23 shown is a plan view with the shaded lines of the pixel electrode 131 omitted.

[0145] Figure 13A and Figure 13B Show Figure 4A The conductive layer 111a shown has a region protruding in the X direction (first protrusion), and the conductive layer 115a has a region protruding in the -Y direction (second protrusion). Furthermore, Figure 13A and Figure 13B An example is shown where a conductive layer 112a, a semiconductor layer 113a, an opening 121a, and an opening 123a are provided in the area where the first protrusion and the second protrusion overlap.

[0146] Figure 13A and Figure 13B In the example shown, a transistor 51 is disposed in the area where the first protrusion and the second protrusion overlap. Furthermore, in Figure 13A and Figure 13B In the example shown, when viewed from the plane, an opening 125 is provided in the area between wiring 41 and wiring 45.

[0147] exist Figure 13A and Figure 13B In the example shown, for example with Figure 4A Compared to the example shown, the area of ​​the overlapping region between conductive layer 112a and conductive layer 115a can be reduced. Therefore, the parasitic capacitance formed between conductive layer 112a and conductive layer 115a can be reduced. Therefore, for example, the charging time required for wiring 41 can be shortened. As described above, the display device 10 can be driven at high speed. On the other hand, for example... Figure 4A In the example shown, with Figure 13A and Figure 13B Compared to the example shown, subpixel 23 can be miniaturized to allow for a high-density configuration of pixels 21 including subpixel 23.

[0148] Figure 14A and Figure 14B They are shown respectively Figure 4A and Figure 12A The diagram shows an example of a pixel electrode 131 having a region overlapping with wiring 41 and a region overlapping with wiring 43. Note that in Figure 14A and Figure 14B The pixel electrode 131 is shaded with a solid line.

[0149] Figure 14A and Figure 14B The example shown is similar to Figure 4A and Figure 12A Compared to the example shown, the aperture ratio of sub-pixel 23 can be increased. For example, by using a material that is transparent to visible light as wiring 41 and wiring 43, compared to... Figure 4A and Figure 12AThe example shown can improve the aperture ratio of sub-pixel 23. On the other hand, Figure 4A and Figure 12A The example shown is similar to Figure 14A and Figure 14B Compared to the example shown, the area where the pixel electrode 131 overlaps with other conductive layers can be reduced. Therefore, noise generated in the pixel data supplied to the sub-pixel 23 can be suppressed, and the display device 10 can display high-quality images.

[0150] Figure 15A This shows what it looks like when viewed from a plane. Figure 14A The plan view shows an example where the opening 125 is located in the area between the wiring 41 and the wiring 45. Figure 15B It is represented by a dashed line. Figure 15A The pixel electrode 131 in the sub-pixel 23 shown is a plan view with the shaded lines of the pixel electrode 131 omitted.

[0151] exist Figure 15A and Figure 15B The example shown is similar to Figure 14A Compared to the example shown, the area of ​​the region where the pixel electrode 131 and the conductive layer 112a are stacked can sometimes be reduced. Therefore, the aperture ratio of the sub-pixel 23 can sometimes be increased. On the other hand, Figure 14A The example shown is similar to Figure 15A and Figure 15B Compared to the example shown, it is sometimes easier to form an opening 125 while reducing the distance between wiring 41 and wiring 45.

[0152] Figure 16A It is shown that... Figure 1C Circuit diagrams of different structural examples of sub-pixels 23. Figure 16A An example is shown where the other electrode of capacitor 57 and the other electrode of liquid crystal element 70 are common electrodes 46. That is, Figure 16A This illustrates an example where the other electrode of capacitor 57 and the common electrode of liquid crystal element 70 are the same electrode.

[0153] Figure 16B It is shown Figure 16A A plan view of an example structure of subpixel 23. Figure 16B An example of the structure of transistor 51 is shown. Note that... Figure 16B The opening 125 is also shown. Figure 16B An example is shown in which the conductive layer 112a has a region that overlaps with the wiring 43 in a region other than the intersection of wiring 41 and wiring 43, and the opening 125 is provided in a manner that overlaps with this region.

[0154] Figure 16C In addition to showing Figure 16BIn addition to the elements shown, a common electrode 46 is also shown. The common electrode 46 can be disposed over the entire surface of the sub-pixel 23. For example, the common electrode 46 can be disposed on... Figure 1A The entire surface of the display section 20 shown. For example... Figure 16C As shown, the common electrode 46 includes an opening 127 having a region that overlaps with the opening 125.

[0155] Figure 16D Showing the Figure 16C The figure shown includes the addition of pixel electrode 131. Figure 16D The pixel electrode 131 shown has a planar shape with multiple slits. Note that the pixel electrode 131 may also have a comb-like planar shape.

[0156] exist Figure 16C and Figure 16D Although the opening 127 is rectangular when viewed from a plane, one aspect of the invention is not limited to this and may have the same shape as the opening 121, opening 123 or opening 125.

[0157] Figure 17A Show Figure 16D The cross-sectional view shown by the dotted lines B7-B8 illustrates transistor 51, capacitor 57, and liquid crystal element 70. Figure 17A An example is shown where an insulating layer 109 is disposed on an insulating layer 107, and a liquid crystal element 70 is disposed on the insulating layer 109. Therefore, Figure 17A It can be said that Figure 6A Examples of variations of the structure are shown. Furthermore... Figure 17A It can be said that Figure 12B Examples of variations of the structure shown.

[0158] Figure 17A The liquid crystal element 70 shown includes a common electrode 46, an insulating layer 151 on the common electrode 46, a pixel electrode 131 on the insulating layer 151, and liquid crystal 135 on the pixel electrode 131. Figure 17A The liquid crystal element 70 shown is a liquid crystal element employing the FFS mode. As described above, the common electrode 46 includes an opening 127 having a region overlapping with the conductive layer 112a. A material with high transmittance to visible light can be used as the common electrode 46.

[0159] The insulating layer 151 is provided such that it covers the side of the opening 127 of the common electrode 46. Openings 125 leading to the conductive layer 112a are provided in the insulating layers 105, 107, 109, and 151. The pixel electrode 131 is provided such that it has a region located inside the opening 125. The pixel electrode 131 has a region inside the opening 125 that contacts the conductive layer 112a.

[0160] As described above, when viewed from a planar perspective, the opening 125 is arranged to overlap with the opening 127. This prevents the pixel electrode 131, which is arranged with a region located inside the opening 125, from coming into contact with the common electrode 46 and short-circuiting.

[0161] An insulating layer 133 is provided between the pixel electrode 131 and the insulating layer 151 and the liquid crystal 135. In addition, an insulating layer 137 is provided on the liquid crystal 135.

[0162] A light-shielding layer 145, a coloring layer 143, a protective layer 147, an insulating layer 149, and an insulating layer 137 are sequentially disposed on one side of the substrate 101 of the substrate 141. The coloring layer 143 is disposed such that it has a region that overlaps with the common electrode 46 and the pixel electrode 131.

[0163] The pixel electrode 131 may have a slit-like or comb-like shape in the area overlapping with the color layer 143 when viewed from a planar perspective. Therefore, the common electrode 46 has an area that overlaps with the color layer 143 but does not overlap with the pixel electrode 131.

[0164] A capacitor 57 is formed by overlapping the common electrode 46 and the pixel electrode 131 with an insulating layer 151 in the area therebetween. The pixel electrode serves as one electrode, the common electrode 46 as the other electrode, and the insulating layer 151 as the dielectric. Therefore, for example, it is not necessary to separately place the capacitor 57 outside the liquid crystal element 70. This improves the aperture ratio of the sub-pixel 23 and the aperture ratio of the pixel 21. Furthermore, the thickness of the insulating layer 109 can be increased, for example, by a factor greater than [missing value]. Figure 6A and Figure 12B The thickness of the insulating layer 109 shown. By increasing the thickness of the insulating layer 109, the distance between the conductive layer 115a and the common electrode 46 can be increased, and the parasitic capacitance formed between the conductive layer 115a and the common electrode 46 can be reduced. On the other hand, having Figure 6A and Figure 12B The display device with the structure shown, including sub-pixel 23, and having Figure 17A Compared to display devices with sub-pixel 23 of the structure shown, high-contrast images can be displayed.

[0165] Figure 17B It shows from Figure 17A A cross-sectional view of the structural example of insulating layer 109 is omitted. Figure 17B It can also be said that Figure 5A Examples of variations of the structure shown.

[0166] By providing the insulating layer 109 on the insulating layer 107, the unevenness caused by the transistor 51 and capacitor 57 can be reduced as described above, thereby making it easier to manufacture the liquid crystal element 70, for example. On the other hand, by not providing the insulating layer 109, the number of manufacturing steps of the display device 10 can be reduced.

[0167] Figure 18A1 Show Figure 16B The conductive layer 111a shown has a region (protrusion) protruding in the X direction, and the conductive layer 112a, semiconductor layer 113a, wiring 41, opening 121a and opening 123a are arranged in a manner that overlaps with the protrusion. Figure 18A2 It is represented by a dashed line. Figure 18A1 The diagram showing wiring 41 omits the shaded areas. Figure 18A1 and Figure 18A2 In the example shown, a transistor 51 is disposed in the area where the protrusion of the conductive layer 111a overlaps with the wiring 41.

[0168] Figure 18B1 Show Figure 16B The conductive layer 111a shown has a region protruding in the X direction (first protrusion), and the conductive layer 115a has a region protruding in the -Y direction (second protrusion). Furthermore, Figure 18B1 An example is shown where a conductive layer 112a, a semiconductor layer 113a, an opening 121a, and an opening 123a are provided in the area where the first protrusion and the second protrusion overlap.

[0169] Figure 18B2 It is represented by a dashed line. Figure 18B1 The diagram showing wiring 41 omits the shaded areas. Figure 18B1 and Figure 18B2 In the example shown, a transistor 51 is disposed in the area where the first protrusion and the second protrusion overlap.

[0170] exist Figures 18A1 to 18B2 In the example shown, for example with Figure 16B Compared to the example shown, the area of ​​the overlapping region between conductive layers 111a and 112a can be reduced. Therefore, the parasitic capacitance formed between conductive layers 111a and 112a can be reduced. Thus, for example, the charging time required for wiring 43 can be shortened. As described above, the display device 10 can be driven at high speed. On the other hand, for example... Figure 16B The example shown is similar to Figures 18A1 to 18B2 Compared to the example shown, subpixel 23 can be miniaturized to allow for a high-density configuration of pixels 21 including subpixel 23.

[0171] Figure 19 The structure of the liquid crystal element 70 is shown. Figure 17AExamples of different structures are shown.

[0172] Figure 19 The liquid crystal element 70 shown has a pixel electrode 131, an insulating layer 151 on the pixel electrode 131, and a common electrode 46 on the insulating layer 151. That is to say... Figure 19 The liquid crystal element 70 shown illustrates the positional relationship between the pixel electrode and the common electrode with respect to the insulating layer 151. Figure 17A The liquid crystal element 70 shown is a contrasting example.

[0173] An opening 125 is provided in insulating layers 105, 107, and 109. The common electrode 46 has a slit-like or comb-like shape in the area where it overlaps with the color layer 143 when viewed from the plane. Therefore, the pixel electrode 131 overlaps with the color layer 143 but not with the common electrode 46 in that area.

[0174] Figure 20A , Figure 20B , Figure 20C and Figure 20D This is a plan view showing an example of the structure of transistor 51. Figure 20A and Figure 20D The conductive layer 115a is represented by a dashed line, and the shaded line of the conductive layer 115a is omitted.

[0175] Figure 20A An example is shown where the entire semiconductor layer 113a overlaps with conductive layers 112a and 115a. Figure 20A In the structure shown, an electric field can be applied to the entire semiconductor layer 113a by the conductive layer 115a, which serves as the gate electrode of the transistor 51.

[0176] Figure 20B An example is shown where a portion of the semiconductor layer 113a does not overlap with the conductive layer 115a. Figure 20B The structure shown is Figure 20A Compared to the structure shown, the width (length in the Y direction) of the conductive layer 115a can be reduced, and the area of ​​the overlapping region between the conductive layer 115a and the conductive layer 112a can be reduced. Therefore, the parasitic capacitance formed between the conductive layers 115a and 112a can be reduced.

[0177] Figure 20C An example is shown where a portion of openings 121a and 123a does not overlap with the conductive layer 115a when viewed in plan view. Figure 20C The structure shown is Figure 20B Compared to the structure shown, the width of the conductive layer 115a can be reduced, and the area of ​​the overlapping region between the conductive layer 115a and the conductive layer 112a can be reduced. Therefore, compared to... Figure 20BCompared to the structure shown, the parasitic capacitance formed between conductive layer 115a and conductive layer 112a can be further reduced.

[0178] Figure 20D An example is shown where a portion of semiconductor layer 113a does not overlap with conductive layers 112a and 115a. Figure 20D The example shown is similar to Figure 20A , Figure 20B and Figure 20C Compared to the example shown, the area of ​​semiconductor layer 113a can be increased. Therefore, semiconductor layer 113a can be easily manufactured.

[0179] Figures 20A to 20D The structure shown can be used for transistors other than transistor 51. For example, Figures 20A to 20D The structure shown can also be used for the transistors included in the scan line drive circuit 11, signal line drive circuit 13, or circuit 15.

[0180] Figure 21A and Figure 21B They are shown respectively Figure 4B and Figure 12A The diagram shows an example of a semiconductor layer 113a having a region overlapping with wiring 45. Figure 21A and Figure 21B An example is shown where the semiconductor layer 113a has a region overlapping the intersection of wiring 43 and wiring 45. Specifically, an example is shown where the semiconductor layer 113a extends in the -Y direction to the intersection of wiring 43 and wiring 45.

[0181] <Example 2 of pixel structure> In addition to being used in display devices that include liquid crystal elements as display elements, this invention can also be used in display devices that include light-emitting elements. Figure 22A , Figure 22B , Figure 22C , Figure 22D and Figure 23 This is a circuit diagram showing an example of the structure of sub-pixel 23, in which an example of a light-emitting element 60 is shown as a display element. Figure 22A The sub-pixel 23 shown includes pixel circuit 40A and light-emitting element 60.

[0182] Pixel circuit 40A includes transistor 59, transistor 52, and capacitor 69. That is to say, pixel circuit 40A is a 2Tr1C type pixel circuit.

[0183] In pixel circuit 40A, one of the source and drain of transistor 59 is electrically connected to wiring 43. The other of the source and drain of transistor 59 is electrically connected to the gate of transistor 52. The gate of transistor 52 is electrically connected to one electrode of capacitor 69. The gate of transistor 59 is electrically connected to wiring 41.

[0184] One of the source and drain terminals of transistor 52 is electrically connected to wiring 45. The other of the source and drain terminals of transistor 52 is electrically connected to another electrode of capacitor 69. The other electrode of capacitor 69 is electrically connected to one electrode of light-emitting element 60. The other electrode of light-emitting element 60 is electrically connected to wiring 47. Here, one electrode of light-emitting element 60 is referred to as the pixel electrode. Additionally, since wiring 47 can be shared among all sub-pixels 23, for example, the other electrode of light-emitting element 60 can be referred to as the common electrode.

[0185] As described above, wiring 41 is used as a scan line, wiring 43 is used as a signal line, and wiring 45 is used as a power line. Additionally, wiring 47 is used as a power line, for example, when wiring 45 is supplied with a high power supply potential, wiring 47 is supplied with a low power supply potential. Wiring 47 can, for example, be electrically connected to circuit 15.

[0186] Transistor 59 is used as a switch, also known as a selection transistor. Transistor 59 has the function of controlling the on and off states between the gate of wiring 43 and transistor 52 according to the potential of wiring 41. When transistor 59 is in the on state, image data is written to pixel circuit 40A, and when transistor 59 is in the off state, the written image data is retained.

[0187] Transistor 52, also known as a driving transistor, controls the amount of current flowing through the light-emitting element 60. Capacitor 69 maintains the gate potential of transistor 52. The brightness of the light-emitting element 60 is controlled based on the potential supplied to the gate of transistor 52 corresponding to the image data. Specifically, when wiring 45 is supplied with a high power supply potential and wiring 47 is supplied with a low power supply potential, the magnitude of the current flowing from wiring 45 to wiring 47 is controlled according to the gate potential of transistor 52, thereby controlling the brightness of the light-emitting element 60.

[0188] OS transistors are preferably used as transistors 59 and 52. For example, OS transistors have higher field-effect mobility than transistors using amorphous silicon. Therefore, by using OS transistors as transistors 59 and 52, the display device 10 can be driven at high speed.

[0189] Furthermore, as mentioned above, the off-state current of the OS transistor is significantly small. Therefore, by using the OS transistor as transistor 59, the charge stored in capacitor 69 can be maintained for a longer period. Thus, image data written to sub-pixel 23 can be maintained for an extended period, thereby reducing the refresh frequency. This, in turn, reduces the power consumption of the display device 10.

[0190] To increase the brightness of the light-emitting element 60, it is necessary to increase the current flowing through it. This requires increasing the source-drain voltage of the driving transistor 52. Because the source-drain breakdown voltage of an OS transistor is higher than that of a silicon transistor (also known as a Si transistor), a higher voltage can be applied between its source and drain. Therefore, by using an OS transistor as transistor 52, the current flowing through the light-emitting element 60 can be increased, thereby increasing its brightness.

[0191] When the transistor is driven in the saturation region, the OS transistor allows for a smaller change in the source-drain current in response to changes in the gate-source voltage, compared to a Si transistor. Therefore, by using an OS transistor as transistor 52, the current flowing through the source-drain can be determined precisely based on the change in the gate-source voltage. This allows for precise control of the amount of current flowing through the light-emitting element 60. Consequently, the brightness of the light emitted by the sub-pixel 23 can be precisely controlled. This, in turn, increases the number of grayscale values ​​that the sub-pixel 23 can display.

[0192] Regarding the saturation characteristics of the current flowing through a transistor when driven in the saturation region, compared to a Si transistor, an OS transistor can maintain a stable current (saturation current) even when the source-drain voltage is gradually increased. Therefore, by using an OS transistor as transistor 52, even if the current-voltage characteristics of the light-emitting element 60 are non-uniform for each light-emitting element 60, a stable current can still flow through the light-emitting element 60. In other words, when driven in the saturation region, the source-drain current remains almost unchanged even when the source-drain voltage is increased, thus stabilizing the brightness of the light-emitting element 60.

[0193] As described above, by using the OS transistor as transistor 52, it is possible to achieve "suppression of black blur", "increase in light emission brightness", "multi-grayscale conversion" and "suppression of light emission brightness of light emission element 60 non-uniformly per light emission element 60".

[0194] As the light-emitting element 60, OLED (Organic Light Emitting Diode) or QLED (Quantum-dot Light Emitting Diode) are preferably used, for example. Examples of light-emitting materials contained in the light-emitting element 60 include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (e.g., quantum dot materials). Furthermore, LEDs such as micro-LEDs (Light Emitting Diodes) can also be used as the light-emitting element 60.

[0195] Figure 22B The sub-pixel 23 shown includes a pixel circuit 40B and a light-emitting element 60. The pixel circuit 40B has a structure in which a transistor 53 is added to the pixel circuit 40A. The pixel circuit 40B is a 3Tr1C type pixel circuit.

[0196] In pixel circuit 40B, the gate of transistor 59 is electrically connected to wiring 41a. One of the source and drain of transistor 53 is electrically connected to the other of the source and drain of transistor 52, the other electrode of capacitor 69, and one electrode of light-emitting element 60. The other of the source and drain of transistor 53 is electrically connected to wiring 48. The gate of transistor 53 is electrically connected to wiring 41b. That is, as wiring 41 used as a scan line, wiring 41a and wiring 41b are electrically connected to pixel circuit 40B.

[0197] Transistor 53 is used as a switch, which controls the conduction and non-conductivity states between wiring 48 and one electrode of the light-emitting element 60 according to the potential of wiring 41b. Wiring 48 is supplied with a reference potential, for example. Based on the reference potential of wiring 48 supplied through transistor 53, the non-uniformity of the gate-source potential of each transistor 52 can be suppressed.

[0198] Furthermore, the current value of wiring 48 can be used to set pixel parameters. More specifically, wiring 48 can be used as a monitoring line to output the current flowing through transistor 52 or the current flowing through light-emitting element 60 to the outside of pixel 21. The current output to wiring 48 can be converted to a potential by a source follower circuit, for example, or converted to a digital signal by an AD converter, for example.

[0199] As transistor 53, an OS transistor is preferably used. As mentioned above, for example, OS transistors have higher field-effect mobility compared to transistors using amorphous silicon. Therefore, by using an OS transistor as transistor 53, the display device 10 can be driven at high speed.

[0200] Figure 22C The sub-pixel 23 shown includes a pixel circuit 40C and a light-emitting element 60. The pixel circuit 40C has a structure that adds a transistor 54 and a capacitor 58 to the pixel circuit 40B. The pixel circuit 40C is a 4Tr2C type pixel circuit.

[0201] In pixel circuit 40C, one of the source and drain of transistor 52 is electrically connected to one of the source and drain of transistor 54. The other of the source and drain of transistor 54 is electrically connected to wiring 45. The gate of transistor 54 is electrically connected to wiring 41c. One electrode of capacitor 58 is electrically connected to the other of the source and drain of transistor 52, one of the source and drain of transistor 53, the other electrode of capacitor 69, and one electrode of light-emitting element 60.

[0202] Wiring 41c and Figure 1A The scan line driving circuit 11 shown is electrically connected. That is, in the sub-pixel 23 included by pixel 21, it has... Figure 22C In the structure shown, wiring 41a, wiring 41b and wiring 41c are provided as wiring 41 in the display device 10.

[0203] Transistor 54 is used as a switch, which has the function of controlling the on and off states between wiring 45 and one of the source and drain of transistor 52 according to the potential of wiring 41c.

[0204] When transistor 54 is turned on, a current corresponding to the gate potential of transistor 52 flows, for example, from wiring 45 to wiring 47. As a result, light-emitting element 60 emits light with a brightness corresponding to the gate potential of transistor 52. Conversely, when transistor 54 is turned off, no current flows through light-emitting element 60, thereby preventing light emission from occurring.

[0205] As transistor 54, an OS transistor is preferably used. As mentioned above, for example, OS transistors have higher field-effect mobility compared to transistors using amorphous silicon. Therefore, by using an OS transistor as transistor 54, the display device 10 can be driven at high speed.

[0206] Figure 22D The sub-pixel 23 shown includes a pixel circuit 40D and a light-emitting element 60. The pixel circuit 40D has a structure in which a transistor 54 is added to the pixel circuit 40B. The pixel circuit 40D is a 4Tr1C type pixel circuit.

[0207] In pixel circuit 40D, one of the source and drain of transistor 54 is electrically connected to the other of the source and drain of transistor 59, the gate of transistor 52, and one electrode of capacitor 69. The other of the source and drain of transistor 54 is electrically connected to wiring 49. The gate of transistor 54 is electrically connected to wiring 41c. In sub-pixel 23... Figure 22D In the structure shown, wiring 41a, wiring 41b and wiring 41c are provided as wiring 41 in the display device 10.

[0208] When transistor 54 is turned on, the gate potential of transistor 52 can be the potential of wiring 49. Here, wiring 49 can be supplied with a low potential, for example. As described above, for example, no current flows through the light-emitting element 60, so the light-emitting element 60 does not emit light.

[0209] Figure 23 The sub-pixel 23 shown includes pixel circuit 40E and light-emitting element 60.

[0210] Pixel circuit 40E includes transistors 61, 62, 63, 64, 65, and 66, capacitors 67 and 68. In other words, pixel circuit 40E is a 6Tr2C type pixel circuit.

[0211] In pixel circuit 40E, one of the source and drain of transistor 61 is electrically connected to wiring 45. The other of the source and drain of transistor 61 is electrically connected to one of the source and drain of transistor 62. One of the source and drain of transistor 62 is electrically connected to one of the source and drain of transistor 63. The gate of transistor 61 is electrically connected to wiring 41d.

[0212] The other of the source and drain of transistor 62 is electrically connected to the gate of transistor 63. The gate of transistor 63 is electrically connected to one electrode of capacitor 67. The gate of transistor 62 is electrically connected to wiring 41e.

[0213] One of the source and drain of transistor 64 is electrically connected to wiring 43. The other of the source and drain of transistor 64 is electrically connected to the other of the source and drain of transistor 63. The other of the source and drain of transistor 63 is electrically connected to one of the source and drain of transistor 65. The gate of transistor 64 is electrically connected to wiring 41f.

[0214] One of the source and drain terminals of transistor 65 is electrically connected to one of the source and drain terminals of transistor 66. One of the source and drain terminals of transistor 66 is electrically connected to the other electrode of capacitor 67. The other electrode of capacitor 67 is electrically connected to one electrode of capacitor 68. One electrode of capacitor 68 is electrically connected to one electrode of light-emitting element 60. The gate of transistor 65 is electrically connected to wiring 41g.

[0215] The other of the source and drain of transistor 66 is electrically connected to wiring 48. The gate of transistor 66 is electrically connected to wiring 41e.

[0216] The other electrode of capacitor 68 is electrically connected to wiring 41f. The other electrode of light-emitting element 60 is electrically connected to wiring 47.

[0217] Wiring 41d, wiring 41e, wiring 41f and wiring 41g and Figure 1A The scan line driving circuit 11 shown is electrically connected. That is, when the sub-pixel 23 included in pixel 21 has... Figure 23 In the structure shown, wiring 41d, wiring 41e, wiring 41f and wiring 41g are provided as wiring 41 in the display device 10.

[0218] Transistors 61, 62, 64, 65, and 66 are used as switches. Transistor 61 has the function of controlling the conduction and non-conductivity states between wiring 45 and one of the source and drain of transistor 62, and between the source and drain of transistor 63, according to the potential of wiring 41d. Transistor 62 has the function of controlling the conduction and non-conductivity states between the other of the source and drain of transistor 61, and between one of the source and drain of transistor 63 and the gate of transistor 63 and one electrode of capacitor 67, according to the potential of wiring 41e. Transistor 64 has the function of controlling the conduction and non-conductivity states between wiring 43 and one of the source and drain of transistor 63, and between the source and drain of transistor 65, according to the potential of wiring 41f. Transistor 65 has the function of controlling the conduction and non-conductivity states between the other of the source and drain of transistor 63, and between the other of the source and drain of transistor 64 and one electrode of light-emitting element 60, according to the potential of wiring 41g. Transistor 66 has the function of controlling the conduction and non-conductivity states between wiring 48 and one electrode of light-emitting element 60 according to the potential of wiring 41e.

[0219] Transistors 61 to 66 are preferably OS transistors. For example, OS transistors have higher field-effect mobility than transistors using amorphous silicon. Therefore, by using OS transistors as transistors 61 to 66, the display device 10 can be driven at high speed.

[0220] Figure 24A It is shown Figure 22A A plan view of an example structure of subpixel 23. Figure 24A The pixel electrode of the light-emitting element 60 is represented by a dashed line, and the shadow line of the pixel electrode is omitted. Figure 24B It is represented by a dashed line. Figure 24A The diagram shows the gate electrode of transistor 52, the gate electrode of transistor 59, and the conductive layer formed on the same surface as them in sub-pixel 23, with their shaded plan views omitted. Figure 25 yes Figure 24A and Figure 24B The cross-sectional view shown by the dotted line C1-C2 illustrates a structural example of transistor 52, transistor 59, capacitor 69, and light-emitting element 60. (See diagram below.) Figure 25 As shown, transistor 52, transistor 59, capacitor 69 and light-emitting element 60 are disposed between substrate 101 and substrate 141.

[0221] exist Figure 24A , Figure 24B and Figure 25 In the example shown, the structures of transistors 52 and 59 are similar to... Figure 2A1 and Figure 2B The structure of transistor 50 shown is the same. Here, the conductive layer 111, conductive layer 112, semiconductor layer 113, and conductive layer 115 included in transistor 52 are conductive layer 111b, conductive layer 112b, semiconductor layer 113b, and conductive layer 115b, respectively. Furthermore, the conductive layer 111, conductive layer 112, semiconductor layer 113, and conductive layer 115 included in transistor 59 are conductive layer 111c, conductive layer 112c, semiconductor layer 113c, and conductive layer 115c, respectively. Moreover, the openings 121 and 123 provided in transistor 52 are opening 121b and opening 123b, respectively, and the openings 121 and 123 provided in transistor 59 are opening 121c and opening 123c, respectively.

[0222] The capacitor 69 includes a conductive layer 112b on the insulating layer 103, an insulating layer 105 on the conductive layer 112b, and a conductive layer 115b disposed on the insulating layer 105 and having a region overlapping with the conductive layer 112b. The conductive layer 112b serves as another electrode of the capacitor 69. The insulating layer 105 serves as the dielectric layer of the capacitor 69. The conductive layer 115b serves as one electrode of the capacitor 69. Thus, the same conductive layer 112b can be used for the other of the source and drain electrodes of the transistor 52 and the other electrode of the capacitor 69. Furthermore, the same insulating layer 105 can be used for the gate insulating layer of the transistor 52, the gate insulating layer of the transistor 59, and the dielectric of the capacitor 69. Also, the same conductive layer 115b can be used for the gate electrode of the transistor 52 and one electrode of the capacitor 69.

[0223] Insulating layers 103 and 105 have openings 128 leading to conductive layer 111b. Furthermore, insulating layer 105 has an opening 129 leading to conductive layer 112c. Conductive layer 118 is disposed with a region located inside the opening 128, and conductive layer 115b is disposed with a region located inside the opening 129. Conductive layer 118 has a region inside the opening 128 that contacts the top surface of conductive layer 111b. Conductive layer 115b has a region inside the opening 129 that contacts the top surface of conductive layer 112c. Note that... Figure 24A and Figure 24B In this invention, the openings 128 and 129 are rectangular with rounded corners when viewed from a plane. However, one aspect of the invention is not limited to this, and for example, they may have the same shape as the opening 125.

[0224] At least a portion of the conductive layer 111c is used as wiring 43 with signal line functionality, and is connected to... Figure 1A The signal line driving circuit 13 shown is electrically connected. At least a portion of the conductive layer 115c is used as wiring 41 with scan line function, and is connected to... Figure 1A The scan line drive circuit 11 shown is electrically connected. At least a portion of the conductive layer 118 is used as wiring 45, which functions as a power line, and is connected to... Figure 1A The circuit 15 shown is electrically connected.

[0225] In this specification, the region extending in the first direction of the conductive layer 111c is used as wiring 43. Furthermore, the region extending in the second direction of the conductive layer 115c is used as wiring 41. Moreover, the region extending in the second direction of the conductive layer 118 is used as wiring 45. Figure 24A and Figure 24B In this context, the first direction is set as the Y direction, and the second direction is set as the X direction.

[0226] Openings 121c and 123c, and a semiconductor layer 113c are provided at the intersection of wiring 41 and wiring 43. Therefore, a transistor 59 is provided at the intersection of wiring 41 and wiring 43. Thus, the transistor 59 includes wiring 41 used as a gate electrode, wiring 43 used as one of a source electrode and a drain electrode, a conductive layer 112c used as the other of the source electrode and drain electrode, a semiconductor layer 113c, and an insulating layer 105 used as a gate insulating layer.

[0227] By placing the transistor 59 at the intersection of wiring 41 and wiring 43, the aperture ratio of sub-pixel 23 can be increased compared to placing the transistor 59 in an area outside the intersection of wiring 41 and wiring 43. Therefore, the aperture ratio of pixel 21, including sub-pixel 23, can be increased. As a result, display device 10 can be a low-power display device. Furthermore, display device 10 can display high-brightness images without increasing power consumption.

[0228] A conductive layer 118, at least a portion of which is used as wiring 45, is disposed on the same formed surface as a conductive layer 115c, at least a portion of which is used as wiring 41. Therefore, by arranging wiring 41 and wiring 45 in a parallel direction, short-circuiting due to contact between conductive layer 115c and conductive layer 118 can be prevented. Furthermore, by providing a conductive layer 115b having a region extending in a direction parallel to conductive layers 115c and 118, short-circuiting due to contact between conductive layer 115b and conductive layer 115c can be prevented. Here, since conductive layer 118 is disposed on the same formed surface as conductive layers 115b and 115c, conductive layer 118 can contain the same material as conductive layers 115b and 115c and can be formed using the same process. For example, conductive layers 115b, 115c, and 118 can be formed by processing the same conductive film.

[0229] Figure 24A , Figure 24B and Figure 25 In the sub-pixel 23 shown, the conductive layer 111c disposed under the insulating layer 103 is used as a wiring 43 that functions as a signal line. Therefore, for example, compared to the case where the conductive layer 112c disposed on the insulating layer 103 is used as the wiring 43, the parasitic capacitance formed by the wiring 43 and wiring 45 is reduced. Thus, the charging time required for the wiring 43 can be shortened. Therefore, the display device 10 can be a high-speed driven display device. Note that the conductive layer 112c can be used as the wiring 43. In this case, the opening 129 is provided in the insulating layers 103 and 105 such that it reaches the conductive layer 111c. Furthermore, the conductive layer 115b is electrically connected to the conductive layer 111c.

[0230] Figure 24A , Figure 24B and Figure 25 An example is shown where, outside the intersection of wiring 41 and wiring 43, the conductive layer 112c has a region overlapping with wiring 43 and an opening 129 is provided in a manner that overlaps with this region. Furthermore, Figure 24A , Figure 24B and Figure 25 An example is shown where the conductive layer 112c does not overlap with the wiring 41 in the area other than the intersection of wiring 41 and wiring 43. This reduces the parasitic capacitance formed between wiring 41 and conductive layer 112c. Furthermore, when conductive layer 115b is provided in a direction extending parallel to wiring 41, the wiring distance from transistor 59 to conductive layer 115b can be shortened. Specifically, the distance from the region of conductive layer 112c that contacts semiconductor layer 113c to the region of conductive layer 112c that contacts conductive layer 115b can be shortened.

[0231] An insulating layer 107 is provided on conductive layers 115b, 115c, 118, and insulating layer 105. In other words, an insulating layer 107 is provided on wiring 41, wiring 45, and insulating layer 105. The insulating layer 107 is used as a barrier layer to suppress impurities from the outside, for example, diffusing into transistors 52 and 59.

[0232] An insulating layer 109 is provided on the insulating layer 107. As described above, the insulating layer 109 is used as a planarization layer. An opening 126 is provided in the insulating layer 105, the insulating layer 107 and the insulating layer 109 to reach the conductive layer 112b.

[0233] A light-emitting element 60 is disposed on the insulating layer 109, and a protective layer 331 is disposed to cover the light-emitting element 60. A substrate 141 is attached to the protective layer 331 by an adhesive layer 142.

[0234] The light-emitting element 60 includes a pixel electrode 311 on an insulating layer 107, an island-shaped layer 313 on the pixel electrode 311, and a common electrode 315 on the island-shaped layer 313. Layer 313 includes at least a light-emitting layer. Alternatively, layer 313 may also include one or more of a hole injection layer, a hole transport layer, a hole blocking layer, a charge generation layer, an electron blocking layer, an electron transport layer, and an electron injection layer. Note that layer 313 can be considered an EL layer. Additionally, the common electrode is also referred to as a counter electrode.

[0235] In this specification, the term "island-like" refers to the state in which two or more layers formed in the same process and using the same material are physically separated. For example, an island-like light-emitting layer means that the light-emitting layer is physically separated from the adjacent light-emitting layer.

[0236] Layer 313 can be formed, for example, using a vacuum evaporation method with a high-precision metal mask. In many cases, in the vacuum evaporation method using a high-precision metal mask, evaporation is performed over an area larger than the opening of the high-precision metal mask. Therefore, it is possible to form layer 313 over an area larger than the opening of the high-precision metal mask. Furthermore, the ends of layer 313 are tapered. Here, layer 313 can be formed not only on the pixel electrode 311 but also on the insulating layer 237. Note that layer 313 can also be formed using sputtering or inkjet methods with a high-precision metal mask.

[0237] Figure 25 An example of a top-emission display device 10 is shown. In this case, the light emitted by the light-emitting element 60 is emitted to the substrate 141. Therefore, the substrate 141 is preferably made of a material with high transmittance to visible light. On the other hand, there is no limitation on the transmittance of the material used for the substrate 101. Note that the display device 10 including the light-emitting element 60 can be either bottom-emission or dual-emission. In this case, the light emitted by the light-emitting element 60 is emitted to the substrate 101. Therefore, the substrate 101 is preferably made of a material with high transmittance to visible light. Note that when the display device 10 is bottom-emission, there is no limitation on the transmittance of the material used for the substrate 141.

[0238] When the display device 10 is a top-emitting type, the common electrode 315 is made of a material with high transmittance to visible light. The pixel electrodes 311R, 311G, and 311B are each preferably made of a material with high reflectivity to visible light.

[0239] Pixel electrode 311 is disposed such that it covers opening 126. Pixel electrode 311 has a shape along the top and side surfaces of insulating layer 109, the side surface of insulating layer 107, the side surface of insulating layer 105, and the top surface of conductive layer 112b. Pixel electrode 311 has a region inside opening 126 that contacts the top surface of conductive layer 112b. Pixel electrode 311 may have a region that contacts the top surface of insulating layer 109, a region that contacts the side surface of insulating layer 109, a region that contacts the side surface of insulating layer 107, a region that contacts the side surface of insulating layer 105, and a region that contacts the top surface of conductive layer 112b. Note that in Figure 24A and Figure 24B In the present invention, the opening 126 is a rectangle with rounded corners when viewed from a plane. However, one aspect of the invention is not limited to this and may have the same shape as the opening 125.

[0240] Here, the pixel electrode 311 preferably has a region overlapping the conductive layer 115b with the insulating layer 107 and the insulating layer 109. Thus, besides the conductive layer 112b, the pixel electrode 311 can also serve as another electrode of the capacitor 69. In this case, besides the insulating layer 105, the insulating layers 107 and 109 can also serve as the dielectric of the capacitor 69. In other words, the capacitor 69 can have a structure in which the capacitor composed of the conductive layer 112b, the insulating layer 105, and the conductive layer 115b is connected in parallel with the capacitor composed of the pixel electrode 311, the insulating layer 107, the insulating layer 109, and the conductive layer 115b. Note that when the pixel electrode 311 has a region overlapping the conductive layer 115b with the insulating layer 107 and the insulating layer 109, the insulating layers 107 and 109 are disposed on the wiring 41, the wiring 45, the conductive layer 115b, and the insulating layer 105, and can have a region located between the conductive layer 115b and the pixel electrode 311.

[0241] As described above, compared to the case where the pixel electrode 311 does not overlap with the conductive layer 115b, when the pixel electrode 311 has a region overlapping the conductive layer 115b with the insulating layer 107 and the insulating layer 109, the capacitance value can be increased without increasing the occupied area of ​​the capacitor 69. Furthermore, the occupied area of ​​the capacitor 69 can be reduced without decreasing the capacitance value. Therefore, the aperture ratio of the sub-pixel 23 and the aperture ratio of the pixel 21 can be improved. Here, the thinner the insulating layer 109, the greater the capacitance value of the capacitor composed of the pixel electrode 311, the insulating layer 107, the insulating layer 109, and the conductive layer 115b can be. Thus, the capacitance value of the capacitor 69 can be increased. Note that the pixel electrode 311 may also not overlap with the conductive layer 115b.

[0242] Furthermore, by providing the opening 126 in a manner that reaches the conductive layer 112b, for example, compared to providing the opening 126 in a manner that reaches the conductive layer 111b, the depth of the opening 126 can be shallower. Therefore, the depth of the recess formed in the layer overlapping the opening 126 can be shallower, improving the flatness of the layer. This makes it easier to manufacture the display device 10.

[0243] An insulating layer 237 can be provided to cover the top end of the pixel electrode 311. The insulating layer 237 is used as a partition wall (also called a dike, dam, or spacer). By providing the insulating layer 237, it is possible to prevent the pixel electrode 311 from contacting the common electrode 315 and short-circuiting the light-emitting element 60.

[0244] Note that the pixel electrode 311 may have a region overlapping with wiring 41, wiring 43, or wiring 45. The pixel electrode 311 may also have a region overlapping with transistor 59, for example. Therefore, compared to the case where the pixel electrode 311 does not overlap with wiring 41, 43, and 45, the aperture ratio of the sub-pixel 23 can be increased. On the other hand, for example, when the pixel electrode 311 does not overlap with wiring 41, 43, and 45, the area of ​​the region where the pixel electrode 131 overlaps with other conductive layers can be reduced. Therefore, noise generated in the pixel data supplied to the sub-pixel 23 can be suppressed, and the display device 10 can display a high-quality image.

[0245] Figure 26 Showing with Figure 25 Examples of different structures for the light-emitting element 60 shown. Figure 26 An example is shown of a stacked structure of pixel electrode 311 having a conductive layer 324, a conductive layer 326 on the conductive layer 324, and a conductive layer 329 on the conductive layer 326.

[0246] The conductive layer 324 is provided to cover the opening 126. The conductive layer 324 has a shape along the top and side surfaces of the insulating layer 109, the side surface of the insulating layer 107, the side surface of the insulating layer 105, and the top surface of the conductive layer 112b. The pixel electrode 311 has a region that contacts the top surface of the conductive layer 112b inside the opening 126. The pixel electrode 311 may have a region that contacts the top surface of the insulating layer 109, a region that contacts the side surface of the insulating layer 109, a region that contacts the side surface of the insulating layer 107, a region that contacts the side surface of the insulating layer 105, and a region that contacts the top surface of the conductive layer 112b.

[0247] The end of conductive layer 326 is located inside the end of conductive layer 324 and the end of conductive layer 329. That is, the end of conductive layer 326 is located on conductive layer 324, and the top and side surfaces of conductive layer 326 are covered by conductive layer 329.

[0248] There are no particular restrictions on the transmittance and reflectivity of the conductive layer 324 to visible light. The conductive layer 324 can be a conductive layer that is transmittance to visible light or a conductive layer that is reflective to visible light.

[0249] Conductive layer 326 may use a conductive layer that is reflective to visible light. Conductive layer 326 may also have a stacked structure of a conductive layer that is transparent to visible light and a reflective conductive layer on top of that conductive layer. Conductive layer 326 may use materials suitable for conductive layer 324. Specifically, conductive layer 326 is suitable for a stacked structure of In-Si-Sn oxide (ITSO) or an alloy of silver, palladium, and copper (APC) on In-Si-Sn oxide (ITSO).

[0250] The conductive layer 329 can use the same material as the conductive layer 324. For example, the conductive layer 329 can be a conductive layer that is transparent to visible light. Specifically, the conductive layer 329 can use In-Si-Sn oxide (ITSO).

[0251] When the conductive layer 326 uses a material that is easily oxidized, the conductive layer 329 uses a material that is not easily oxidized and covers the conductive layer 326, thereby suppressing the oxidation of the conductive layer 326. Furthermore, the precipitation of metal components contained in the conductive layer 326 can be suppressed. For example, when the conductive layer 326 uses a material containing silver, the conductive layer 329 is suitable to use In-Si-Sn oxide (ITSO). This suppresses both the oxidation of the conductive layer 326 and the precipitation of silver.

[0252] A recess is formed in the region of the conductive layer 324 that overlaps with the opening 126. Layer 328 is embedded in this recess. Layer 328 has the function of planarizing the recess.

[0253] exist Figure 26 In the example shown, the end of layer 313 is located outside the end of pixel electrode 311. Layer 313 is formed to cover the end of pixel electrode 311. By adopting this structure, the entire top surface of pixel electrode 311 can be used as a light-emitting area, which improves the aperture ratio compared to an island-shaped structure where the end of layer 313 is located inside the end of pixel electrode 311. In addition, by using layer 313 to cover the side of pixel electrode 311, contact between pixel electrode 311 and common electrode 315 can be suppressed, thereby suppressing short circuits in light-emitting element 60.

[0254] No insulating layer 237 is provided between the pixel electrode 311 and layer 313. This reduces the distance between adjacent light-emitting elements 60. Therefore, the display device 10 can be a high-definition or high-resolution display device. Furthermore, a mask for forming the insulating layer is not required, thereby reducing the manufacturing cost of the display device 10.

[0255] Layer 313 can be formed without using a high-precision metal mask. Layer 313 can be formed, for example, using photolithography and etching. Specifically, after forming pixel electrodes 311 in each sub-pixel, a film that will become layer 313 is deposited across multiple pixel electrodes 311. Next, a mask layer is formed on the film that will become layer 313, and a resist mask is formed on the mask layer using photolithography. Then, for example, the mask layer and the film that will become layer 313 are processed using etching, thereby removing the resist mask. For example, the mask layer has a two-layer structure of a first mask layer and a second mask layer on the first mask layer. In this case, a resist mask is formed on the second mask layer, and the second mask layer is processed. Then, the resist mask is removed. Then, for example, the first mask layer and the film that will become layer 313 are processed using the second mask layer as a hard mask. Thus, an island-shaped layer 313 is formed for each pixel electrode 311. Therefore, by dividing the layer 313 in each sub-pixel, an island-shaped layer 313 can be formed.

[0256] In this specification, the mask layer (also known as the sacrificial layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape in the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0257] By forming island-shaped layers 313 without using a high-precision metal mask, a fine layer 313 can be formed. Furthermore, by providing island-shaped layers 313 in each light-emitting element 60, leakage current between adjacent light-emitting elements 60 can be suppressed. Therefore, unintentional light emission caused by crosstalk can be suppressed, thereby enabling a display device with very high contrast. In particular, a display device with high current efficiency at low brightness can be realized.

[0258] In this specification, devices manufactured using a metal mask or a fine metal mask (FMM) are sometimes referred to as devices having an MM (Metal Mask) structure. Furthermore, devices manufactured without a metal mask or FMM are sometimes referred to as devices having an MML (Metal Mask Less) structure.

[0259] The area where no light-emitting element 60 is provided is provided with an insulating layer 325 and an insulating layer 327 on the insulating layer 325. Figure 26 The diagram shows cross-sections of multiple insulating layers 325 and multiple insulating layers 327, but when viewed in plan view, the insulating layers 325 and 327 are each formed as a continuous layer. In other words, the display device 10 may, for example, include one insulating layer 325 and one insulating layer 327. Alternatively, the display device 10 may also include multiple insulating layers 325 and multiple insulating layers 327 that are separate from each other.

[0260] The insulating layer 325 preferably has a region that contacts the side of the layer 313. By adopting a structure in which the insulating layer 325 has a region that contacts the layer 313, film peeling of the layer 313 can be suppressed. When the insulating layer 325 is in close contact with the layer 313, the layer 313 is fixed or bonded by the insulating layer 325. As a result, the reliability of the light-emitting element 60 can be improved. In addition, the manufacturing yield of the light-emitting element 60 can be improved.

[0261] The insulating layer 325 preferably functions as a barrier insulating layer against at least one of water and oxygen. Furthermore, the insulating layer 325 preferably functions as a barrier insulating layer against the diffusion of at least one of water and oxygen. Additionally, the insulating layer 325 preferably functions as a trapping or fixing (also referred to as gettering) of at least one of water and oxygen. Note that in this specification, a barrier insulating layer refers to an insulating layer with barrier properties. Furthermore, in this specification, barrier properties refer to the function of inhibiting the diffusion of the corresponding substance (or, in other words, low permeability).

[0262] When the insulating layer 325 functions as a barrier insulating layer or a gettering layer, it can have a structure that suppresses the entry of impurities (typically at least one of water and oxygen) that may diffuse from the outside into each light-emitting element. By adopting this structure, the reliability of the light-emitting element 60 can be improved.

[0263] The insulating layer 325 can be made of a material that can also be used for the protective layer 331, such as an inorganic material. In particular, using aluminum oxide as the protective layer 331 can improve the etch selectivity ratio between the insulating layer 325 and the layer 313, thereby protecting the layer 313, and is therefore preferred.

[0264] Insulating layer 327 is disposed on insulating layer 325 in such a way as to fill the recesses formed in insulating layer 325. Insulating layer 327 may have a structure that overlaps a portion of the top surface and side surface of layer 313 with insulating layer 325. Insulating layer 327 preferably covers at least a portion of the side surface of insulating layer 325. By providing insulating layer 325 and insulating layer 327, the unevenness of the surface formed on layer 313, such as the common electrode 315, can be reduced, thereby improving coverage. Therefore, poor connection caused by disconnection can be suppressed. In addition, the increase in resistance caused by localized thinning of the thickness of common electrode 315 due to steps can be suppressed. Although the top surface of insulating layer 327 preferably has a highly flat shape, it may also have a protrusion, a convex curved surface, a concave curved surface, or a recess.

[0265] As the insulating layer 327, it is suitable to use an insulating layer containing organic materials. As the organic material, a photosensitive organic resin is preferred, for example, a photosensitive resin composition containing acrylic resin is preferred. Note that in this specification, etc., acrylic resin does not only refer to polymethacrylate or methacrylic resin, but sometimes also refers to acrylic polymers in a broader sense.

[0266] A mask layer 318 is located on layer 313 included in the light-emitting element 60. The mask layer 318 is disposed around the light-emitting area. In other words, the mask layer 318 has an opening in the portion overlapping the light-emitting area. The mask layer 318 is a residual portion of the mask layer disposed on layer 313 during the formation of layer 313. Thus, the display device 10 may also retain a portion of the mask layer used to protect layer 313 during its manufacturing process.

[0267] In the display device 10, a common layer 314 is provided on layer 313 and insulating layer 327, and a common electrode 315 is provided on the common layer 314. When the light-emitting element 60 includes the common layer 314, layer 313 and the common layer 314 can be collectively referred to as the EL layer. Note that the EL layer may also not include the common layer 314.

[0268] The common layer 314 may include, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 314 may be a stack of either an electron transport layer and an electron injection layer, or a stack of either a hole transport layer and a hole injection layer. Here, the layer included in the common layer 314 may not be present in layer 313. For example, if the common layer 314 includes an electron injection layer, layer 313 may not include an electron injection layer. Similarly, if the common layer 314 includes a hole injection layer, layer 313 may not include a hole injection layer.

[0269] When a common layer 314 is provided in a display device, a common electrode 315 can be deposited continuously after the common layer 314 is deposited, without the need for etching or other processes in between. For example, after the common layer 314 is formed in a vacuum, the substrate 101 does not need to be exposed to the atmosphere, and the common electrode 315 can be formed in a vacuum. That is, the common layer 314 and the common electrode 315 can always be formed in a vacuum. As a result, the bottom surface of the common electrode 315 can be kept clean compared to the case where no common layer 314 is provided in the display device. Therefore, when the surface of layer 313 is exposed to the atmosphere after the formation of layer 313, it is preferable to provide a common layer 314 in the display device.

[0270] Figure 27A and Figure 28A It is shown Figure 22A A plan view of an example structure of subpixel 23. Figure 27A and Figure 28A In the diagram, pixel electrode 311 is represented by a dashed line, and the shaded line of pixel electrode 311 is omitted. Figure 27B and Figure 28B It is represented by a dashed line. Figure 27A and Figure 28AThe plan view of conductive layers 115b, 115c and 118 in sub-pixel 23 shown is omitted, with the shaded lines of the aforementioned conductive layers omitted.

[0271] Figure 27A and Figure 27B The following example is shown: Figure 24A and Figure 24B The conductive layer 111c shown has a region (protrusion) protruding in the X direction, and conductive layer 112c, semiconductor layer 113c, wiring 41, opening 121c, and opening 123c are disposed overlapping this protrusion. Figure 27A and Figure 27B In the example shown, a transistor 59 is disposed in the region where the protrusion of conductive layer 111c overlaps with conductive layer 115c.

[0272] Figure 28A and Figure 28B Show Figure 24A and Figure 24B The conductive layer 111c shown has a region protruding in the X direction (first protrusion), and the conductive layer 115c has a region protruding in the -Y direction (second protrusion). Furthermore, Figure 28A and Figure 28B An example is shown where a conductive layer 112c, a semiconductor layer 113c, an opening 121c, and an opening 123c are provided in the area where the first protrusion and the second protrusion overlap. Figure 28A and Figure 28B In the example shown, a transistor 59 is disposed in the area where the first protrusion and the second protrusion overlap.

[0273] <Components of a Display Device> The following description includes the constituent elements of the display device in this embodiment.

[0274] [Semiconductor layer 113] There are no particular limitations on the semiconductor materials that can be used in semiconductor layer 113. For example, a single-material semiconductor or a compound semiconductor can be used. Examples of single-material semiconductors include silicon or germanium. Examples of compound semiconductors include gallium arsenide and silicon-germanium. Compound semiconductors can also be organic materials with semiconductor properties or metal oxides with semiconductor properties. Note that these semiconductor materials may also contain impurities as dopants.

[0275] There are no particular restrictions on the crystallinity of the semiconductor material used for semiconductor layer 113; amorphous semiconductors or crystalline semiconductors (single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or semiconductors in which a portion has crystalline regions) can be used. When using crystalline semiconductors, the degradation of transistor characteristics can be suppressed, so it is preferred.

[0276] Semiconductor layer 113 may be made of silicon. Examples of silicon include monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polycrystalline silicon (LTPS).

[0277] Transistors using amorphous silicon as the semiconductor layer 113 can be formed on a large glass substrate and can be manufactured at low cost. Transistors using polycrystalline silicon as the semiconductor layer 113 have high field-effect mobility and can be driven at high speed. Furthermore, compared with transistors using amorphous silicon, transistors using microcrystalline silicon as the semiconductor layer 113 have high field-effect mobility and can be driven at high speed.

[0278] Semiconductor layer 113 preferably comprises a metal oxide (oxide semiconductor). Examples of metal oxides that can be used in semiconductor layer 113 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably comprises at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably comprises two or three elements selected from indium, element M, and zinc. Note that element M is selected from one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, element M is preferably selected from one or more of aluminum, gallium, yttrium, and tin.

[0279] Semiconductor layer 113 may use, for example, indium oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also denoted as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), indium tin gallium oxide (In-Sn-Ga oxide), or indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. Alternatively, indium tin oxide containing silicon may be used. Alternatively, the above-mentioned oxides having an amorphous structure may be used. For example, indium oxide or indium tin oxide having an amorphous structure may be used.

[0280] In particular, element M is preferably selected from one or more of gallium, aluminum, yttrium, and tin. In particular, element M is preferably gallium.

[0281] Here, the composition of the metal oxide contained in the semiconductor layer 113 has a significant impact on the electrical characteristics and reliability of the transistor 50 of the transistor included in the display device, which is an embodiment of the present invention.

[0282] For example, by increasing the indium content in metal oxides, transistors with high on-state current can be achieved. By using this transistor in transistors that require high on-state current, display devices with excellent electrical characteristics can be realized.

[0283] In this specification, the ratio of the number of indium atoms to the number of atoms of the metal elements contained therein is sometimes referred to as the indium content. The same applies to other metal elements.

[0284] Furthermore, by increasing the proportion of zinc atoms relative to the total number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, variations in the electrical characteristics of the transistor are suppressed, and reliability is improved.

[0285] Furthermore, by increasing the atomic ratio of element M, which is relative to the total number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, thereby enabling transistors with low off-state currents. In addition, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0286] When using an In-Zn oxide as the semiconductor layer 113, it is preferable to use a metal oxide in which the atomic ratio of indium is greater than or equal to that of zinc. For example, metal oxides with atomic ratios of In:Zn = 1:1, In:Zn = 2:1, In:Zn = 3:1, In:Zn = 4:1, In:Zn = 5:1, In:Zn = 7:1, In:Zn = 10:1, or similar ratios can be used.

[0287] When using an In-Sn oxide as the semiconductor layer 113, it is preferable to use a metal oxide in which the atomic ratio of indium is greater than or equal to that of tin. For example, metal oxides with atomic ratios of In:Sn = 1:1, In:Sn = 2:1, In:Sn = 3:1, In:Sn = 4:1, In:Sn = 5:1, In:Sn = 7:1, In:Sn = 10:1 or similar can be used.

[0288] When using an In-M-Zn oxide as the semiconductor layer 113, a metal oxide in which the atomic ratio of indium relative to the number of atoms of the metal element is higher than the atomic ratio of element M can be used. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M is more preferred. For example, the semiconductor layer 113 can use metal oxides with atomic ratios of In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. M:Zn = 6:1:6, In:M:Zn = 10:1:3, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10 or similar metal oxides.

[0289] Note that the atomic ratio of indium in the In-M-Zn oxide can be lower than the atomic ratio of element M. For example, semiconductor layer 113 can use metal oxides with atomic ratios of In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4 or similar.

[0290] Note that when element M comprises multiple metallic elements, the total number of atoms of these metallic elements can be the atomic ratio of element M. For example, when using an In-Ga-Al-Zn oxide comprising gallium and aluminum as element M, the total number of atoms of gallium and aluminum can be the atomic ratio of element M. Furthermore, the atomic ratio of indium, element M, and zinc is preferably within the range described above.

[0291] Preferably, the metal oxide used has an indium atom ratio of 30 atomic percent or more and 100 atomic percent or less relative to the number of atoms of the metal element, preferably 30 atomic percent or more and 95 atomic percent or less, more preferably 35 atomic percent or more and 95 atomic percent or less, more preferably 35 atomic percent or more and 90 atomic percent or less, more preferably 40 atomic percent or more and 90 atomic percent or less, more preferably 45 atomic percent or more and 90 atomic percent or less, more preferably 50 atomic percent or more and 80 atomic percent or less, more preferably 60 atomic percent or more and 80 atomic percent or less, and more preferably 70 atomic percent or more and 80 atomic percent or less. For example, when In-Ga-Zn oxide is used as semiconductor layer 113, the indium atom ratio relative to the total number of atoms of indium, element M, and zinc is preferably within the above range.

[0292] The composition of metal oxides can be analyzed using methods such as energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, multiple methods can be combined. Note that the actual content of elements with low concentrations can sometimes differ from the analytically obtained content due to variations in analytical precision. For example, when the content of element M is low, the analytically obtained content of element M may sometimes be lower than the actual content.

[0293] In this specification, the term "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when the atomic ratio is denoted as In:M:Zn = 4:2:3 or a near-near composition, it includes the following cases: when the atomic ratio of indium is 4, the atomic ratio of M is 1 or more and 3 or less, and the atomic ratio of zinc is 2 or more and 4 or less. Furthermore, when the atomic ratio is denoted as In:M:Zn = 5:1:6 or a near-near composition, it includes the following cases: when the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and less than 2, and the atomic ratio of zinc is 5 or more and less than 7. Furthermore, when the atomic ratio is denoted as In:M:Zn = 1:1:1 or a near-near composition, it includes the following cases: when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and less than 2, and the atomic ratio of zinc is greater than 0.1 and less than 2.

[0294] Metal oxides are suitable for formation using sputtering or atomic layer deposition (ALD). Note that when forming metal oxides using sputtering, the atomic ratio of the target material sometimes differs from that of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide is sometimes lower than that of zinc in the target material. Specifically, the atomic ratio of zinc in the metal oxide is sometimes about 40% to 90% of the atomic ratio of zinc in the target material.

[0295] Here, we will explain the reliability of transistors. One indicator of transistor reliability is the GBT (Gate Bias Temperature) stress test, which maintains an applied electric field on the gate. Specifically, the test that maintains a positive gate potential (positive bias) at high temperature relative to the source and drain potentials is called the PBTS (Positive Bias Temperature Stress) test, and the test that maintains a negative gate potential (negative bias) at high temperature is called the NBTS (Negative Bias Temperature Stress) test. Furthermore, the PBTS and NBTS tests performed under illumination are respectively called the PBTIS (Positive Bias Temperature Illumination Stress) test and the NBTIS (Negative Bias Temperature Illumination Stress) test.

[0296] In an n-type transistor, a positive potential is applied to the gate when the transistor is in the turn-on state (the state in which current flows). Therefore, the variation in the threshold voltage of the PBTS test is one of the important factors to consider as a reliability indicator of the transistor.

[0297] By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer 113, a transistor with high reliability under forward bias can be realized. In other words, a transistor with small fluctuations in the threshold voltage during PBTS testing can be achieved. Furthermore, when using a gallium-containing metal oxide, the gallium content is preferably lower than the indium content. This results in a transistor with high reliability.

[0298] One reason for the variation in threshold voltage during PBTS testing can be the presence of defect states at or near the interface between the semiconductor layer and the gate insulating layer. A higher defect state density results in more significant degradation during PBTS testing. The formation of these defect states can be suppressed by reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer.

[0299] One reason for suppressing threshold voltage variations in PBTS testing by using metal oxides containing little or no gallium in the semiconductor layer can be considered as follows: Gallium contained in metal oxides is more likely to draw oxygen than other metals (e.g., indium or zinc). Therefore, it can be inferred that at the interface between the metal oxide containing more gallium and the gate insulating layer, carrier (in this case, electron) trap sites are easily generated through gallium bonding with excess oxygen in the gate insulating layer. Thus, it can be assumed that when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, causing a change in the threshold voltage.

[0300] More specifically, when using an In-Ga-Zn oxide as the semiconductor layer 113, a metal oxide with a higher atomic ratio of indium than gallium can be used in the semiconductor layer 113. Furthermore, a metal oxide with a higher atomic ratio of zinc than gallium is more preferred. In other words, it is preferable to use a metal oxide in the semiconductor layer 113 where the atomic ratios of the metal elements satisfy In>Ga and Zn>Ga.

[0301] For example, in semiconductor layer 113, the atomic ratios of metal elements can be In:Ga:Zn = 2:1:3, In:Ga:Zn = 3:1:2, In:Ga:Zn = 4:2:3, In:Ga:Zn = 4:2:4.1, In:Ga:Zn = 5:1:3, In:Ga:Zn = 5:1:6, In:Ga:Zn = 5:1:7, In:Ga:Zn = 5:1:8, In: Metal oxides of Ga:Zn = 6:1:6, In:Ga:Zn = 10:1:3, In:Ga:Zn = 10:1:6, In:Ga:Zn = 10:1:7, In:Ga:Zn = 10:1:8, In:Ga:Zn = 5:2:5, In:Ga:Zn = 10:1:10, In:Ga:Zn = 20:1:10, In:Ga:Zn = 40:1:10 or similar.

[0302] Semiconductor layer 113 preferably uses a metal oxide with a gallium atom content ratio of more than 0 atomic% and less than 50 atomic% relative to the number of atoms of the contained metal element, preferably more than 0.1 atomic% and less than 40 atomic%, more preferably more than 0.1 atomic% and less than 35 atomic%, more preferably more than 0.1 atomic% and less than 30 atomic%, more preferably more than 0.1 atomic% and less than 25 atomic%, more preferably more than 0.1 atomic% and less than 20 atomic%, more preferably more than 0.1 atomic% and less than 15 atomic%, and more preferably more than 0.1 atomic% and less than 10 atomic%. By reducing the gallium content in the semiconductor layer, transistors with high tolerance to PBTS testing can be achieved. Note that by containing gallium in the metal oxide, it is less likely to generate oxygen vacancies (V0) in the metal oxide. O Effects such as Oxygen Vacancy.

[0303] As the semiconductor layer 113, a gallium-free metal oxide can also be used. For example, In-Zn oxide can be used as the semiconductor layer 113. In this case, when the atomic ratio of indium to the number of metal atoms in the metal oxide is increased, the field-effect mobility of the transistor can be improved. On the other hand, when the atomic ratio of zinc to the number of metal atoms in the metal oxide is increased, the metal oxide has high crystallinity, thus suppressing variations in the electrical characteristics of the transistor and improving reliability. Furthermore, indium oxide and other gallium- and zinc-free metal oxides can also be used as the semiconductor layer 113. By using a gallium-free metal oxide, the variation in the threshold voltage during PBTS testing can be made extremely small.

[0304] For example, an oxide containing indium and zinc can be used as the semiconductor layer 113. In this case, metal oxides with an atomic ratio of, for example, In:Zn = 2:3, In:Zn = 4:1, or similar can be used.

[0305] Note that gallium is typically used as an example, but this can also be applied to cases where element M is used instead of gallium. Preferably, the semiconductor layer 113 uses a metal oxide in which the atomic ratio of indium is higher than that of element M. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than that of element M is preferred.

[0306] By using a metal oxide with a low content of element M as the semiconductor layer 113, a transistor with high reliability under forward bias can be realized. By using this transistor as a transistor that requires high reliability under forward bias, a display device with high reliability can be realized.

[0307] As described above, the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used in the semiconductor layer 113. Therefore, by varying the composition of the metal oxide according to the required electrical characteristics and reliability of the transistor, a display device with both excellent electrical characteristics and high reliability can be realized.

[0308] Semiconductor layer 113 may also have a stacked structure comprising two or more metal oxide layers. The compositions of the two or more metal oxide layers comprising semiconductor layer 113 may also be the same or substantially the same. By employing a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thus reducing manufacturing costs.

[0309] The compositions of the two or more metal oxide layers included in the semiconductor layer 113 can also be different from each other. For example, a stacked structure using a first metal oxide layer with an In:M:Zn ratio of 1:3:4 or similar, and a second metal oxide layer disposed on the first metal oxide layer with an In:M:Zn ratio of 1:1:1 or similar, is suitable. Furthermore, gallium or aluminum is particularly preferred as element M. For example, a stacked structure selected from any one of indium oxide, indium gallium oxide, and IGZO, and any one of IAZO, IAGZO, and ITZO (registered trademark) can also be used.

[0310] A crystalline metal oxide layer is preferably used as the semiconductor layer 113. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, or a nano-crystal (nc) structure can be used. By using a crystalline metal oxide layer as the semiconductor layer 113, the defect state density in the semiconductor layer 113 can be reduced, thereby enabling a display device with high reliability.

[0311] The higher the crystallinity of the metal oxide layer used for semiconductor layer 113, the lower the defect state density in semiconductor layer 113 can be. On the other hand, by using a metal oxide layer with low crystallinity, transistors capable of carrying large currents can be realized.

[0312] When forming metal oxide layers using sputtering, the higher the substrate temperature (stage temperature) during formation, the more crystalline the metal oxide layer can be formed. Furthermore, the higher the oxygen flow rate ratio relative to the overall deposition gas used during formation (also known as the oxygen flow rate ratio), the more crystalline the metal oxide layer can be formed.

[0313] Semiconductor layer 113 may also have a stacked structure of two or more metal oxide layers with different crystallinity. For example, it may have a stacked structure of a first metal oxide layer and a second metal oxide layer disposed on the first metal oxide layer, wherein the second metal oxide layer may include regions with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may include regions with lower crystallinity than the first metal oxide layer. The compositions of the two or more metal oxide layers included in semiconductor layer 113 may also be the same or substantially the same. By employing a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. For example, by using the same sputtering target and making different oxygen flow ratios, a stacked structure of two or more metal oxide layers with different crystallinity can be formed. Note that the compositions of the two or more metal oxide layers included in semiconductor layer 113 may also be different from each other.

[0314] The thickness of the semiconductor layer 113 is preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, more preferably 20 nm or more and 50 nm or less, more preferably 20 nm or more and 40 nm or less, and more preferably 25 nm or more and 40 nm or less.

[0315] The substrate temperature for forming the semiconductor layer 113 is preferably above room temperature (25°C) and below 200°C, more preferably above room temperature and below 130°C. By using a substrate temperature within the above range, bending or distortion of the substrate can be suppressed when using a large-area glass substrate.

[0316] Here, oxygen vacancies that may form in semiconductor layer 113 will be explained.

[0317] When an oxide semiconductor is used in semiconductor layer 113, sometimes hydrogen in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, creating oxygen vacancies (V0) in the oxide semiconductor. O Furthermore, sometimes hydrogen enters the defects in oxygen vacancies (hereinafter referred to as V). O H is used as a donor to generate electrons as charge carriers. Additionally, sometimes electrons are generated as charge carriers due to the bonding of a portion of the hydrogen with oxygen atoms bonded to metal atoms. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have always-on characteristics. Furthermore, because hydrogen in oxide semiconductors is easily moved by heat or electric fields, a large amount of hydrogen in the oxide semiconductor may lead to a decrease in transistor reliability.

[0318] VO H can be used as a donor in oxide semiconductors. However, it is difficult to quantitatively evaluate this defect. Therefore, in oxide semiconductors, evaluation is sometimes based on carrier concentration rather than donor concentration. Consequently, in this specification, etc., the carrier concentration under the assumption of no applied electric field is sometimes used as a parameter for oxide semiconductors instead of donor concentration. That is to say, the "carrier concentration" described in this specification, etc., may sometimes be referred to as "donor concentration".

[0319] Therefore, when an oxide semiconductor is used as the semiconductor layer 113, it is preferable to minimize the V in the semiconductor layer 113. O H is used to make it a high-purity intrinsic or substantially high-purity intrinsic. To obtain this V... O For oxide semiconductors with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation); and supply oxygen to the oxide semiconductor to repair oxygen vacancies (V). O ). By V O Oxide semiconductors with sufficiently reduced impurities such as hydrogen (H) can impart stable electrical characteristics when used in the channel formation region of transistors. Note that sometimes oxygen is supplied to the oxide semiconductor to repair oxygen vacancies (V0). O The treatment of ) is called oxidation treatment.

[0320] When an oxide semiconductor is used as semiconductor layer 113, the carrier concentration of the oxide semiconductor in the region used as the channel formation region is preferably 1 × 10⁻⁶. 18 cm -3 Below, less than 1×10 is preferred. 17 cm -3 Further optimization of less than 1×10 16 cm -3 Further optimization of less than 1×10 13 cm -3 Further optimization of less than 1×10 12 cm -3 Note that there is no specific limit to the lower limit of the carrier concentration of the oxide semiconductor in the region used as the channel formation region; for example, it can be set to 1 × 10⁻⁶. -9 cm -3 .

[0321] [Insulation layer 103] The insulating layer 103 preferably has a laminated structure. As described above, the accompanying drawings of this specification show an example of the insulating layer 103 including an insulating layer 103a, an insulating layer 103b on the insulating layer 103a, and an insulating layer 103c on the insulating layer 103b.

[0322] The region in semiconductor layer 113 that contacts insulating layer 103b is used as a channel formation region. Insulating layer 103b preferably contains oxygen, and preferably uses one or more of the oxides and oxynitrides described above. Specifically, insulating layer 103b is suitable to use one or both of silicon oxide and silicon oxynitride.

[0323] More preferably, the insulating layer 103b is a film that releases oxygen upon heating. Oxygen is released from the insulating layer 103b by heat applied during the manufacturing process of the display device, thereby supplying oxygen to the semiconductor layer 113. By supplying oxygen from the insulating layer 103b to the semiconductor layer 113, particularly to the channel formation region of the semiconductor layer 113, oxygen vacancies (V... O The oxygen vacancy (V) is repaired, thereby reducing the number of oxygen vacancies. O Therefore, transistors exhibiting good electrical characteristics and high reliability can be realized.

[0324] For example, oxygen can be supplied to the insulating layer 103b by heating or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied by forming a film on the top surface of the insulating layer 103b using sputtering in an oxygen-containing atmosphere. This film can then be removed.

[0325] The insulating layer 103b is preferably formed using deposition methods such as sputtering or plasma-enhanced chemical vapor deposition (PECVD). In particular, by using sputtering and not using hydrogen gas as the deposition gas, a film with extremely low hydrogen content can be achieved. Therefore, the supply of hydrogen to the channel formation region can be suppressed, thereby stabilizing the electrical characteristics of the transistor 50.

[0326] like Figure 3B The thickness T103b of the insulating layer 103b shown can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, or less than 2.5 μm, less than 2 μm, less than 1.5 μm, less than 1.2 μm, less than 1 μm, less than 500 nm, less than 300 nm, less than 200 nm, less than 100 nm, less than 50 nm, less than 30 nm, or less than 20 nm.

[0327] Here, by using a material with high conductivity in semiconductor layer 113, a transistor with a large on-state current can be realized. However, oxygen vacancies (V0) are easily formed when using a material with high conductivity. O ), oxygen vacancies (V) in the channel formation region OWhen the number of oxygen vacancies increases, the threshold voltage of the transistor sometimes drifts, and the drain current (hereinafter also referred to as the cutoff current) flowing through it when the gate voltage is 0V increases. For example, in an n-channel transistor, the cutoff current sometimes increases when the threshold voltage drifts negatively. By providing an insulating layer 103b, oxygen is supplied to at least the region in the semiconductor layer 113 that is in contact with the insulating layer 103b, i.e., the channel formation region, thus reducing the number of oxygen vacancies (V) in the channel formation region. O ) and V O H. Therefore, threshold voltage drift can be suppressed, enabling the realization of transistors with low cutoff current and high on-state current. This allows for the realization of display devices that combine low power consumption and high performance.

[0328] The region in semiconductor layer 113 that contacts conductive layer 111 is used as one of the source and drain regions of transistor 50, and the region that contacts conductive layer 112 is used as the other. The source and drain regions are regions with lower resistance compared to the channel formation region. The source and drain regions can also be described as regions with higher carrier concentration and higher oxygen defect density compared to the channel formation region.

[0329] An insulating layer 103a is disposed between an insulating layer 103b and a conductive layer 111. An insulating layer 103c is disposed between an insulating layer 103b and a conductive layer 112. The insulating layers 103a and 103c preferably release small amounts of impurities (e.g., hydrogen and water) and are not easily permeable. This suppresses the diffusion of impurities contained in the insulating layers 103a and 103c into the channel formation region. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0330] The insulating layers 103a and 103c are preferably made of films that are not easily permeable to oxygen. This prevents oxygen contained in the insulating layer 103b from diffusing through the insulating layer 103a to the conductive layer 111. Similarly, it prevents oxygen contained in the insulating layer 103b from diffusing through the insulating layer 103c to the conductive layer 112. This prevents the resistance of the conductive layers 111 and 112 from increasing. Simultaneously, by suppressing the diffusion of oxygen contained in the insulating layer 103b to both the insulating layer 103a and insulating layer 103c sides, the amount of oxygen supplied from the insulating layer 103b to the channel forming region increases, thereby reducing the oxygen vacancies (V) in the channel forming region. O ) and V O H.

[0331] By using membranes that do not readily diffuse oxygen as both insulating layers 103a and 103c, oxygen can be effectively supplied from insulating layer 103b to the channel forming region. Alternatively, one or both of insulating layers 103a and 103c may not be provided.

[0332] Both insulating layers 103a and 103c preferably contain nitrogen, and one or more of the aforementioned nitrides and oxynitrides are preferred. For example, silicon nitride or silicon oxynitride can be used for both insulating layers 103a and 103c. Alternatively, one or more of oxides and oxynitrides can be used for one or both of insulating layers 103a and 103c. For example, aluminum oxide can be used for both insulating layers 103a and 103c. Note that insulating layer 103a can be made of the same material as insulating layer 103c or a different material.

[0333] Note that in this specification, etc., different materials refer to materials whose constituent elements are partially or completely different, or materials whose constituent elements are the same but whose composition is different.

[0334] like Figure 3B The thickness T103a of the insulating layer 103a shown can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 20 nm or more, 50 nm or more, or 70 nm or more and less than 1 μm, 500 nm or less, 400 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, or 120 nm or less. The thickness T103a can be the shortest distance between the surface of the insulating layer 103a that is formed (in this case, the top surface of the conductive layer 111) and the top surface of the insulating layer 103a when viewed from a cross-section.

[0335] When the thickness T103a of the insulating layer 103a is relatively thick, the amount of impurities released from the insulating layer 103a may increase, leading to an increase in the amount of impurities diffusing into the channel formation region. On the other hand, when the thickness T103a is relatively thin, oxygen contained in the insulating layer 103b may diffuse through the insulating layer 103a to the conductive layer 111 side, reducing the amount of oxygen supplied to the channel formation region. By setting the thickness T103a within the aforementioned range, the oxygen vacancies (V) in the channel formation region can be reduced. O ) and V O H. In addition, it can suppress the increase in resistance of conductive layer 111 due to oxidation of conductive layer 111 caused by oxygen contained in insulating layer 103b.

[0336] like Figure 3B The thickness T103c of the insulating layer 103c shown can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 15 nm or more, or 20 nm or more and less than 1 μm, 500 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, 120 nm or less, or 100 nm or less. The thickness T103c can be the shortest distance between the surface of the insulating layer 103c that is formed (in this case, the top surface of the insulating layer 103b) and the top surface of the insulating layer 103c when viewed from a cross-section.

[0337] When the thickness T103c of the insulating layer 103c is relatively thick, the amount of impurities released from the insulating layer 103c sometimes increases, and the amount of impurities diffusing into the channel formation region also increases. On the other hand, when the thickness T103c is relatively thin, oxygen contained in the insulating layer 103b sometimes diffuses through the insulating layer 103c to the conductive layer 112 side, reducing the amount of oxygen supplied to the channel formation region. By setting the thickness T103c to the above range, the oxygen vacancies (V) in the channel formation region can be reduced. O ) and V O H. In addition, it can suppress the increase in resistance of conductive layer 112 due to oxidation of conductive layer 112 caused by oxygen contained in insulating layer 103b.

[0338] At least one of the regions of semiconductor layer 113 that contact insulating layer 103a and insulating layer 103c can also be regions with low resistance compared to the channel formation region (hereinafter also referred to as low-resistance regions). This region can also be described as a region with high carrier concentration and high oxygen vacancy density compared to the channel formation region. By using a material that releases impurities (e.g., water or hydrogen) for insulating layer 103a, the region of semiconductor layer 113 that contacts insulating layer 103a can be used as a low-resistance region. Semiconductor layer 113 can have a structure in which a low-resistance region exists between the region that contacts conductive layer 111 (one of the source region and drain region) and the channel formation region. Similarly, by using an impurity-releasing material as insulating layer 103c, the region of semiconductor layer 113 that contacts insulating layer 103c can be used as a low-resistance region. Semiconductor layer 113 can have a structure in which a low-resistance region exists between the region that contacts conductive layer 112 (the other of the source region and drain region) and the channel formation region. The low-resistance region can be used as a buffer region to mitigate the drain electric field. In addition, these low-resistance regions can also be used as source or drain regions.

[0339] Note that sometimes impurities released from insulating layer 103a diffuse through insulating layer 103b or one of the source and drain regions of semiconductor layer 113 to the channel formation region. Similarly, sometimes impurities released from insulating layer 103c diffuse through insulating layer 103b or the other of the source and drain regions of semiconductor layer 113 to the channel formation region. However, at least the region of semiconductor layer 113 in contact with insulating layer 103b is supplied with oxygen from insulating layer 103b, thus reducing the oxygen vacancies (V) in the channel formation region. O ) and V O H. Therefore, threshold voltage drift can be suppressed, enabling the realization of transistors with low cutoff current and high on-state current. This allows for the realization of display devices that combine low power consumption and high performance.

[0340] However, when too much impurity is released from insulating layers 103a and 103c, oxygen vacancies (V) generated by these impurities... O ) and V O The amount of H may be greater than the oxygen vacancies repaired by the oxygen supplied from the insulation layer 103b (V O ) and V O The amount of H. Even if materials that release impurities are used as insulating layers 103a and 103c, the amount of released impurities is preferably low.

[0341] The insulating layer 103 preferably includes at least the insulating layer 103b. For example, it may not include one or both of the insulating layers 103a and 103c. In addition, the insulating layer 103 may have a stacked structure of two or more layers or a single-layer structure.

[0342] [Conductive layer 111, conductive layer 112 and conductive layer 115] The conductive layers 111 and 112, used as source or drain electrodes, and the conductive layer 115, used as gate electrodes, can be formed using one or more of chromium, copper, aluminum, magnesium, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or alloys composed of one or more of the aforementioned metals. Conductive layers 111, 112, and 115 are preferably made of low-resistance conductive materials containing one or more of copper, silver, gold, and aluminum. In particular, copper or aluminum has advantages in mass production and is therefore preferred.

[0343] Conductive layers 111, 112, and 115 may be made of metal oxides (also known as oxide conductors). Examples of oxide conductors (OC) include In-Sn oxide (ITO), In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide (ITSO), and In-Ga-Zn oxide.

[0344] Here, oxide conductors (OC) will be explained. For example, an oxygen vacancy is formed in a metal oxide that has semiconductor properties, and hydrogen is added to this oxygen vacancy to form a donor level near the conduction band. As a result, the conductivity of the metal oxide increases, and it becomes a conductor. Metal oxides that can become conductors are called oxide conductors.

[0345] Conductive layers 111, 112, and 115 can also be constructed using a stacked structure of conductive layers containing the aforementioned oxide conductor (metal oxide) and conductive layers containing metal or alloy. By using conductive layers containing metal or alloy, wiring resistance can be reduced.

[0346] As conductive layers 111, 112, and 115, Cu-X alloys (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be used. By using Cu-X alloys, processing can be performed using a wet etching process, thereby reducing manufacturing costs.

[0347] Note that conductive layers 111, 112, and 115 may be made of the same or different materials.

[0348] Here, taking the structure in which a metal oxide is used as the semiconductor layer 113 as an example, the conductive layer 111 and the conductive layer 112 will be specifically described.

[0349] When an oxide semiconductor is used as the semiconductor layer 113, the resistance sometimes increases because the conductive layers 111 and 112 are oxidized due to the oxygen contained in the semiconductor layer 113. The resistance sometimes increases because the conductive layers 111 and 112 are oxidized due to the oxygen contained in the insulating layer 103a. Furthermore, the resistance sometimes increases because the oxygen vacancies (V0) in the semiconductor layer 113 are oxidized due to the oxygen contained in the semiconductor layer 113. O The amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 may decrease due to the oxidation of conductive layers 111 and 112 caused by oxygen contained in the insulating layer 103a.

[0350] Both conductive layers 111 and 112 are preferably made of materials that are not easily oxidized. Both conductive layers 111 and 112 are preferably made of oxide conductors. For example, In-Sn oxide (ITO) or In-Sn-Si oxide (ITSO) may be suitable. Both conductive layers 111 and 112 may also be made of nitride conductors. Examples of nitride conductors include tantalum nitride and titanium nitride. Conductive layers 111 and 112 may also have a laminated structure of the above materials.

[0351] By using materials that are not easily oxidized in conductive layers 111 and 112, the high resistance caused by oxidation of oxygen contained in semiconductor layer 113 or oxygen contained in insulating layer 103a can be suppressed. Furthermore, oxygen vacancies (V0) in semiconductor layer 113 can be utilized to reduce oxidation. O While suppressing the increase of oxygen vacancies, the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 is increased. Therefore, the number of oxygen vacancies (V) in the semiconductor layer 113 can be reduced. O ) and V O H. Thus, transistor 50 can be a transistor exhibiting good electrical characteristics and high reliability. Note that conductive layers 111 and 112 can be made of the same material or different materials.

[0352] [Insulation layer 105] The defect density of the insulating layer 105, which serves as the gate insulating layer, is preferably low. When the defect density of the insulating layer 105 is low, a transistor exhibiting good electrical characteristics can be realized. Furthermore, the insulating layer 105 preferably has a high dielectric withstand voltage. Because the insulating layer 105 has a high dielectric withstand voltage, the transistor 50 can be a highly reliable transistor.

[0353] The insulating layer 105 may be one or more of the following: oxides, oxynitrides, oxynitrides, and nitrides, which have insulating properties. The insulating layer 105 may be one or more of the following: silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxides. The insulating layer 105 may also be a single layer or a stacked layer. The insulating layer 105 may also have a stacked structure of oxides and nitrides, for example.

[0354] Note that in micro-transistors, leakage current sometimes increases when the gate insulating layer is thin. By using a material with a relatively high permittivity (also known as a high-k material) in the gate insulating layer, it is possible to achieve low voltage during transistor operation while maintaining the physical thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0355] Preferably, the amount of impurities (e.g., water and hydrogen) released from the insulating layer 105 itself is small. Because the amount of impurities released from the insulating layer 105 is small, impurity diffusion to the semiconductor layer 113 can be suppressed. Therefore, the transistor 50 can be a transistor exhibiting good electrical characteristics and high reliability.

[0356] Since the insulating layer 105 is formed on the semiconductor layer 113, it is preferable to form the film under conditions that minimize damage to the semiconductor layer 113. For example, it is preferable to form the film under conditions that are sufficiently slow in deposition rate, specifically slower than that of the insulating layer 103b. For example, when forming the insulating layer 105 using the PECVD method, forming it under low power conditions can minimize damage to the semiconductor layer 113.

[0357] Here, taking the structure of semiconductor layer 113 using metal oxide as an example, the insulating layer 105 will be specifically explained.

[0358] To improve the interface properties with the semiconductor layer 113, the insulating layer 105 is preferably made of an oxide. For example, the insulating layer 105 may be suitable as one or more of silicon oxide and silicon oxynitride. Furthermore, the insulating layer 105 is more preferably made of a film that releases oxygen upon heating.

[0359] Note that the insulating layer 105 may also have a stacked structure. The insulating layer 105 may have a stacked structure of an oxide film contacting the semiconductor layer 113 and a nitride film contacting the conductive layer 115. For example, one or more of silicon oxide and silicon oxynitride can be used as the oxide film. Silicon nitride can be used as the nitride film. When the insulating layer 105 has a stacked structure, using an oxide on at least the side of the insulating layer 105 in contact with the semiconductor layer 113 can improve the interface characteristics with the semiconductor layer 113, and is therefore preferred.

[0360] [Substrate 101] While there are no particular restrictions on the material of substrate 101, it must at least possess heat resistance capable of withstanding subsequent heat treatment. For example, single-crystal or polycrystalline semiconductor substrates made of silicon or silicon carbide, compound semiconductor substrates such as silicon-germanium, SOI substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or organic resin substrates can be used as substrate 101. Alternatively, substrates with semiconductor elements disposed on the aforementioned substrates can also be used as substrate 101. Furthermore, printed circuit boards can also be used as substrate 101. Note that the semiconductor substrate and insulating substrate can be circular or angular in shape.

[0361] A flexible substrate can also be used as substrate 101, and transistor 50 can be formed directly on the flexible substrate, for example. Alternatively, a release layer can be provided between substrate 101 and transistor 50, etc. A release layer can be used when a part or all of the display device is manufactured on the release layer, and then it is separated from substrate 101 and transferred to another substrate. In this case, transistor 50, etc., can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0362] [Substrate 141] The substrate 141 can be made of glass, quartz, ceramic, sapphire, resin, metal, alloy, or semiconductor, etc. The substrate on the side from which light from the light-emitting element 60 is extracted uses a material that allows the light to pass through. By using a flexible material for the substrate 141, the flexibility of the display device can be improved. A polarizer can also be used as the substrate 141. Furthermore, an adhesive film or a substrate film can also be used as the substrate 141.

[0363] The substrate 141 can be made of materials such as polyester resins (e.g., polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, polymethyl methacrylate resins, polycarbonate (PC) resins, polyethersulfone (PES) resins, polyamide resins (nylon or aramid, etc.), polysiloxane resins, cycloolefin resins, polystyrene resins, polyamide-imide resins, polyurethane resins, polyvinyl chloride resins, polyvinylidene chloride resins, polypropylene resins, polytetrafluoroethylene (PTFE) resins, ABS resins, or cellulose nanofibers. Glass with a flexible thickness can also be used as the substrate 141.

[0364] When a thin film is used as a substrate, the display device may experience shape changes such as wrinkles due to water absorption. Therefore, it is preferable to use a thin film with low water absorption as a substrate. For example, it is preferable to use a thin film with a water absorption rate of 1% or less, more preferably a thin film with a water absorption rate of 0.1% or less, and even more preferably a thin film with a water absorption rate of 0.01% or less.

[0365] Furthermore, various optical components can be disposed on the outer side of the substrate 141. These optical components may include polarizers (e.g., circular polarizers), retardation plates, light diffusion layers (e.g., diffusion films), antireflective layers, and condensing films. Additionally, surface protective layers such as antistatic films to suppress dust adhesion, water-repellent films to prevent soiling, hard coatings to prevent damage during use, or impact-absorbing layers can also be disposed on the outer side of the substrate 141. For example, a glass layer or a silicon dioxide layer (SiO2) can be provided as a surface protective layer. x A protective layer (such as a diamond-like carbon layer) is preferred as it can prevent the surface from getting dirty or damaged. Alternatively, DLC (diamond-like carbon) and aluminum oxide (Al₂O₃) can also be used as surface protective layers. x Materials such as polyester or polycarbonate can be used. Furthermore, materials with high visible light transmittance are preferred for the surface protective layer. Additionally, materials with high hardness are preferred for the surface protective layer.

[0366] When a circular polarizer is superimposed on a display device, it is preferable to use a substrate with high optical isotropy as the substrate included in the display device. A substrate with high optical isotropy has lower birefringence (or, in other words, less birefringence).

[0367] The absolute value of the retardation value of the substrate with high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0368] Examples of films with high optical isotropy include cellulose triacetate (TAC) films, cyclic olefin polymer (COP) films, cyclic olefin copolymer (COC) films, and acrylic films.

[0369] [Light-shielding layer 145] Examples of materials that can be used for the light-shielding layer 145 include carbon black, titanium black, metals, metal oxides, and composite oxides containing solid solutions of multiple metal oxides. Alternatively, the light-shielding layer 145 may also be a structure consisting of multiple layers of material containing coloring layers. For example, the light-shielding layer 145 may be a stacked structure containing layers of material containing coloring layers for transmitting a certain color of light and layers containing coloring layers for transmitting other colors of light.

[0370] [Insulation layer 107] The insulating layer 107 is preferably made of a material that does not readily diffuse impurities. Therefore, the insulating layer 107 serves as a barrier layer to suppress the diffusion of impurities from the outside into the transistor. Examples of impurities include water and hydrogen. By providing the insulating layer 107, the reliability of the display device can be improved.

[0371] The insulating layer 107 can be an insulating layer containing inorganic materials or an insulating layer containing organic materials. For example, inorganic materials such as oxides or nitrides can be suitable for use in the insulating layer 107. More specifically, one or more of silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, silicon oxynitride is suitable for use in the insulating layer 107 because it releases fewer impurities (e.g., water and hydrogen) and can be used as a barrier layer to suppress the diffusion of impurities from the top of the transistor to the transistor. For example, one or more of acrylic resin and polyimide resin can be used as organic materials. Photosensitive materials can also be used as organic materials. Furthermore, two or more of the above-described insulating films can be laminated. The insulating layer 107 can also have a laminated structure containing both inorganic and organic insulating layers.

[0372] [Insulation layer 109] As described above, insulating layer 109 is used as a planarization layer. Insulating layer 109 is preferably an insulating layer containing organic materials. As the organic material, a photosensitive organic resin is preferred, for example, a photosensitive resin composition containing acrylic resin is preferred. Note that in this specification, acrylic resin does not refer only to polymethacrylate or methacrylate resin, but sometimes also to acrylic polymers in a broader sense.

[0373] The insulating layer 109 can also be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of the above resins. Alternatively, the insulating layer 109 can also be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. Furthermore, a photoresist can be used as the photosensitive resin. Both positive and negative photosensitive organic resins can be used.

[0374] The insulating layer 109 may also have a stacked structure of an organic insulating layer and an inorganic insulating layer. For example, the insulating layer 109 may have a stacked structure of an organic insulating layer and an inorganic insulating layer on the organic insulating layer. By providing an inorganic insulating layer on the outermost surface of the insulating layer 109, the inorganic insulating layer can be used as an etching protection layer. As a result, the deterioration of the flatness of the insulating layer 109 due to the etching of a portion of the insulating layer 109 during the formation of the pixel electrode 311 can be suppressed.

[0375] Note that sometimes a portion of the insulating layer 109 is removed during the formation of the pixel electrode 311. The insulating layer 109 may also have recesses in areas that do not overlap with the pixel electrode 311.

[0376] [Pixel electrode 131, pixel electrode 311, conductive layer 324, common electrode 139, common electrode 315 and common electrode 46] Pixel electrode 131, pixel electrode 311, conductive layer 324, common electrode 139, common electrode 315, and common electrode 46 can be made of conductive materials with high transmittance to visible light or conductive materials with high reflectivity to visible light. Examples of conductive materials with high transmittance to visible light include indium oxide, indium tin oxide, indium zinc oxide, and zinc oxide. Furthermore, conductive oxides such as zinc oxide with added gallium can also be used as conductive materials with high transmittance. Graphene can also be used as a conductive material with high transmittance. Graphene can be formed by reducing graphene oxide. For example, graphene can be formed by heating graphene oxide.

[0377] Examples of conductive materials that exhibit high transmittance of visible light include metals such as aluminum, magnesium, titanium, chromium, nickel, copper, yttrium, zirconium, silver, tin, zinc, silver, platinum, gold, molybdenum, tantalum, and tungsten, as well as alloys with these elements as the main components. Examples of such alloys include aluminum-containing alloys such as the aluminum-nickel-lanthanum alloy (Al-Ni-La), silver-containing alloys such as the silver-magnesium alloy, and silver-containing alloys such as the silver-palladium-copper alloy (APC: Ag-Pd-Cu).

[0378] [Protective layer 147] Organic insulating materials are preferably used as the protective layer 147, which can be used as a planarization layer. Inorganic insulating materials can also be used as the protective layer 147. In addition, the protective layer 147 can also have a laminated structure of inorganic and organic insulating materials.

[0379] When an organic insulating material is used as the protective layer 147, the protective layer 147 can be acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of the above resins. Alternatively, as the protective layer 147, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can also be used.

[0380] [Insulation layer 237] Insulating layer 237 can be an insulating layer containing inorganic materials or an insulating layer containing organic materials. Insulating layer 237 can use materials suitable for insulating layer 107 or insulating layer 109. Insulating layer 237 can also have a laminated structure containing both inorganic and organic insulating layers.

[0381] [Protective layer 331] The protective layer 331 can have a single-layer structure or a stacked structure of two or more layers. Furthermore, there are no limitations on the conductivity of the protective layer 331. The protective layer 331 can be at least one of an insulating film, a semiconductor film, and a conductive film.

[0382] By including an inorganic film in the protective layer 331, oxidation of the common electrode 315 and the entry of impurities (such as moisture and oxygen) into the light-emitting element 60 can be suppressed. Therefore, the deterioration of the light-emitting element 60 is suppressed, and the reliability of the display device can be improved.

[0383] The protective layer 331 can be, for example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or an oxynitride insulating film. The protective layer 331 can be an insulating layer containing inorganic materials. The protective layer 331 can be, for example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or an oxynitride insulating film. The protective layer 331 can have a single-layer structure or a multilayer structure. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, indium gallium zinc oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, and tantalum oxide films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. In particular, the protective layer 331 preferably includes a nitrided insulating film or a nitrogen-oxidized insulating film, and more preferably includes a nitrided insulating film.

[0384] Alternatively, an inorganic film comprising In-Sn oxide (ITO), In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or In-Ga-Zn oxide (IGZO) may be used for the protective layer 331. This inorganic film preferably has high resistance; specifically, it preferably has a higher resistance than the common electrode 315. The inorganic film may also contain nitrogen.

[0385] When the light emitted by the light-emitting element 60 is extracted through the protective layer 331, the visible light transmittance of the protective layer 331 is preferably high. For example, ITO, IGZO and alumina are inorganic materials with high visible light transmittance, so they are preferred.

[0386] As a protective layer 331, for example, a stacked structure of an alumina film and a silicon nitride film on the alumina film, or a stacked structure of an alumina film and an IGZO film on the alumina film can be used. By using this stacked structure, impurities (such as water and oxygen) can be suppressed from entering the EL layer side.

[0387] The protective layer 331 can also be made of organic materials. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of the above resins can be used as the protective layer 331. Alternatively, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can also be used as the protective layer 331. Furthermore, the protective layer 331 can also comprise both inorganic and organic materials.

[0388] The protective layer 331 can also have a two-layer structure formed using different deposition methods. Specifically, the first layer of the protective layer 331 can be formed using the ALD method, while the second layer of the protective layer 331 can be formed using the sputtering method.

[0389] [Adhesive layer 142] As the adhesive layer 142, various curing adhesives such as UV-curing adhesives, reactive curing adhesives, thermosetting adhesives, or anaerobic adhesives can be used. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins can also be used. Furthermore, adhesive sheets can also be used, for example.

[0390] The above is an explanation of the constituent elements.

[0391] <Example 2 of display device structure> The following describes an example of the structure of the driving circuit included in a display device according to one aspect of the present invention.

[0392] [Signal line drive circuit] Figure 29A It is shown Figure 1A The block diagram shown illustrates an example structure of the signal line driving circuit 13. The signal line driving circuit 13 includes a shift register circuit 71 and a latch circuit 73. <1> To latch circuit 73 <n 2>and demultiplexing circuit 75 <1> To demultiplexing circuit 75 <n 2>.

[0393] Latch circuit 73 <1> To latch circuit 73 <n 2>The circuit 17 is electrically connected to a circuit located outside the signal line drive circuit 13. Alternatively, the circuit 17 may also be included within the signal line drive circuit 13. Furthermore, the latch circuit 73 is electrically connected to the input terminal of the demultiplexing circuit 75 via wiring 44. The output terminal of the demultiplexing circuit 75 is electrically connected to wiring 43. Figure 29A An example is shown where the demultiplexing circuit 75 includes two output terminals, each electrically connected to a different wiring 43. Specifically, the demultiplexing circuit 75 is shown. <1> An example is shown where the two output terminals are electrically connected to wiring 43[1] and wiring 43[2], respectively. Additionally, a demultiplexing circuit 75 is also shown. <n 2>An example of two output terminals being electrically connected to wiring 43[n-1] and wiring 43[n] respectively.

[0394] Circuit 17 has from Figure 1A The display device 10 shown functions as an interface for receiving external image data. Circuit 17 can also generate image data.

[0395] The image data output by circuit 17 is supplied to latch circuit 73. <1> To latch circuit 73 <n 2>The shift register circuit 71 has the function of generating signals to control the latch circuit 73. For example, when a start pulse is supplied to the shift register circuit 71, the shift register circuit 71 sequentially outputs signals to control the latch circuit 73. <1> To latch circuit 73 <n 2>The driving signal.

[0396] The latch circuit 73 has the function of holding or outputting the image data output from the circuit 17. The latch circuit 73 is selected to hold or output the image data based on the signal supplied from the shift register circuit 71.

[0397] The demultiplexing circuit 75 has the function of outputting the image data output by the latching circuit 73 from any one of the output terminals of the demultiplexing circuit 75. The demultiplexing circuit 75 can determine the output terminal of the output image data based on the selection signal input to the selection signal input terminal of the demultiplexing circuit 75. The selection signal generation circuit 19, which is located outside the signal line drive circuit 13, can generate the selection signal. Alternatively, the selection signal generation circuit 19 can be included in the signal line drive circuit 13.

[0398] By incorporating a demultiplexing circuit 75 into the signal line drive circuit 13, the size of the signal line drive circuit 13 can be reduced. For example, the number of latch circuits 73 included in the signal line drive circuit 13 can be reduced. Additionally, the number of transistors included in the shift register circuit 71 can be reduced.

[0399] For example, if the demultiplexing circuit 75 is not provided in the signal line driving circuit 13, the signal line driving circuit 13 includes n latch circuits 73. On the other hand, by providing the demultiplexing circuit 75 in the signal line driving circuit 13, the number of latch circuits 73 can be less than n. As a result, the size of the signal line driving circuit 13 can be reduced.

[0400] Therefore, when the pixel density of the display unit 20 is equal, compared to the case where the demultiplexing circuit 75 is not provided, for example, the density of transistors provided in the signal line drive circuit 13 can be reduced. Thus, when the transistor density provided in the signal line drive circuit 13 is equal, the pixel density of the display unit 20 can be increased. Therefore, the pixel 21 can be miniaturized to achieve a high-definition display device 10. Furthermore, when the transistor density provided in the signal line drive circuit 13 is increased, the signal line drive circuit 13 can be miniaturized. Therefore, the display device 10 can be a small display device. Moreover, the display device 10 can be a display device with a narrow bezel. Note that the demultiplexing circuit 75 may not be provided in the signal line drive circuit 13. Alternatively, the demultiplexing circuit 75 may be provided externally to the signal line drive circuit 13.

[0401] Figure 29A The example shown is of a demultiplexing circuit 75 including two output terminals, but the demultiplexing circuit 75 may also include three or more output terminals. For example, if the demultiplexing circuit 75 includes three output terminals, the signal line drive circuit 13 may include n / 3 demultiplexing circuits 75.

[0402] The more output terminals a demultiplexing circuit 75 includes, the smaller the signal line drive circuit 13 can be. This allows the display device 10 to achieve higher resolution, smaller size, and narrower bezels.

[0403] Figure 29B This is a circuit diagram showing an example of the structure of latch circuit 73. Note that in Figure 29B In order to illustrate the connection relationship, circuit 17 and shift register circuit 71 are also shown.

[0404] In this specification and other materials, the circuit diagrams sometimes do not show all the components of the circuit. For example, in addition to the components shown in the circuit diagram, the circuit may sometimes include a buffer amplifier.

[0405] The latch circuit 73 is electrically connected to terminals R, D, and Q. Terminal R is electrically connected to the output terminal of the shift register circuit 71. Terminal D is electrically connected to the output terminal of circuit 17. Terminal Q is electrically connected to wiring 44. From the perspective of the latch circuit 73, terminals R and D are used as input terminals, and terminal Q is used as an output terminal.

[0406] The latch circuit 73 includes transistor 81, transistor 83, capacitor 85, and inverter circuit 90.

[0407] The gate of transistor 81 and the input terminal of inverter circuit 90 are electrically connected to terminal R. One of the source and drain of transistor 81 is electrically connected to terminal D. The other of the source and drain of transistor 81 is electrically connected to one of the source and drain of transistor 83. One of the source and drain of transistor 83 is electrically connected to one electrode of capacitor 85. The other of the source and drain of transistor 83 is electrically connected to terminal Q. A potential VSS can be supplied to the other electrode of capacitor 85.

[0408] like Figure 29B As shown, the on and off states of each of transistors 81 and 83 switch according to the signal input to terminal R. For example, when a signal equivalent to the logic value "1" is input to terminal R, transistor 81 is in the on state and transistor 83 is in the off state. Conversely, for example, when a signal equivalent to the logic value "0" is input to terminal R, transistor 81 is in the off state and transistor 83 is in the on state.

[0409] When a signal equivalent to the logic value "1" is input to terminal R, the potential representing the image data input from circuit 17 to terminal D is maintained in capacitor 85. Thus, the image data is held in latch circuit 73.

[0410] Next, when a signal equivalent to the logic value "0" is input to terminal R, transistor 81 is turned off and transistor 83 is turned on. Therefore, the potential held in capacitor 85 is output from terminal Q. Consequently, image data is output from latch circuit 73.

[0411] Therefore, the drive of the latch circuit 73 can be controlled based on the signal input to terminal R. As described above, terminal R is electrically connected to the output terminal of the shift register circuit 71. Therefore, the shift register circuit 71 can control the drive of the latch circuit 73.

[0412] Transistors 81 and 83 are preferably OS transistors. In particular, OS transistors preferably use a metal oxide containing at least one of indium, element M (where element M is aluminum, gallium, yttrium, or tin), and zinc in the channel formation region. By using such OS transistors in transistors 81 and 83, the off-state current of transistors 81 and 83 can be made extremely low. This suppresses leakage of the potential held in capacitor 85. Consequently, the image data held in latch circuit 73 can be converted into analog data. Alternatively, latch circuit 73 can also hold digital data. In this case, signal line drive circuit 13 includes a digital-to-analog converter (D / A converter) circuit, which supplies analog data to demultiplexing circuit 75 after the digital data output from latch circuit 73 has been converted into analog data by the D / A converter.

[0413] Here, by Figure 2A1 and Figure 2B When transistor 50 is used in transistors 81 and 83, it can reduce the area occupied by the latch circuit 73, so it is preferred.

[0414] Figure 29C This is a circuit diagram showing an example of the structure of an inverter circuit 90. The inverter circuit 90 includes transistors 91, 93, 95, and 97, and a capacitor 99.

[0415] A potential VDD can be supplied to one of the source and drain terminals of transistor 91, the gate of transistor 91, and one of the source and drain terminals of transistor 95 included in the latch circuit 73. The other of the source and drain terminals of transistor 91 is electrically connected to one of the source and drain terminals of transistor 93. One of the source and drain terminals of transistor 93 is electrically connected to the gate of transistor 95. The other of the source and drain terminals of transistor 95 is electrically connected to one electrode of capacitor 99. The gate of transistor 95 is electrically connected to the other electrode of capacitor 99. One electrode of capacitor 99 is electrically connected to one of the source and drain terminals of transistor 97. One of the source and drain terminals of transistor 97 is electrically connected to the gate of transistor 83. A potential VSS can be supplied to the other of the source and drain terminals of transistor 93 and transistor 97. The gates of transistor 93 and transistor 97 are electrically connected to terminal R.

[0416] The transistors included in the latch circuit 73 can all be transistors of the same polarity; for example, an n-channel transistor can be used. Therefore, transistors of the same type can be used for all transistors included in the latch circuit 73. For example, an OS transistor can be used for all transistors included in the latch circuit 73. Figure 2A1 and Figure 2B The transistor 50 shown serves as all the transistors included in the latch circuit 73.

[0417] By using the same type of transistor for all transistors included in the latch circuit 73, all transistors included in the latch circuit 73 can be manufactured through the same process. Therefore, compared to the case where the latch circuit 73 includes more than two types of transistors, the number of manufacturing steps for the latch circuit 73 can be reduced. In addition, by using transistor 50 as all transistors included in the latch circuit 73, the latch circuit 73 can be miniaturized.

[0418] Note that transistor 50 may not be used as a transistor included in latching circuit 73. For example, at least one of transistors 81, 83, 91, 93, 95, and 97 may be used in a structure that does not include openings 121 and 123. Specifically, a planar transistor may also be used.

[0419] At least one of transistors 91, 93, 95, and 97 included in inverter circuit 90 does not need to be an OS transistor; for example, a Si transistor can also be used. Furthermore, one or both of transistors 81 and 83 also do not need to be OS transistors; for example, Si transistors can also be used.

[0420] Figure 30 It is shown Figure 1A A block diagram illustrating a specific structural example of the demultiplexing circuit 75 included in the signal line driving circuit 13 shown. Figure 30 The selection signal generation circuit 19 is also shown. Figure 30 An example of a demultiplexing circuit 75 including two transistors 33 is shown.

[0421] The signal line driving circuit 13 includes transistors 33[1] to 33[n]. Figure 30 The demultiplexing circuit 75 is shown. <1> Including transistor 33[1] and transistor 33[2], demultiplexing circuit 75 <n 2>Examples include transistor 33[n-1] and transistor 33[n].

[0422] One of the source and drain of transistor 33[1] and one of the source and drain of transistor 33[2] are used as demultiplexing circuit 75 <1> The input terminals, and wiring 44 <1> Electrical connection. One of the source and drain of transistor 33[n-1] and one of the source and drain of transistor 33[n] are used as demultiplexing circuit 75. <n 2>The input terminals, and wiring 44 <n 2>Electrical connection.

[0423] The other of the source and drain of transistor 33[1] is used as a demultiplexing circuit 75. <1> The first output terminal is electrically connected to wiring 43[1]. The other of the source and drain of transistor 33[2] is used as a demultiplexing circuit 75. <1> The second output terminal is electrically connected to wiring 43[2]. Another of the source and drain terminals of transistor 33[n-1] is used as a demultiplexing circuit 75. <n 2>The first output terminal is electrically connected to wiring 43[n-1]. The other of the source and drain terminals of transistor 33[n] is used as a demultiplexing circuit 75. <n 2>The second output terminal is electrically connected to wiring 43[n].

[0424] The gate of transistor 33[1] is used as the demultiplexing circuit 75 <1> The selection signal input terminal is connected to the selection signal generation circuit 19 via wiring 42_1. The gate of transistor 33[2] is used as the demultiplexing circuit 75. <1> The selection signal input terminal is connected to the selection signal generation circuit 19 via wiring 42_2. The gate of transistor 33[n-1] is used as the demultiplexing circuit 75. <n 2>The selection signal input terminal is connected to the selection signal generation circuit 19 via wiring 42_1. The gate of transistor 33[n] is used as a demultiplexing circuit 75. <n 2>The selection signal input terminal is connected to the selection signal generation circuit 19 via wiring 42_2.

[0425] The selection signal generation circuit 19 can generate a first signal and a second signal as selection signals, for example. In this case, the selection signal generation circuit 19 can output the first signal to wiring 42_1 and the second signal to wiring 42_2. Here, for example, by setting the first signal to a signal that turns on transistor 33 and setting the second signal to a signal that turns off transistor 33, the demultiplexing circuit 75 can output image data from the first output terminal. Alternatively, for example, by setting the first signal to a signal that turns off transistor 33 and setting the second signal to a signal that turns on transistor 33, the demultiplexing circuit 75 can output image data from the second output terminal.

[0426] As described above, for example, when the first signal is a signal that turns transistor 33 on, the second signal can be a signal that turns transistor 33 off. Furthermore, when the first signal is a signal that turns transistor 33 off, the second signal can be a signal that turns transistor 33 on. Thus, the first and second signals can be complementary signals. For example, when both the first and second signals are 1-bit digital signals, the second signal can be at a low potential when the first signal is high, and vice versa.

[0427] The demultiplexing circuit 75 may also include more than three transistors 33. In this case, the demultiplexing circuit 75 may include more than three output terminals.

[0428] Figure 31A It is shown Figure 1C Sub-pixel 23 shown Figure 30 A plan view of an example structure of the demultiplexing circuit 75 shown. Figure 31A The following is a structural example of sub-pixel 23[2k-1], sub-pixel 23[2k] and demultiplexing circuit 75[k] (k is an integer greater than 1 and less than n / 2).

[0429] Figure 31B yes Figure 31A The cross-sectional view shown by the dotted line D1-D2 illustrates a structural example of transistor 33[2k-1]. Note that in... Figure 31B The layers that constitute the liquid crystal element 70 and the light-emitting element 60, which are disposed above the insulating layer 107, are omitted.

[0430] Figure 31A and Figure 31B As shown, the demultiplexing circuit 75[k] includes transistor 33[2k-1] and transistor 33[2k]. In Figure 31A and Figure 31B In the diagram, the structures of transistors 33[2k-1] and 33[2k] are similar to... Figure 2A1 and Figure 2B The structure of the transistor 50 shown is the same. Here, the conductive layer 112, semiconductor layer 113, and conductive layer 115 included in the transistor 33 are conductive layer 112d, semiconductor layer 113d, and conductive layer 115d, respectively. In addition, the opening 121 and opening 123 provided in the transistor 33 are opening 121d and opening 123d, respectively.

[0431] Conductive layer 111a[2k-1] is used as another of the source and drain electrodes of transistor 33[2k-1]. Conductive layer 111a[2k] is used as another of the source and drain electrodes of transistor 33[2k]. Conductive layer 112d is used as another of the source and drain electrodes of transistor 33[2k] and another of the source and drain electrodes of transistor 33[2k]. Conductive layer 115d_1 is used as the gate electrode of transistor 33[2k-1]. Conductive layer 115d_2 is used as the gate electrode of transistor 33[2k].

[0432] Transistor 33[2k-1] includes a semiconductor layer 113d[2k-1]. Transistor 33[2k] includes a semiconductor layer 113d[2k]. Transistor 33[2k-1] has an opening 121d[2k-1] and an opening 123d[2k-1]. Transistor 33[2k] has an opening 121d[2k] and an opening 123d[2k].

[0433] Figure 31A This shows subpixel 23 in the first row. Therefore, Figure 31A The transistor 51 shown has a conductive layer 115a as a gate electrode.

[0434] At least a portion of conductive layer 111a[2k-1] is used as wiring 43[2k-1] which functions as a signal line. At least a portion of conductive layer 111a[2k] is used as wiring 43[2k] which functions as a signal line. At least a portion of conductive layer 115d_1 is used as wiring 42_1, and is connected to... Figure 30 The selection signal generation circuit 19 shown is electrically connected. At least a portion of the conductive layer 115d_2 is used as wiring 42_2 and is connected to... Figure 30 The selection signal generation circuit 19 shown is electrically connected.

[0435] Wiring 42_1 and wiring 42_2 extend in the second direction. In this specification, the region in the conductive layer 115d that extends in the second direction is used as wiring 42.

[0436] The demultiplexing circuit 75 has an area where wiring 42 and wiring 43 overlap. In other words, the demultiplexing circuit 75 has an area where wiring 42 and wiring 43 intersect. More specifically, the demultiplexing circuit 75 has a crossover portion between wiring 42 and wiring 43.

[0437] An opening 121d, an opening 123d, and a semiconductor layer 113d are disposed at the intersection of wiring 42 and wiring 43. Therefore, a transistor 33 is disposed at the intersection of wiring 42 and wiring 43. Thus, the transistor 33 includes wiring 42 used as a gate electrode, wiring 43 used as one of a source electrode and a drain electrode, a conductive layer 112d used as the other of the source electrode and drain electrode, a semiconductor layer 113d, and an insulating layer 105 used as a gate insulating layer.

[0438] By placing transistor 33 at the intersection of wiring 42 and wiring 43, the area occupied by the demultiplexing circuit 75 can be reduced compared to placing transistor 33 in an area outside the intersection of wiring 42 and wiring 43. Therefore, miniaturization of the display device 10 can be achieved. Thus, the display device 10 can be a small display device. Furthermore, the display device 10 can be a display device with a narrow bezel.

[0439] By using transistor 50 as both transistor 51 in sub-pixel 23 and transistor 33 in demultiplexing circuit 75, sub-pixel 23 and demultiplexing circuit 75 can be manufactured using the same process. Furthermore, by using transistor 50 as all transistors in sub-pixel 23 and all transistors in signal line driving circuit 13, sub-pixel 23 and signal line driving circuit 13 can be manufactured using the same process. This reduces the number of manufacturing steps in display device 10. Note that... Figure 31A and Figure 31B This diagram shows an example of the demultiplexing circuit 75 when sub-pixel 23 includes a liquid crystal element, but it can also be used when sub-pixel 23 includes a light-emitting element. Figure 31A and Figure 31B The structure shown.

[0440] [Line drawing drive circuit] Figure 32A This is a block diagram illustrating a structural example of the scan line drive circuit 11, and more specifically, a block diagram illustrating a structural example of the shift register circuit in the scan line drive circuit 11. Figure 32A Pulse output circuits 34[1] to 34[n+2] are shown. The output terminals of pulse output circuits 34[1] to 34[n+2] are electrically connected to wirings 41[1] to 41[n+2], which are used as scan lines, respectively. In addition, the output terminals of pulse output circuits 34 other than the last stage pulse output circuit 34[n+2] are electrically connected to the input terminals of the next stage pulse output circuit 34. Note that wirings 41[n+1] and 41[n+2] can be used as so-called pseudo wirings that are not electrically connected to pixel 21.

[0441] The first-stage pulse output circuit 34[1] is input with a start pulse signal. The pulse output circuits 34[1] to 34[n+2] are input with clock signals CK_A and CK_B. The clock signal CK_B can be a signal whose phase is different from that of the clock signal CK_A.

[0442] Figure 32B This is a circuit diagram showing an example of the structure of the pulse output circuit 34. The pulse output circuit 34 includes transistors 35, 36, 37, and 38, and a capacitor 39.

[0443] One of the source and drain of transistor 35 is electrically connected to one of the source and drain of transistor 36. One of the source and drain of transistor 36 is electrically connected to the gate of transistor 37. The gate of transistor 37 is electrically connected to one electrode of capacitor 39. One of the source and drain of transistor 37, one of the source and drain of transistor 38, and the other electrode of capacitor 39 are electrically connected to wiring 41. Here, the node electrically connected to one of the source and drain of transistor 35, one of the source and drain of transistor 36, the gate of transistor 37, and one electrode of capacitor 39 is called node net A.

[0444] The start pulse signal SP or the output signal Former P from the previous stage pulse output circuit 34 is supplied to the other of the source and drain terminals of transistor 35 and the gate of transistor 35. The output signal Next P from the next stage pulse output circuit 34 is supplied to the gate of transistor 36. The other of the source and drain terminals of transistor 37 is input with clock signal CK_A. The gate of transistor 38 is input with clock signal CK_B. The output signal P is output from wiring 41. The potential VSS is supplied to the other of the source and drain terminals of transistor 36 and the other of the source and drain terminals of transistor 38.

[0445] Figure 32C It is shown Figure 32B The timing diagram shows an example of the driving method for the pulse output circuit 34. Figure 32C At time T1, clock signal CK_A is set to low and clock signal CK_B is set to high. At this time, the start pulse signal SP or output signal Former P is set to high. As a result, transistor 35 is turned on, and the potential of node netA rises. Note that because transistor 38 is turned on, the potential of wiring 41 is low.

[0446] At time T2, clock signal CK_A is set to high and clock signal CK_B is set to low. At this time, the start pulse signal SP or output signal Former P is set to low. Therefore, transistor 35 is in the off state. Since transistor 36 is also in the off state, node net A is in a floating state. Here, clock signal CK_A is high and clock signal CK_B is low, so the potential of node net A rises through the capacitive coupling of capacitor 39. Therefore, transistor 37 is in the on state, and output signal P, like clock signal CK_A, becomes high.

[0447] At time T3, clock signal CK_A is set to low and clock signal CK_B is set to high. When the output signal Next P goes high at this time, transistor 36 is turned on. Since transistor 35 is turned off, the potential of node net A becomes low.

[0448] Figure 32A and Figure 32B The example of the shift register circuit structure shown and Figure 32C An example of the driving method for the shift register circuit shown can be applied to Figure 29A The shift register circuit 71 shown is illustrated.

[0449] Figure 33A It is shown Figure 1C Sub-pixel 23 shown Figure 32B A plan view of an example structure of the pulse output circuit 34 shown. Figure 33A An example of the structure of the transistor 37 included in the pulse output circuit 34 is shown.

[0450] Figure 33B yes Figure 33A The cross-sectional view shown by the dotted lines D3-D4 illustrates an example of the structure of transistor 37. Note that in... Figure 33B The layers that constitute the liquid crystal element 70 and the light-emitting element 60, which are disposed above the insulating layer 107, are omitted.

[0451] exist Figure 33A and Figure 33B In the middle, the structure of transistor 37 is similar to Figure 2A1 and Figure 2B The transistor 50 shown has the same structure. Here, the conductive layer 111, conductive layer 112, semiconductor layer 113, and conductive layer 115 included in transistor 37 are conductive layer 111e, conductive layer 112e, semiconductor layer 113e, and conductive layer 115e, respectively. Furthermore, the openings 121 and 123 provided in transistor 37 are opening 121e and opening 123e, respectively. Note that... Figure 32B The structures of transistors 35, 36 and 38 shown can also be the same as those of transistor 50.

[0452] The insulating layer 105 includes an opening 161 reaching the conductive layer 112e. A conductive layer 115a is disposed such that it has a region located inside the opening 161. The conductive layer 115a has a region inside the opening 161 that contacts the top surface of the conductive layer 112e. Note that in Figure 33A In this invention, although the shape of the opening 161 when viewed from a plane is a rectangle with rounded corners, one aspect of the invention is not limited to this and it may have the same shape as the openings 125 to 129.

[0453] When transistor 50 is used as both the transistor included in sub-pixel 23 and the transistor included in scan line driving circuit 11, sub-pixel 23 and scan line driving circuit 11 can be manufactured using the same process. Specifically, by using transistor 50 as both the transistor included in sub-pixel 23 and the transistor included in scan line driving circuit 11, sub-pixel 23 and scan line driving circuit 11 can be manufactured using the same process. This reduces the number of manufacturing steps in the display device 10. Note that... Figure 33A and Figure 33B The diagram shows an example of the structure of transistor 37 when sub-pixel 23 includes a liquid crystal element, but it can also be used when sub-pixel 23 includes a light-emitting element. Figure 33A and Figure 33B The structure shown.

[0454] <Example of Touch Panel Structure> The display device 10 may also include a touch sensor. That is, the display device 10 may also be a touch panel. Figure 34 It shows the... Figure 17A A cross-sectional view of an example structure with an added touch sensor.

[0455] In this specification and the like, a touch panel is shown as a display device including a touch sensor.

[0456] exist Figure 34 In the touch panel shown, a conductive layer 117 is provided on the same surface as conductive layer 115a. Therefore, conductive layer 117 can contain the same material as conductive layer 115a and can be formed by the same process. For example, conductive layer 115a and conductive layer 117 can be formed by processing the same conductive film.

[0457] The conductive layer 117 is electrically connected to the detection circuit (not shown). Note that it can be... Figure 1A The circuit 15 shown serves as a detection circuit. In this case, the conductive layer 117 can be used as wiring 45. Alternatively, the conductive layer 117 can be electrically connected to wiring 45.

[0458] Insulating layers 107, 109, and 151 include an opening 171 extending into the conductive layer 117. A sensor electrode 173 is disposed such that it has a region located inside the opening 171. The sensor electrode 173 has a region inside the opening 171 that contacts the top surface of the conductive layer 117.

[0459] The opening 171 can be formed in parallel with the opening 125. The sensor electrode 173 is disposed on the same surface as the pixel electrode 131. Therefore, the sensor electrode 173 can contain the same material as the pixel electrode 131 and be formed using the same process. For example, the pixel electrode 131 and the sensor electrode 173 can be formed by processing the same conductive film. Note that an insulating layer 133 can be provided between the sensor electrode 173 and the liquid crystal 135.

[0460] exist Figure 34 In the diagram, the electric field 175 formed between the sensor electrode 173 and the common electrode 46 is represented by a dashed line. Furthermore, Figure 34 This illustrates, for example, the case where the object being detected 177 crosses the electric field 175. When the object being detected 177 crosses the electric field 175, the electric field 175 is shielded. As a result, the capacitance value of the capacitor formed between the sensor electrode 173 and the common electrode 46 changes. When the detection circuit detects the change in capacitance value, it can detect the object's contact or proximity to the touch panel.

[0461] Figure 35 yes Figure 34 The example shown is a cross-sectional view of an example where conductive layer 117 is formed on the same surface as conductive layer 112a. Figure 35 In the touch panel shown, conductive layer 117 may contain the same material as conductive layer 112a and may be formed by the same process. For example, conductive layer 112a and conductive layer 117 may be formed by processing the same conductive film.

[0462] exist Figure 35 In the touch panel shown, insulating layers 105, 107, 109, and 151 include an opening 174 extending into the conductive layer 117. A sensor electrode 173 is disposed such that it has a region located inside the opening 174. The sensor electrode 173 has a region inside the opening 174 that contacts the top surface of the conductive layer 117.

[0463] Figure 36 yes Figure 34 The example shown is a cross-sectional view of an example where the conductive layer 117 is formed on the same surface as the conductive layer 111a. Figure 36 In the touch panel shown, conductive layer 117 may contain the same material as conductive layer 111a and may be formed by the same process. For example, conductive layer 111a and conductive layer 117 may be formed by processing the same conductive film.

[0464] exist Figure 36 In this configuration, sensor electrode 173 is electrically connected to conductive layer 117 via conductive layer 172. Insulating layers 103 and 105 include openings 178 extending to conductive layer 117, with conductive layer 172 disposed such that it has a region located inside opening 178. Furthermore, insulating layers 107, 109, and 151 include openings 179 extending to conductive layer 172, with sensor electrode 173 disposed such that it has a region located inside opening 179. Conductive layer 172 has a region that contacts conductive layer 117 inside opening 178, and sensor electrode 173 has a region that contacts conductive layer 172 inside opening 179. Note that conductive layer 117 and sensor electrode 173 may also be electrically connected without being separated by conductive layer 172. In this case, sensor electrode 173, for example, has a region that contacts conductive layer 117 inside the openings provided in insulating layers 103, 105, 107, 109, and 151.

[0465] Figure 37A This is a cross-sectional view showing a structural example of the connection between conductive layer 112 and conductive layer 115. Figure 37A An example is shown where the insulating layer 105 includes an opening 181 leading to the conductive layer 112, and the conductive layer 112 is connected to the conductive layer 115 inside the opening 181. Figure 37A Specifically, an example is shown where the conductive layer 115 has a region inside the opening 181 that contacts the top surface of the conductive layer 112.

[0466] Figure 37B This is a cross-sectional view showing a structural example of the connection between conductive layer 111 and conductive layer 115. Figure 37B An example is shown where insulating layers 103 and 105 include an opening 183 leading to conductive layer 111, and inside the opening 183, conductive layer 111 is connected to conductive layer 115. Figure 37B Specifically, an example is shown where the conductive layer 115 has a region inside the opening 183 that contacts the top surface of the conductive layer 111.

[0467] Figure 37C This is a cross-sectional view showing a structural example of the connection between conductive layer 111 and conductive layer 112. Figure 37C An example is shown where the insulating layer 103 includes an opening 185 leading to the conductive layer 111, and inside the opening 185, the conductive layer 111 is connected to the conductive layer 112. Figure 37C Specifically, an example is shown where the conductive layer 112 has a region inside the opening 185 that contacts the top surface of the conductive layer 111.

[0468] Figure 37D This is a cross-sectional view showing an example of an electrical connection between conductive layer 111 and conductive layer 112 separated by conductive layer 188. Figure 37D In the example shown, insulating layer 105 includes an opening 187 leading to conductive layer 112, within which conductive layer 112 is connected to conductive layer 188. Furthermore, insulating layers 103 and 105 include openings 189 leading to conductive layer 111, within which conductive layer 111 is connected to conductive layer 188. Figure 37D The example shown is an example of conductive layer 188 having a region inside opening 187 that contacts the top surface of conductive layer 112 and a region inside opening 189 that contacts the top surface of conductive layer 111.

[0469] The conductive layer 188 can be disposed on the same surface as the conductive layer 115. Therefore, the conductive layer 188 can contain the same material as the conductive layer 115 and can be formed by the same process. For example, the conductive layer 115 and the conductive layer 188 can be formed by processing the same conductive film.

[0470] Figure 37D The openings 187 and 189 shown can be connected with Figure 37A The opening 181 shown and Figure 37B The openings 183 shown are formed in parallel. Therefore, with... Figure 37C Compared to the method shown, which electrically connects conductive layers 111 and 112, the number of manufacturing steps in a display device according to one aspect of the present invention can sometimes be reduced. On the other hand, when using... Figure 37C When the conductive layer 111 and the conductive layer 112 are electrically connected using the method shown, it is sometimes possible to connect them with... Figure 37D The method shown reduces wiring resistance when making electrical connections.

[0471] <Example 1 of a manufacturing method for a display device> Hereinafter, a method for manufacturing a display device according to one aspect of the present invention will be described with reference to the accompanying drawings.

[0472] Thin films (insulating films, semiconductor films, and conductive films, etc.) constituting display devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and alumina deposition (ALD). CVD methods include PECVD and thermal CVD. Furthermore, metal-organic chemical vapor deposition (MOCVD) is one type of thermal CVD method.

[0473] Thin films (insulating films, semiconductor films, conductive films, etc.) that make up display devices can be formed using wet deposition methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, or doctor blade coating.

[0474] In the processing of the aforementioned thin films, for example, the film can be etched according to the pattern of the photoresist mask after forming it using photolithography. Alternatively, the film can be processed using nanoimprint lithography, sandblasting, or lift-off methods. Furthermore, island-shaped thin films can be directly formed using deposition methods that employ masking techniques such as metal masks. Additionally, photosensitive thin films can be processed by exposure and development. In other words, photosensitive thin films can be processed using photolithography.

[0475] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these. Additionally, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can also be used. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Alternatively, an electron beam can be used instead of the light for exposure. Extreme ultraviolet light, X-rays, or electron beams allow for extremely fine processing and are therefore preferred. Note that when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0476] In thin film etching, one or more of the following methods can be used: dry etching, wet etching, and sandblasting.

[0477] Here, refer to Figures 38A to 42C right Figure 6A An example of a method for manufacturing the display device will be described. Figures 38A to 40C and Figures 42A to 42C Showing the corresponding Figure 4A and Figure 4B The cross-sectional view shown is the dotted line B1-B2. Figure 41A A floor plan is shown. Figure 41B and Figure 41C Show Figure 41A The cross-sectional view shown is the dotted line B1-B2.

[0478] First, a conductive film that will become the conductive layer 111a is formed on the substrate 101, and the conductive film is processed to form the conductive layer 111a. Figure 38A The conductive film is suitable for formation using sputtering. The processing of the conductive layer film can be performed using one or both of wet etching and dry etching, with wet etching being preferred. As described above, at least a portion of the conductive layer 111a is used as wiring 43 and extends in the first direction.

[0479] Next, insulating layers 103a and 103b are formed on conductive layer 111a. Figure 38B ).

[0480] When forming insulating layers 103a and 103b, sputtering or PECVD is preferred. It is preferable to form insulating layer 103b after forming insulating layer 103a in a manner that prevents the surface of insulating layer 103a from being exposed to the atmosphere. This suppresses the adhesion of atmospheric impurities to the surface of insulating layer 103a. Examples of such impurities include water and organic matter. For example, it is preferable to continuously form insulating layer 103b using the same apparatus after forming insulating layer 103a.

[0481] The substrate temperature during the formation of insulating layers 103a and 103b is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. By setting the substrate temperature during the formation of insulating layers 103a and 103b to the above range, the amount of impurities (e.g., water and hydrogen) released from the insulating layers 103a and 103b themselves can be reduced, thereby suppressing the diffusion of impurities into the semiconductor layer 113. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0482] Note that since insulating layers 103a and 103b are formed first, and then semiconductor layer 113 is formed, there is no concern about oxygen being removed from semiconductor layer 113 due to the heat applied during the formation of insulating layers 103a and 103b.

[0483] Alternatively, heat treatment can be performed after the insulating layers 103a and 103b are formed. By performing heat treatment, impurities (such as water and hydrogen) can be removed from the film of insulating layer 103a, the film of insulating layer 103b, and the surface.

[0484] After the insulating layer 103b is formed, oxygen can also be supplied to the insulating layer 103b. Methods for supplying oxygen include, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. For plasma treatment, an apparatus that plasma-plasmizes oxygen gas at high-frequency power can be suitably used. Examples of apparatuses that plasma-plasmize gas at high-frequency power include PECVD apparatuses, plasma etching apparatuses, and plasma ashing apparatuses. Plasma treatment is preferably performed in an oxygen-containing atmosphere. For example, plasma treatment is preferably performed in an atmosphere containing one or more of oxygen, nitrous oxide (N₂O), nitrogen dioxide (NO₂), carbon monoxide, and carbon dioxide.

[0485] Note that after forming the insulating layer 103b, the plasma treatment can be performed without exposing the surface of the insulating layer 103b to the atmosphere. For example, if a PECVD apparatus is used when forming the insulating layer 103b, it is preferable to use the PECVD apparatus for the plasma treatment. This can improve productivity. Specifically, N2O plasma treatment can be performed continuously after forming the insulating layer 103b using a PECVD apparatus.

[0486] Next, preferably a film 130 is formed on the insulating layer 103b. Figure 38C Oxygen can be supplied to the insulating layer 103b by forming a film 130 in an oxygen-containing atmosphere.

[0487] There are no limitations on the conductivity of the film 130. At least one of insulating films, semiconductor films, and conductive films can be used as the film 130. For example, the film 130 can be made of alumina, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0488] As the film 130, it is preferable to use an oxide material containing one or more elements that are the same as those in the semiconductor layer 113. In particular, it is preferable to use an oxide semiconductor material that can be used in the semiconductor layer 113.

[0489] When film 130 is formed, the higher the oxygen flow rate ratio of the deposition gas introduced into the processing chamber of the deposition apparatus, or the higher the oxygen partial pressure in the processing chamber, the greater the amount of oxygen supplied to the insulating layer 103b. The oxygen flow rate ratio or oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% ​​or more and 100% or less, more preferably 80% or more and 100% or less, and even more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% so that the oxygen partial pressure is as close as possible to 100%.

[0490] Thus, by forming film 130 using sputtering in an oxygen-containing atmosphere, oxygen can be supplied to insulating layer 103b while preventing oxygen from escaping from insulating layer 103b during film formation. As a result, more oxygen can be confined within insulating layer 103b. Furthermore, more oxygen can be supplied to semiconductor layer 113 through subsequent heat treatment. As a result, oxygen vacancies and Vo in semiconductor layer 113 can be reduced. O H, which can realize transistors that exhibit good electrical characteristics and high reliability.

[0491] After the film 130 is formed, a heat treatment can also be performed. By performing a heat treatment after the film 130 is formed, oxygen can be effectively supplied from the film 130 to the insulating layer 103b.

[0492] The heat treatment temperature is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, and oxygen. Dry air (CDA) can also be used as a nitrogen-containing or oxygen-containing atmosphere. Note that the content of hydrogen and oxygen in this atmosphere is preferably as low as possible. As this atmosphere, a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, is preferred. By using an atmosphere with the lowest possible content of hydrogen and water, the absorption of hydrogen and water by insulating layers 103a and 103b can be prevented as much as possible. This heat treatment can be performed using an oven or a rapid thermal annealing (RTA) apparatus. By using an RTA apparatus, the heat treatment time can be shortened.

[0493] Oxygen may also be supplied to the insulating layer 103b through the membrane 130 after the formation of the membrane 130 or after the above-described heat treatment. As a method of supplying oxygen, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment may be used, for example. Regarding plasma treatment, please refer to the above description, so its detailed explanation is omitted.

[0494] Next, film 130 is removed. While there are no particular limitations on the method for removing film 130, wet etching can be suitably employed. By using wet etching, etching of the insulating layer 103b during the removal of film 130 can be suppressed. Therefore, the reduction in the thickness of the insulating layer 103b can be suppressed, and the thickness of the insulating layer 103b can be made uniform.

[0495] The treatment of supplying oxygen to the insulating layer 103b is not limited to the methods described above. For example, oxygen free radicals, oxygen atoms, oxygen atom ions, oxygen molecular ions, etc., can be supplied to the insulating layer 103b using ion doping, ion implantation, plasma treatment, etc. Alternatively, oxygen can be supplied to the insulating layer 103b after forming a film that inhibits oxygen desorption on the insulating layer 103b. Preferably, the film is removed after oxygen supply. As the aforementioned film that inhibits oxygen desorption, conductive films or semiconductor films containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten can be used.

[0496] After removing membrane 130, oxygen can still be supplied to insulating layer 103b. The method for supplying oxygen can be referred to the above description. For example, as... Figure 38D As shown, a film 140 is formed on the insulating layer 103b, and oxygen can also be supplied to the insulating layer 103b through the film 140. As this process, plasma treatment in an oxygen-containing atmosphere can be used. Figure 38D The arrows in the diagram symbolically indicate the supply of oxygen to the insulation layer 103b.

[0497] The film 140 is preferably a conductive film or a semiconductor film. The film 140 can be a metal oxide film, a metal film, or an alloy film. When a metal oxide is used as the film 140, it is preferred because when it is formed in an oxygen-containing atmosphere, for example by sputtering, oxygen can be supplied to the insulating layer 103b during the formation of the film 140.

[0498] The thickness of film 140 is preferably thin. Specifically, the thickness of film 140 is preferably 1 nm or more, 2 nm or more, or 3 nm or more and 20 nm or less, 15 nm or less, or 10 nm or less. Typically, it can be around 5 nm.

[0499] The substrate temperature during film formation 140 is preferably 350°C or lower, more preferably 340°C or lower, even more preferably 330°C or lower, and even more preferably 300°C or lower. This increases the amount of oxygen supplied to the insulating layer 103b.

[0500] By providing membrane 140, ionized oxygen is readily attracted when a bias voltage is applied between a pair of electrodes while oxygen is supplied. Therefore, the amount of oxygen supplied to the insulating layer 103b can be increased.

[0501] As the oxygen supply apparatus, dry etching apparatus, ashing apparatus, or PECVD apparatus are suitable. In particular, an ashing apparatus is preferred. When applying a bias voltage between a pair of electrodes included in the processing apparatus, the bias voltage can be set to, for example, 10V or more and 1kV or less. Alternatively, the power density of the bias voltage can be set to, for example, 1W / cm². 2 Above and 5W / cm 2 That's all.

[0502] Next, film 140 is removed. Film 140 is suitable for removal using a wet etching method.

[0503] Next, an insulating layer 103c is formed on the insulating layer 103b. Figure 38E Since the formation of insulating layer 103c can be referred to the description of the formation of insulating layers 103a and 103b, detailed descriptions are omitted.

[0504] Next, a conductive film 112af, which will become the conductive layer 112a, is formed on the insulating layer 103c. Figure 39A The conductive film 112af can be formed, for example, by sputtering.

[0505] Next, the conductive film 112af is processed to form the conductive layer 112a. Figure 39B The conductive layer 112a can be formed using one or both of wet etching and dry etching, with wet etching being preferred.

[0506] Next, a portion of the conductive layer 112a is removed to form an opening 123a that overlaps with the conductive layer 111a. Figure 39C The opening 123a can be formed using one or both of wet etching and dry etching, with wet etching being preferred.

[0507] Next, a portion of the insulating layer 103 is removed to form an opening 121a reaching the conductive layer 111a. Figure 39D That is, opening 121a has a region that overlaps with opening 123a. By forming opening 121a, a portion of conductive layer 111a is exposed. Opening 121a can be formed, for example, by using one or both of wet etching and dry etching, wherein dry etching is preferred.

[0508] The opening 121a can be formed, for example, using the same photoresist mask used to form the opening 123a. Specifically, a photoresist mask can be formed on the conductive layer 112a, a portion of the conductive layer 112a can be removed using the photoresist mask to form the opening 123a, and a portion of the insulating layer 103 can be removed using the same photoresist mask to form the opening 121a. The opening 121a can also be formed using a different photoresist mask than the one used to form the opening 123a.

[0509] Next, a semiconductor film 113af, which will become the semiconductor layer 113a, is formed in such a way that it covers the openings 121a and 123a. Figure 40A The semiconductor film 113af is formed in such a way that it has a region in contact with the top surface of the conductive layer 112a, a region in contact with the side surface of the conductive layer 112a, a region in contact with the top surface of the insulating layer 103, a region in contact with the side surface of the insulating layer 103, and a region in contact with the top surface of the conductive layer 111a.

[0510] The semiconductor film 113af is preferably formed by sputtering using a metal oxide target. Alternatively, the semiconductor film 113af is preferably formed using the ALD method.

[0511] Because of its high coverage, the ALD method is suitable for forming the semiconductor film 113af, which covers both openings 121a and 123a. Using the ALD method, the semiconductor film 113af can also be formed with high coverage on the side of the insulating layer 103. Furthermore, the ALD method allows for easy control of the deposition rate, thus enabling the formation of thin films with high yields. Additionally, the semiconductor film 113af can be formed using CVD instead of sputtering and the ALD method.

[0512] When forming the semiconductor film 113af using the ALD method, it is preferable to use a deposition method such as thermal ALD or PEALD (Plasma Enhanced ALD). Thermal ALD is preferred because it has extremely high coverage. PEALD is preferred because it not only has high coverage but also allows for low-temperature deposition.

[0513] Semiconductor films 113af can be formed, for example, using precursors containing constituent metal elements and oxidants and the ALD method.

[0514] For example, when forming In-Ga-Zn oxide, three precursors can be used: one containing indium, one containing gallium, and one containing zinc. Alternatively, two precursors can be used: one containing indium, and one containing both gallium and zinc.

[0515] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptadecanoic acid)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]-indium.

[0516] Examples of gallium-containing precursors include trimethylgallium, triethylgallium, tris(dimethylamide)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptadecanoate)gallium, dimethylgallium chloride, diethylgallium chloride, and gallium(III) chloride.

[0517] As aluminum-containing precursors, aluminum chloride and trimethylaluminum can be used, for example.

[0518] Examples of tin-containing precursors include tin(IV) chloride and tetra(dimethylamide)tin.

[0519] Examples of zinc-containing precursors include dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5-heptadecanoic acid) zinc, and zinc chloride.

[0520] Examples of oxidizing agents include ozone, oxygen, and water.

[0521] As a method for controlling the composition of the obtained membrane, one or more of the following can be adjusted: the type of source gas, the flow rate ratio of the source gas, the time the source gas flows through, and the order in which the source gas flows through. By adjusting these, the composition of the semiconductor film 113af can be controlled.

[0522] Before depositing the semiconductor film 113af, it is preferable to perform at least one of a treatment to remove water, hydrogen, organic matter, etc., adsorbed on the surface of the insulating layer 103 and a treatment to supply oxygen to the insulating layer 103. For example, a heating treatment can be performed at a temperature of 70°C or higher and 200°C or lower under a reduced pressure atmosphere. Alternatively, a plasma treatment in an oxygen-containing atmosphere can be performed. Alternatively, oxygen can be supplied to the insulating layer 103 by performing a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O). When performing a plasma treatment containing nitrous oxide gas, organic matter on the surface of the insulating layer 103 can be appropriately removed and oxygen can be supplied to the insulating layer 103. Preferably, after such treatment, the semiconductor film 113af is continuously deposited in a manner that does not expose the surface of the insulating layer 103 to the atmosphere.

[0523] Next, the semiconductor film 113af is processed into islands to form the semiconductor layer 113a. Figure 40B The semiconductor layer 113a is formed having a region that contacts the top surface of the conductive layer 111a, a region that contacts the side surface of the opening 121a in the insulating layer 103, a region that contacts the side surface of the opening 123a in the conductive layer 112a, and a region that contacts the top surface of the conductive layer 112a. The semiconductor layer 113a is formed having a region located inside the opening 121a and a region located inside the opening 123a.

[0524] The semiconductor layer 113a can be formed using one or both of wet etching and dry etching, with wet etching being preferred. In this case, sometimes a portion of the conductive layer 112a in a region that does not overlap with the semiconductor layer 113a is etched, resulting in a reduced thickness. Similarly, sometimes a portion of the insulating layer 103 in a region that does not overlap with either the semiconductor layer 113a or the conductive layer 112a is etched, resulting in a reduced thickness. For example, sometimes the insulating layer 103c in the insulating layer 103 disappears due to etching, exposing the surface of the insulating layer 103b. Note that in the etching of the semiconductor film 113af, by using a material with a high selectivity as the insulating layer 103c, the reduction in the thickness of the insulating layer 103c can be suppressed.

[0525] Preferably, heat treatment is performed after depositing the semiconductor film 113af or processing the semiconductor film 113af into a semiconductor layer 113a. Heat treatment can remove hydrogen or water contained in or adsorbed on the surface of the semiconductor film 113af or semiconductor layer 113a. Furthermore, heat treatment can sometimes improve the quality of the semiconductor film 113af or semiconductor layer 113a (e.g., reduce defects or increase crystallinity).

[0526] Oxygen can be supplied from the insulating layer 103b to the semiconductor film 113af or the semiconductor layer 113a through heat treatment. More preferably, the heat treatment is performed before processing into the semiconductor layer 113a. Details regarding the heat treatment can be found above, so further explanation is omitted.

[0527] Note that this heat treatment is not always necessary. Alternatively, a heat treatment performed in a later step can be used instead of this one. Sometimes, high-temperature treatments in later steps (e.g., deposition processes) can be used as the heat treatment for this step.

[0528] Next, an insulating layer 105 is formed by covering the semiconductor layer 113a, the conductive layer 112a, and the insulating layer 103. Figure 40C The insulating layer 105 is formed on the semiconductor layer 113a and the conductive layer 112a in such a way that it has a region located inside the opening 121a and a region located inside the opening 123a. When forming the insulating layer 105, for example, PECVD, sputtering or ALD can be suitably used.

[0529] When an oxide semiconductor is used in the semiconductor layer 113a, the insulating layer 105 is preferably used as a barrier film to suppress oxygen diffusion. By making the insulating layer 105 have the function of suppressing oxygen diffusion, oxygen can be prevented from diffusing from the top of the insulating layer 105 to the conductive layer 115a formed in a subsequent process, thus preventing the conductive layer 115a from being oxidized. As a result, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0530] By increasing the formation temperature of the insulating layer 105 used as the gate insulating layer, an insulating layer with fewer defects can be formed. However, when the formation temperature of the insulating layer 105 is high, oxygen detaches from the semiconductor layer 113a, and sometimes oxygen vacancies and V in the semiconductor layer 113a... O H increases. The substrate temperature during the formation of the insulating layer 105 is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, and even more preferably 300°C or higher and 400°C or lower. By keeping the substrate temperature during the formation of the insulating layer 105 within the above range, defects in the insulating layer 105 can be reduced while oxygen detachment from the semiconductor layer 113a can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0531] Plasma treatment can be performed on the surface of the semiconductor layer 113a before forming the insulating layer 105. This plasma treatment reduces impurities such as water adsorbed on the surface of the semiconductor layer 113a. Therefore, impurities at the interface between the semiconductor layer 113a and the insulating layer 105 can be reduced, resulting in a transistor with high reliability. In particular, plasma treatment is preferred when the surface of the semiconductor layer 113a is exposed to the atmosphere between the formation of the semiconductor layer 113a and the formation of the insulating layer 105. The plasma treatment can be performed, for example, in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, or argon. Furthermore, the plasma treatment and the deposition of the insulating layer 105 are preferably performed continuously without exposure to the atmosphere.

[0532] Next, a conductive film 115af, which will become conductive layers 115a and 116, is formed on the insulating layer 105. Figure 40C The conductive film 115af is suitable for formation by methods such as sputtering, thermal CVD (including MOCVD) or ALD.

[0533] Next, the conductive film 115af is processed to form conductive layer 115a and conductive layer 116. Figure 41A and Figure 41B The conductive layers 115a and 116 can be formed, for example, by using one or both of wet etching and dry etching, with dry etching being preferred.

[0534] like Figure 41A As shown, at least a portion of the conductive layer 115a is used as wiring 41 and extends in the second direction. Furthermore, at least a portion of the conductive layer 116 is used as wiring 45 and extends in the second direction. As described above, wiring 43 extends in the first direction, and the second direction is perpendicular to the first direction. Thus, wiring 41 and wiring 45 extend in a direction perpendicular to wiring 43. Furthermore, wiring 45 extends in a direction parallel to wiring 41.

[0535] The conductive layer 115a is formed on the insulating layer 105 such that it has a region located inside the opening 121a and a region located inside the opening 123a. The conductive layer 116 is formed on the insulating layer 105 such that it has a region overlapping with the conductive layer 112a.

[0536] By forming a conductive layer 115a, a transistor 51 is formed, comprising a conductive layer 111a, a conductive layer 112a, a conductive layer 115a, a semiconductor layer 113a, and an insulating layer 105.

[0537] Next, an insulating layer 107 is formed in such a way that it covers transistor 51 and conductive layer 116, and an insulating layer 109 is formed on the insulating layer 107. Figure 41C Insulating layer 107 is formed on conductive layer 115a, conductive layer 116 and insulating layer 105, and insulating layer 109 is formed on insulating layer 107.

[0538] As described above, for example, inorganic materials are suitable for insulating layer 107, while organic materials are suitable for insulating layer 109. In this case, insulating layer 107 can be formed using methods such as CVD, sputtering, PLD, or ALD. Furthermore, insulating layer 109 can be formed using methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor blade coating, slot coating, roller coating, curtain coating, or doctor blade coating.

[0539] Next, a portion of insulating layers 109, 107, and 105 is removed to form an opening 125 reaching the conductive layer 112a. Figure 42A The opening 125 can be formed, for example, by using one or both of wet etching and dry etching, with dry etching being preferred.

[0540] Next, a conductive film that will become the pixel electrode 131 is formed in a manner that covers the opening 125, and the conductive film is processed to form the pixel electrode 131. Figure 42B The conductive film can be formed, for example, by sputtering or vacuum evaporation. The pixel electrode 131 is formed such that it has a region in contact with the conductive layer 112a inside the opening 125 and a region overlapping the conductive layer 116. The pixel electrode 131 can be formed such that it has a region in contact with the top surface of the insulating layer 109, a region in contact with the side surface of the insulating layer 109, a region in contact with the side surface of the insulating layer 107, a region in contact with the side surface of the insulating layer 105, and a region in contact with the top surface of the conductive layer 112a.

[0541] By forming pixel electrode 131, a capacitor 57 is formed, comprising conductive layer 112a, conductive layer 116, pixel electrode 131, insulating layer 105, insulating layer 107, and insulating layer 109. Note that sometimes pixel electrode 131, insulating layer 107, and insulating layer 109 are not included in the constituent elements of capacitor 57.

[0542] Next, an insulating layer 133 is formed in a manner that covers the pixel electrode 131. Figure 42B An insulating layer 133 is formed on the pixel electrode 131 and the insulating layer 109. The insulating layer 133 can be formed by performing a rubbing process after depositing a thin film of resin or the like.

[0543] Next, a light-shielding layer 145 and a coloring layer 143 are formed on the substrate 141. Figure 42C The light-shielding layer 145 and the coloring layer 143 can be formed, for example, by spin coating or inkjet printing.

[0544] Next, a protective layer 147 is formed on the light-shielding layer 145, the coloring layer 143, and the substrate 141. Figure 42C The formation of the protective layer 147 is suitable, for example, by using the PECVD method.

[0545] Next, a common electrode 139 is formed on the protective layer 147. Figure 42C The common electrode 139 can be formed by methods such as sputtering or vacuum evaporation.

[0546] Next, an insulating layer 149, which serves as a spacer, is formed on the common electrode 139. Figure 42C The insulating layer 149 is formed, for example, by a dry or wet distribution method.

[0547] Next, insulating layer 137 is formed in such a way as to cover insulating layer 149. Figure 42C Insulating layer 137 is formed on insulating layer 149 and common electrode 139. Insulating layer 137 can be formed by the same method as insulating layer 133.

[0548] Next, in Figure 42B The insulating layer 133 shown is Figure 42C Liquid crystal 135 is disposed between the insulating layers 137 shown. Figure 6A The liquid crystal 135 can be configured, for example, by liquid crystal injection or liquid crystal droplet method. By configuring the liquid crystal 135, a liquid crystal element 70 including pixel electrode 131, common electrode 139 and liquid crystal 135 is formed.

[0549] Through the above processes, it is possible to manufacture Figure 6A The display device shown.

[0550] <Example 2 of a manufacturing method for a display device> The following is for reference Figures 43A to 45B illustrate Figure 17A An example of a method for manufacturing a display device is shown. Figures 43A to 45B Showing the corresponding Figure 16D The cross-sectional view shown is the dotted-dash line B7-B8.

[0551] First, through with Figures 38A to 41C Using the same method as shown, conductive layer 111a, insulating layer 103, conductive layer 112a, semiconductor layer 113a, insulating layer 105, conductive layer 115a, insulating layer 107, and insulating layer 109 are formed. Next, a common electrode 46 is formed on insulating layer 109. Figure 43A The common electrode 46 can be formed by methods such as sputtering or vacuum evaporation.

[0552] Next, a portion of the common electrode 46 is removed to form an opening 127 having a region overlapping the conductive layer 112a. Figure 43B The opening 127 can be formed using one or both of wet etching and dry etching, with wet etching being preferred.

[0553] Next, an insulating layer 151 is formed covering the opening 127. Figure 44A The insulating layer 151 is formed on the common electrode 46 and the insulating layer 109 in such a way that it has a region located inside the opening 127. The insulating layer 151 can be formed by, for example, PECVD, sputtering or ALD.

[0554] Next, by removing a portion of insulating layers 151, 109, 107, and 105, an opening 125 is formed that, when viewed in plan view, overlaps with the opening 127 and reaches the conductive layer 112a. Figure 44B The opening 125 can be formed, for example, by using one or both of wet etching and dry etching, with dry etching being preferred.

[0555] Next, a conductive film that will become the pixel electrode 131 is formed in a manner that covers the opening 125, and the conductive film is processed to form the pixel electrode 131. Figure 45A As described above, the conductive film can be formed, for example, by sputtering or vacuum evaporation. The pixel electrode 131 is formed with a region that contacts the conductive layer 112a inside the opening 125 and a region that overlaps with the common electrode 46. Figure 45A In the example shown, the pixel electrode 131 can be formed with a region contacting the top surface of the insulating layer 151, a region contacting the side surface of the insulating layer 151, a region contacting the side surface of the insulating layer 109, a region contacting the side surface of the insulating layer 107, a region contacting the side surface of the insulating layer 105, and a region contacting the top surface of the conductive layer 112a. Furthermore, in Figure 45A In the example shown, the pixel electrode 131 is formed in a way that has a slit-like or comb-like shape when viewed from a plane.

[0556] By forming pixel electrode 131, a capacitor 57 is formed, including common electrode 46, insulating layer 151 and pixel electrode 131.

[0557] Next, an insulating layer 133 is formed in a manner that covers the pixel electrode 131. Figure 45A An insulating layer 133 is formed on the pixel electrode 131 and the insulating layer 151. As described above, the insulating layer 133 can be formed by performing a rubbing process after depositing a thin film of resin or the like.

[0558] Next, through communication with Figure 42C The same method shown is used to form a light-shielding layer 145, a coloring layer 143, a protective layer 147, an insulating layer 149, and an insulating layer 137 on the substrate 141. Figure 45B Note that a common electrode 139 is not formed.

[0559] Next, in Figure 45A The insulating layer 133 shown is Figure 45B Liquid crystal 135 is disposed between the insulating layers 137 shown. Figure 17A As described above, the liquid crystal 135 can be configured, for example, by liquid crystal injection or liquid crystal droplet method. By configuring the liquid crystal 135, a liquid crystal element 70 including a common electrode 46, a pixel electrode 131, and the liquid crystal 135 is formed.

[0560] Through the above processes, it is possible to manufacture Figure 17A The display device shown.

[0561] The various structural examples shown in this embodiment can be appropriately combined. Furthermore, this embodiment can be appropriately combined with other embodiments.

[0562] (Implementation Method 2) In this embodiment, a transistor included in a display device according to one aspect of the present invention is described with reference to the accompanying drawings. Specifically, an example of a structure different from the transistor shown in Embodiment 1 is described with reference to the accompanying drawings.

[0563] The structure of transistor 50 is described in this embodiment. As described above, transistor 50 can be applied to various transistors shown in Embodiment 1.

[0564] Figure 46A This is a plan view showing an example of the structure of transistor 50. Figure 46B1 yes Figure 46A The cross-sectional view shown is along the dotted line A1-A2. In this embodiment, the direction in which the conductive layer 111 extends is designated as the X direction. Furthermore, the direction perpendicular to the X direction and, for example, parallel to the top surface of the substrate 101 is the Y direction, and the direction perpendicular to the top surface of the substrate 101 is the Z direction.

[0565] exist Figure 46A and Figure 46B1 An example is shown in which the end of the conductive layer 115 in the X direction is located outside the end of the conductive layer 112 in the region where the conductive layer 111 overlaps with the conductive layer 112. Figure 46A and Figure 46B1 In the example shown, conductive layer 115 covers the entire area where conductive layers 111 and 112 overlap. With this structure, for example, when forming conductive layer 115 using photolithography and etching, the alignment accuracy of the photomask can be reduced. Therefore, transistor 50 can be easily manufactured.

[0566] Figure 46B2 yes Figure 46B1 The illustrated modified example shows an instance where the top end of the insulating layer 105 coincides with or substantially coincides with the bottom end of the conductive layer 115. For example, when the conductive layer 115 is formed using photolithography and etching, sometimes a low etching selectivity between the conductive layer 115 and the insulating layer 105 results in… Figure 46B2 The structure shown.

[0567] Figure 46B3 yes Figure 46B2 The illustrated modified example shows an instance where the bottom end of the conductive layer 115 is located inside the top end of the insulating layer 105, i.e., on the side of the conductive layer 112. For example, when the etching rate of the conductive layer 115 in the X direction is faster than the etching rate of the insulating layer 105 in the X direction, sometimes this results in... Figure 46B3 The structure shown.

[0568] Note, regarding Figure 46B2 and Figure 46B3 The plan view of the structure shown can be referred to. Figure 46A .

[0569] Figure 47A and Figure 47B This is a plan view showing an example of the structure of transistor 50, in which the shape of openings 121 and 123 is a rectangle with rounded corners when viewed from the plane. Figure 47A Examples are shown where the length of opening 121 and opening 123 in the X direction is longer than its length in the Y direction. Figure 47B Examples are shown where the length of opening 121 and opening 123 in the X direction is shorter than its length in the Y direction. Note that... Figure 47A and Figure 47B The cross-sectional view of the structure shown can be referred to in Embodiment 1. Figure 2B .

[0570] exist Figure 47A and Figure 47B In the example shown, the side surfaces of the insulating layer 103 in opening 121 and the side surfaces of the conductive layer 112 in opening 123 have planar areas instead of curved surfaces. Therefore, the coverage of the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 can be improved inside opening 121 and opening 123. Note that when viewed from a planar perspective, the corners of opening 121 and opening 123 may not be rounded; for example, the planar shapes of opening 121 and opening 123 may be rectangular, rhomboid, or square. Furthermore, the planar shapes of opening 121 and opening 123 may also be triangular or triangular with rounded corners. Moreover, the planar shapes of opening 121 and opening 123 may also be pentagonal or other polygonal shapes, or shapes with rounded corners.

[0571] Figure 48A1 This is a plan view showing an example of the structure of transistor 50, where it is shown that, when viewed from the plane, conductive layer 112 covers a portion of the outer periphery of opening 121 but not the entirety. Figure 48A2 yes Figure 48A1 A modified example of the structure is shown, in which the end of the conductive layer 112 makes point contact with the outer periphery of the opening 121 when viewed from the plane. Figure 48A2 In the example shown, the opening 121 is circular when viewed from a plane, and one end of the extension of the conductive layer 112 in the Y direction is a tangent to the opening 121. Figure 48B yes Figure 48A1 and Figure 48A2 The cross-sectional view of the dotted line A1-A2 shown....

Claims

1. A display device, comprising: transistor; Capacitor; as well as First insulating layer, The transistor includes a first wiring layer, a second wiring layer, a conductive layer, a semiconductor layer, and a second insulating layer. The capacitor includes a third wiring, the conductive layer, and the second insulating layer. The first insulating layer is disposed on the first wiring. The first insulating layer includes a first opening extending to the first wiring. The conductive layer is disposed on the first insulating layer. The conductive layer includes a second opening having a region that overlaps with the first opening. The semiconductor layer is disposed in such a manner that it has a region in contact with the first wiring and a region in contact with the conductive layer, and has a region located inside the first opening and a region located inside the second opening. The second insulating layer is disposed on the semiconductor layer and the conductive layer in such a manner that it has a region located inside the first opening and a region located inside the second opening. The second wiring is disposed on the second insulating layer in such a manner that it has a region located inside the first opening and a region located inside the second opening. The third wiring is disposed on the second insulating layer in such a way that it has a region overlapping with the conductive layer. The first wiring extends in the first direction. Furthermore, the second wiring and the third wiring extend in a second direction perpendicular to the first direction when viewed from a plane.

2. The display device according to claim 1 further includes a liquid crystal element. The second insulating layer includes a third opening that extends into the conductive layer. The pixel electrode of the liquid crystal element has a region inside the third opening that contacts the conductive layer. Furthermore, the pixel electrode has a region that overlaps with the third wiring.

3. The display device according to claim 2 further includes a third insulating layer. The third insulating layer is disposed on the second wiring, the third wiring and the second insulating layer, and has a region located between the third wiring and the pixel electrode. Furthermore, the third insulating layer includes the third opening.

4. The display device according to any one of claims 1 to 3, The semiconductor layer comprises a metal oxide.

5. A method for manufacturing a display device, comprising the following steps: Forming a first wiring extending in the first direction; A first insulating layer is formed on the first wiring; A conductive layer is formed on the first insulating layer; A first opening overlapping the first wiring is formed in the conductive layer; A second opening is formed in the first insulating layer to reach the first wiring in such a way that it has a region that overlaps with the first opening; A semiconductor layer is formed in such a manner that it has a region in contact with the first wiring and a region in contact with the conductive layer, and has a region located inside the first opening and a region located inside the second opening; A second insulating layer is formed on the semiconductor layer and the conductive layer in such a manner that it has a region located inside the first opening and a region located inside the second opening; A conductive film is formed on the second insulating layer; as well as By processing the conductive film, a second wiring is formed having a region located inside the first opening and a region located inside the second opening, and a third wiring having a region overlapping the conductive layer. Wherein, the second wiring and the third wiring extend in a second direction perpendicular to the first direction when viewed from a plane.

6. The method for manufacturing a display device according to claim 5 further includes the following steps: A third insulating layer is formed on the second wiring, the third wiring, and the second insulating layer; A third opening leading to the conductive layer is formed in the third insulating layer and the second insulating layer; The pixel electrode is formed in such a manner that it has a region inside the third opening that contacts the conductive layer and has a region that overlaps with the third wiring; as well as A liquid crystal element is formed, comprising the pixel electrode, the common electrode, and the liquid crystal.

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