A hard disk access method of a hard disk backplane, a server and a storage medium

Abstract

The application discloses a hard disk access method of a hard disk backboard, a server and a storage medium, relates to the technical field of server hardware management, and comprises the following steps: accessing a register of a programmable logic device with a first preset fixed address in a target hard disk backboard, and acquiring topology information of the target hard disk backboard; based on NVME support states of each port contained in the topology information, a target hard disk adaptation type of the target hard disk backboard is determined from multiple hard disk adaptation types; and based on access strategy information matched with the target hard disk adaptation type, a target hard disk in place is accessed. The problem of high coupling between BMC code and the hard disk backboard adaptation type is effectively solved, and the flexibility and scalability of server hardware adaptation are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of server hardware management, and particularly relates to a hard disk access method of a hard disk backboard, a server and a storage medium. BACKGROUND

[0002] In a server system, a BMC (Baseboard Management Controller) is used for monitoring, managing and maintaining various hardware devices inside the server. Among them, the hard disk backboard as a key hardware device connecting the server mainboard and the hard disk directly affects the stability of the server in accessing the hard disk.

[0003] Under the related art, the adaptation of the BMC and the hard disk backboard mainly adopts a code coupling mode. The BMC describes the topology information of the hard disk backboard through a data structure defined in the internal code, which specifically includes the number of hard disks, the interface type, the connection mode and other parameters. However, when a new hard disk backboard needs to be added or replaced, since different models or specifications of hard disk backboards have differences in topology structure, the static content contained in the data structure defined in the internal code of the BMC does not match the topology information of the new hard disk backboard, and the internal code of the BMC must be modified to adapt to the topology information of the new hard disk backboard. Therefore, the traditional code coupling mode has low compatibility and scalability for hardware adaptation. SUMMARY

[0004] The present application provides a hard disk access method of a hard disk backboard to at least solve the problem of low compatibility and scalability of the hard disk backboard in the related art.

[0005] In a first aspect, an embodiment of the present application provides a hard disk access method of a hard disk backboard. A baseboard management controller pre-stores a first preset fixed address, a plurality of hard disk adaptation types and access strategy information matched with each hard disk adaptation type. Each hard disk adaptation type includes an NVME hard disk adaptation type, a serial interface hard disk adaptation type and a hybrid hard disk adaptation type. The hard disk access method of a hard disk backboard includes:

[0006] Accessing a register of a programmable logic device with the first preset fixed address in a target hard disk backboard to obtain topology information of the target hard disk backboard. The topology information includes the number of ports of the target hard disk backboard, the NVME support state of each port and the hard disk in-place information of each port.

[0007] Based on the NVME support state of each port contained in the topology information, determining a target hard disk adaptation type of the target hard disk backboard from the plurality of hard disk adaptation types.

[0008] Based on the access strategy information matched with the target hard disk adaptation type, accessing the target hard disk in place.

[0009] In a second aspect, embodiments of the present application provide a baseboard management controller for implementing the hard disk access method of the hard disk backplane provided in any embodiment of the first aspect.

[0010] In a third aspect, embodiments of the present application provide a server comprising at least one hard disk backplane and a baseboard management controller;

[0011] The at least one hard disk backplane is provided with a programmable logic device with a first preset fixed address, at least one I2C switch with a second preset fixed address, and an electrically erasable programmable read-only memory with a third preset fixed address;

[0012] The baseboard management controller is used to implement the hard disk access method of the hard disk backplane provided in any embodiment of the first aspect.

[0013] In a fourth aspect, embodiments of the present application provide a computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the hard disk access method of the hard disk backplane provided in any embodiment of the first aspect.

[0014] The present application also provides a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the steps of the hard disk access method of the hard disk backplane provided in any embodiment of the first aspect.

[0015] By unifying the addresses of the programmable logic devices of the hard disk backplanes of different hard disk adaptation types and pre-storing the addresses in the code of the BMC, the BMC can parse the topology information of the hard disk backplanes of all hard disk adaptation types based on the fixed addresses. In the case of replacing or adding a hard disk backplane, the BMC can identify the hard disk backplanes of the NVME hard disk adaptation type, the SATA / SAS hard disk adaptation type and the mixed hard disk adaptation type without modifying the BMC code, effectively solving the problem of high coupling between the BMC code and the hard disk backplane adaptation type, and improving the flexibility and scalability of the server hardware adaptation. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 A hard disk access method of a hard disk backplane provided by an embodiment of the present application is shown in the application environment diagram;

[0018] Figure 2 A flowchart of a hard disk access method of a hard disk backplane provided by an embodiment of the present application is shown in FIG. 1.

[0019] Figure 3 A flowchart of configuration information related to an I2C switch in some embodiments is shown in FIG. 3.

[0020] Figure 4 A flowchart related to temperature information in some embodiments is shown in FIG. 4.

[0021] Figure 5 A logic diagram of a BMC connected to multiple hard disk backplanes through multiple I2C buses in some embodiments is shown in FIG. 5.

[0022] Figure 6 A logic diagram of a BMC connected to multiple hard disk backplanes through an I2C switch connected to an I2C bus in some embodiments is shown in FIG. 6. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0024] It should be noted that in the description of the present application, the terms “comprise”, “contain” or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0025] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0026] In combination with the specific application environment architecture or specific hardware architecture on which the hard disk access method of the hard disk backplane in the embodiments of the present application depends, the specific application environment architecture or specific hardware architecture is described here.

[0027] In a first aspect, the embodiments of the present application provide a hard disk access method of a hard disk backplane. The method can be applied to, for example, Figure 1The application environment shown. Among them, the server 100 includes the BMC 110 and the hard disk backboard 120, wherein the hard disk backboard 120 has a first preset fixed address. The BMC 110 can communicate with the hard disk backboard 120 through the I2C bus to access the hard disk connected on the hard disk backboard 120. The first preset fixed address, a plurality of hard disk adaptation types and the access strategy information matched with each hard disk adaptation type are pre-stored in the BMC 110; each hard disk adaptation type includes an NVME hard disk adaptation type, a serial interface hard disk adaptation type and a hybrid hard disk adaptation type. The programmable logic device with the first preset fixed address is arranged on the hard disk backboard 120, and the BMC 110 can identify the hard disk adaptation type of the hard disk backboard 120 by accessing the topology information of the hard disk backboard 120 stored in the register in the programmable logic device, and access different types of hard disks connected on the hard disk backboard 120.

[0028] Of course, the container image cleaning method provided by the embodiments of the present disclosure can also be applied to more unillustrated scenarios.

[0029] The hard disk access method based on the hard disk backboard is applied to Figure 1 The BMC 110 in the server 100 is taken as an example for illustration. In some embodiments, as shown in Figure 2 The hard disk access method based on the hard disk backboard includes steps S210 to S230 that can be executed by the BMC 110. Each step is described below.

[0030] Step S210: Access the register of the programmable logic device with the first preset fixed address in the target hard disk backboard to obtain the topology information of the target hard disk backboard.

[0031] The topology information includes the number of ports of the target hard disk backboard, the NVME support state of each port and the hard disk in-place information of each port.

[0032] The first preset fixed address is the address corresponding to the programmable logic device, and the address offset of the register relative to the programmable logic device is 0, so the addresses of the programmable logic device and the register can be considered the same, i.e. the register in the programmable logic device can be directly accessed according to the first preset fixed address. In some optional embodiments, the first preset fixed address stored in the BMC code can be unique, i.e. only one specific address is saved as the first preset fixed address in the data structure of the BMC code. In some optional embodiments, any one of a plurality of candidate addresses can be saved as the first preset fixed address in the data structure of the BMC code.

[0033] NVME (Non-Volatile Memory Express) is a non-volatile memory host controller interface specification, which has the advantages of low delay, high throughput, multi-queue parallel and high scalability. The hard disk supporting NVME is NVME hard disk, and the hard disk backplane port capable of connecting NVME hard disk is NVME port.

[0034] One BMC can be connected to multiple hard disk backplanes, and each hard disk backplane is installed with a programmable logic device. The target hard disk backplane is any one of the multiple hard disk backplanes. Among them, the programmable logic device can be a CPLD (Complex Programmable Logic Device), an FPGA (Field Programmable Gate Array), or an MCU (Microcontroller Unit), etc. The present application does not limit this (hereinafter, the programmable logic device is taken as an example of CPLD).

[0035] In the hardware design stage, the address of the CPLD on each hard disk backplane is fixed as a first preset fixed address, for example, 0x80 (hexadecimal number). The first preset fixed address is pre-written into the code of the BMC, and the BMC can access the CPLD of each hard disk backplane through the pre-stored first preset fixed address, so as to obtain the topology information about the hard disk backplane.

[0036] In some optional embodiments, the first preset fixed address can be arbitrarily selected according to actual conditions, and the present application does not limit this.

[0037] Step S220: Based on the NVME support state of each port contained in the topology information, the target hard disk adaptation type of the target hard disk backplane is determined from multiple hard disk adaptation types.

[0038] The support state of NVME can be obtained by analyzing the specific storage information in the register, for example, the 7th bit of a certain byte of the register is 1, which indicates that the corresponding port supports NVME, and if the bit is 0, it indicates that the corresponding port does not support NVME.

[0039] Optionally, the storage bit of the NVME support state and the 0 / 1 signal and the corresponding relationship of the NVME support state are only used as an example for illustration, and other possible ways can be used in actual application, and the present application does not limit this.

[0040] Each port supports the NVME hard disk backboard for the NVME hard disk adaptation type, and can be connected to the NVME hard disk; each port does not support NVME, and only supports the hard disk backboard of the SATA (Serial ATA) or SAS (Serial Attached SCSI) standard for the serial interface hard disk adaptation type, and can only be connected to the SATA / SAS hard disk; part of the ports support NVME, and part of the ports only support the hard disk backboard of the SATA / SAS for the mixed hard disk adaptation type, and can be connected to the NVME hard disk and the SATA / SAS hard disk at the same time.

[0041] In addition, the port supporting the NVME hard disk usually has good downward compatibility and can also be connected to the SATA / SAS hard disk.

[0042] Step S230: Access the target hard disk in place based on the access policy information matched with the target hard disk adaptation type.

[0043] The pre-stored code in the BMC contains access policy information of different hard disk adaptation types, which corresponds to the hardware design rules of the hard disk backboard, and the access policy information specifically includes the access address of the CPLD and the like.

[0044] By unifying the CPLD addresses of the hard disk backboards of different hard disk adaptation types and pre-storing the addresses in the code of the BMC, the BMC can parse the topology information of the hard disk backboards of all hard disk adaptation types based on the fixed address in the fixed code. In the case of replacing or adding the hard disk backboard, the BMC code does not need to be modified to identify the hard disk backboard of the NVME hard disk adaptation type, the SATA / SAS hard disk adaptation type and the mixed hard disk adaptation type, effectively solving the problem of high coupling between the BMC code and the hard disk backboard adaptation type, and improving the flexibility and scalability of the server hardware adaptation.

[0045] In some embodiments, as shown in Figure 3 When the BMC 110 performs step S230, it can also include steps S231 to S232.

[0046] Step S231: If the target hard disk adaptation type is the NVME hard disk adaptation type or the mixed hard disk adaptation type, the configuration information of the I2C switch is determined based on the number of NVME hard disks in place.

[0047] The configuration information at least includes the number of I2C switches, the model of I2C switch and the address of I2C switch.

[0048] I2C (Inter-Integrated Circuit) is a simple, flexible and widely supported serial communication protocol, suitable for short-distance data transmission between electronic devices. I2C switch is an integrated circuit used to expand the number of I2C bus connected devices, which realizes communication between the host controller and multiple devices through multi-channel switching.

[0049] The number of NVME ports supported by the hard disk backplane represents the number of NVME hard disks that the hard disk backplane can dock.

[0050] In the hardware design stage of the hard disk backplane, according to the number of NVME hard disks that the hard disk backplane can dock, the configuration information of the I2C switch is determined, and the I2C configuration information is written into the BMC code. After the BMC identifies the NVME hard disk adaptation type and the hybrid hard disk adaptation type, the configuration information of the I2C switch is parsed, and according to the number of NVME hard disks currently in place, one or more different models of I2C switch access channels are switched to access each NVME hard disk.

[0051] Step S232: Determine the access channel corresponding to each NVME hard disk according to the configuration information of the I2C switch, and access the NVME hard disk based on the access channel.

[0052] In some specific embodiments, an I2C switch can contain multiple access channels, and each access channel can communicate with a port of the hard disk backplane. BMC can control the opening and closing state of multiple access channels of I2C switch by accessing the address of I2C switch, and access the port of hard disk backplane through the opened access channel, so as to access the NVME hard disk in place of the port.

[0053] Generally, multiple access channels of I2C switch follow a serial working mode, that is, only one access channel of multiple access channels of I2C switch can be in an open state at the same time, and other access channels must be in a closed state. Although this serial working mode limits the parallel communication capability, it can guarantee the uniqueness and accuracy of I2C bus data transmission, and effectively avoid system abnormalities caused by signal confusion.

[0054] In some embodiments, when BMC 110 performs step S231, it can also include steps S231-A to S231-C (not shown).

[0055] Step S231-A: If the number of NVME hard disks in place is not greater than the first preset number threshold, determine the number of I2C switches to be one and the model of I2C switch to be the first model.

[0056] The number of channels corresponding to the first model is the first preset number threshold.

[0057] In some specific embodiments, there are various models of I2C switches, typically including CA9545 (4 channels), CA9548 (8 channels), and PCA9546APW (4 channels) with reset function and TCA9548APWR (8 channels) with reset function. Each I2C channel can communicate with a port of a hard disk backplane, and the number of NVME hard disks can determine one or more different models of I2C switches to achieve various channel combinations to interface with multiple ports of the hard disk backplane.

[0058] For example, if the number of in-place NVME hard disks is not greater than 4 (the first preset number threshold), it can be determined that one I2C switch needs to be enabled, and the I2C switch model is 4-channel CA9545 or PCA9546APW. Using one 4-channel I2C switch can meet the access requirements of NVME hard disks with a number not greater than 4.

[0059] Step S231-B: If the number of in-place NVME hard disks is greater than the first preset number threshold and not greater than the second preset number threshold, it is determined that the number of I2C switches is one, and the I2C switch model is the second model.

[0060] Among them, the channel number corresponding to the second model is the second preset number threshold.

[0061] For example, if the number of in-place NVME hard disks is greater than 4 (the first preset threshold) and not greater than 8 (the second preset threshold), it can be determined that one I2C switch needs to be enabled, and the I2C switch model is 8-channel CA9548 or TCA9548APWR. Using one 8-channel I2C switch can meet the access requirements of NVME hard disks with a number greater than 4 and less than 8.

[0062] Step S231-C: If the number of in-place NVME hard disks is greater than the second preset number threshold, it is determined that the number of I2C switches is the number of NVME hard disks divided by the second preset number, and the I2C switch model is the second model.

[0063] For example, if the number of in-place NVME hard disks is greater than 8 (the second preset number threshold), it can be determined that the number of I2C switches that need to be enabled is the number of NVME hard disks divided by 8, and the model of the I2C switch is the model contained in the 8-channel I2C switch.

[0064] For example, assuming that the number of in-place NVME hard disks is 10, it can be determined that the number of I2C switches that need to be enabled is ⌈10 / 8⌉=2, and using two 8-channel I2C switches can meet the access requirements of NVME hard disks with a number greater than 8.

[0065] In some optional embodiments, when the number of in-place NVME hard disks is greater than 8, a plurality of 4-channel I2C switches can also be combined to realize access channels of more than 8 channels, and the present application does not limit this.

[0066] Notably, in order to facilitate the management and maintenance of hardware devices by developers or maintenance personnel, when the number of in-place NVME hard disks is greater than 8, a 4-channel I2C switch is usually not combined with an 8-channel I2C switch, but a I2C switch with the same number of basic channels is preferred.

[0067] Specifically, as the core communication hub between the BMC and the hard disk backplane ports, the number of channels and the combination mode of the I2C switch directly affect the complexity of overall hardware management. If a 4-channel I2C switch is combined with an 8-channel I2C switch, the difference in channel capacity between the two types of I2C switches will cause the mapping logic of the ports and channels to be fragmented, bringing multiple inconveniences to hardware management.

[0068] For example, when 12 NVME ports need to be managed, if one 8-channel I2C switch and one 4-channel I2C switch are used, the developer needs to separately design different channel calculation methods for the two types of I2C switches when writing BMC code, and a large number of conditional judgment statements need to be added to the code to distinguish between the two types of I2C switches, which not only increases code redundancy, but also may cause channel matching errors due to logical omissions. Moreover, the mixed combination will increase the difficulty of troubleshooting for maintenance personnel. When a NVME port communication is abnormal, the maintenance personnel need to first determine whether the port corresponds to a 4-channel I2C switch or an 8-channel I2C switch, and then consult the hardware manuals and channel test procedures of the two types of I2C switches respectively, which cannot form a unified troubleshooting standard, especially when multiple groups of mixed I2C switches are deployed in a server, the troubleshooting efficiency will decrease significantly.

[0069] However, by combining I2C switches with the same number of basic channels, there is no need to design differential logic in the BMC code, and only a unified calculation module needs to be called to achieve accurate matching of ports and channels, and the code structure is more concise. In addition, the combination of I2C switches with the same number of channels also provides convenience for subsequent hardware expansion. If the number of NVME hard disks increases to 24 in the future, only the same number of I2C switches need to be added, and the original mapping logic can be used, without the need to restructure the hardware connection and software code, further reducing long-term operation and maintenance costs.

[0070] In some embodiments, when the BMC 110 performs step S231, it can also include steps S231-D to S231-E (not shown).

[0071] Step S231-D: If the number of I2C switches is one, determine that the I2C switch address is a second preset fixed address.

[0072] Specifically, during the hardware design phase of the hard drive backplane, when the number of I2C switches is determined to be one, the address of the I2C switch is fixed to a second preset fixed address, such as 0xE2, and the second preset fixed address is written into the code of the BMC.

[0073] During the communication between the BMC and the target hard disk backplane, when the BMC identifies the number of NVMEs present on the target hard disk backplane, it determines the number of I2C switches that need to be enabled. Then, it can access the I2C switches according to the second preset fixed address stored in the code, thereby controlling each channel of the I2C switches.

[0074] Step S231-E: If the number of I2C switches is greater than one, then the second preset fixed address is used as the starting address, and the address of each I2C switch is incremented at a preset interval.

[0075] Specifically, during the hardware design phase of the hard drive backplane, when it is determined that the number of I2C switches is greater than one, the address of the first I2C switch is fixed to a second preset fixed address (e.g., 0xE2), and the second preset fixed address is used as the base address of the entire I2C switch group. The addresses of subsequent I2C switches are allocated sequentially according to the rule of incrementing by 2 bytes.

[0076] For example, the address two bytes below the second preset fixed address (e.g., 0xE4) is used as the fixed address of the second I2C switch, and the address four bytes below the second preset fixed address (e.g., 0xE6) is used as the fixed address of the third I2C switch, and so on. The second preset fixed address and the preset interval are written into the BMC code. The preset interval is two bytes.

[0077] During the communication between the BMC and the target hard disk backplane, when the BMC identifies the number of NVMEs present on the target hard disk backplane, it determines the number of I2C switches that need to be enabled. Then, it can access each I2C switch according to the second preset fixed address and preset interval stored in the code, thereby controlling each channel of each I2C switch.

[0078] By allocating addresses at fixed intervals, address conflicts between multiple I2C switches on the same I2C bus can be avoided, ensuring that control commands sent by the BMC can be received by a single I2C switch. At the same time, the standardized address increment rule eliminates the need for the BMC code to store complex address mapping tables. The target address can be directly calculated using the I2C switch number, which greatly simplifies the address call logic in the code and reduces development difficulty.

[0079] In addition, choosing 2 bytes as the interval unit is based on the address characteristics optimization of the I2C protocol: I2C device addresses are usually 7 or 10 bits. Taking the common 7-bit address as an example, the 2-byte interval (i.e., the binary address increments by 10) can not only ensure the efficient use of address space, but also reserve enough address offset for each switch, so as to avoid exhausting the available address resources due to the subsequent expansion of more switches.

[0080] In some optional embodiments, the second preset fixed address can be arbitrarily selected according to the actual situation, and this application does not impose any restrictions on it.

[0081] By determining the model and number of I2C switches based on the number of NVMe hard drives during the hardware design phase, the addresses of I2C switches in different hard drive backplanes are unified into a fixed address, and the configuration information of the I2C switches is pre-stored in the BMC code, enabling the BMC to access the I2C switches based on the fixed address, thereby realizing access to each NVMe port in hard drive backplanes for different hard drive adapter types.

[0082] In some embodiments, when performing step S232, BMC 110 may also include step S232-A (not shown).

[0083] Step S232-A: Calculate the remainder when the port number of the target port is divided by the number of channels corresponding to the I2C switch model; use the target channel with the remainder as the access channel of the target port.

[0084] The target port can be any one of the ports.

[0085] Typically, multiple channels of an I2C switch correspond sequentially to multiple ports on the hard drive backplane. For example, channels 1 to 8 of an 8-channel I2C switch correspond to ports 1 to 8 and channel 2 on the hard drive backplane, respectively. When the number of ports on the hard drive backplane exceeds the channel capacity of a single I2C switch, a second I2C switch is introduced to expand the channels. For example, channels 1 to 8 of a second 8-channel I2C switch correspond to ports 9 to 16 on the hard drive backplane, respectively. Multiple I2C switches are combined until the number of channels is greater than or equal to the number of ports on the hard drive backplane.

[0086] Specifically, when BMC determines the access channel corresponding to the target port, the access channel number is calculated as x = Port ID mod M, where x is the channel number of the access channel corresponding to the target port, Port ID is the port number of the target port, and M is the number of channels corresponding to the I2C switch (usually 4 or 8).

[0087] It should be noted that when determining the access channel corresponding to the target port, the BMC also determines the I2C switch to which the access channel corresponding to the target port belongs, including determining the address of the I2C switch.

[0088] According to the content described in the foregoing step S231-E, the addressing formula of the I2C switch can be Addr = 0xE2 + 2 x (Port ID / M), where Addr is the address of each I2C switch.

[0089] Exemplarily, assuming that the number of channels corresponding to the I2C switch designed on the target hard disk backplane is 4, and the port number of the target port is 3, then the channel number of the access channel corresponding to the target port is 3 mod 4 = 3, and the address of the I2C switch to which the access channel belongs is 0xE2 + 2 x (3 / 4) = 0xE2, that is, the access channel corresponding to the target port is Channel 3 of the first I2C switch.

[0090] For another example, assuming that the number of channels corresponding to the I2C switch designed on the target hard disk backplane is 8, and the port number of the target port is 17, then the channel number of the access channel corresponding to the target port is 17 mod 8 = 3, and the address of the I2C switch to which the access channel belongs is 0xE2 + 2 x (17 / 8) = 0xE6, that is, the access channel corresponding to the target port is Channel 3 of the third I2C switch.

[0091] The combination determination mode of the I2C switch address and the channel number can accurately locate any port, effectively avoiding the problem of channel and port mapping confusion that may occur when multiple switches are used in parallel, and at the same time, leaving clear serial number expansion space for subsequent hardware expansion.

[0092] By recording the calculation mode of the access channel corresponding to each port in the BMC code, the BMC code structure is simple and clear, and the difficulty of later maintenance and upgrading is significantly reduced, thereby reducing the maintenance cost of the server.

[0093] In some optional embodiments, the BMC 110 can further perform step S240: accessing an electrically erasable programmable read-only memory with a third preset fixed address in the target hard disk backplane to obtain temperature information of the target hard disk backplane, so as to monitor the temperature of the target hard disk backplane.

[0094] In some specific embodiments, as shown in Figure 4 Step S240 further includes steps S241 to S242.

[0095] Step S241: determining a sensor address of a temperature sensor from the electrically erasable programmable read-only memory according to the third preset fixed address and a preset temperature address offset.

[0096] The third preset fixed address is a physical address of a hardware component, and has the same format as the first preset fixed address and the second preset fixed address but different content.

[0097] Specifically, an electrically erasable programmable read-only memory (EEPROM) is installed on the hard disk backboard. In the hardware design stage of the hard disk backboard, the address of the EEPROM is fixed as the third preset fixed address, for example, 0x0A, and the third fixed address is written into the code of the BMC. The BMC can directly read the EEPROM according to the pre-stored code.

[0098] The EEPROM stores the sensor addresses of the temperature sensors.

[0099] In some optional embodiments, the temperature sensors are core devices for monitoring the temperature of the hard disk backboard, and the number of the temperature sensors can increase with the increase of the hard disk backboard. To ensure that the BMC can accurately identify each temperature sensor and avoid monitoring failure caused by confusion of the sensor addresses, a special storage space can be planned in the EEPROM, for example, a 1 KB storage space is divided at a position with an address offset of 0x1000 relative to the starting address 0x0A of the EEPROM, and the address information of all the temperature sensors is stored in the 1 KB storage space. Compared with dispersively storing the address information in different hardware modules, the BMC can more conveniently read and manage the address information, and clear address query basis is provided for later sensor maintenance or replacement.

[0100] Step S242: Accessing the temperature sensor according to the sensor address to obtain the temperature information of the target hard disk backboard.

[0101] The BMC can access the temperature sensor and read the temperature parameter of the temperature sensor by reading the EEPROM to obtain the sensor address of the temperature sensor, thereby obtaining the temperature information of the target hard disk backboard.

[0102] In some optional embodiments, the temperature sensor can be provided with multiple temperature sensors. The sensor addresses of the temperature sensors can be all stored in the EEPROM, or the sensor addresses of the temperature sensors can be set at a fixed interval, and the sensor address of the first temperature sensor and the fixed interval are stored in the EEPROM. In addition, the type of the temperature sensor and the number of the hard disk backboards that need to be monitored can also be stored in the EEPROM, which is not limited in the present application.

[0103] By storing the address of the temperature sensor in the EEPROM and setting the address of the EEPROM as a fixed address, the BMC can parse the code to obtain the sensor address stored in the EEPROM, and then obtain the temperature information of the hard disk backboard, thereby realizing temperature monitoring of the hard disk backboard of different hard disk adaptation types.

[0104] In some embodiments, the BMC 110 can further perform step S250: reading the register according to the preset access period, determining the hard disk in-place state of each NVME port according to the hard disk in-place information of each port saved in the register; updating the opening and closing state of the access channel of the I2C switch corresponding to each NVME port according to the hard disk in-place state of each NVME port.

[0105] In some specific embodiments, step S250 includes step S251: if the current hard disk in-place state of the target NVME port is opposite to the last historical hard disk in-place state of the target NVME port, the opening and closing state of the access channel corresponding to the target NVME port is updated to be opposite to the last historical opening and closing state.

[0106] Wherein, the target NVME port is any one of the NVME ports.

[0107] Illustratively, the BMC reads the register of the CPLD once every 1 second, obtains the current hard disk in-place state of each NVME port in the register, and compares it with the last obtained historical hard disk in-place state. If the current hard disk state is not in place, and the last historical hard disk in-place state is in place, it indicates that the NVME hard disk of the NVME port is pulled out, and the BMC closes the access channel of the I2C switch corresponding to the NVME port to save the communication resource overhead. On the contrary, if the current hard disk in-place state is in place, and the last historical hard disk in-place state is not in place, it indicates that the NVME hard disk of the NVME port has been inserted, and the BMC reopens the access channel of the I2C switch corresponding to the NVME port to realize normal hard disk access.

[0108] In some embodiments, the BMC 110 can further perform step S260: saving the hard disk in-place state change log of the NVME port, so as to maintain the NVME port.

[0109] Wherein, the hard disk in-place state change log at least includes: port number of the NVME port, hard disk in-place state change type.

[0110] Illustratively, when the BMC detects that the hard disk of the NVME port 6 is pulled out, the BMC generates the hard disk in-place state change log: "Port 6: NVME hard disk pulled out". Similarly, when the BMC detects that the hard disk of the NVME port 6 is inserted, it also generates the corresponding hard disk in-place state change log: "Port 6: NVME hard disk inserted".

[0111] Optionally, the hard disk can also include information such as the NVME support state of the port in the on-site state change log, and the BMC can also detect the on-site state of the serial interface hard disk, which is not limited in the present application.

[0112] By periodically detecting the on-site state of the NVME port, the hot plug monitoring of the NVME hard disk can be realized, so as to adaptively adjust the opening and closing of the access channel, balance the communication resource overhead and the demand of hard disk access. Especially in a high-density NVME storage server, when some ports are not connected to hard disks, closing the access channel of the port can release a large amount of bus resources, so that the ports with hard disks can obtain more sufficient communication bandwidth, and the data read-write efficiency is improved. At the same time, the hard disk on-site state change log is generated for each port, so that when the port appears abnormity, the maintenance personnel can quickly locate the associated events of the problem by backtracking the log, and by analyzing the long-term log, if the hard disk on-site state change frequency of a certain NVME port is significantly higher than that of other ports, it can be predicted in advance that the port may have physical interface wear, poor signal contact and other hidden troubles, and timely arrange port maintenance or replacement to avoid the problem of hard disk offline and data access interruption caused by sudden failure.

[0113] In some embodiments, the BMC 110 can also perform step S270: if the target adaptation type is a serial interface hard disk adaptation type or a mixed hard disk adaptation type, directly access the serial interface hard disk corresponding to each port of the target hard disk based on the number of on-site serial interface hard disks.

[0114] Specifically, each port of the serial interface hard disk adaptation type does not support NVME, so it does not need to be accessed related to NVME, and the access to the serial interface hard disk does not need to pass through the access channel of the I2C switch, and the conventional access mode corresponding to the serial interface hard disk is adopted, for example, the traditional AHCI protocol is accessed, which is not described herein.

[0115] The access of the serial interface hard disk is independent of the I2C communication system, which can simplify the access link and avoid the delay that may be caused by the occupation of the I2C bus bandwidth.

[0116] It should be noted that the NVME port is not limited to connecting the NVME protocol hard disk, but has the downward compatibility of the serial interface hard disk (such as SATA hard disk, SAS hard disk, etc.) through hardware compatibility optimization and protocol adaptation. When the port supporting NVME is inserted into the serial interface hard disk, the system does not need to additionally replace the hardware interface or redeploy the communication link, and still can use the original I2C switch access channel to realize data interaction and device management.

[0117] In the hardware management architecture of the server, the BMC is a core unit of hardware monitoring and management, and usually needs to be connected to multiple hard disk backplanes, such as 2, 4 or even more, and the specific number depends on the storage expansion requirements of the server. Therefore, before accessing the hard disk on the target hard disk backplane, the BMC determines the target hard disk backplane to be accessed from the multiple hard disk backplanes according to the connection mode of the BMC and the multiple hard disk backplanes.

[0118] In an alternative embodiment, the BMC can be directly connected to multiple hard disk backplanes through multiple I2C buses, wherein one I2C bus is connected to one hard disk backplane. At this time, the BMC can scan multiple I2C buses to determine the target hard disk from the multiple hard disk backplanes connected by the multiple I2C buses.

[0119] The I2C bus is a simple, bidirectional two-wire synchronous serial bus, and devices connected to the I2C bus can transmit information between them.

[0120] For example, as shown in Figure 5 , the BMC is directly connected to the hard disk backplane through the I2C bus, wherein the BMC is directly connected to the hard disk backplane 1 through the I2C bus 1, the BMC is directly connected to the hard disk backplane 2 through the I2C bus 2, the BMC is directly connected to the hard disk backplane 3 through the I2C bus 3, and so on.

[0121] Since each hard disk backplane is independently connected to a different I2C bus, that is, each I2C bus only carries communication data of a single hard disk backplane, this "one-to-one" bus allocation mode provides a hardware basis for parallel access. For example, at the same time, the BMC can obtain hard disk health information of the hard disk backplane 1 through the I2C bus 1, and send fan speed adjustment instructions to the hard disk backplane 2 through the I2C bus 2; in addition, it can also communicate or send instructions to the hard disk backplane 3 through the I2C bus 3. This parallel access capability not only avoids the response delay caused by the single bus bottleneck, but also significantly improves the centralized management efficiency of the BMC on multiple hard disk backplanes, especially in the scenario where the server is equipped with a large number of hard disk backplanes, which can effectively guarantee the real-time and stability of hardware monitoring and management.

[0122] In another alternative embodiment, the BMC can be indirectly connected to multiple hard disk backplanes through the channels of a bus I2C switch connected to the I2C bus, wherein the bus I2C switch has multiple bus channels, and one hard disk backplane can be connected to one bus channel.

[0123] For example, as shown in Figure 6As shown, the BMC is indirectly connected with multiple hard disk backplanes through a 4-channel bus I2C switch connected with the I2C bus, wherein access channel 1 of the I2C switch is connected with hard disk backplane 1, access channel 2 of the I2C switch is connected with hard disk backplane 2, access channel 3 of the I2C switch is connected with hard disk backplane 3, and access channel 4 of the I2C switch is connected with hard disk backplane 4.

[0124] The bus I2C switch can be selected from the various types of I2C switches described above. When a 4-channel I2C switch is selected as the bus I2C switch, the BMC can be connected with up to 4 hard disk backplanes through one I2C bus; when an 8-channel I2C switch is selected as the bus I2C switch, the BMC can be connected with up to 8 hard disk backplanes through one I2C bus.

[0125] Since different hard disk backplanes are connected on the same I2C bus, the BMC can only access different hard disk backplanes in series by switching the channels of the bus I2C switch.

[0126] For example, when the BMC needs to interact with hard disk backplane A, it needs to first send a control instruction to the bus I2C switch to switch the communication channel of the bus I2C switch to the channel Channel 1 corresponding to the hard disk backplane A, and after the channel switching is completed and stable communication is established, data interaction can be carried out; if subsequent access to hard disk backplane B is required, the connection of the current channel Channel 1 needs to be disconnected, and an instruction needs to be sent to the bus I2C switch again to switch to channel Channel 2. In the entire process, there is a clear sequence of access operations for different hard disk backplanes, and the access task of the previous hard disk backplane has not been completed and the channel has not been switched before the next hard disk backplane can establish communication with the BMC. This serial access mode can simplify bus wiring and reduce hardware costs.

[0127] It should be noted that the address of the bus I2C switch connected with multiple hard disk backplanes cannot be the same as the addresses of the multiple I2C switches corresponding to the target hard disk backplanes described above, to avoid the problem that different I2C switches cannot be accessed and controlled individually, leading to communication chaos and data damage.

[0128] In the case where the BMC is connected with multiple hard disk backplanes, since different hard disk backplanes all have a CPLD with a first preset fixed address, at least one I2C switch with a second preset fixed address, and an EEPROM with a third preset fixed address, the BMC only needs to parse the fixed code to identify and access different hard disk backplanes, and when a hard disk backplane needs to be added or replaced, the BMC code does not need to be modified.

[0129] The access method of the hard disk backplane will be further explained in detail below using specific embodiments.

[0130] Embodiment one: the target hard disk backplane is NVME hard disk adaptation type, there are 2 ports and 2 NVME hard disks have been inserted.

[0131] (1) The BMC sends a read instruction to the CPLD with a fixed address of 0x80 on the target hard disk backplane through the I2C bus, and the CPLD responds to the read instruction and returns the topology information stored in the register to the BMC. After the BMC parses, it is determined that each Prot supports NVME, and 2 ports have inserted NVME hard disks.

[0132] (2) The BMC determines the model of the corresponding I2C switch as PCA9546APW (4 channels) according to the number of NVME hard disks in place, and the address of the corresponding I2C switch is 0xE2. The BMC controls the I2C switch to switch to Channel 1 and Channel 2 respectively to correspond to access the NVME hard disks on Port 1 and Port 2, and realize the data interaction of state monitoring of the 2 NVME hard disks.

[0133] (3) The BMC accesses the EEPROM with an address of 0x0A through the I2C bus, reads that the number of temperature sensors in the EEPROM is 1, the sensor type is EMC1413, and the sensor address of the temperature sensor is 0x98. The BMC sends a temperature reading instruction to the address 0x98 to obtain temperature data, and completes the temperature monitoring of the target hard disk backplane.

[0134] (4) The BMC reads the CPLD register every 1 second, and when it finds that the NVME hard disk of Port 2 is pulled out, it generates a hard disk in-place state change log: "Port 2: NVME hard disk pulled out, support NVME". At the same time, the BMC stops accessing Port 2 through Channel 2 of the I2C switch. After a period of time, when the BMC detects that a new NVME hard disk is inserted into Port 2, the BMC generates a new hard disk in-place state change log: "Port 2: NVME hard disk inserted, support NVME", and re-accesses the new hard disk of Port 2 through Channel 2 of the I2C switch.

[0135] Embodiment two: the target hard disk backplane is a serial interface hard disk adaptation type, there are 6 ports and 6 SATA / SAS hard disks have been inserted.

[0136] (1) The BMC sends a read instruction to the CPLD with a fixed address of 0x80 on the target hard disk backplane through the I2C bus, and the CPLD responds to the read instruction and returns the topology information stored in the register to the BMC. After the BMC parses, it is determined that each Prot does not support NVME, and 6 ports have inserted SATA / SAS hard disks.

[0137] (2) Since all the Ports do not support NVME, the BMC does not need to perform channel switching and access operation of the I2C switch related to NVME, and manages in the conventional access mode of SATA / SAS. The conventional access mode of SATA / SAS can refer to the existing related technology, which is not described here.

[0138] (3) The BMC accesses the EEPROM at address 0x0A through the I2C bus, reads that the number of temperature sensors stored in the EEPROM is 1, the sensor type is EMC1413, and the sensor address of the temperature sensor is 0x98, and the BMC sends a temperature reading instruction to the address 0x98 to obtain temperature data, and completes the temperature monitoring of the target hard disk backplane.

[0139] (4) The BMC reads the CPLD register every 1 second, and when it finds that the SATA hard disk of Port 5 is pulled out, it generates a hard disk in-place state change log: "Port 5: SATA / SAS hard disk is pulled out, does not support NVME". At the same time, the BMC stops the regular access to Port 5. After a period of time, when the BMC detects that Port 5 inserts a new SAS hard disk, the BMC generates a new hard disk in-place state change log: "Port 2: SATA / SAS hard disk is inserted, does not support NVME", and re-performs regular access to the new hard disk of Port 5.

[0140] Example Three: The target hard disk backplane is of NVME hard disk adaptation type, and there are 10 ports and 10 NVME hard disks have been inserted.

[0141] (1) The BMC sends a read instruction to the CPLD at a fixed address 0x80 on the target hard disk backplane through the I2C bus, and the CPLD responds to the read instruction and returns the topology information stored in the register to the BMC. After the BMC analyzes, it is determined that each Port supports NVME, and 10 ports have inserted NVME hard disks.

[0142] (2) The BMC determines that 2 I2C switches of TCA9548APWR (8 channels) are needed according to the number of in-place NVME hard disks, and the corresponding I2C switch addresses are 0xE2 and 0xE4. For Port 1 to Port 8, the BMC controls the I2C switch at address 0xE2 to switch to Channel 1 and Channel 8 for access, and for Port 9 to Port 10, the BMC controls the I2C switch at address 0xE4 to switch to Channel 1 and Channel 2 for access, thereby realizing comprehensive access to 10 NVME hard disks.

[0143] (3) BMC accesses the EEPROM at address 0x0A through the I2C bus, reads the number of temperature sensors stored in the EEPROM as 1, the sensor type as EMC1413, and the sensor address of the temperature sensor as 0x98, sends a temperature reading instruction to the address 0x98, obtains temperature data, and completes the temperature monitoring of the target hard disk backplane.

[0144] (4) BMC reads the CPLD register every 1 second, and when it finds that the NVME hard disk of Port 2 is pulled out, generates a hard disk present state change log: “Port 2: NVME hard disk pulled out, support NVME”. At the same time, BMC stops accessing Port 2 through Channel 2 of the I2C switch. After a period of time, when BMC detects that a new NVME hard disk is inserted into Port 2, BMC generates a new hard disk present state change log: “Port 2: NVME hard disk inserted, support NVME”, and re-accesses the new hard disk of Port 2 through Channel 2 of the I2C switch.

[0145] Embodiment Four: The target hard disk backplane is of a mixed hard disk adaptation type, and has a total of 8 ports, into which 4 NVME hard disks and 4 SATA hard disks are inserted.

[0146] (1) BMC sends a read instruction to the CPLD at a fixed address 0x80 on the target hard disk backplane through the I2C bus, and the CPLD responds to the read instruction and returns the topology information stored in the register to the BMC. After analysis by the BMC, it is determined that Port 1 to Port 4 support NVME and have inserted NVME hard disks, and Port 5 to Port 8 do not support NVME.

[0147] (2) BMC determines to use one PCA9546APW (4-channel) I2C switch according to the number of NVME hard disks present (4), and the corresponding I2C switch address is 0xE2. For Port 1 to Port 4, BMC controls the I2C switch at address 0xE2 to switch to Channel 1 and Channel 4 to access the NVME hard disk, respectively; for Port 5 to Port 8, because they do not support NVME, no NVME-related access is performed, and they are managed in the conventional access mode of SATA hard disks.

[0148] (3) BMC accesses the EEPROM at address 0x0A through the I2C bus, reads the number of temperature sensors stored in the EEPROM as 1, the sensor type as EMC1413, and the sensor address of the temperature sensor as 0x98, sends a temperature reading instruction to the address 0x98, obtains temperature data, and completes the temperature monitoring of the target hard disk backplane.

[0149] (4) BMC reads CPLD registers every 1 second, and when it finds that the NVME hard disk of Port 3 is unplugged, it generates a hard disk present state change log: “Port 3: NVME hard disk unplugged, support NVME”. At the same time, BMC stops accessing Port 3 through Channel 3 of the I2C switch. When BMC detects that the SATA hard disk of Port 6 is unplugged, BMC generates a hard disk present state change log: “Port 6: SATA hard disk unplugged, no support for NVME”, and stops regular access to it.

[0150] The present application unifies the information storage specifications of CPLD (fixed address 0x80) and EEPROM (fixed address 0x0A), and clearly defines the dynamic matching rules of I2C switch model, address and NVME hard disk quantity, which provides a hardware basis for BMC automatic parsing. When the hard disk backplane is replaced or added, BMC can automatically identify the I2C switch model and address according to the fixed address reading of CPLD and EEPROM information, and adjust the control logic of the access channel. The whole process does not need to manually modify the BMC code, breaks through the limitation of traditional code coupling, greatly improves the compatibility of BMC to different hard disk backplanes, and also reduces the cost of later hardware upgrade and maintenance.

[0151] It should be understood that although Figures 2 to 4 The steps in the flowchart of the method of the present application are shown in sequence according to the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Figures 2 to 4 The steps shown and the steps involved in other embodiments have no strict order limitation in execution unless explicitly stated herein. These steps can be executed in other orders. Moreover, at least part of the steps of the foregoing embodiments can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or sub-steps or stages of other steps.

[0152] From the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment.

[0153] In the second aspect, the embodiments of the present application provide a baseboard management controller for implementing the hard disk access method of the hard disk backplane provided in any of the embodiments of the first aspect of the present application.

[0154] In a third aspect, embodiments of the present application provide a server, comprising at least one hard disk backplane and a baseboard management controller;

[0155] The at least one hard disk backplane is provided with a programmable logic device with a first preset fixed address, at least one I2C switch with a second preset fixed address, and an electrically erasable programmable read-only memory with a third preset fixed address.

[0156] The baseboard management controller is configured to implement the hard disk access method of the hard disk backplane provided in any of the embodiments of the first aspect.

[0157] In some embodiments, the server further comprises that the electrically erasable programmable read-only memory stores a sensor address of a temperature sensor, and the temperature sensor is configured to detect temperature information of the at least one hard disk backplane.

[0158] In some embodiments, the server further comprises that the at least one hard disk backplane is directly connected to the baseboard management controller through the at least one I2C bus, and one I2C bus is connected to one hard disk backplane.

[0159] In some embodiments, the server further comprises that the at least one hard disk backplane is indirectly connected to the baseboard management controller through a bus I2C switch connected to the I2C bus, and the bus I2C switch corresponds to a plurality of bus channels, and one bus channel is connected to one hard disk backplane.

[0160] In a fourth aspect, embodiments of the present application provide a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the hard disk access method of the hard disk backplane provided in any of the embodiments of the first aspect.

[0161] In an example embodiment, the computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0162] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing relevant hardware, and the foregoing computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, the computer program can include the processes of the above-mentioned embodiment methods. Any reference to memory, storage, database or other medium used in the embodiments of the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct RAMbus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0163] Any combination of the technical features of the above embodiments can be made, and in order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered as the range disclosed in the present application.

[0164] The above embodiments only express some implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the protection scope of the present application. It should be pointed out that for those skilled in the art, some modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A hard disk access method of a hard disk backplane, applied to a baseboard management controller, characterized in that, The baseboard management controller pre-stores a first preset fixed address, a plurality of hard disk adapter types, and access strategy information matched with each hard disk adapter type; each hard disk adapter type includes an NVME hard disk adapter type, a serial interface hard disk adapter type, and a hybrid hard disk adapter type; the method includes: Accessing a register of a programmable logic device with the first preset fixed address in a target hard disk backplane to obtain topology information of the target hard disk backplane; the topology information includes the number of ports of the target hard disk backplane, the NVME support state of each port, and hard disk in-place information of the each port; Based on the NVME support state of the each port contained in the topology information, determining a target hard disk adapter type of the target hard disk backplane from the plurality of hard disk adapter types; Based on the access strategy information matched with the target hard disk adapter type, accessing the in-place target hard disk.

2. The method of claim 1, wherein, The access of the in-place target hard disk based on the access strategy information matched with the target hard disk adapter type includes: If the target hard disk adapter type is the NVME hard disk adapter type or the hybrid hard disk adapter type, determining configuration information of an I2C switch based on the number of in-place NVME hard disks; the configuration information at least includes the number of I2C switches, the model of the I2C switch, and the address of the I2C switch; Determining the access channel corresponding to each NVME hard disk according to the configuration information of the I2C switch, and accessing the NVME hard disk based on the access channel.

3. The method of claim 2, wherein, The determination of the configuration information of the I2C switch based on the number of in-place NVME hard disks includes: If the number of in-place NVME hard disks is not greater than a first preset number threshold, determining that the number of I2C switches is one and the model of the I2C switch is a first model; the number of channels corresponding to the first model is the first preset number threshold; If the number of in-place NVME hard disks is greater than the first preset number threshold and not greater than a second preset number threshold, determining that the number of I2C switches is one and the model of the I2C switch is a second model; the number of channels corresponding to the second model is the second preset number threshold; If the number of in-place NVME hard disks is greater than the second preset number threshold, determining that the number of I2C switches is the number of in-place NVME hard disks divided by the second preset number and rounded up, and the model of the I2C switch is the second model.

4. The method of claim 3, wherein, The determination of the configuration information of the I2C switch based on the number of in-place NVME hard disks further includes: If the number of I2C switches is one, determining that the address of the I2C switch is a second preset fixed address; If the number of I2C switches is greater than one, each I2C switch address is incremented by a preset interval from the second preset fixed address as a starting address.

5. The method of claim 2, wherein, The determination of the access channel corresponding to each NVME hard disk according to the configuration information of the I2C switch includes: Calculating the remainder of the port number of a target port divided by the number of channels corresponding to the model of the I2C switch; The target channel numbered as the remainder is taken as an access channel of the target port; wherein the target port is any one of the ports.

6. The method of claim 1, wherein, The method further comprises: The target hard disk backboard is determined based on a plurality of hard disk backboards connected under a plurality of I2C buses; wherein one I2C bus is connected with one hard disk backboard.

7. The method of claim 1, wherein, The method further comprises: The target hard disk backboard is determined according to a bus I2C switch connected with the I2C bus; wherein the bus I2C switch corresponds to a plurality of bus channels, and one bus channel is connected with one hard disk backboard.

8. The method of claim 1, wherein, The method further comprises: An electrically erasable programmable read-only memory with a third preset fixed address in the target hard disk backboard is accessed to obtain temperature information of the target hard disk backboard, so as to monitor the temperature of the target hard disk backboard.

9. The method of claim 8, wherein, The access to the electrically erasable programmable read-only memory with the third preset fixed address in the target hard disk backboard to obtain the temperature information of the target hard disk backboard comprises: A sensor address of a temperature sensor is determined from the electrically erasable programmable read-only memory according to the third preset fixed address and a preset temperature address offset; The temperature sensor is accessed according to the sensor address to obtain the temperature information of the target hard disk backboard.

10. The method of claim 1, wherein, The method further comprises: The hard disk in-place states of the NVME ports are determined according to the hard disk in-place information of the ports saved in the register read at a preset access period; The open / close states of the access channels of the I2C switches corresponding to the NVME ports are updated according to the hard disk in-place states of the NVME ports.

11. The method of claim 10, wherein, The open / close states of the access channels corresponding to the NVME ports are updated according to the hard disk in-place states of the NVME ports, comprising: If the current hard disk in-place state of a target NVME port is opposite to the historical hard disk in-place state of the target NVME port last time, the open / close state of the access channel corresponding to the target NVME port is updated to be opposite to the last historical open / close state; wherein the target NVME port is any one of the NVME ports.

12. The method of claim 10, wherein, The method further comprises: A hard disk in-place state change log of the NVME port is saved to maintain the NVME port; wherein the hard disk in-place state change log at least comprises a port number of the NVME port and a hard disk in-place state change type.

13. The method of claim 1, wherein, The target hard disk is accessed based on the access strategy information matched with the target hard disk adaptation type, comprising: If the target hard disk adaptation type is the serial interface hard disk adaptation type or the hybrid hard disk adaptation type, the target hard disk is directly accessed based on the number of in-place serial interface hard disks corresponding to the ports of the target hard disk.

14. A server, characterized by The server comprises at least one hard disk backboard and a baseboard management controller. The at least one hard disk backboard is provided with a programmable logic device with a first preset fixed address, at least one I2C switch with a second preset fixed address, and an electrically erasable programmable read-only memory with a third preset fixed address. The baseboard management controller is configured to perform the steps of the method according to any one of claims 1 to 13 on the at least one hard disk backboard.

15. The server of claim 14, wherein, Further comprising: The electrically erasable programmable read-only memory stores a sensor address of a temperature sensor, and the temperature sensor is configured to detect temperature information of the at least one hard disk backboard.

16. The server of claim 14, wherein, Further comprising: The at least one hard disk backboard is directly connected to the baseboard management controller through at least one I2C bus, and one I2C bus is connected to one hard disk backboard.

17. The server of claim 14, wherein, Further comprising: The at least one hard disk backboard is indirectly connected to the baseboard management controller through a bus I2C switch connected to an I2C bus, and the bus I2C switch corresponds to a plurality of bus channels, and one bus channel is connected to one hard disk backboard.

18. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the method according to any one of claims 1 to 13.

19. A computer program product, characterised in that, The computer program is executed by the processor to implement the steps of the method according to any one of claims 1 to 13.

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