Control methods, devices, and media for server loading PCIe card Option ROM fault tolerance mechanism

Abstract

The application discloses a kind of server loading PCIE card Option ROM fault-tolerant mechanism control method, device and medium, method includes: entering PCI bus to the enumeration detection link of PCIE card to be measured;If the configuration space information of current enumeration PCIE card is different from the content of PCIE card link table, the Option Rom program of current PCIE card is loaded into memory, and generates EFI_IMAGE_HANDLE information, records the configuration space information of current PCIE card Option ROM program in memory by EFI_IMAGE_HANDLE information;According to the configuration space information of current enumeration PCIE card, new node is constructed and is inserted into PCIE card link table, and PCIE card hardware initialization is executed;Check the execution state of the Option Rom program of current PCIE card, if the Option Rom program of PCIE card is normally executed, delete the relevant information of current PCIE card stored in nonvolatile storage area, skip the detection of current PCIE card, and continue to enumerate next PCIE card to be measured.The application effectively avoids repeated loading, can quickly skip abnormal PCIE card, and record relevant log information, improve the overall performance and reliability of server.

Description

Technical Field

[0001] This invention relates to the field of server technology, and in particular to a control method, apparatus, and medium for loading a PCIe card Option ROM fault tolerance mechanism in a server. Background Technology

[0002] With the continuous development of server technology, server hardware architecture is becoming increasingly complex. PCIe (Peripheral Component Interconnect Express) cards, as important expansion devices, are widely used in servers to provide various functions such as network connectivity, storage expansion, and graphics processing. However, some problems exist in the initialization and configuration process of PCIe cards, especially in the Option ROM (Optional Read-Only Memory) loading stage.

[0003] Option ROM is firmware provided by PCIe card manufacturers to initialize the hardware functions of the PCIe card. However, existing PCIe card Option ROM loading mechanisms have the following shortcomings: Limited fault tolerance: When the PCIe card Option ROM program encounters anomalies (such as program crashes, timeouts, etc.), the existing mechanism often cannot handle it effectively, leading to server startup failures or significantly extended startup times. Duplicate loading issues: In some cases, the server may repeatedly load the same PCIe card Option ROM program, especially after a system reboot. This not only wastes startup time but may also cause compatibility issues. Inadequate handling of abnormal devices: When an abnormal PCIe card is detected, the existing mechanism cannot effectively skip these devices, resulting in unnecessary waiting and resource waste during system startup. Summary of the Invention

[0004] This invention provides a control method, apparatus, and medium for loading a PCIe card Option ROM fault tolerance mechanism in a server, aiming to at least solve one of the technical problems existing in the prior art.

[0005] The technical solution of this invention is a control method for loading a PCIe card Option ROM fault tolerance mechanism in a server, comprising:

[0006] When the server is detected to be powered on, the process enters the PCI bus enumeration and detection phase for the PCIe card under test.

[0007] If the configuration space information of the currently enumerated PCIe card is different from the content of the PCIe card linked list, the current PCIe card's Option ROM program is loaded into memory through the UEFI firmware's LoadImage() service, and EFI_IMAGE_HANDLE information is generated. The configuration space information of the current PCIe card's Option ROM program in memory is recorded through the EFI_IMAGE_HANDLE information.

[0008] Based on the configuration space information of the currently enumerated PCIe cards, a new node is constructed and inserted into the PCIe card linked list. The UEFI firmware's StartingImage() service is called and combined with the EFI_IMAGE_HANDLE information to transfer control to the PCIe card Option Rom program that has been loaded into memory and execute PCIe card hardware initialization.

[0009] Check the execution status of the Option ROM program of the current PCIe card. If the Option ROM program of the PCIe card is executing normally, delete the relevant information of the current PCIe card stored in the non-volatile memory area, skip the detection of the current PCIe card, and continue to enumerate the next PCIe card to be tested.

[0010] According to some embodiments of the present invention, the enumeration detection step of entering the PCI bus to detect the PCIe card under test includes:

[0011] The BIOS reads from the non-volatile memory area and constructs a list of PCIe cards that need to be skipped. The contents of the PCIe card list include the manufacturer ID, device ID, PCIe slot number and node information of several PCIe cards.

[0012] The BIOS traverses the PCIe card linked list and performs a consistency comparison with the configuration space information of the currently enumerated PCIe card. The configuration space information includes the manufacturer ID, device ID, PCIe slot number, and node information of the currently enumerated PCIe card.

[0013] If the configuration space information of the currently enumerated PCIe card is the same as the content of the PCIe card linked list, the configuration space information of the currently enumerated PCIe card is reported to the BMC through the IPMI interface, and the currently enumerated PCIe card is recorded as an abnormal device card in the log file. The abnormal device card is skipped, and the process returns to continue enumerating the next PCIe card.

[0014] According to some embodiments of the present invention, the control method for loading the PCIe card Option ROM fault tolerance mechanism in the server further includes:

[0015] The cached information generated during the enumeration and detection of the PCI bus on the PCIE card under test is stored in the non-volatile storage area.

[0016] When it is detected that the Option ROM program of the currently enumerated PCIe card is in a crash state, a restart command is triggered to restart the server;

[0017] Once the server restarts, it retrieves the cached information from the non-volatile storage area and re-enters the PCI bus enumeration and detection phase for the PCIe card under test.

[0018] According to some embodiments of the present invention, the step of constructing a new node based on the configuration space information of the currently enumerated PCIe card and inserting the new node into the PCIe card Option ROM linked list includes:

[0019] The structure of the PCIe card Option ROM linked list is constructed using the configuration space information, linked list nodes, and linked list head pointer of the currently enumerated PCIe card.

[0020] The structure of the PCIe card Option ROM linked list is initialized by initializing the head pointer of the linked list;

[0021] Perform a data deduplication check on the PCIe card Option ROM linked list. Traverse the PCIe card Option ROM linked list and call the ContainsValue() function to compare all fields of the data in the configuration space of the currently enumerated PCIe card. If a match is found, return an error status.

[0022] Based on the configuration space information of the currently enumerated PCIe cards, call AllocatePool() to allocate memory space to create a new node. If the allocation fails, return an error status and copy the Value field value of the currently enumerated PCIe cards to the Data structure of the new node.

[0023] The Data structure of the new node is inserted into the PCIe card Option ROM linked list using the head insertion method. The Next pointer of the new node is set to point to the original head node. The head pointer of the linked list is updated, and a success status is returned.

[0024] According to some embodiments of the present invention, the control method for loading the PCIe card Option ROM fault tolerance mechanism in the server further includes:

[0025] The validity of the PCIe card Option ROM linked list is verified by judging the validity of the linked list head pointer. If the linked list head pointer is invalid, an error status is returned.

[0026] Starting from the original node, check the Data structure of each node one by one. If all field values ​​of the Data structure of a certain node are completely consistent with the field values ​​of the Value of the currently enumerated PCIe card, return the correct status.

[0027] If no matching item is found after traversing the PCIe card Option ROM linked list, an error status is returned.

[0028] According to some embodiments of the present invention, the control method for loading the PCIe card Option ROM fault tolerance mechanism in the server further includes:

[0029] Check if the parameter of the PCIe card Option ROM linked list is NULL. If it is NULL, return the EFI_INVALID_PARAMETER error code.

[0030] Call the GetListSize() function to obtain the number of nodes in the PCIe card Option ROM linked list and calculate the total storage size;

[0031] Allocate a temporary buffer, traverse the PCIe card Option ROM linked list and write the Data structure of each node into the temporary buffer in sequence. If memory allocation fails, return the error code EFI_OUT_OF_RESOURCES.

[0032] Call the gRT->SetVariable() interface to store data with UEFI variable names and globally unique identifiers. The variable is non-volatile and can be accessed during both the service startup phase and the runtime phase.

[0033] If memory allocation is successful, release the temporary buffer memory and return a success status.

[0034] According to some embodiments of the present invention, the BIOS traverses the PCIe card linked list and performs a consistency comparison process with the configuration space information of the currently enumerated PCIe card, including:

[0035] The PCI bus driver installs an EFI_PCI_IO_PROTOCOL interface for each PCI controller.

[0036] The EFI_PCI_IO_PROTOCOL interface provides a Pci.Read function, through which a pointer to EFI_PCI_IO_PROTOCOL is used to specify the width of the read operation, set the size of the read data, and the starting address of the buffer where the read data is stored;

[0037] Based on the pointer to EFI_PCI_IO_PROTOCOL, the width of the read operation is specified, the size of the read data is set, and the starting address of the buffer where the read data is stored is read, the configuration space information of the currently enumerated PCIe card is read, including the manufacturer ID, device ID, PCIe slot number, and node information.

[0038] The manufacturer ID, device ID, PCIe slot number, and node information of the currently enumerated PCIe card are compared with the manufacturer ID, device ID, PCIe slot number, and node information of each PCIe card stored in the PCIe card linked list.

[0039] If the vendor ID, device ID, PCIe slot number, and node information of the currently enumerated PCIe card are the same as the information in the PCIe card linked list, it indicates that the vendor ID, device ID, PCIe slot number, and node information of the currently enumerated PCIe card already exist in the non-volatile storage area, and the Option ROM loading process of the currently enumerated card is skipped.

[0040] According to some embodiments of the present invention, the configuration space information of the currently enumerated PCIe card is reported to the BMC via the IPMI interface, and the currently enumerated PCIe card is recorded as an abnormal device card in the log file, including:

[0041] Call the LocateProtocol() service of the UEFI firmware to obtain the IPMI protocol handle;

[0042] Create an EFI_SEL_RECORD_DATA structure and populate the relevant fields of the EFI_SEL_RECORD_DATA structure based on the vendor ID, device ID, PCIe slot number, and node information of the currently enumerated PCIe cards to build a log file;

[0043] The gIpmiTransport->SendIpmiCommand() function is called to send the constructed log file to the IPMI interface, and the configuration space information of the abnormal PCIe card recorded in the log file is reported to the BMC through the IPMI interface.

[0044] The present invention also relates to a computer device, including a memory and a processor, wherein the processor performs the above-described method when executing a computer program stored in the memory.

[0045] The present invention also relates to a computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement the above-described method.

[0046] The control method, apparatus, and medium for loading the PCIe card Option ROM fault tolerance mechanism in the server provided by this invention have at least one of the following advantages or beneficial effects: By enumerating and detecting PCIe cards during server startup and comparing the current PCIe card's configuration space information with the PCIe card linked list content, abnormal or newly added PCIe cards can be quickly identified, thereby achieving effective management and fault tolerance of PCIe cards. Secondly, when inconsistent configuration space information is detected, the PCIe card Option ROM program is loaded through the UEFI firmware and its configuration space information in memory is recorded, ensuring the accuracy and reliability of PCIe card hardware initialization and avoiding system startup anomalies caused by PCIe card Option ROM loading failure. Furthermore, after the PCIe card Option ROM program executes normally, the relevant information of the current PCIe card stored in the non-volatile storage area is deleted, the detection of the current PCIe card is skipped, and the next PCIe card to be tested is enumerated, effectively improving system startup efficiency, reducing unnecessary detection steps, and speeding up server startup. Meanwhile, by monitoring the execution status of the PCIe card's Option ROM in real time, the loading of abnormal PCIe card Option ROMs is automatically skipped, further enhancing the system's stability and fault tolerance. The method of this invention can effectively improve the server's fault tolerance, stability, and startup efficiency when loading PCIe cards.

[0047] Furthermore, additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0048] Figure 1 This is a general flowchart of the control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to an embodiment of the present invention;

[0049] Figure 2 This is a detailed flowchart of step S100 in the control method for loading the PCIe card Option ROM fault tolerance mechanism in the server provided in this embodiment of the invention;

[0050] Figure 3 This is a detailed flowchart of the first embodiment of the control method for loading the PCIe card Option ROM fault tolerance mechanism in the server provided by the present invention.

[0051] Figure 4 This is a detailed flowchart of step S300 in the control method for loading the PCIe card Option ROM fault tolerance mechanism in the server provided in this embodiment of the invention;

[0052] Figure 5This is a second detailed flowchart of the control method for loading the PCIe card Option ROM fault tolerance mechanism in the server according to an embodiment of the present invention;

[0053] Figure 6 This is a third detailed flowchart of the control method for loading the PCIe card Option ROM fault tolerance mechanism in the server according to the embodiments of the present invention;

[0054] Figure 7 This is a detailed flowchart of step S120 in the control method for loading the PCIe card Option ROM fault tolerance mechanism in the server provided in the embodiment of the present invention;

[0055] Figure 8 This is a detailed flowchart of step S130 in the control method for loading the PCIe card Option ROM fault tolerance mechanism in the embodiment of the present invention. Detailed Implementation

[0056] The following will provide a clear and complete description of the concept, specific structure, and technical effects of the present invention in conjunction with the embodiments and accompanying drawings, so as to fully understand the purpose, solution, and effects of the present invention.

[0057] It should be noted that, unless otherwise specified, when a feature is referred to as "fixed" or "connected" to another feature, it can be directly fixed or connected to the other feature, or indirectly fixed or connected to the other feature. The singular forms "a," "described," and "the" used herein are also intended to include the plural forms, unless the context clearly indicates otherwise. Furthermore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and not for limiting the invention. The term "and / or" as used herein includes any combination of one or more of the associated listed items.

[0058] It should be understood that although the terms first, second, third, etc., may be used to describe various elements in this invention, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from each other. For example, a first element may also be referred to as a second element without departing from the scope of the invention, and similarly, a second element may also be referred to as a first element. Any and all instances or exemplary language (“e.g.,” “such as,” etc.) provided herein are intended only to better illustrate embodiments of the invention and, unless otherwise required, do not impose a limitation on the scope of the invention.

[0059] With the continuous development of server technology, server hardware architecture is becoming increasingly complex. PCIe (Peripheral Component Interconnect Express) cards, as important expansion devices, are widely used in servers to provide various functions such as network connectivity, storage expansion, and graphics processing. However, some problems exist in the initialization and configuration process of PCIe cards, especially in the Option ROM (Optional Read-Only Memory) loading stage.

[0060] Option ROM is firmware provided by PCIe card manufacturers to initialize the hardware functions of the PCIe card. However, existing PCIe card Option ROM loading mechanisms have the following shortcomings: Limited fault tolerance: When the PCIe card Option ROM program encounters anomalies (such as program crashes, timeouts, etc.), the existing mechanism often cannot handle it effectively, leading to server startup failures or significantly extended startup times. Duplicate loading issues: In some cases, the server may repeatedly load the same PCIe card Option ROM program, especially after a system reboot. This not only wastes startup time but may also cause compatibility issues. Inadequate handling of abnormal devices: When an abnormal PCIe card is detected, the existing mechanism cannot effectively skip these devices, resulting in unnecessary waiting and resource waste during system startup.

[0061] Based on this, embodiments of the present invention provide a control method, apparatus, and medium for loading the PCIe card Option ROM fault tolerance mechanism in a server. By improving the enumeration detection, Option ROM loading, execution status monitoring, and exception handling of the PCIe card, a control method is provided that can effectively avoid repeated loading, quickly skip abnormal devices, and record relevant log information, thereby improving the overall performance and reliability of the server.

[0062] Please refer to the following. Figures 1 to 8 The control method, apparatus, and medium for loading PCIe card Option ROM fault tolerance mechanism in servers provided in this embodiment of the invention will be further described.

[0063] Referring to Figure 1, Figure 1 This is a general flowchart of the control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to an embodiment of the present invention. The control method for loading the PCIe card Option ROM fault tolerance mechanism in a server includes, but is not limited to, steps S100 to S400. Specifically,

[0064] S100: When the server is detected to be powered on, the PCI bus enumeration and detection phase of the PCIE card under test is initiated.

[0065] S200: If the configuration space information of the currently enumerated PCIe card is different from the content of the PCIe card linked list, load the current PCIe card's Option ROM program into memory through the UEFI firmware's LoadImage() service, and generate EFI_IMAGE_HANDLE information. Record the configuration space information of the current PCIe card's Option ROM program in memory through the EFI_IMAGE_HANDLE information.

[0066] S300: Based on the configuration space information of the currently enumerated PCIe card, construct a new node and insert the new node into the PCIe card linked list. Call the StartingImage() service of the UEFI firmware and combine it with the EFI_IMAGE_HANDLE information to transfer control to the PCIe card Option Rom program that has been loaded into memory and execute PCIe card hardware initialization.

[0067] S400: Check the execution status of the Option ROM program of the current PCIe card. If the Option ROM program of the PCIe card is executing normally, delete the relevant information of the current PCIe card stored in the non-volatile memory area, skip the detection of the current PCIe card, and continue to enumerate the next PCIe card to be tested.

[0068] In some embodiments of the present invention, the control method for loading the PCIe card Option ROM fault tolerance mechanism in the server includes: when the server powers on, the UEFI firmware scans the PCI bus to discover all PCIe cards connected to the system. This is achieved through enumeration detection of the PCIe cards under test via the PCI bus. The enumeration process involves the UEFI firmware checking each PCIe card on the PCI bus and reading the configuration space information of each PCIe card. It is understood that the configuration space is a standardized area containing the identification information of the PCIe card.

[0069] If the configuration space information of the currently enumerated PCIe card is inconsistent with the contents of the PCIe card linked list, it indicates that this is a new PCIe card or that the configuration space information of the PCIe card has changed. In this case, the PCIe card's Option ROM program is processed. It's understood that the Option ROM is the firmware program provided by the PCIe card manufacturer, used to initialize the hardware functions of the PCIe card; it is stored in the PCIe card's non-volatile memory. The UEFI firmware loads the Option ROM program into memory through the LoadImage() service. After loading, the UEFI firmware generates an EFI_IMAGE_HANDLE, a handle used to identify the program loaded into memory. Through EFI_IMAGE_HANDLE, the UEFI firmware can record the current PCIe card Option ROM program's configuration space information in memory.

[0070] Based on the current PCIe card configuration space information, a new node is constructed and inserted into the PCIe card linked list for subsequent tracking and management of the device. The UEFI firmware calls the StartingImage() service, combining the EFI_IMAGE_HANDLE information (which records the Option ROM program's memory load address, size, and entry point), and transfers control to the Option ROM program already loaded into memory. The Option ROM program is then started, responsible for initializing the PCIe card's hardware functions, such as configuring registers and initializing hardware resources.

[0071] After the Option ROM program completes execution, the UEFI firmware checks its execution status. If the Option ROM program executes normally, it indicates that the PCIe card has been successfully initialized. The relevant information of the current PCIe card stored in the non-volatile memory area is deleted, and the detection of the current PCIe card is skipped. The next PCIe card to be tested is then enumerated, and this process repeats until all PCIe cards have been enumerated and processed. By monitoring the execution status of the Option ROM in real time and automatically skipping the loading of Option ROMs for abnormal PCIe cards, system startup speed is accelerated and system stability is improved.

[0072] The typical process of UEFI firmware detecting and initializing the PCIe card under test during server startup involves steps such as enumeration, consistency comparison, loading the Option ROM program, hardware initialization, and status checks. UEFI firmware ensures that all PCIe cards can be correctly initialized and ready for use by the operating system.

[0073] In one embodiment of the present invention, the control method for loading the PCIe card Option ROM fault tolerance mechanism in the server further includes:

[0074] Upon server startup, the hardware initialization process begins, entering the PCI bus enumeration and detection phase for PCIe cards. The PCI bus enumerates and scans for PCIe cards, determining whether all PCIe cards have been enumerated. If all PCIe cards have been enumerated, the process proceeds directly to "PCIe card enumeration complete," ending the enumeration process. If not all PCIe cards have been enumerated, the process continues with the next PCIe card.

[0075] The PCI bus scans the PCIe cards one by one. Each PCIe card has a unique configuration space. During the scan, the system determines whether the current PCIe card has been enumerated. If the current PCIe card has been enumerated (i.e., all devices have been identified and recorded), the system enters the "PCIe card enumeration complete" stage and ends the enumeration process. If the current PCIe card has not been enumerated (i.e., there are still unidentified devices), the system continues to enumerate the next PCIe card. When all PCIe cards have been enumerated, the system enters the "PCIe card enumeration complete" stage.

[0076] After enumeration, the system performs further hardware initialization and configuration based on the enumerated PCIe card information. This includes loading the PCIe card driver and configuring its resource allocation. Finally, the system transfers control to the operating system, completing the entire hardware initialization process. This process ensures that all PCIe cards are correctly identified and initialized during system startup, providing the necessary hardware support for the operating system's operation.

[0077] Referring to Figure 2, Figure 2 This is a detailed flowchart of step S100 in the control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to an embodiment of the present invention. Step S100 includes, but is not limited to, steps S110 to S130. Specifically,

[0078] S110: The BIOS reads from the non-volatile memory area and constructs a list of PCIe cards that need to be skipped. The contents of the PCIe card list include the manufacturer ID, device ID, PCIe slot number and node information of several PCIe cards.

[0079] S120: The BIOS traverses the PCIe card linked list and performs a consistency comparison with the configuration space information of the currently enumerated PCIe card. The configuration space information includes the manufacturer ID, device ID, PCIe slot number, and node information of the currently enumerated PCIe card.

[0080] S130: If the configuration space information of the currently enumerated PCIe card is the same as the content of the PCIe card linked list, the configuration space information of the currently enumerated PCIe card is reported to the BMC through the IPMI interface, and the currently enumerated PCIe card is recorded as an abnormal device card in the log file. The abnormal device card is skipped, and the process returns and continues to enumerate the next PCIe card.

[0081] In some embodiments of the present invention, the enumeration and detection step of the PCI bus for the PCIe card under test includes: when the server is detected to be powered on, the BIOS reads from the non-volatile memory area and constructs a linked list of PCIe cards to be skipped. The non-volatile memory area refers to data stored in the BIOS chip or other non-volatile storage devices, which is retained even after the system server is powered off. The contents of the PCIe card linked list include the manufacturer ID, device ID, PCIe slot number, and node information of several PCIe cards. The manufacturer ID is a code that uniquely identifies the device manufacturer; the device ID is a code that uniquely identifies the device model; the PCIe slot number indicates the slot number of the PCIe card to which the device is inserted; and the node information includes pointers in the linked list or other device-related metadata.

[0082] The BIOS traverses the PCIe card linked list, checking the information of each PCIe card in the list one by one to obtain the configuration space information of the currently enumerated PCIe card, including the manufacturer ID, device ID, PCIe slot number, node information, etc. Then, it compares the manufacturer ID, device ID, PCIe slot number, node information, etc. stored in the PCIe card in the linked list with the configuration space information of the currently enumerated PCIe card item by item.

[0083] If the configuration space information of the currently enumerated PCIe card is completely consistent with the contents of the linked list, it means that the PCIe card is a device that needs to be skipped. The configuration space information of the currently enumerated PCIe card is then reported to the BMC via the IPMI interface, a standard interface for hardware monitoring and management. Through the IPMI interface, the BIOS can report the configuration space information (vendor ID, device ID, PCIe slot number, etc.) of the skipped PCIe card to the BMC, marking the currently enumerated PCIe card as an abnormal device card and recording it in the log file. The BIOS directly skips further initialization or configuration of the abnormal device card and returns to continue enumerating the next PCIe card to be tested. This entire process will loop until all PCIe cards have been enumerated and processed, speeding up system startup and improving system stability.

[0084] The above process ensures that the BIOS can correctly identify and skip PCIe cards that need to be ignored, while providing necessary monitoring and maintenance information through the BMC and log files, which are used for subsequent troubleshooting and maintenance.

[0085] Reference Figure 3 As shown, Figure 3 This is a detailed flowchart of the first embodiment of the control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to an embodiment of the present invention. The control method for loading the PCIe card Option ROM fault tolerance mechanism in a server also includes, but is not limited to, steps S500 to S520. Specifically,

[0086] S500: Stores the cached information generated during the enumeration and detection of the PCI bus PCIE card under test into a non-volatile storage area.

[0087] S510: When the Option ROM program of the currently enumerated PCIe card is detected to be in a crash state, a restart command is triggered to restart the server;

[0088] S520: After the server restarts, it retrieves cached information from the non-volatile storage area and re-enters the PCI bus enumeration and detection phase of the PCIE card under test.

[0089] In some embodiments of the present invention, during the enumeration and detection of the PCIe card under test on the PCI bus, some intermediate information is generated, such as cached information like the configuration space information of the enumerated PCIe cards (vendor ID, device ID, PCIe slot number, etc.). This cached information is stored in a non-volatile memory area (such as the BIOS chip or other non-volatile memory devices). The characteristic of non-volatile memory areas is that the stored information is not lost even after the system is powered off. Storing this cached information allows the system to quickly restore the previous enumeration state after a restart, avoiding repetitive work.

[0090] The Option ROM program is firmware provided by the device manufacturer to initialize the device's hardware functions; it is typically stored in the device's non-volatile memory. During enumeration testing, the BIOS attempts to load and execute the PCIe card's Option ROM program. If the Option ROM program fails to execute correctly, such as due to a crash or timeout, the BIOS detects this failure. When a failure is detected in the Option ROM program, the BIOS triggers a reboot command, restarting the server.

[0091] After the server restarts, the BIOS retrieves previously stored cached information from the non-volatile memory area. Based on this cached information, the BIOS then re-enters the PCI bus enumeration and detection phase for the PCIe card under test.

[0092] By using cached information, the BIOS can quickly restore the previous enumeration state and continue to detect incomplete PCIe cards instead of starting from scratch. This process ensures that if an error occurs in the Option ROM program, the system can automatically restart and restore the previous enumeration state, thereby guaranteeing the integrity and reliability of hardware initialization.

[0093] Reference Figure 4 As shown, Figure 4 This is a detailed flowchart of step S300 in the control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to an embodiment of the present invention. Step S300 includes, but is not limited to, steps S310 to S350. Specifically,

[0094] S310: Construct the structure of the PCIe card Option ROM linked list using the configuration space information, linked list nodes, and linked list head pointer of the currently enumerated PCIe card;

[0095] S320: The structure of the PCIe card Option ROM linked list is initialized by initializing the head pointer of the linked list;

[0096] S330: Perform data deduplication check on the PCIe card Option ROM linked list, traverse the PCIe card Option ROM linked list and call the ContainsValue() function to compare all fields of the data in the configuration space of the currently enumerated PCIe card. If a match is found, return an error status.

[0097] S340: Based on the configuration space information of the currently enumerated PCIe card, call AllocatePool() to allocate memory space to create a new node. If the allocation fails, return an error status and copy the Value field value of the currently enumerated PCIe card to the Data structure of the new node.

[0098] S350: The new node's Data structure is inserted into the PCIe card's Option ROM linked list using the head insertion method. The new node's Next pointer is set to point to the original head node, the linked list head pointer is updated, and a success status is returned.

[0099] In some embodiments of the present invention, constructing a new node based on the configuration space information of the currently enumerated PCIe card and inserting the new node into the PCIe card Option ROM linked list includes: obtaining configuration space information from the currently enumerated PCIe cards, including vendor ID, device ID, PCIe slot number, etc., as well as linked list nodes and a head pointer, to construct the structure of the PCIe card Option ROM linked list. It can be understood that the structure of the PCIe card Option ROM linked list includes a data part (such as configuration space information) and a pointer part (a pointer to the next node). Initializing the linked list head pointer can initialize the structure of the PCIe card Option ROM linked list. Typically, the linked list head pointer is initialized to NULL, indicating that the linked list is empty.

[0100] The function iterates through the PCIe card's Option ROM linked list, calling the ContainsValue() function to compare all fields of the target data (i.e., the data in the configuration space of the currently enumerated PCIe card). Specifically, the ContainsValue() function compares all fields (such as manufacturer ID, device ID, PCIe slot number, etc.) of the data in the configuration space of the currently enumerated PCIe card. If a match is found, it means that the same PCIe card information already exists in the PCIe card's Option ROM linked list, and an error status is returned.

[0101] Based on the configuration space information of the currently enumerated PCIe card, the AllocatePool() function is called to allocate memory space to create a new node. If memory allocation fails, an error status is returned, and the configuration space information of the currently enumerated PCIe card is copied into the Data structure of the new node. The new node is inserted into the PCIe card's Option ROM linked list using the head insertion method. The Next pointer of the new node is set to point to the original head node, and the head pointer of the linked list is updated. Upon successful insertion, a success status is returned.

[0102] The above process ensures the correct construction and management of the PCIe card Option ROM linked list, while avoiding the insertion of duplicate data, thus improving the efficiency and reliability of linked list operations.

[0103] This invention provides functions for processing PCIe card Option ROM linked lists. The PCIe card's configuration space information includes a structure `OEM_OPTION_ROM_DEVICE_DATA` containing the PCIe card manufacturer ID, device ID, and PCIe slot number. The PCIe card also includes a node structure `OEM_OPTION_ROM_DEVICE_NODE` storing data and the address of the next node, `Next`, and a structure `LINKED_LIST` for the entire PCIe card linked list. Specifically, the `InitList()` function initializes the PCIe card linked list, the `InsertNode()` function inserts PCIe card data into the generated PCIe card linked list, `DeleteNode()` deletes data from PCIe nodes in the linked list, and the `GetListSize()` function retrieves the number of PCIe card Option ROM program information stored in the linked list. SaveListToNVRAM() stores the entire PCIe card list into a non-volatile memory area, LoadListFromNVRAM() constructs a PCIe card list from the non-volatile memory area, and ContainsValue() determines whether the PCIe card list contains information about a specific PCIe card.

[0104] The storage structure of the PCIe card Option ROM linked list is defined using three structures:

[0105] OEM_OPTION_ROM_DEVICE_DATA: Stores key information about the PCIe card (manufacturer ID, device ID, slot number).

[0106] OEM_OPTION_ROM_DEVICE_NODE: A linked list node containing data fields (the structure mentioned above) and a pointer to the next node.

[0107] LINKED_LIST: The head pointer of the linked list (pointing to the head node), which forms the basic structure of the PCIe card's Option ROM linked list.

[0108] VOID InitList(LINKED_LIST* List);

[0109] Initialize the PCIe card Option ROM linked list (InitList)

[0110] Step description:

[0111] The Head pointer of the PCIe card Option ROM linked list structure LINKED_LIST is initialized to NULL, indicating that the PCIe card Option ROM linked list is empty.

[0112] EFI_STATUS InsertNode(LINKED_LIST* List, OEM_OPTION_ROM_DEVICE_DATAValue);

[0113] Insert a new node (InsertNode)

[0114] Step description:

[0115] Parameter check: If List is NULL, return EFI_INVALID_PARAMETER.

[0116] Data deduplication check: Traverse the linked list and call the ContainsValue() function to compare all fields (VendorId, DeviceId, SlotNum) of the data in the configuration space of the currently enumerated PCIe card.

[0117] If a match is found, return EFI_ALREADY_STARTED.

[0118] Create a new node:

[0119] Call AllocatePool() to allocate memory space and create a new node OEM_OPTION_ROM_DEVICE_NODE.

[0120] If allocation fails, return EFI_OUT_OF_RESOURCES.

[0121] Copy the Value field value of the currently enumerated PCIe card to the Data structure of the new node.

[0122] Inserting a node using the head insertion method: Set the Next pointer of the new node to point to the original head node (List->Head), and update the head pointer of the linked list List->Head = NewNode. Return status: Returns EFI_SUCCESS on success.

[0123] In some embodiments of the present invention, the method further includes: deleting a node from the storage structure of the PCIe card Option ROM linked list, wherein the steps for deleting a node are as follows:

[0124] Parameter check:

[0125] If the PCIe card Option ROM list is empty or List is NULL, return EFI_NOT_FOUND.

[0126] Traverse to find the target node:

[0127] Initialize the Previous pointer to NULL, and the Current pointer to point to the head node.

[0128] Traverse the PCIe card Option ROM linked list and compare all fields (VendorId, DeviceId, SlotNum) of each node.

[0129] Deletion operation:

[0130] If a matching node is found:

[0131] If Previous == NULL (the target node is the head node), then List->Head = Current->Next.

[0132] Otherwise, Previous->Next = Current->Next.

[0133] Release the memory of the current node (FreePool()).

[0134] If not found, return EFI_NOT_FOUND.

[0135] Successfully returned EFI_SUCCESS.

[0136] Understandably, in this embodiment of the invention, before performing any operation, it first checks whether the PCIe card Option ROM is empty or whether the head pointer of the linked list is NULL. If the PCIe card Option ROM linked list is empty or the head pointer is NULL, the error status EFI_NOT_FOUND is returned. The Previous pointer is initialized to NULL, representing the previous node of the current node, and the Current pointer is initialized to point to the head node of the linked list, representing the node currently being checked. The linked list is traversed, and the fields (VendorId, DeviceId, SlotNum) of each node are compared one by one. If a matching node is found, the node and its previous node are recorded, and the linked list pointer is updated according to the position of the node (whether it is the head node).

[0137] If Previous == NULL, it means that the target node is the head node.

[0138] Update the head pointer of the linked list, List->Head, to Current->Next.

[0139] If Previous != NULL, it means that the target node is not the head node.

[0140] Update Previous->Next to Current->Next.

[0141] Use FreePool() to release the memory of the current node.

[0142] This process ensures the proper management and maintenance of the PCIe card's Option ROM linked list, especially in correctly handling the head node and other nodes when deleting a node.

[0143] In some embodiments of the present invention, the method further includes: obtaining the length of the PCIe card Option ROM linked list. Obtaining the length of the PCIe card Option ROM linked list includes the following steps:

[0144] Parameter check: If List is NULL, return 0.

[0145] Traverse the PCIe card Option ROM linked list:

[0146] Initialize the counter count to 0.

[0147] Traverse the PCIe card Option ROM linked list starting from the head node, incrementing the count by 1 for each node visited.

[0148] Returns the final count value as the length of the PCIe card Option ROM linked list.

[0149] Understandably, the process involves checking the value of the linked list head pointer. If the head pointer `List` is NULL, it indicates that the PCIe card Option ROM linked list is empty, and the length is returned as 0. A counter `count` is initialized to 0 to record the length of the linked list. Starting from the head node, each node is traversed sequentially. The counter `count` is incremented by 1 after each node is visited. After the traversal is complete, the final value of the counter is returned as the length of the linked list. This process ensures that the length of the PCIe card Option ROM linked list can be correctly obtained.

[0150] Reference Figure 5 As shown, Figure 5 This is a second detailed flowchart of the control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to an embodiment of the present invention. The control method for loading the PCIe card Option ROM fault tolerance mechanism in a server further includes, but is not limited to, steps S600 to S620. Specifically,

[0151] S600: Verifies the validity of the PCIe card Option ROM linked list by checking the validity of the linked list head pointer. If the linked list head pointer is invalid, an error status is returned.

[0152] S610: Starting from the original node, check the Data structure of each node one by one. If all field values ​​of the Data structure of a certain node are completely consistent with the value of the Value field of the currently enumerated PCIe card, return the correct status.

[0153] S620: If no matching item is found after traversing the PCIe card Option ROM linked list, an error status is returned.

[0154] In some embodiments of the present invention, the control method for the server loading PCIe card Option ROM fault tolerance mechanism further includes: checking whether the head pointer of the linked list is NULL; if the head pointer is NULL, it indicates that the PCIe card Option ROM linked list is invalid or empty, and an error status is returned. Then, the Current pointer is initialized to point to the original head node of the PCIe card Option ROM linked list, and the Data structure of each node is checked one by one. The field values ​​(VendorID, DeviceID, SlotNum) of the Data structure of each node are compared with the field values ​​of the currently enumerated PCIe card to see if they are completely consistent. If a matching node is found, a correct status is returned. If no matching item is found after traversing the linked list, an error status is returned. This process ensures that the validity of the linked list can be correctly verified and that a node matching the target PCIe card exists in the linked list.

[0155] In one embodiment, the existence check of the PCIe card Option ROM linked list loaded by the server includes:

[0156] Parameter check: Verify that the head pointer of the linked list List is valid. If invalid, return FALSE.

[0157] Traversing a linked list: Starting from the original head node, check the Data field of each node one by one.

[0158] Matching conditions: If all fields (VendorId, DeviceId, SlotNum) of a node are exactly the same as the input Value, return TRUE; if no match is found after traversing the entire linked list, return FALSE.

[0159] Reference Figure 6 As shown, Figure 6This is a third detailed flowchart of the control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to an embodiment of the present invention. The control method for loading the PCIe card Option ROM fault tolerance mechanism in a server further includes, but is not limited to, steps S700 to S740. Specifically,

[0160] S700: Check if the parameters of the PCIe card Option ROM list are NULL. If they are NULL, return the EFI_INVALID_PARAMETER error code.

[0161] S710: Call the GetListSize() function to get the number of nodes in the PCIe card Option ROM linked list and calculate the total storage size;

[0162] S720: Allocate a temporary buffer, traverse the PCIe card Option ROM linked list and write the Data structure of each node into the temporary buffer in sequence. If memory allocation fails, return the error code EFI_OUT_OF_RESOURCES.

[0163] S730: Call the gRT->SetVariable() interface to store data with UEFI variable names and globally unique identifiers. The variable is non-volatile and can be accessed during both the service startup phase and the runtime phase.

[0164] S740: If memory allocation is successful, release the temporary buffer memory and return a success status.

[0165] In some embodiments of the present invention, the control method for the server loading PCIe card Option ROM fault tolerance mechanism further includes: checking whether the PCIe card Option ROM linked list parameter is NULL; if it is NULL, it indicates that the PCIe card Option ROM linked list is invalid or empty, and the EFI_INVALID_PARAMETER error code is returned.

[0166] The GetListSize() function is called to get the number of nodes in the PCIE card Option ROM linked list and calculate the total storage size. It can be understood that the size of the Data structure of each node is sizeof(PCIECardInfo), so the total storage size is the number of nodes * sizeof(PCIECardInfo).

[0167] Allocate a temporary buffer based on the calculated total storage size, traverse the PCIe card Option ROM linked list and write the Data structure of each node into the temporary buffer in sequence. If memory allocation fails, return the error code EFI_OUT_OF_RESOURCES.

[0168] The `gRT->SetVariable()` interface is used to store data in a UEFI variable. This variable is non-volatile (`EFI_VARIABLE_NON_VOLATILE`) and accessible during both the startup and runtime phases (`EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS`). If memory allocation is successful, the temporary buffer is released, and the `EFI_SUCCESS` status is returned.

[0169] In one embodiment, the method for saving the PCIe card Option ROM linked list to a non-volatile memory area includes the following steps:

[0170] Parameter check: If the parameter of the PCIe card Option ROM list is NULL, return EFI_INVALID_PARAMETER.

[0171] Computational storage space:

[0172] Call GetListSize() to get the number of nodes Size.

[0173] The total storage size is Size * sizeof(OEM_OPTION_ROM_DEVICE_DATA).

[0174] Serialized data:

[0175] Allocate a temporary buffer named Data, and traverse the linked list to write the Data field of each node into the temporary buffer in order.

[0176] If memory allocation fails, return EFI_OUT_OF_RESOURCES.

[0177] Write to NVRAM:

[0178] Call the gRT->SetVariable() interface to store data using the UEFI variable name OEM_PCI_OPTION_ROM_VARIABLE_NAME and GUID.

[0179] The variable attributes are EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS.

[0180] Release resources: Upon success, release the temporary buffer memory and return EFI_SUCCESS.

[0181] In some embodiments of the present invention, the functions and processes related to non-volatile storage regions include:

[0182] In the UEFI firmware, the GetVariable() and SetVariable() services are used to read and write to this non-volatile memory area. The generated PCIe card Option ROM linked list is stored in this non-volatile memory area, or a PCIe card Option ROM linked list is constructed based on existing non-volatile memory area data to retrieve PCIe cards that need to be skipped from failure. OEM_PCI_OPTION_ROM_VARIABLE_NAME is defined as the name storing the VariableName, and the VendorGuid is defined as gOemOptionRomErrorDeviceGuid to identify the variable.

[0183] #define OEM_PCI_OPTION_ROM_VARIABLE_NAME L"OemOptionRomList"

[0184] / / Wide character string, identifying the UEFI variable storing the PCIe card Option ROM linked list.

[0185] EFI_GUID gOemOptionRomErrorDeviceGuid = {

[0186] 0xf10ef561, 0xf839, 0x4f01, {0x9d, 0x63, 0x07, 0x10, 0x08, 0xc9,0xbb, 0xdb}

[0187] };

[0188] / / Globally unique identifier (GUID) to ensure the uniqueness of variables

[0189] SetVariable (Sets a variable)

[0190] typedef EFI_STATUS SetVariable(

[0191] IN CHAR16 *VariableName, / / Variable name (e.g., OEM_PCI_OPTION_ROM_VARIABLE_NAME)

[0192] IN EFI_GUID *VendorGuid, / / Vendor GUID (e.g., gOemOptionRomErrorDeviceGuid)

[0193] IN UINT32 Attributes, / / Variable attributes (such as non-volatile, access permissions)

[0194] IN UINTN DataSize, / / Data length

[0195] IN VOID *Data / / Stored binary data );

[0197] Persistence across reboots is achieved by serializing the PCIe card Option ROM linked list data and writing it to UEFI variables.

[0198] Key parameter descriptions:

[0199] Attributes are set to:

[0200] EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS

[0201] Non-volatile: Data is stored in a non-volatile storage area;

[0202] Startup service / runtime access: Allows access during UEFI phase and operating system runtime.

[0203] GetVariable (Get Variable)

[0204] typedef EFI_STATUS GetVariable(

[0205] IN CHAR16 *VariableName, / / Variable name

[0206] IN EFI_GUID *VendorGuid, / / Vendor GUID

[0207] OUT UINT32 *Attributes OPTIONAL, / / Optional to return variable attributes

[0208] INOUT UINTN *DataSize, / / Input / output data length

[0209] OUT VOID *Data OPTIONAL / / Returned data buffer );

[0211] The stored PCIe card Option ROM linked list data is read from UEFI variables and deserialized.

[0212] Reference Figure 7 As shown, Figure 7 This is a detailed flowchart of step S120 in the control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to an embodiment of the present invention. Step S120 includes, but is not limited to, steps S121 to S125. Specifically,

[0213] S121: The PCI bus driver installs an EFI_PCI_IO_PROTOCOL interface for each PCI controller;

[0214] S122: The EFI_PCI_IO_PROTOCOL interface provides a Pci.Read function, through which a pointer to EFI_PCI_IO_PROTOCOL is used to specify the width of the read operation, set the size of the read data, and the starting address of the buffer where the read data is stored;

[0215] S123: Based on the pointer to EFI_PCI_IO_PROTOCOL, specify the width of the read operation, set the size of the read data, and read the starting address of the buffer where the read data is stored, read the configuration space information of the currently enumerated PCIe card, including the manufacturer ID, device ID, PCIe slot number, and node information.

[0216] S124: Compare the read manufacturer ID, device ID, PCIE slot number, and node information of the currently enumerated PCIE card with the manufacturer ID, device ID, PCIE slot number, and node information of each PCIE card stored in the PCIE card linked list.

[0217] S125: If the vendor ID, device ID, PCIE slot number, and node information of the currently enumerated PCIE card are the same as the information in the PCIE card linked list, it indicates that the vendor ID, device ID, PCIE slot number, and node information of the currently enumerated PCIE card already exist in the non-volatile storage area, then skip the Option ROM loading process of the currently enumerated card.

[0218] In some embodiments of the present invention, the BIOS traversing the PCIe card linked list and performing a consistency comparison with the configuration space information of the currently enumerated PCIe cards includes: the PCI bus driver installing an EFI_PCI_IO_PROTOCOL interface for each PCI controller. This interface provides a series of functions. In an EFI environment, the PCI bus interacts with the system through the EFI_PCI_IO_PROTOCOL interface and provides a unified access method for each PCI controller, allowing software to read and write the configuration space and I / O space of the PCI device. The EFI_PCI_IO_PROTOCOL interface provides a Pci.Read function, which is a function within the EFI_PCI_IO_PROTOCOL interface used to read the configuration space of the PCIe card. By calling the Pci.Read function, a specific location (such as an offset) in the configuration space is specified, and the vendor ID, device ID, PCIe slot number, and node information are read and stored in a buffer. The process iterates through the PCIe card list, comparing the configuration space information of the currently enumerated PCIe card with the information of each PCIe card stored in the list. The comparison fields include the manufacturer ID, device ID, PCIe slot number, and node information. If the configuration space information of the currently enumerated PCIe card matches the information in the list, it indicates that the PCIe card's information already exists in the non-volatile memory area, meaning the PCIe card has been identified and configured. Therefore, the Option ROM loading process for the currently enumerated card can be skipped to save boot time and resources. If no matching node is found, it means the currently enumerated PCIe card is a new device.

[0219] This mechanism can effectively avoid repeatedly loading Option ROM, improve system startup efficiency, and ensure system stability and compatibility.

[0220] Reference Figure 8 As shown, Figure 8 This is a detailed flowchart of step S130 in the control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to an embodiment of the present invention. Step S130 includes, but is not limited to, steps S131 to S133. Specifically,

[0221] S131: Call the LocateProtocol() service of the UEFI firmware to obtain the IPMI protocol handle;

[0222] S132: Create an EFI_SEL_RECORD_DATA structure and populate the relevant fields of the EFI_SEL_RECORD_DATA structure based on the vendor ID, device ID, PCIE slot number and node information of the currently enumerated PCIE card to build the log file;

[0223] S133: Call the gIpmiTransport->SendIpmiCommand() function to send the constructed log file to the IPMI interface, and report the configuration space information of the abnormal PCIe card recorded in the log file to the BMC through the IPMI interface.

[0224] In some embodiments of the present invention, reporting the configuration space information of the currently enumerated PCIe card to the BMC via the IPMI interface and recording the currently enumerated PCIe card as an abnormal device card via a log file includes:

[0225] The LocateProtocol() service of the UEFI firmware is invoked to obtain the IPMI protocol handle. The LocateProtocol() service is a service provided by the UEFI firmware used to find and obtain the handle of a specified protocol. In UEFI, a protocol is a mechanism used to share functionality or data between different drivers or applications.

[0226] By calling the LocateProtocol() service and passing in the IPMI protocol's GUID (Globally Unique Identifier), a handle to the IPMI protocol can be obtained. This handle will be used for subsequent IPMI operations. An EFI_SEL_RECORD_DATA structure is created and populated. Specifically, the relevant fields of the EFI_SEL_RECORD_DATA structure are populated based on the vendor ID, device ID, PCIe slot number, and node information of the currently enumerated PCIe card. The EFI_SEL_RECORD_DATA structure is used to construct System Event Log (SEL) records, which are typically used to record hardware events or exception information.

[0227] The `gIpmiTransport->SendIpmiCommand()` function is called. `SendIpmiCommand()` is a function provided by the IPMI protocol for sending IPMI commands. In this scenario, it is used to send the built log file to the IPMI interface. The log file contains configuration space information of the abnormal PCIe card (such as vendor ID, device ID, PCIe slot number, and node information). The log file is then sent to the BMC via the IPMI interface. The BMC will record this information so that the system administrator can perform subsequent troubleshooting and processing.

[0228] In one embodiment of the present invention, the relevant functions and processing for reporting the configuration space information of the currently enumerated PCIe card to the BMC through the IPMI interface are as follows:

[0229] Core data structure definition

[0230] typedef struct {

[0231] UINT16 RecordId; / / Unique identifier for system events

[0232] UINT8 RecordType; / / Event recording type (0x01: System event)

[0233] TIME_STAMP TimeStamp; / / Timestamp (UEFI time format)

[0234] UINT16 GeneratorId; / / Event generator ID (firmware module identifier)

[0235] UINT8 EvMRevision; / / Event model version (compliant with IPMI 2.0 specification)

[0236] UINT8 SensorType; / / Sensor type (0x13: PCI Option ROM error)

[0237] UINT8 SensorNumber; / / Sensor number (SlotNum + 0x90 encoding rule)

[0238] UINT8 EventDirType; / / Event direction and type (0x03: Discrete event)

[0239] UINT8 OEMEvData1; / / OEM Extended Field 1 (0x0F: Option ROM Error Type)

[0240] UINT8 OEMEvData2; / / OEM extended field 2 (PCIe bus number)

[0241] UINT8 OEMEvData3; / / OEM Extended Field 3 (PCIe Device Number (high 4 bits) + Function Number (low 4 bits))

[0242] } EFI_SEL_RECORD_DATA;

[0243] The EFI_SEL_RECORD_DATA structure is the core data format for implementing system-level tracing of Option ROM error events.

[0244] Field design specifications:

[0245] SensorType (0x13): PCI Option ROM error type as defined by the IPMI standard.

[0246] OEMEvData encoding:

[0247] OEMEvData3 = (Device << 4) | Function Implements compact coding of device / function numbers.

[0248] SensorNumber = SlotNum + 0x90 establishes the mapping relationship between the physical location of the slot and its logical number.

[0249] Extended fields: Manufacturer-defined error classification and location information can be implemented through OEMEvData1-3.

[0250] EFI_STATUS IpmiOptionRomErrorDevice(OEM_OPTION_ROM_DEVICE_DATA Value,

[0251] UINT8 Bus,UINT8 Device,UINT8 Function);

[0252] IPMI error logging (IpmiOptionRomErrorDevice)

[0253] Send IPMI command:

[0254] Call gIpmiTransport->SendIpmiCommand() to send the SEL record to the IPMI management interface.

[0255] The command code is 0x44 (ADD_SEL_ENTRY), and the channel is 0xA (system event log).

[0256] Return status: EFI_STATUS is returned based on the result of the IPMI command execution.

[0257] The above steps ensure that the IPMI protocol has been initialized. Based on the incoming PCI device information (Bus, Device, Function) and slot number (SlotNum), a SEL record is constructed. The SEL record is sent to the IPMI management interface to record Option ROM error events. The status is returned based on the execution result of the IPMI command. This mechanism effectively records Option ROM error events in the BMC, facilitating remote monitoring and troubleshooting by system administrators.

[0258] It should be understood that the method steps in the embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium. The method can use standard programming techniques. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if necessary, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Furthermore, for this purpose, the program can run on a programmed application-specific integrated circuit (ASIC).

[0259] Furthermore, the procedures described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The procedures described herein (or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions, and may be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The computer program comprises a plurality of instructions executable by one or more processors.

[0260] Furthermore, the method can be implemented in any suitable type of computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or in communication with charged particle tools or other imaging devices, etc. Aspects of the invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it is readable by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein. Furthermore, the machine-readable code, or portions thereof, can be transmitted via wired or wireless networks. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media comprises instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. When programmed according to the methods and techniques described in the invention, the invention may also include the computer itself.

[0261] A computer program can be applied to input data to perform the functions described herein, thereby transforming the input data to generate output data stored in non-volatile memory. The output information can also be applied to one or more output devices, such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including specific visual depictions of physical and tangible objects generated on the display.

[0262] The above description is merely a preferred embodiment of the present invention. The present invention is not limited to the above-described embodiments. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention, as long as they achieve the technical effects of the present invention by the same means, should be included within the scope of protection of the present invention. Within the scope of protection of the present invention, the technical solutions and / or implementation methods can have various modifications and variations.

Claims

1. A control method for loading the PCIe card Option ROM fault tolerance mechanism in a server, characterized in that, include: When the server is detected to be powered on, the process enters the PCI bus enumeration and detection phase for the PCIe card under test. If the configuration space information of the currently enumerated PCIe card is different from the content of the PCIe card linked list, the current PCIe card's Option ROM program is loaded into memory through the UEFI firmware's LoadImage() service, and EFI_IMAGE_HANDLE information is generated. The configuration space information of the current PCIe card's Option ROM program in memory is recorded through the EFI_IMAGE_HANDLE information. Based on the configuration space information of the currently enumerated PCIe card, a new node is constructed and inserted into the PCIe card Option ROM linked list. The BIOS StartingImage() service is called and combined with the EFI_IMAGE_HANDLE information to transfer control to the PCIe card Option ROM program that has been loaded into memory and execute PCIe card hardware initialization. Check the execution status of the Option ROM program of the current PCIe card. If the Option ROM program of the PCIe card is executing normally, delete the relevant information of the current PCIe card stored in the non-volatile memory area, skip the detection of the current PCIe card, and continue to enumerate the next PCIe card to be tested.

2. The control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to claim 1, characterized in that, The enumeration and detection process for the PCIe card under test entering the PCI bus includes: The BIOS reads from the non-volatile memory area and constructs a list of PCIe cards that need to be skipped. The contents of the PCIe card list include the manufacturer ID, device ID, PCIe slot number and node information of several PCIe cards. The BIOS traverses the PCIe card linked list and performs a consistency comparison with the configuration space information of the currently enumerated PCIe card. The configuration space information includes the manufacturer ID, device ID, PCIe slot number, and node information of the currently enumerated PCIe card. If the configuration space information of the currently enumerated PCIe card is the same as the content of the PCIe card linked list, the configuration space information of the currently enumerated PCIe card is reported to the BMC through the IPMI interface, and the currently enumerated PCIe card is recorded as an abnormal device card in the log file. The abnormal device card is skipped, and the next PCIe card is enumerated.

3. The control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to claim 2, characterized in that, Also includes: The cached information generated during the enumeration and detection of the PCI bus on the PCIE card under test is stored in the non-volatile storage area. When it is detected that the Option ROM program of the currently enumerated PCIe card is in a crash state, a restart command is triggered to restart the server; Once the server restarts, it retrieves the cached information from the non-volatile storage area and re-enters the PCI bus enumeration and detection phase for the PCIe card under test.

4. The control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to claim 2, characterized in that, The step of constructing a new node based on the configuration space information of the currently enumerated PCIe card and inserting the new node into the PCIe card Option ROM linked list includes: The structure of the PCIe card OptionROM linked list is constructed using the configuration space information, linked list nodes, and linked list head pointer of the currently enumerated PCIe card. The structure of the PCIe card Option ROM linked list is initialized by initializing the head pointer of the linked list; Perform a data deduplication check on the PCIe card Option ROM linked list. Traverse the PCIe card Option ROM linked list and call the ContainsValue() function to compare all fields of the data in the configuration space of the currently enumerated PCIe card. If a match is found, return an error status. Based on the configuration space information of the currently enumerated PCIe cards, call AllocatePool() to allocate memory space to create a new node. If the allocation fails, return an error status and copy the Value field value of the currently enumerated PCIe cards to the Data structure of the new node. The Data structure of the new node is inserted into the PCIe card Option ROM linked list using the head insertion method. The Next pointer of the new node is set to point to the original head node. The head pointer of the linked list is updated, and a success status is returned.

5. The control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to claim 4, characterized in that, Also includes: The validity of the PCIe card Option ROM linked list is verified by judging the validity of the linked list head pointer. If the linked list head pointer is invalid, an error status is returned. Starting from the original node, check the Data structure of each node one by one. If all field values ​​of the Data structure of a certain node are completely consistent with the field values ​​of the Value of the currently enumerated PCIe card, return the correct status. If no matching item is found after traversing the PCIe card Option ROM linked list, an error status is returned.

6. The control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to claim 4, characterized in that, Also includes: Check if the parameter of the PCIe card Option ROM linked list is NULL. If it is NULL, return the EFI_INVALID_PARAMETER error code. Call the GetListSize() function to obtain the number of nodes in the PCIe card Option ROM linked list and calculate the total storage size; Allocate a temporary buffer, traverse the PCIe card Option ROM linked list and write the Data structure of each node into the temporary buffer in sequence. If memory allocation fails, return the error code EFI_OUT_OF_RESOURCES. Call the gRT->SetVariable() interface to store data with UEFI variable names and globally unique identifiers. The variable is non-volatile and can be accessed during both the service startup phase and the runtime phase. If memory allocation is successful, release the temporary buffer memory and return a success status.

7. The control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to claim 2, characterized in that, The BIOS traverses the PCIe card linked list and performs a consistency comparison with the configuration space information of the currently enumerated PCIe card, including: The PCI bus driver installs an EFI_PCI_IO_PROTOCOL interface for each PCI controller. The EFI_PCI_IO_PROTOCOL interface provides a Pci.Read function, through which a pointer to EFI_PCI_IO_PROTOCOL is used to specify the width of the read operation, set the size of the read data, and the starting address of the buffer where the read data is stored; Based on the pointer to EFI_PCI_IO_PROTOCOL, the width of the read operation is specified, the size of the read data is set, and the starting address of the buffer where the read data is stored is read, the configuration space information of the currently enumerated PCIe card is read, including the manufacturer ID, device ID, PCIe slot number, and node information. The manufacturer ID, device ID, PCIe slot number, and node information of the currently enumerated PCIe card are compared with the manufacturer ID, device ID, PCIe slot number, and node information of each PCIe card stored in the PCIe card linked list. If the vendor ID, device ID, PCIe slot number, and node information of the currently enumerated PCIe card are the same as the information in the PCIe card linked list, it indicates that the vendor ID, device ID, PCIe slot number, and node information of the currently enumerated PCIe card already exist in the non-volatile storage area, and the Option ROM loading process of the currently enumerated card is skipped.

8. The control method for loading the PCIe card Option ROM fault tolerance mechanism in a server according to claim 2, characterized in that, The step of reporting the configuration space information of the currently enumerated PCIe card to the BMC via the IPMI interface and recording the currently enumerated PCIe card as an abnormal device card in the log file includes: Call the LocateProtocol() service of the UEFI firmware to obtain the IPMI protocol handle; Create an EFI_SEL_RECORD_DATA structure and populate the relevant fields of the EFI_SEL_RECORD_DATA structure based on the vendor ID, device ID, PCIe slot number, and node information of the currently enumerated PCIe cards to build a log file; The gIpmiTransport->SendIpmiCommand() function is called to send the constructed log file to the IPMI interface, and the configuration space information of the abnormal PCIe card recorded in the log file is reported to the BMC through the IPMI interface.

9. A computer device comprising a memory and a processor, characterized in that, When the processor executes a computer program stored in the memory, it performs the method as described in any one of claims 1 to 8.

10. A computer-readable storage medium having program instructions stored thereon, characterized in that, When the program instructions are executed by the processor, they perform the method as described in any one of claims 1 to 8.

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