A server link structure, a method for determining a silk print of an external device, and a server

Abstract

The application discloses a server link structure, a silk print determination method of an external device and a server, and relates to the technical field of computers. The server link structure comprises a mainboard and a downlink board card; in response to the type of the downlink board card comprising an expansion card, a first signal path is selected to perform signal transmission between a processor and a gating module. Through the server link structure, the silk print determination method of the external device and the server provided by the embodiments of the application, the VPP I 2 C signal path is multiplexed between the mainboard and the downlink board card, the number of required pins of the interlayer card input / output connector on the mainboard is effectively reduced, the pin number pressure of the interlayer card input / output connector is relieved, the transmission of bus signals and management signals is supported, through the silk print determination method, the silk print contrast relationship of the expansion card slot can be accurately and flexibly determined according to the external device carried by the expansion card, and the development cost of the expansion card is reduced.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a server link structure, a method for determining the silkscreen of external devices, and a server. Background Technology

[0002] Expansion cards are crucial components in servers, enabling the addition of more external devices. Typically, server motherboards connect expansion cards via MCIO (Mezzanine Card Input / Output). However, with the continuous advancement of server technology, the pin count of the MCIO connector is insufficient to meet the bus and sideband signals supported by the PCIe (Peripheral Component Interconnect express) 6.0 protocol, necessitating measures to alleviate the pin load on the MCIO connector. Summary of the Invention

[0003] This application provides a server link structure, a method for determining the silkscreen of external devices, and a server, which at least solves the problem of scarce MCIO pin resources on the server motherboard.

[0004] In a first aspect, this application provides a server link structure, including a motherboard and a downlink board;

[0005] The motherboard is equipped with a gating module, a first switching module, a management module, and a processor;

[0006] The processor is connected to the gating module, the gating module is connected to the first switching module, and the first switching module is connected to the downlink board via a serial bus to transmit serial signals.

[0007] The first switching module has several expansion ports. The first switching module determines the communication port among the several expansion ports, so that the motherboard can form a communication link with the downlink board through the communication port and the serial bus.

[0008] If the downlink board type includes an expansion card, then the first signal path is selected for signal transmission between the processor and the gating module;

[0009] The expansion card is equipped with an expansion device module and a second switching module;

[0010] The expansion device module receives signals via a serial bus and transmits the signals to the management module via the second switching module.

[0011] Secondly, this application also provides a method for determining the silkscreen print of an external device, applied to the server link structure described in the first aspect, comprising:

[0012] If the downlink card in the server link structure is identified as an expansion card, the system switches to the first signal path to transmit the master device signal.

[0013] The master device address and the virtual pin port address are output sequentially to the first expansion device in the expansion device module;

[0014] The controller obtains the output master device address, virtual pin port address, and device asset information, and binds the master device address, virtual pin port address, and device asset information to obtain the silkscreen information corresponding to the slot of the first expansion device.

[0015] Thirdly, this application also provides a server, including the server link structure described in the first aspect, wherein when the downlink card is an expansion card, the motherboard is configured to perform:

[0016] If the downlink card in the server link structure is identified as an expansion card, the system switches to the first signal path to transmit the master device signal.

[0017] The master device address and the virtual pin port address are output sequentially to the first expansion device in the expansion device module;

[0018] The controller obtains the output master device address, virtual pin port address, and device asset information, and binds the master device address, virtual pin port address, and device asset information to obtain the silkscreen information corresponding to the slot of the first expansion device.

[0019] The beneficial effects of the technical solution provided in this application embodiment are: by implementing the server link structure, external device silkscreen determination method and server provided in this application embodiment, VPPI is multiplexed between the motherboard and the downlink board (expansion card or backplane). 2 The C signal path effectively reduces the number of pins required for the mezzanine card input / output connectors on the motherboard, alleviating the pin count pressure of the mezzanine card input / output connectors to support the transmission of bus signals and management signals. Through the silkscreen identification method for external devices, the silkscreen correspondence of the expansion card slot can be accurately and flexibly determined according to the external devices mounted on the expansion card, reducing the development cost of the expansion card. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a typical server hardware architecture;

[0022] Figure 2 This is a schematic diagram of a server link structure provided in an embodiment of this application;

[0023] Figure 3 This is a schematic diagram of the backplate structure provided in an embodiment of this application;

[0024] Figure 4 This is a schematic diagram of the gating module structure provided in an embodiment of this application;

[0025] Figure 5 This is a schematic diagram of a gating module including a repeater provided in an embodiment of this application;

[0026] Figure 6 This is a schematic diagram of the structure of the first switching module provided in an embodiment of this application;

[0027] Figure 7 This is a schematic diagram of the management module structure provided in an embodiment of this application;

[0028] Figure 8 This is a schematic diagram of the extended device module structure provided in the embodiments of this application;

[0029] Figure 9 This is a schematic diagram of the overall server link provided in the embodiments of this application;

[0030] Figure 10 This is a schematic diagram of a method for determining the screen printing of an external device provided in an embodiment of this application;

[0031] Figure 11 This is a schematic diagram of the complete process for confirming screen printing provided in the embodiments of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The numbers in the accompanying drawings are only used to distinguish individual functional parts or modules and do not indicate logical relationships between parts or modules. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the term encompasses the element or object listed following the term and its equivalents, without excluding other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. “Above,” “below,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0034] The various embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components having substantially the same or similar structure and function, and repeated descriptions of them will be omitted.

[0035] In server hardware architecture, two common methods are used to overcome the limitation of MCIO pin count. One method is to move all CPU (Central Processing Unit) and VPP (Virtual Pin Port) address signals to the downstream board. Signals are no longer transmitted from the motherboard's MCIO. The downstream board fixes the CPU and VPP addresses internally using pull-up and pull-down switches according to the connection configuration in the shipping configuration. The Baseboard Management Controller (BMC) and Basic Input Output System (BIOS) can still communicate via I / O pins. 2The C (Inter-Integrated Circuit) bus is used to identify the silkscreen of the external device connected to the current server. This reduces the versatility of the expansion card and requires increasing the number of development boards depending on the configuration. Secondly, the Complex Programmable Logic Device (CPLD) on the motherboard outputs a presence signal to each MCIO interface. At the same time, a controller (e.g., Microcontroller Unit, MCU) is set up on the expansion card. The controller parses the CPU and VPP address signals in the presence signal. This requires a controller on each expansion card. The controller communicates with the upstream motherboard to determine the source of the high-speed signal. However, setting the controller on the expansion card increases the manufacturing cost of the expansion card. Moreover, each MCIO interface requires the CPLD on the motherboard to output a sideband signal, which will cause a shortage of logic resources of the CPLD on the motherboard.

[0036] VPP I 2 C, as a low-speed bus signal path, is primarily used for handling PCIe device hot-plug events and managing NVMe (Non-Volatile Memory Express) devices. Typically, each MCIO interface on the motherboard is associated with this NVMe interface. 2 The C signal path is connected to ensure that when the downstream card type is a backplane, the system can effectively manage storage devices such as hard drives through this signal path. However, when the downstream card type is an expansion card, this VPP I... 2 The C signal path is idle; meanwhile, CPU I 2 C signal and BMC I 2 The C signal passes through an I 2 The C arbitration device is integrated onto the same hardware circuit and connected to the expansion card via a connector, such as... Figure 1 As shown.

[0037] In existing technologies, increasing the number of MCIO pins on a server motherboard can lead to decreased expandability, increased cost, and a shortage of logic resources for complex programmable logic devices on the motherboard. This is addressed by utilizing the idle VPP I when the downlink card type is an expansion card. 2 Regarding the C signal path, this application provides the following implementation method:

[0038] In some embodiments, such as Figure 2 As shown, a server link structure includes: a motherboard 100 and a downlink board;

[0039] The motherboard 100 is equipped with a gating module 110, a first switching module 120, a management module 130, and a processor 140;

[0040] The processor 140 is connected to the gating module 110, the gating module 110 is connected to the first switching module 120, and the first switching module 120 is connected to the downlink board via a serial bus to transmit serial signals.

[0041] The first switching module 120 has several expansion ports 120a. The first switching module 120 determines a communication port among the several expansion ports 120a, so that the motherboard 100 forms a communication link with the downlink board through the communication port and the serial bus.

[0042] In response to the downlink board type including expansion card 200, the first signal path is selected for signal transmission between processor 140 and gating module 110;

[0043] The expansion card 200 is equipped with an expansion device module 210 and a second switching module 220;

[0044] The expansion device module 210 receives signals via a serial bus and transmits the signals to the management module 130 via the second switching module 220.

[0045] A serial bus is a bus used to transmit serial signals. Schematic illustration uses VPP I. 2 The C-bus connects the first switching module 120 to the downlink board.

[0046] The processor can be a central processing unit. The gating module selects whether to use the first signal path or the second signal path to transmit signals between the processor and the gating module, depending on the type of the downlink board.

[0047] The first signal path is used to transmit CPU I. 2 C signal; the second signal path is used to transmit VPP I. 2 C signal.

[0048] Several expansion ports of the first switching module are connected to corresponding MCIO connectors. The communication port is determined according to the selection signal, and the MCIO connector connected to the communication port will be connected to the link.

[0049] VPP I is used for multiplexing between the motherboard and the downlink board. 2 In the C signal path, when the downlink board is an expansion card, the first signal path is selected for signal transmission between the processor and the gating module. This effectively utilizes the idle VPP I when the downlink board is an expansion card. 2 The C signal path is used to alleviate the pin count pressure of the MCIO connector.

[0050] like Figure 3 As shown, in response to the type of downlink board also including a backplane, a second signal path is selected for signal transmission between the processor 140 and the gating module 110;

[0051] The back panel 300 is equipped with a hard drive 310 and a hard drive controller 320;

[0052] Hard disk 310 is connected to hard disk controller 320;

[0053] The hard disk controller 320 generates a hot-plug signal based on changes in the presence signal sent by the hard disk 310, and transmits it to the motherboard 100 via the serial bus. The presence status of the hard disk on the backplane can be monitored via the serial bus.

[0054] like Figure 4 As shown, the processor 140 has: a processor first port 140a and a processor second port 140b;

[0055] The gating module 110 includes: a multiplexer 112 and a signal setting unit 113;

[0056] The multiplexer 112 has a first port 112a, a second port 112b, a third port 112c, and a channel selection port 112d;

[0057] The processor's first port 140a is connected to the multiplexer's first port 112a, serving as the first signal path;

[0058] The processor's second port 140b is connected to the multiplexer's second port 112b as a second signal path;

[0059] The channel selection port 112d is connected to the signal setting unit 113 and is used to receive the channel selection signal from the signal setting unit 113. Based on the channel selection signal, it selects the signal transmission link to be composed of the first port 112a and the third port 112c of the multiplexer, or the signal transmission link to be composed of the second port 112b and the third port 112c of the multiplexer.

[0060] The signal setting unit 113 is used to acquire the type signal of the downlink board and generate a channel selection signal based on the type signal of the downlink board.

[0061] The signal setting unit can be a CPLD. The CPLD acquires the downlink board type signal, generates a channel selection signal, and sends it to the multiplexer, enabling the multiplexer to access the signal channel indicated by the channel selection signal. The downlink board type signal can be configured with high and low levels corresponding to the backplane and expansion card, respectively, to distinguish the board type. The specific correspondence method is not limited in this application. The type signal can be implemented by setting a pull-down circuit. For example, if the expansion card has a pull-down circuit, when the expansion card is connected to the link, the downlink board type signal is pulled down to a low level; while no pull-down setting is made on the backplane, so that when the backplane is connected to the link, the downlink board type signal remains at a high level. This method distinguishes the type of the downlink board.

[0062] Preferably, such as Figure 5 As shown, the gating module 110 also includes: a first repeater 114 and a second repeater 115;

[0063] The first repeater 114 is connected between the processor first port 140a and the multiplexer first port 112a to improve the signal transmission capability between the processor first port 140a and the multiplexer first port 112a.

[0064] The second repeater 115 is connected between the processor's second port 140b and the multiplexer's second port 112b to improve the signal transmission capability between the processor's second port 140b and the multiplexer's second port 112b.

[0065] By setting up a first repeater and a second repeater, the signal quality between the processor's first port and the multiplexer's first port, as well as between the processor's second port and the multiplexer's second port, is enhanced, enabling long-distance transmission of the corresponding signals.

[0066] like Figure 6 As shown, the first switching module 120 includes: a first switching device 121 and several multi-channel input / output interfaces 122;

[0067] The first switching device 121 has a first switching device first port 121a and a plurality of first switching device second ports 121b;

[0068] Several first switching devices have second ports 121b connected to several multi-channel input / output interfaces 122 in a one-to-one correspondence, and several multi-channel input / output interfaces 122 are used as several expansion ports 120a in a one-to-one correspondence.

[0069] like Figure 7 As shown, the management module 130 includes: a controller 131 and a second switching device 132;

[0070] Controller 131 has controller signal port 131a;

[0071] The second switching device 132 has a second switching device first port 132a and a plurality of second switching device second ports 132b;

[0072] The controller signal port 131a is connected to the first port 132a of the second switching device;

[0073] The second switching device 132 determines a communication port among a plurality of second switching device second ports 132b, so that the controller signal port 131a and the communication port form a communication link.

[0074] The controller is preferably a baseboard management controller.

[0075] Typically, the CPU and BMC do not communicate via a direct connection. This is because the CPU and BMC have different power domains, different clock domains, incompatible communication protocols, unreliable physical connections, and require security isolation.

[0076] The difference in power domains is: CPU I 2 The C bus relies on the main power supply, while the BMC can operate in standby mode. When the CPU is powered off, the CPU I... 2 The C bus is powered off and communication is impossible.

[0077] The difference in clock domains is: CPU I 2 C is driven by the CPU clock, BMC I 2 C is driven by the BMC's own crystal oscillator (usually 32.768MHz or 25MHz). The two clocks are not synchronized and cannot be directly bridged.

[0078] Therefore, the expansion device module on the expansion card is needed as a "transferrer" to transmit information such as the CPU address to the BMC.

[0079] like Figure 8 As shown, the expansion device module 210 is configured and connected to a plurality of expansion ports 120a in a one-to-one correspondence. Each expansion device module 210 includes: a first expansion device 211 and a second expansion device 212.

[0080] The first expansion device 211 is connected to the second expansion device 212. The first expansion device 211 is also connected to the corresponding expansion port 120a, which is used to transmit the address signal received by the corresponding expansion port 120a to the second expansion device 212.

[0081] The second expansion device 212 is used to transmit the address signal received by the first expansion device 211 to the second switching module 220.

[0082] The expansion card 200 also includes several external device slots 230 and a storage module 240;

[0083] The second switching module 220 includes a third switching device 221;

[0084] The third switching device 221 has a third switching device first port 221a and a plurality of third switching device second ports 221b;

[0085] Several third switching devices have second ports 221b for connecting to several external device slots 230 and storage modules 240 in a one-to-one correspondence;

[0086] Storage module 240 stores device asset information of external devices connected to expansion card 200;

[0087] The second port of the third switching device connected to the external device slot 230 is used to obtain the device status of the external device connected to the external device slot;

[0088] The second port of the third switching device connected to the storage module 240 is used to acquire equipment asset information;

[0089] The first port 221a of the third switching device transmits the acquired equipment asset information and equipment status to the management module 130.

[0090] On the expansion card, each slot corresponds to two expansion devices: a first expansion device and a second expansion device. The first expansion device connects to the CPU I / O pin. 2 In C-type communication, the primary device is the CPU, and the output slots correspond to the CPU address and VPP address for high-speed signals. Simultaneously, the bandwidth ID signal corresponding to the input slots is used to identify the bandwidth. The second expansion device connects via BMC I... 2 In C-channel communication, the master device is the BMC. The second expansion device receives the CPU address and VPP address transmitted by the first expansion device and sends the CPU address and VPP address to the BMC. The BMC then parses the source of the high-speed signal for each slot.

[0091] The storage module here typically refers to a Field Replaceable Unit (FRU), used to store board asset information.

[0092] Only one master device is allowed to control either the first or second expansion device. This master device is typically the CPU or BMC. The CPU usually controls the first expansion device for communication, while the BMC controls the second expansion device. Since neither the first nor the second expansion device has signal storage capabilities, the signals received by the CPU are transmitted from the first expansion device to the second expansion device so that the BMC can receive the corresponding signals.

[0093] The overall link between the motherboard and the expansion card is as follows: Figure 2 As shown. The hardware structure and functions of each part of the link have been described above, and will not be repeated here.

[0094] Since the CPU address signal is typically transmitted in parallel using 3 MCIO pins for 3 bits of data, and the VPP address signal is transmitted in parallel using 4 MCIO pins for 4 bits of data, implementing the server link structure described in this application can reduce the number of MCIO connector pins occupied by transmitting the CPU address signal, the number of MCIO connector pins occupied by transmitting the VPP address signal, and the number of MCIO connector pins occupied by transmitting the bandwidth ID signal.

[0095] By implementing the server link structure provided in the embodiments of this application, VP1 is multiplexed between the motherboard and the downlink board. 2 The C-signal path effectively reduces the number of pins required for the mezzanine card's input / output connectors on the motherboard, alleviating the pin count pressure on the mezzanine card's input / output connectors; it also provides pin resources for the transmission of bus signals and management signals. Furthermore, regarding the components used, although two expansion devices are added to each MCIO connector on the expansion card, compared to the switching devices and I / O devices on the motherboard... 2 For C-type arbitration devices, material costs are significantly reduced, saving overall costs.

[0096] In other embodiments, such as Figure 10 As shown, a method for determining the silkscreen print of an external device is applied to the server link structure described above. The method for determining the silkscreen print of an external device includes:

[0097] S100: In response to the identification that the downlink card in the server link structure is an expansion card, the system switches to the first signal path to transmit the master device signal;

[0098] S200: Sequentially output the master device address and the virtual pin port address to the first expansion device in the expansion device module;

[0099] S300: Obtain the output master device address, virtual pin port address and device asset information through the controller, and bind the master device address, virtual pin port address and device asset information to obtain the silkscreen information corresponding to the slot of the first expansion device.

[0100] Specifically, the controller obtains the output master device address, virtual pin port address, and device asset information, including:

[0101] S310: Obtain the master device address transmitted to the first expansion device through the second expansion device;

[0102] S320: Obtain device port information transmitted to the first expansion device through the second expansion device;

[0103] S330: Obtain the front and rear window information of the chassis corresponding to the slot from the storage module;

[0104] S340: Obtain the combination domain information of the slot from the storage module. The combination domain information includes the slot number information that constitutes the combination domain.

[0105] Confirm the complete screen printing process as follows Figure 11 As shown.

[0106] 1. Assemble the server according to the configuration, and power on after confirming that all expansion cards and PCIe devices are in place. Each MCIO has an expansion card presence signal. When the downstream card of the MCIO is an expansion card, the signal is pulled low, and the motherboard CPLD controls the multiplexer to switch the HOST end to CPU I. 2 C communicates; if the MCIO downlink board is connected to the backplane, the motherboard CPLD control multiplexer switches the HOST end to VPP I. 2 C manages the hard drive.

[0107] 2. CPU I 2 C communicates with the first expansion device in the corresponding slot on the expansion card. The control chip outputs the CPU address and VPP address corresponding to the MCIO connector to the second expansion device. The second expansion device reads the bandwidth ID signal on the first expansion device to confirm the bandwidth allocation of the slot.

[0108] 3. BMC I 2 C starts accessing the downlink daughter card, and uses the address and channel of the second switching device to correspond to the front and rear windows and location identifiers of the chassis. For example, LOC PIN0 corresponds to PCIE0, 1, and 2 on the chassis silkscreen; LOC PIN1 corresponds to PCIE3, 4, and 5 on the chassis silkscreen.

[0109] 4. BMC I 2 C opens channel 0 of the third switching device of the expansion card, accesses the storage module, and obtains the asset information of the expansion card, the number of slots, the offset position of the slots, the presence status of PCIe devices, etc., and binds it with the silkscreen on the outside of the chassis.

[0110] 5. BMC I 2 C opens the channel in the third switching device of the expansion card that is connected to the slot, accesses the PCIe device, obtains the BDF (Bus / Device / Function) information of the external device, and forms a binding relationship between the channel of the third switching device and the slot.

[0111] 6. BMC I 2C sequentially accesses the second expansion device of the expansion card, reads the correspondence between the second expansion device and the slot from the storage module, and obtains the high-speed signal source of the slot;

[0112] 7. BMC integrates all the above information and displays the silkscreen information of each PCIe device in the BMC Web management interface. Illustratively, the silkscreen format is: CPUx_PEx_Front and Rear Windows_Chassis Slot Silkscreen.

[0113] External devices refer to PCIe devices.

[0114] Preferably, after obtaining the silkscreen information corresponding to the slot of the first expansion device, the method further includes:

[0115] S410: The controller polls the PCIe devices at preset time intervals. 2 C interface.

[0116] The controller mentioned here typically refers to the substrate management controller. The substrate management controller sends a signal to the BMC I at preset intervals (e.g., 10 seconds). 2 The C bus sequentially controls the second switching device to switch its second port and access the corresponding I... 2 The C interface is used to obtain the communication status of external devices.

[0117] S420: Response to a preset number of consecutive unresponsive external devices. 2 If a C request is received, the corresponding external device is determined to be offline.

[0118] Indicatively, if an external device fails to respond 3 times consecutively... 2 If a C request is received, the external device is determined to be offline. Prioritize issuing an alert on the BMC web interface to indicate that the external device may have been unplugged, has poor contact, or is even damaged.

[0119] S430: In response to reading external device I 2 After processing the C data, the asset information of the corresponding external devices is parsed and compared with historical records.

[0120] The asset information for the corresponding external devices includes: device model, serial number, etc.

[0121] If the asset information of the corresponding external device changes compared to historical records, a notification will be displayed on the BMC Web interface indicating that the external device has been replaced. The asset change will also be recorded to prevent unauthorized device replacement.

[0122] S440: Detects the temperature of external devices; issues an alarm if the temperature of an external device exceeds a preset temperature.

[0123] The temperature of external devices is obtained by reading their temperature registers. If the temperature of an external device exceeds a preset temperature (e.g., 85 degrees Celsius), an alarm is issued on the BMC web interface to prevent damage to the external device due to overheating. Maintenance personnel can then perform tasks such as dust cleaning and fan checks based on the alerts to troubleshoot the overheating issue.

[0124] S450: Obtain the power supply status of external devices and perform power supply status detection for external devices.

[0125] If the power supply current of the external device is read and the power supply current of the external device is 0, but the external device is in place, a power interruption alarm will be triggered.

[0126] If the current of an external device is detected to be much higher than the normal value, an alarm will be triggered for short circuit or overload of the external device.

[0127] If the current of an external device is detected to be much lower than the normal value, an alarm will be issued indicating that the external device is not fully loaded or that the external device is faulty.

[0128] The system prompts you to perform operations such as power configuration troubleshooting and connector contact troubleshooting.

[0129] S460: Obtain the firmware status of external devices and perform firmware status detection on external devices.

[0130] It can quickly identify non-physical faults and guide firmware maintenance.

[0131] Preferably, the alarm information can be displayed via the BMC Web interface. The real-time alarm interface highlights the silkscreen location, external device model, and anomaly type of the corresponding external device.

[0132] Alternatively, it can be sent to the network management system (such as Zabbix, Nagios, etc.) via SNMP Trap (Simple Network Management Protocol Trap).

[0133] Alerts can also be sent to administrators via email. They can also be recorded in the system log via the IPMI Event Log for future reference.

[0134] Once the baseboard management controller confirms in subsequent polls that the anomaly has disappeared, it automatically clears the alarm status on the BMC web interface and records the "alarm recovery" event. This prevents false alarms from persisting for extended periods.

[0135] It should be understood that, although Figure 10The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 10 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0136] By using the silkscreen identification method for external devices, the silkscreen correspondence of the expansion card slot can be accurately and flexibly determined based on the external devices connected to the expansion card, thereby reducing the development cost of the expansion card.

[0137] In other embodiments, a server includes the server link structure described above, comprising:

[0138] Motherboard 100 and downstream circuit boards;

[0139] The motherboard 100 is equipped with a gating module 110, a first switching module 120, a management module 130, and a processor 140;

[0140] The processor 140 is connected to the gating module 110, the gating module 110 is connected to the first switching module 120, and the first switching module 120 is connected to the downlink board via a serial bus to transmit serial signals.

[0141] The first switching module 120 has several expansion ports 120a. The first switching module 120 determines a communication port among the several expansion ports 120a, so that the motherboard 100 forms a communication link with the downlink board through the communication port and the serial bus.

[0142] In response to the downlink board type including expansion card 200, the first signal path is selected for signal transmission between processor 140 and gating module 110;

[0143] The expansion card 200 is equipped with an expansion device module 210 and a second switching module 220;

[0144] The expansion device module 210 receives signals via a serial bus and transmits the signals to the management module 130 via the second switching module 220.

[0145] If the downlink board type also includes a backplane, then a second signal path is selected for signal transmission between the processor 140 and the gating module 110;

[0146] The back panel 300 is equipped with a hard drive 310 and a hard drive controller 320;

[0147] Hard disk 310 is connected to hard disk controller 320;

[0148] The hard disk controller 320 generates a hot-plug signal based on the change in the presence signal sent by the hard disk 310, and transmits it to the motherboard 100 via the serial bus.

[0149] Specifically, the processor 140 has: a processor first port 140a and a processor second port 140b;

[0150] The gating module 110 includes: a multiplexer 112 and a signal setting unit 113;

[0151] The multiplexer 112 has a first port 112a, a second port 112b, a third port 112c, and a channel selection port 112d;

[0152] The processor's first port 140a is connected to the multiplexer's first port 112a, serving as the first signal path;

[0153] The processor's second port 140b is connected to the multiplexer's second port 112b as a second signal path;

[0154] The channel selection port 112d is connected to the signal setting unit 113 and is used to receive the channel selection signal from the signal setting unit 113. Based on the channel selection signal, it selects the signal transmission link to be composed of the first port 112a and the third port 112c of the multiplexer, or the signal transmission link to be composed of the second port 112b and the third port 112c of the multiplexer.

[0155] The signal setting unit 113 is used to acquire the type signal of the downlink board and generate a channel selection signal based on the type signal of the downlink board.

[0156] Preferably, the gating module 110 further includes: a first repeater 114 and a second repeater 115;

[0157] The first repeater 114 is connected between the processor first port 140a and the multiplexer first port 112a to improve the signal transmission capability between the processor first port 140a and the multiplexer first port 112a.

[0158] The second repeater 115 is connected between the processor's second port 140b and the multiplexer's second port 112b to improve the signal transmission capability between the processor's second port 140b and the multiplexer's second port 112b.

[0159] Specifically, the first switching module 120 includes: a first switching device 121 and a plurality of multi-channel input / output interfaces 122;

[0160] The first switching device 121 has a first switching device first port 121a and a plurality of first switching device second ports 121b;

[0161] Several first switching devices have second ports 121b connected to several multi-channel input / output interfaces 122 in a one-to-one correspondence, and several multi-channel input / output interfaces 122 are used as several expansion ports 120a in a one-to-one correspondence.

[0162] Specifically, the management module 130 includes: a controller 131 and a second switching device 132;

[0163] Controller 131 has controller signal port 131a;

[0164] The second switching device 132 has a second switching device first port 132a and a plurality of second switching device second ports 132b;

[0165] The controller signal port 131a is connected to the first port 132a of the second switching device;

[0166] The second switching device 132 determines a communication port among a plurality of second switching device second ports 132b, so that the controller signal port 131a and the communication port form a communication link.

[0167] Specifically, each expansion device module 210 is configured and connected to a plurality of expansion ports 120a in a one-to-one correspondence. Each expansion device module 210 includes: a first expansion device 211 and a second expansion device 212.

[0168] The first expansion device 211 is connected to the second expansion device 212. The first expansion device 211 is also connected to the corresponding expansion port 120a, which is used to transmit the address signal received by the corresponding expansion port 120a to the second expansion device 212.

[0169] The second expansion device 212 is used to transmit the address signal received by the first expansion device 211 to the second switching module 220.

[0170] Specifically, the expansion card 200 also includes several external device slots 230 and a storage module 240;

[0171] The second switching module 220 includes a third switching device 221;

[0172] The third switching device 221 has a third switching device first port 221a and a plurality of third switching device second ports 221b;

[0173] Several third switching devices have second ports 221b for connecting to several external device slots 230 and storage modules 240 in a one-to-one correspondence;

[0174] Storage module 240 stores device asset information of external devices connected to expansion card 200;

[0175] The second port of the third switching device connected to the external device slot 230 is used to obtain the device status of the external device connected to the external device slot;

[0176] The second port of the third switching device connected to the storage module 240 is used to acquire equipment asset information;

[0177] The first port 221a of the third switching device transmits the acquired equipment asset information and equipment status to the management module 130.

[0178] When the downstream card is an expansion card, the motherboard is configured to perform:

[0179] S100: In response to the identification that the downlink card in the server link structure is an expansion card, the system switches to the first signal path to transmit the master device signal;

[0180] S200: Sequentially output the master device address and the virtual pin port address to the first expansion device in the expansion device module;

[0181] S300: Obtain the output master device address, virtual pin port address and device asset information through the controller, and bind the master device address, virtual pin port address and device asset information to obtain the silkscreen information corresponding to the slot of the first expansion device.

[0182] S310: Obtain the master device address transmitted to the first expansion device through the second expansion device;

[0183] S320: Obtain device port information transmitted to the first expansion device through the second expansion device;

[0184] S330: Obtain the front and rear window information of the chassis corresponding to the slot from the storage module;

[0185] S340: Obtain the combination domain information of the slot from the storage module. The combination domain information includes the slot number information that constitutes the combination domain.

[0186] By implementing a server provided in the embodiments of this application, VPPI is multiplexed between the motherboard and the downlink board. 2The C signal path effectively reduces the number of pins required for the mezzanine card input / output connectors on the motherboard, alleviating the pin count pressure of the mezzanine card input / output connectors to support the transmission of bus signals and management signals. Through the silkscreen identification method for external devices, the silkscreen correspondence of the expansion card slot can be accurately and flexibly determined according to the external devices mounted on the expansion card, reducing the development cost of the expansion card.

[0187] The beneficial effects of the technical solution provided in this application embodiment are: by implementing the server link structure, external device silkscreen determination method and server provided in this application embodiment, VPPI is multiplexed between the motherboard and the downlink board (expansion card or backplane). 2 The C-signal path effectively reduces the number of pins required for the mezzanine card's input / output connectors on the motherboard, alleviating the pin count pressure on the mezzanine card's input / output connectors to support the transmission of bus signals and management signals. The external device silkscreen identification method allows for accurate and flexible determination of the silkscreen correspondence between the expansion card slots based on the external devices connected to the expansion card, reducing expansion card development costs. Furthermore, regarding the components used, although the expansion card adds two expansion devices for each MCIO connector, compared to the switching devices and I / O devices on the motherboard... 2 For C-type arbitration devices, material costs are significantly reduced, saving overall costs.

[0188] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0189] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as steps controlled by a computer software program. For example, embodiments of this application include a computer program product comprising a computer program loaded on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from memory, or installed from ROM. When the computer program is executed by an external processor, it performs the functions defined in the methods of embodiments of this application.

[0190] It should be noted that the computer-readable medium in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the embodiments of this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the embodiments of this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (Radio Frequency), etc., or any suitable combination thereof.

[0191] The aforementioned computer-readable medium may be included in the aforementioned server; or it may exist independently and not assembled into the server. The aforementioned computer-readable medium carries one or more programs that, when executed by the server, cause the server to: in response to detecting that the peripheral mode of the terminal is not activated, acquire the frame rate of the application on the terminal; when the frame rate meets the screen-off condition, determine whether the user is acquiring the terminal's screen information; and in response to the determination that the user is not acquiring the terminal's screen information, control the screen to enter an immediate dimming mode.

[0192] Computer program code for performing the operations of the embodiments of this application can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages—such as Java, Smalltalk, and C++—and conventional procedural programming languages—such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0193] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0194] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

[0195] The foregoing has provided a detailed description of the server link structure, the method for determining the silkscreen of external devices, and the server provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. These embodiments are merely preferred embodiments of this application, used to help understand the method and its core ideas, and are not intended to limit this application. It should be noted that for those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application without departing from its principles are also within the protection scope of this application.

Claims

1. A server link structure, characterized in that, Includes the motherboard (100) and the downlink board; The motherboard (100) is provided with a gating module (110), a first switching module (120), a management module (130) and a processor (140). The processor (140) is connected to the gating module (110), the gating module (110) is connected to the first switching module (120), and the first switching module (120) is connected to the downlink board via a serial bus to transmit serial signals; The first switching module (120) has a plurality of expansion ports (120a). The first switching module (120) determines a communication port among the plurality of expansion ports (120a) so that the motherboard (100) forms a communication link with the downlink board through the communication port and the serial bus. In response to the downlink board type including expansion card (200), a first signal path is selected for signal transmission between the processor (140) and the gating module (110); The expansion card (200) is provided with an expansion device module (210) and a second switching module (220). The extended device module (210) receives signals through the serial bus and transmits the signals to the management module (130) through the second switching module (220). The management module (130) includes a controller (131) and a second switching device (132). The controller (131) has a controller signal port (131a); The second switching device (132) has a second switching device first port (132a) and a plurality of second switching device second ports (132b). The controller signal port (131a) is connected to the first port (132a) of the second switching device; The second switching device (132) determines a communication port among the second ports (132b) of the plurality of second switching devices, so that the controller signal port (131a) and the communication port form a communication link; The expansion card (200) also includes several external device slots (230) and a storage module (240). The second switching module (220) includes a third switching device (221); The third switching device (221) has a third switching device first port (221a) and a plurality of third switching device second ports (221b). The second ports (221b) of the plurality of third switching devices are used to connect one-to-one with the plurality of external device slots (230) and the storage module (240). The storage module (240) stores device asset information of external devices connected to the expansion card (200); The second port of the third switching device connected to the external device slot (230) is used to obtain the device status of the external device connected to the external device slot; The second port of the third switching device connected to the storage module (240) is used to acquire the equipment asset information; The first port (221a) of the third switching device transmits the acquired equipment asset information and equipment status to the management module (130). The management module (130) obtains signals from the processor (140) through the expansion device module (210).

2. The server link structure according to claim 1, characterized in that, In response to the downlink board type also including a backplane, a second signal path is selected for signal transmission between the processor (140) and the gating module (110); The back panel (300) is provided with a hard disk (310) and a hard disk controller (320). The hard disk (310) is connected to the hard disk controller (320); The hard disk controller (320) generates a hot-plug signal based on the change in the presence signal sent by the hard disk (310) and transmits it to the motherboard (100) via the serial bus.

3. The server link structure according to claim 1, characterized in that, The processor (140) has: a processor first port (140a) and a processor second port (140b). The gating module (110) includes: a multiplexer (112) and a signal setting unit (113); The multiplexer (112) has a first port (112a), a second port (112b), a third port (112c), and a channel selection port (112d). The processor's first port (140a) is connected to the multiplexer's first port (112a) as a first signal path; The processor's second port (140b) is connected to the multiplexer's second port (112b) as a second signal path; The channel selection port (112d) is connected to the signal setting unit (113) and is used to receive the channel selection signal from the signal setting unit (113), and select, according to the channel selection signal, whether the signal transmission link is composed of the first port (112a) of the multiplexer and the third port (112c) of the multiplexer, or the signal transmission link is composed of the second port (112b) of the multiplexer and the third port (112c) of the multiplexer; The signal setting unit (113) is used to acquire the type signal of the downlink board and generate the channel selection signal according to the type signal of the downlink board.

4. The server link structure according to claim 3, characterized in that, The gating module (110) further includes: a first repeater (114) and a second repeater (115); The first repeater (114) is connected between the processor first port (140a) and the multiplexer first port (112a) to improve the signal transmission capability between the processor first port (140a) and the multiplexer first port (112a); The second repeater (115) is connected between the processor second port (140b) and the multiplexer second port (112b) to improve the signal transmission capability between the processor second port (140b) and the multiplexer second port (112b).

5. The server link structure according to claim 1, characterized in that, The first switching module (120) includes: a first switching device (121) and several multi-channel input / output interfaces (122); The first switching device (121) has a first switching device first port (121a) and a plurality of first switching device second ports (121b). The second ports (121b) of the plurality of first switching devices are connected one-to-one with the plurality of multi-channel input / output interfaces (122), and the plurality of multi-channel input / output interfaces (122) are used one-to-one as the plurality of expansion ports (120a).

6. The server link structure according to claim 1, characterized in that, The expansion device module (210) is configured and connected to the plurality of expansion ports (120a) one by one. Each expansion device module (210) includes: a first expansion device (211) and a second expansion device (212). The first expansion device (211) is connected to the second expansion device (212), and the first expansion device (211) is also connected to the corresponding expansion port (120a) for transmitting the address signal received by the corresponding expansion port (120a) to the second expansion device (212). The second expansion device (212) is used to transmit the address signal received by the first expansion device (211) to the second switching module (220).

7. A method for determining the screen printing on an external device, characterized in that, Applied to the server link structure according to any one of claims 1-6, comprising: In response to the identification that the downlink card in the server link structure is an expansion card, the system switches to the first signal path to transmit the master device signal; The master device address and the virtual pin port address are output sequentially to the first expansion device in the expansion device module; The controller obtains the output master device address, virtual pin port address, and device asset information, and binds the master device address, the virtual pin port address, and the device asset information to obtain the silkscreen information corresponding to the slot of the first expansion device.

8. A server, characterized in that, Including the server link structure according to any one of claims 1-6, where the downlink card is an expansion card, the motherboard is configured to perform: In response to the identification that the downlink card in the server link structure is an expansion card, the system switches to the first signal path to transmit the master device signal; The master device address and the virtual pin port address are output sequentially to the first expansion device in the expansion device module; The controller obtains the output master device address, virtual pin port address, and device asset information, and binds the master device address, the virtual pin port address, and the device asset information to obtain the silkscreen information corresponding to the slot of the first expansion device.

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