Simulation integration method and system of FPGA communication module

Abstract

The application provides a simulation integration method and system of FPGA communication module, comprising the following steps: step S1: converting IP source code of the FPGA communication module into FPGA simulation module code in C++ language; step S2: based on the FPGA simulation module code, performing interface adaptation on the system bus access part of the full-digital simulation system for accessing the FPGA communication module; step S3: introducing another module identical to the FPGA communication module as a symmetric module, and cross-connecting the symmetric module and the FPGA communication module in a transceiving interface; and step S4: on the communication data receiving side of the symmetric module, performing interface adaptation according to the bus access mode in the full-digital simulation system. The FPGA module simulation of the application is based on the source code of the FPGA, thereby improving the accuracy of the FPGA simulation behavior.

Description

Technical Field

[0001] This invention relates to the field of all-digital simulation technology, specifically to a simulation integration method and system for an FPGA communication module, and more particularly to a simulation integration method and system for an FPGA communication module in an all-digital simulation system. Background Technology

[0002] FPGA is a programmable logic device widely used in various scenarios requiring high performance, low latency, and flexible hardware design. In recent years, it has seen widespread application in aerospace, defense, industry, and communications.

[0003] Because the application of FPGAs in defense and other military weaponry places stringent requirements on the correctness and reliability of FPGA software, thorough simulation testing is necessary before delivery. The primary goal of simulation testing is to verify whether the developed program code meets the design expectations based on the application's functional requirements. Simulation testing plays an increasingly important role in FPGA software design.

[0004] FPGA simulation is typically divided into multiple levels, each with different focuses and levels of detail. Based on the level of detail and objectives, FPGA simulation can be categorized into the following main levels:

[0005] a. System-level simulation: Verifies the high-level functions of the design, but does not involve specific hardware implementation details;

[0006] b. Gate-level simulation: Verifies whether the synthesized netlist meets the expected function. It includes gate-level delay information, but does not include detailed timing information after placement and routing. It can discover some timing-related issues and is closer to the actual hardware than behavioral simulation.

[0007] c. Timing-level simulation: This simulates whether the design after placement and routing meets timing requirements. It includes detailed timing information to ensure that the design can work correctly on actual hardware. It is closest to the behavior of actual hardware and can detect all timing-related issues. However, it is the slowest simulation and is more complex to set up.

[0008] The current virtualization simulation technology is developing rapidly in the CPU and MCU fields. In order to achieve better simulation results, there are attempts to combine FPGA simulation with virtualization technology. However, when FPGA simulation is combined with other virtualization technologies, it is necessary to solve the problem of how FPGA simulation can be integrated with the all-digital simulation system. In addition, traditional FPGA simulation only outputs results for level timing, which cannot provide a more intuitive simulation effect.

[0009] Patent document CN118427054A discloses a simulation method for a Tianmai system FC communication daughter card in a fully digital simulation environment, belonging to the field of system simulation technology. The method includes: registering virtual port processing functions in the core layer of the Tianmai operating system's operating system; establishing a register model for the FC communication daughter card and allocating its basic functions and definitions; establishing a simulation driver for the FC communication daughter card, providing access interfaces for basic functions in the simulation driver, and establishing a simulated FC communication daughter card running state machine model; attaching the FC communication daughter card's read / write interface to the virtual port processing functions; registering the FC communication daughter card interface to the operating system in the core layer of the operating system for use by Tianmai system applications; and mapping the FC communication daughter card's external data transmission and reception and register states to the physical machine's operating system. However, this patent document still has the drawback of not providing a more intuitive simulation effect. Summary of the Invention

[0010] In view of the deficiencies in the prior art, the purpose of this invention is to provide a simulation integration method and system for FPGA communication modules.

[0011] The simulation integration method for an FPGA communication module provided by the present invention includes the following steps:

[0012] Step S1: Convert the IP source code of the FPGA communication module into C++ language FPGA simulation module code;

[0013] Step S2: Based on the FPGA simulation module code, perform interface adaptation for the system bus access part of the FPGA communication module in the all-digital simulation system;

[0014] Step S3: Introduce another module that is exactly the same as the FPGA communication module as a symmetrical module, and cross-connect the symmetrical module and the FPGA communication module through the transmit and receive interfaces;

[0015] Step S4: On the communication data receiving side of the symmetrical module, perform interface adaptation according to the bus access method in the all-digital simulation system.

[0016] Preferably, step S1 specifically includes the following steps:

[0017] Step S1.1: Analyze and verify the IP source code of the FPGA communication module, and extract the top-level module interface from the IP source code. The top-level module interface includes the clock and reset interface, the system bus interface, and the communication bus interface.

[0018] Step S1.2: Based on the extracted top-level module interface, convert the IP source code of the FPGA communication module into FPGA simulation module code in C++ language. The FPGA simulation module code in C++ language provides an FPGA simulation model class containing all top-level module interfaces.

[0019] Step S1.3: Compile the C++ language FPGA simulation module code to generate the static link library of the FPGA communication module.

[0020] Preferably, step S2 specifically includes the following steps:

[0021] Step S2.1: Instantiate the FPGA communication module from step S1.2;

[0022] Step S2.2: For the instantiated FPGA communication module, define the data of the bus interface signals. The data of the bus interface signals includes the clock and reset interface, system bus interface and communication bus interface in step S1.1.

[0023] Step S2.3: Change the data of the bus interface signal according to the operation instructions of the bus interface type of the all-digital simulation system, simulate the read and write operation of the bus, and complete the interface adaptation of the system bus access part.

[0024] Preferably, step S3 specifically includes the following steps:

[0025] Step S3.1: Instantiate a module that is exactly the same as the FPGA communication module in step S2.1, as a symmetrical module;

[0026] Step S3.2: Connect the data transmitting end of the FPGA communication module in step S2.1 to the data receiving end of the symmetric module in step S3.1, and at the same time connect the data receiving end of the FPGA communication module in step S2.1 to the data transmitting end of the symmetric module in step S3.1 to realize the cross connection of the two transceiver interfaces.

[0027] Preferably, step S4 specifically includes the following steps:

[0028] Step S4.1: After the bus write operation is completed on the FPGA communication module in step S2.3, the clock is delayed for a preset time. Then, according to the operation instructions of the bus interface type of the all-digital simulation system, the data bus interface part of the symmetric module in step S3.1 is read. The operation data corresponding to the bus write operation is obtained through the read operation, and the interface adaptation related to the write operation on the receiving side of the symmetric module is completed.

[0029] Step S4.2: After performing a write operation on the data bus interface of the symmetric module in step S3.1 according to the operation instructions of the bus interface type of the all-digital simulation system, the clock is delayed for a preset time, and then a read operation is performed on the FPGA communication module in step S2.1 according to the bus access method in step S2.3, thus completing the interface adaptation of the symmetric module receiving side write operation to the corresponding FPGA module read operation.

[0030] This invention also provides a simulation integration system for an FPGA communication module, comprising the following modules:

[0031] Module M1: Converts the IP source code of the FPGA communication module into C++ language FPGA simulation module code;

[0032] Module M2: Based on the FPGA simulation module code, it adapts the interface of the system bus access part that accesses the FPGA communication module in the all-digital simulation system.

[0033] Module M3: Introduce another module that is exactly the same as the FPGA communication module as a symmetrical module, and cross-connect the symmetrical module and the FPGA communication module through the transmit and receive interfaces;

[0034] Module M4: On the communication data receiving side of the symmetrical module, the interface is adapted according to the bus access method in the all-digital simulation system.

[0035] Preferably, module M1 specifically includes the following modules:

[0036] Module M1.1: Analyze and verify the IP source code of the FPGA communication module, and extract the top-level module interface from the IP source code. The top-level module interface includes the clock and reset interface, the system bus interface, and the communication bus interface.

[0037] Module M1.2: Based on the extracted top-level module interface, the IP source code of the FPGA communication module is converted into FPGA simulation module code in C++ language. The FPGA simulation module code in C++ language provides an FPGA simulation model class containing all top-level module interfaces.

[0038] Module M1.3: Compiles the C++ language FPGA simulation module code and generates the static link library for the FPGA communication module;

[0039] Module M2 specifically includes the following modules:

[0040] Module M2.1: Instantiates the FPGA communication module in module M1.2;

[0041] Module M2.2: Defines the bus interface signal data for the instantiated FPGA communication module. The bus interface signal data includes the clock and reset interface, system bus interface, and communication bus interface in module M1.1.

[0042] Module M2.3: Operate the bus interface signal data according to the operation instructions of the bus interface type of the all-digital simulation system, simulate the bus read and write operations, and complete the interface adaptation of the system bus access part.

[0043] Preferably, module M3 specifically includes the following modules:

[0044] Module M3.1: Instantiate a module that is exactly the same as the FPGA communication module in Module M2.1, as a symmetrical module;

[0045] Module M3.2: Connects the data transmitting end of the FPGA communication module in module M2.1 to the data receiving end of the symmetric module in module M3.1, and simultaneously connects the data receiving end of the FPGA communication module in module M2.1 to the data transmitting end of the symmetric module in module M3.1, thereby realizing the cross-connection of the transceiver interfaces of the two.

[0046] Module M4 specifically includes the following modules:

[0047] Module M4.1: After the bus write operation is completed in the FPGA communication module in module M2.3, the clock delay is preset, and then the data bus interface part of the symmetric module in module M3.1 is read according to the operation instructions of the bus interface type of the all-digital simulation system. The operation data corresponding to the bus write operation is obtained through the read operation, and the interface adaptation related to the write operation of the symmetric module receiving side is completed.

[0048] Module M4.2: After performing a write operation on the data bus interface of the symmetric module in Module M3.1 according to the operation instructions of the bus interface type of the all-digital simulation system, the clock is delayed for a preset time, and then a read operation is performed on the FPGA communication module in Module M2.1 according to the bus access method of Module M2.3, thus completing the interface adaptation of the symmetric module receiving side write operation to the corresponding FPGA module read operation.

[0049] The present invention also provides a simulation integration system for an FPGA communication module, comprising: a first simulation bus interface module, a first simulation FPGA communication module, a second simulation FPGA communication module, and a second simulation bus interface module;

[0050] Data transmission occurs between the first simulation bus interface module and the first simulation FPGA communication module, between the first simulation FPGA communication module and the second simulation FPGA communication module, and between the second simulation FPGA communication module and the second simulation bus interface module.

[0051] The first simulated FPGA communication module converts its IP source code into C++ language FPGA simulation module code, and the first simulated bus interface module adapts the interface based on the FPGA simulation module code.

[0052] The second simulated FPGA communication module is the same as the first simulated FPGA communication module, and the second simulated FPGA communication module serves as a symmetrical module to the first simulated FPGA communication module.

[0053] The transceiver interface of the second simulation bus interface module is cross-connected with the transceiver interface of the first simulation bus interface module to achieve interface adaptation of the second simulation bus interface module.

[0054] Preferably, the first simulation bus interface module includes: a simulation CPU access interface, a first clock and reset interface, and a first system bus interface;

[0055] The first simulated FPGA communication module includes: a second clock and reset interface, a second system bus interface, and a first communication bus interface;

[0056] The second simulated FPGA communication module includes: a third clock and reset interface, a third system bus interface, and a second communication bus interface;

[0057] The second simulation bus interface module includes: a fourth clock and reset interface, a fourth system bus interface, and a UI interaction interface;

[0058] The simulated CPU access interface is connected to the simulated CPU, the first clock and reset interface is connected to the second clock and reset interface, and the first system bus interface is connected to the second system bus interface;

[0059] The first communication bus interface is connected to the second communication bus interface;

[0060] The third clock and reset interface is connected to the fourth clock and reset interface, the third system bus interface is connected to the fourth system bus interface, and the UI interaction interface is connected to the UI interaction module.

[0061] Compared with the prior art, the present invention has the following beneficial effects:

[0062] 1. This invention can be combined with other virtualization technologies. Current virtualization simulation technology is developing rapidly in the fields of CPU and MCU. In system-level simulation, since some modules use FPGA logic, it is necessary to solve the problem of how to integrate FPGA simulation with the all-digital simulation system during overall simulation. This invention solves this problem.

[0063] 2. This invention enables more intuitive simulation results of FPGA communication modules. Traditional FPGA simulation only outputs results for level timing. By utilizing the concept of symmetrical modules, this invention can convert the output level timing signals into digital signals that interact with the system, allowing the overall system to use them or allowing users to more intuitively view the simulation results.

[0064] 3. This invention relates to a simulation method for integrated system verification of components such as MCU and FPGA in a fully digital simulation system. In this method, the FPGA simulation uses system-level behavioral simulation. By integrating with a simulation MCU model with running real firmware, the simulation operation of the entire system can be realized. Attached Figure Description

[0065] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0066] Figure 1 This is a schematic diagram illustrating the integration method of the FPGA communication module in the simulation system.

[0067] Figure 2 This is a schematic diagram of the simulation integration method for the FPGA communication module in a fully digital simulation system. Detailed Implementation

[0068] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0069] Example 1

[0070] like Figure 1 and Figure 2 As shown, this embodiment provides a simulation integration method for an FPGA communication module, including the following steps:

[0071] Step S1: Convert the IP source code of the FPGA communication module into C++ language FPGA simulation module code;

[0072] Step S1 specifically includes the following steps:

[0073] Step S1.1: Analyze and verify the IP source code of the FPGA communication module, and extract the top-level module interface from the IP source code. The top-level module interface includes the clock and reset interface, the system bus interface, and the communication bus interface.

[0074] Step S1.2: Based on the extracted top-level module interface, convert the IP source code of the FPGA communication module into FPGA simulation module code in C++ language. The FPGA simulation module code in C++ language provides an FPGA simulation model class containing all top-level module interfaces.

[0075] Step S1.3: Compile the C++ language FPGA simulation module code to generate the static link library of the FPGA communication module.

[0076] Step S2: Based on the FPGA simulation module code, perform interface adaptation for the system bus access part of the FPGA communication module in the all-digital simulation system;

[0077] Step S2 specifically includes the following steps:

[0078] Step S2.1: Instantiate the FPGA communication module from step S1.2;

[0079] Step S2.2: For the instantiated FPGA communication module, define the data of the bus interface signals. The data of the bus interface signals includes the clock and reset interface, system bus interface and communication bus interface in step S1.1.

[0080] Step S2.3: Change the data of the bus interface signal according to the operation instructions of the bus interface type of the all-digital simulation system, simulate the read and write operation of the bus, and complete the interface adaptation of the system bus access part.

[0081] Step S3: Introduce another module that is exactly the same as the FPGA communication module as a symmetrical module, and cross-connect the symmetrical module and the FPGA communication module through the transmit and receive interfaces;

[0082] Step S3 specifically includes the following steps:

[0083] Step S3.1: Instantiate a module that is exactly the same as the FPGA communication module in step S2.1, as a symmetrical module;

[0084] Step S3.2: Connect the data transmitting end of the FPGA communication module in step S2.1 to the data receiving end of the symmetric module in step S3.1, and at the same time connect the data receiving end of the FPGA communication module in step S2.1 to the data transmitting end of the symmetric module in step S3.1 to realize the cross connection of the two transceiver interfaces.

[0085] Step S4: On the communication data receiving side of the symmetrical module, perform interface adaptation according to the bus access method in the all-digital simulation system;

[0086] Step S4 specifically includes the following steps:

[0087] Step S4.1: After the bus write operation is completed on the FPGA communication module in step S2.3, the clock is delayed for a preset time. Then, according to the operation instructions of the bus interface type of the all-digital simulation system, the data bus interface part of the symmetric module in step S3.1 is read. The operation data corresponding to the bus write operation is obtained through the read operation, and the interface adaptation related to the write operation on the receiving side of the symmetric module is completed.

[0088] Step S4.2: After performing a write operation on the data bus interface of the symmetric module in step S3.1 according to the operation instructions of the bus interface type of the all-digital simulation system, the clock is delayed for a preset time, and then a read operation is performed on the FPGA communication module in step S2.1 according to the bus access method in step S2.3, thus completing the interface adaptation of the symmetric module receiving side write operation to the corresponding FPGA module read operation.

[0089] The present invention also provides a simulation integration system for an FPGA communication module. The simulation integration system for the FPGA communication module can be implemented by executing the process steps of the simulation integration method for the FPGA communication module. That is, those skilled in the art can understand the simulation integration method for the FPGA communication module as a preferred embodiment of the simulation integration system for the FPGA communication module.

[0090] This embodiment can be combined with other virtualization technologies. Current virtualization simulation technology is developing rapidly in the fields of CPU and MCU. In system-level simulation, since some modules use FPGA logic, it is necessary to solve the problem of how to integrate FPGA simulation with the all-digital simulation system during overall simulation. This embodiment solves this problem.

[0091] This embodiment makes the simulation effect of the FPGA communication module more intuitive. Traditional FPGA simulation only outputs results for level timing. Using the concept of symmetrical modules, this embodiment can convert the output level timing signal into a digital signal that interacts with the system, so that it can be used by the overall system or for users to view the simulation effect more intuitively.

[0092] Example 2

[0093] This embodiment provides a simulation integration system for an FPGA communication module, characterized by including the following modules:

[0094] Module M1: Converts the IP source code of the FPGA communication module into C++ language FPGA simulation module code;

[0095] Module M1 specifically includes the following modules:

[0096] Module M1.1: Analyze and verify the IP source code of the FPGA communication module, and extract the top-level module interface from the IP source code. The top-level module interface includes the clock and reset interface, the system bus interface, and the communication bus interface.

[0097] Module M1.2: Based on the extracted top-level module interface, the IP source code of the FPGA communication module is converted into FPGA simulation module code in C++ language. The FPGA simulation module code in C++ language provides an FPGA simulation model class containing all top-level module interfaces.

[0098] Module M1.3: Compiles the C++ language FPGA simulation module code and generates a static link library for the FPGA communication module.

[0099] Module M2: Based on the FPGA simulation module code, it adapts the interface of the system bus access part that accesses the FPGA communication module in the all-digital simulation system.

[0100] Module M2 specifically includes the following modules:

[0101] Module M2.1: Instantiates the FPGA communication module in module M1.2;

[0102] Module M2.2: Defines the bus interface signal data for the instantiated FPGA communication module. The bus interface signal data includes the clock and reset interface, system bus interface, and communication bus interface in module M1.1.

[0103] Module M2.3: Operate the bus interface signal data according to the operation instructions of the bus interface type of the all-digital simulation system, simulate the bus read and write operations, and complete the interface adaptation of the system bus access part.

[0104] Module M3: Introduce another module that is exactly the same as the FPGA communication module as a symmetrical module, and cross-connect the symmetrical module and the FPGA communication module through the transmit and receive interfaces;

[0105] Module M3 specifically includes the following modules:

[0106] Module M3.1: Instantiate a module that is exactly the same as the FPGA communication module in Module M2.1, as a symmetrical module;

[0107] Module M3.2: Connects the data transmitting end of the FPGA communication module in module M2.1 to the data receiving end of the symmetric module in module M3.1, and simultaneously connects the data receiving end of the FPGA communication module in module M2.1 to the data transmitting end of the symmetric module in module M3.1, thereby realizing the cross-connection of the transceiver interfaces of the two.

[0108] Module M4: On the communication data receiving side of the symmetrical module, the interface is adapted according to the bus access method in the all-digital simulation system;

[0109] Module M4 specifically includes the following modules:

[0110] Module M4.1: After the bus write operation is completed in the FPGA communication module in module M2.3, the clock delay is preset, and then the data bus interface part of the symmetric module in module M3.1 is read according to the operation instructions of the bus interface type of the all-digital simulation system. The operation data corresponding to the bus write operation is obtained through the read operation, and the interface adaptation related to the write operation of the symmetric module receiving side is completed.

[0111] Module M4.2: After performing a write operation on the data bus interface of the symmetric module in Module M3.1 according to the operation instructions of the bus interface type of the all-digital simulation system, the clock is delayed for a preset time, and then a read operation is performed on the FPGA communication module in Module M2.1 according to the bus access method of Module M2.3, thus completing the interface adaptation of the symmetric module receiving side write operation to the corresponding FPGA module read operation.

[0112] Example 3

[0113] Those skilled in the art can understand this embodiment as a more specific description of Embodiment 1.

[0114] This embodiment provides a simulation integration method for an FPGA communication module in a fully digital simulation system, including the following steps:

[0115] Step S1: Convert the IP source code of the FPGA communication module used in the all-digital simulation system into C++ language FPGA simulation module code;

[0116] Step S2: Perform interface adaptation for the system bus access portion of the FPGA communication module in the all-digital simulation system;

[0117] Step S3: Use another identical FPGA communication module as a symmetrical module to cross-connect the transceiver interface with the original FPGA communication module.

[0118] Step S4: On the communication data receiving side of the symmetrical module, interface adaptation is performed according to the bus access method.

[0119] Further, step S1 includes:

[0120] Step S1.1: Analyze and verify the FPGA source code, and analyze the top-level module interface of the FPGA source code. The top-level interface generally includes clock and reset interface, system bus interface and communication bus interface.

[0121] Step S1.2: Convert the FPGA source code into C++ language model simulation code. The C++ language model simulation code provides an FPGA simulation model class, which includes the top-level module interface of all FPGA source code.

[0122] Step S1.3: Compile the C++ model simulation code to generate the static link library of the FPGA communication module.

[0123] Further, step S2 includes:

[0124] Step S2.1: Instantiate an FPGA communication module from step S1.2;

[0125] Step S2.2: Define the data for the bus interface signals, including the clock and reset interface, system bus interface, and communication bus interface from S1.1;

[0126] Step S2.3: Simulate bus read / write operations by changing the data of the bus interface signals according to the bus interface type description.

[0127] Further, step S3 includes:

[0128] Step S3.1: Instantiate an FPGA communication module that is exactly the same as the one in step S2.1 as a symmetric module;

[0129] Step S3.2: Connect the data transmission of S2.1 to the data reception of S3.1, and connect the data reception of S2.1 to the data transmission of S3.1.

[0130] Further, step S4 includes:

[0131] Step S4.1: After the write operation is performed in step S2.3, after a sufficient clock delay, the data bus interface of the symmetric module is read according to the operation instructions of the bus interface type to obtain the bus write operation data.

[0132] Step S4.2: After performing a write operation on the data bus interface of the symmetric module according to the operation instructions of the bus interface type, and after a sufficient clock delay, perform a read operation on the FPGA communication module according to step S2.3.

[0133] This embodiment provides a simulation integration method for an FPGA communication module in a fully digital simulation system, relating to both the fields of fully digital simulation and FPGA simulation. The symmetrical module in this embodiment can convert the digital level of the FPGA into bus data, thereby enabling direct interaction with the microprocessor simulation, thus achieving overall fully digital simulation. Furthermore, since the FPGA module simulation is based on the FPGA source code, the accuracy of the FPGA simulation behavior is improved.

[0134] Example 4

[0135] Those skilled in the art can understand this embodiment as a more specific description of Embodiment 2.

[0136] This embodiment provides a simulation integration system for an FPGA communication module in a fully digital simulation system, including the following modules:

[0137] Module M1: Simulation bus interface module;

[0138] Module M2: Simulated FPGA communication module;

[0139] Module M3: Symmetrical module for FPGA communication simulation;

[0140] Module M4: Symmetrical module simulation bus interface module.

[0141] Furthermore, the module M1 includes:

[0142] Module M1.1: Accesses the clock and reset interface and system bus interface used by the FPGA communication module;

[0143] Module M1.2: The interface for interacting with the simulated CPU.

[0144] Furthermore, the module M2 includes:

[0145] Module M2.1: Clock and reset interface and system bus interface;

[0146] Module M2.2: Communication bus interface.

[0147] Furthermore, the module M3 includes:

[0148] Module M3.1: Clock and reset interface and system bus interface;

[0149] Module M3.2: Communication bus interface.

[0150] Furthermore, the module M4 includes:

[0151] Module M4.1: Accesses the clock and reset interface and system bus interface used by the FPGA communication module;

[0152] Module M4.2: The interface for interacting with the UI interaction module.

[0153] Example 5

[0154] Those skilled in the art can understand this embodiment as a more specific description of Embodiment 1 and Embodiment 3.

[0155] This embodiment provides a simulation integration method for an FPGA communication module in a fully digital simulation system, including the following steps:

[0156] Step S1: Convert the IP source code of a UART module written in Verilog into C++ code for the UART;

[0157] Step S2: Adapt the clock, reset, and Wishbone bus interface of the UART module IP, and enable the UART bus interface to interact with the all-digital simulation system;

[0158] Step S3: Create another identical UART module as a symmetrical module, assign the signal value of the original UART output TXD to the symmetrical module's RXD, and assign the signal value of the original UART module's RXD to the symmetrical module's TXD.

[0159] Step S4: Adapt the clock, reset, Wishibone bus interface, and UART bus interface of the symmetrical module to interact with the all-digital simulation system.

[0160] Step S1 includes the following steps:

[0161] Step S1.1: Analyze the Verilog source code of the UART module to obtain its top-level module interface, which includes clock, reset, wishbone bus interface, and UART communication interface;

[0162] Step S1.2: The interaction between the UART module and the all-digital simulation system uses the clock, reset, and wishbone bus. Therefore, the C++ class that converts the UART module contains these values ​​as parameters, and the C++ class contains the method function do_a_step() that executes one clock cycle for the FPGA.

[0163] Step S1.3: Compile the simulation model code of the UART module IP from step S1.2 using the C++ compilation environment of the all-digital simulation system to obtain the uart.lib static link library.

[0164] Step S2 includes the following steps:

[0165] Step S2.1: Instantiate a UART class in the all-digital simulation system. This instance serves as the system UART.

[0166] Step S2.2: Define the variables clk_signal, reset_signal, wishbone_interface_class, and uart_interface_class in the all-digital simulation system as the class input values ​​for the UART;

[0167] Step S2.3: In the all-digital simulation system, change the input value in S2.2 in each clock cycle. The method of change is in accordance with the Wishbone bus manual, so as to realize the read and write access of the Wishbone bus, and encapsulate the read and write access into an interface for the system bus read and write interface of the all-digital simulation system to call.

[0168] Step S3 includes the following steps:

[0169] Step S3.1: Instantiate a UART class that is exactly the same as the one in step S2.1 as a symmetric module;

[0170] Step S3.2: In the all-digital simulation system, define pair_clk_signal, pair_reset_signal, pair_wishbone_interface_class, and pair_uart_interface_class as signal inputs for the symmetrical module. Assign the txd value in uart_interface_class in S2.2 to the rxd value in pair_uart_interface_class of the symmetrical module in S3.1, and assign the rxd value in uart_interface_class in S2.2 to the txd value in pair_uart_interface_class of the symmetrical module in S3.1. This completes the cross-connection of two identical communication IPs.

[0171] Step S4 includes the following steps:

[0172] Step S4.1: When writing the system UART register in the all-digital simulation system, first call the system UART write interface. The symmetric UART only performs clock synchronization and does not perform write operations. After the clock has been running for a period of time, the UART data is completely transferred to the symmetric module. The all-digital simulation system then calls the symmetric module's UART read interface to read the system bus write data from the symmetric module.

[0173] Step S4.2: In the all-digital simulation system, when transmitting data to the system UART via the UART bus, the write interface of the symmetric UART is first called. The system UART only performs clock synchronization and does not perform read operations. After the clock has been running for a period of time, the UART data is completely transmitted to the system module. The all-digital simulation system then calls the UART read interface of the system module to read the written data of the UART bus from the system module.

[0174] Example 6

[0175] Those skilled in the art can understand this embodiment as a more specific description of Embodiments 2 and 4.

[0176] This embodiment provides a simulation integration system for an FPGA communication module in a fully digital simulation system, including:

[0177] Module M1: A module for accessing the simulation UART read / write interface in a fully digital simulation system;

[0178] Module M2: System simulation module for UART communication IP in a fully digital simulation system;

[0179] Module M3: A symmetrical module that is identical to the UART communication IP model in the all-digital simulation system;

[0180] Module M4: A read / write interface module that can communicate with symmetric modules in a fully digital simulation system.

[0181] Module M1 includes the following modules:

[0182] Module M1.1: The interface required for the internal simulation CPU of the all-digital simulation system to access the system bus and interact with the simulation CPU;

[0183] Module M1.2: The clock and reset interface is used to control the clock and reset of the UART communication simulation module, and the wishbone interface is used to access the internal registers of the UART communication simulation module.

[0184] Module M2 includes the following modules:

[0185] Module M2.1: The clock and reset interface is used to interface with the read / write interface in module M1. This allows the read / write interface to access the registers of the UART communication simulation module.

[0186] Module M2.2: The serial communication bus interface is used to implement UART communication function, and its output signal is a level signal.

[0187] Module M3 includes the following modules:

[0188] Module M3.1: The clock and reset interface is used to interface with the read / write interface in M4, thereby enabling the read / write interface to access the registers of the symmetric module;

[0189] Module M3.2: The serial communication bus interface is used to implement UART communication function, and its output signal is a level signal. It is cross-connected with the serial bus interface of module M2 to obtain communication data.

[0190] Module M4 includes the following modules:

[0191] Module M4.1: The clock and reset interface is used to control the clock and reset of the symmetric simulation module, and the wish bone interface is used to access the internal registers of the symmetric simulation module.

[0192] Module M4.2: The interface for reading and writing data in the UI part of the all-digital simulation system. Through this interface, the data received by the symmetric module is sent to the UI exchange module. It is also through this interface that the data that the UI interaction part needs to pass in is transmitted to module M3, and then transmitted to module M2 through the serial bus, and then transmitted to module M1 to inform the CPU of the all-digital simulation system.

[0193] Example 7

[0194] This embodiment provides a simulation integration system for an FPGA communication module, including: a first simulation bus interface module, a first simulation FPGA communication module, a second simulation FPGA communication module, and a second simulation bus interface module.

[0195] Data transmission occurs between the first simulation bus interface module and the first simulation FPGA communication module, between the first simulation FPGA communication module and the second simulation FPGA communication module, and between the second simulation FPGA communication module and the second simulation bus interface module. The first simulation FPGA communication module converts its IP source code into C++ FPGA simulation module code, and the first simulation bus interface module performs interface adaptation based on the FPGA simulation module code. The second simulation FPGA communication module is identical to the first simulation FPGA communication module, serving as a symmetrical module to the first simulation FPGA communication module. The transceiver interfaces of the second simulation bus interface module are cross-connected with the transceiver interfaces of the first simulation bus interface module to achieve interface adaptation of the second simulation bus interface module.

[0196] The first simulation bus interface module includes: a simulation CPU access interface, a first clock and reset interface, and a first system bus interface. The first simulation FPGA communication module includes: a second clock and reset interface, a second system bus interface, and a first communication bus interface. The second simulation FPGA communication module includes: a third clock and reset interface, a third system bus interface, and a second communication bus interface. The second simulation bus interface module includes: a fourth clock and reset interface, a fourth system bus interface, and a UI interaction interface.

[0197] The simulated CPU access interface connects to the simulated CPU; the first clock and reset interface connects to the second clock and reset interface; the first system bus interface connects to the second system bus interface; the first communication bus interface connects to the second communication bus interface; the third clock and reset interface connects to the fourth clock and reset interface; the third system bus interface connects to the fourth system bus interface; and the UI interaction interface connects to the UI interaction module.

[0198] The FPGA module simulation of this invention is based on the FPGA source code, thereby improving the accuracy of FPGA simulation behavior.

[0199] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0200] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A simulation integration method for an FPGA communication module, characterized in that, Includes the following steps: Step S1: Convert the IP source code of the FPGA communication module into C++ language FPGA simulation module code; Step S2: Based on the FPGA simulation module code, perform interface adaptation for the system bus access part of the FPGA communication module in the all-digital simulation system; Step S3: Introduce another module that is exactly the same as the FPGA communication module as a symmetrical module, and cross-connect the symmetrical module and the FPGA communication module through the transmit and receive interfaces; Step S4: On the communication data receiving side of the symmetrical module, perform interface adaptation according to the bus access method in the all-digital simulation system; Step S1 specifically includes the following steps: Step S1.1: Analyze and verify the IP source code of the FPGA communication module, and extract the top-level module interface from the IP source code. The top-level module interface includes the clock and reset interface, the system bus interface, and the communication bus interface. Step S1.2: Based on the extracted top-level module interface, convert the IP source code of the FPGA communication module into FPGA simulation module code in C++ language. The FPGA simulation module code in C++ language provides an FPGA simulation model class containing all top-level module interfaces. Step S1.3: Compile the C++ language FPGA simulation module code to generate the static link library of the FPGA communication module; Step S2 specifically includes the following steps: Step S2.1: Instantiate the FPGA communication module from step S1.2; Step S2.2: For the instantiated FPGA communication module, define the data of the bus interface signals. The data of the bus interface signals includes the clock and reset interface, system bus interface and communication bus interface in step S1.

1. Step S2.3: Change the data of the bus interface signal according to the operation instructions of the bus interface type of the all-digital simulation system, simulate the read and write operation of the bus, and complete the interface adaptation of the system bus access part. Step S3 specifically includes the following steps: Step S3.1: Instantiate a module that is exactly the same as the FPGA communication module in step S2.1, as a symmetrical module; Step S3.2: Connect the data transmitting end of the FPGA communication module in step S2.1 to the data receiving end of the symmetric module in step S3.1, and at the same time connect the data receiving end of the FPGA communication module in step S2.1 to the data transmitting end of the symmetric module in step S3.1, so as to realize the cross connection of the two transceiver interfaces; Step S4 specifically includes the following steps: Step S4.1: After the bus write operation is completed on the FPGA communication module in step S2.3, the clock is delayed for a preset time. Then, according to the operation instructions of the bus interface type of the all-digital simulation system, the data bus interface part of the symmetric module in step S3.1 is read. The operation data corresponding to the bus write operation is obtained through the read operation, and the interface adaptation related to the write operation on the receiving side of the symmetric module is completed. Step S4.2: After performing a write operation on the data bus interface of the symmetric module in step S3.1 according to the operation instructions of the bus interface type of the all-digital simulation system, the clock is delayed for a preset time, and then a read operation is performed on the FPGA communication module in step S2.1 according to the bus access method in step S2.3, thus completing the interface adaptation of the symmetric module receiving side write operation to the corresponding FPGA module read operation.

2. A simulation integration system for an FPGA communication module, characterized in that, Includes the following modules: Module M1: Converts the IP source code of the FPGA communication module into C++ language FPGA simulation module code; Module M2: Based on the FPGA simulation module code, it adapts the interface of the system bus access part that accesses the FPGA communication module in the all-digital simulation system. Module M3: Introduce another module that is exactly the same as the FPGA communication module as a symmetrical module, and cross-connect the symmetrical module and the FPGA communication module through the transmit and receive interfaces; Module M4: On the communication data receiving side of the symmetrical module, the interface is adapted according to the bus access method in the all-digital simulation system; Module M1 specifically includes the following modules: Module M1.1: Analyze and verify the IP source code of the FPGA communication module, and extract the top-level module interface from the IP source code. The top-level module interface includes the clock and reset interface, the system bus interface, and the communication bus interface. Module M1.2: Based on the extracted top-level module interface, the IP source code of the FPGA communication module is converted into FPGA simulation module code in C++ language. The FPGA simulation module code in C++ language provides an FPGA simulation model class containing all top-level module interfaces. Module M1.3: Compiles the C++ language FPGA simulation module code and generates the static link library for the FPGA communication module; Module M2 specifically includes the following modules: Module M2.1: Instantiates the FPGA communication module in module M1.2; Module M2.2: Defines the bus interface signal data for the instantiated FPGA communication module. The bus interface signal data includes the clock and reset interface, system bus interface, and communication bus interface in module M1.

1. Module M2.3: Change the data of the bus interface signal according to the operation instructions of the bus interface type of the all-digital simulation system, simulate the read and write operation of the bus, and complete the interface adaptation of the system bus access part; Module M3 specifically includes the following modules: Module M3.1: Instantiate a module that is exactly the same as the FPGA communication module in Module M2.1, as a symmetrical module; Module M3.2: Connects the data transmitting end of the FPGA communication module in module M2.1 to the data receiving end of the symmetric module in module M3.1, and simultaneously connects the data receiving end of the FPGA communication module in module M2.1 to the data transmitting end of the symmetric module in module M3.1, thereby realizing the cross-connection of the transceiver interfaces of the two. Module M4 specifically includes the following modules: Module M4.1: After the bus write operation is completed in the FPGA communication module in module M2.3, the clock delay is preset, and then the data bus interface part of the symmetric module in module M3.1 is read according to the operation instructions of the bus interface type of the all-digital simulation system. The operation data corresponding to the bus write operation is obtained through the read operation, and the interface adaptation related to the write operation of the symmetric module receiving side is completed. Module M4.2: After performing a write operation on the data bus interface of the symmetric module in Module M3.1 according to the operation instructions of the bus interface type of the all-digital simulation system, the clock is delayed for a preset time, and then a read operation is performed on the FPGA communication module in Module M2.1 according to the bus access method of Module M2.3, thus completing the interface adaptation of the symmetric module receiving side write operation to the corresponding FPGA module read operation.

3. A simulation integration system for an FPGA communication module, characterized in that, include: The system comprises a first simulation bus interface module, a first simulation FPGA communication module, a second simulation FPGA communication module, and a second simulation bus interface module. Data transmission occurs between the first simulation bus interface module and the first simulation FPGA communication module, between the first simulation FPGA communication module and the second simulation FPGA communication module, and between the second simulation FPGA communication module and the second simulation bus interface module. The first simulated FPGA communication module converts its IP source code into C++ language FPGA simulation module code, and the first simulated bus interface module adapts the interface based on the FPGA simulation module code. The second simulated FPGA communication module is the same as the first simulated FPGA communication module, and the second simulated FPGA communication module serves as a symmetrical module to the first simulated FPGA communication module. The transceiver interface of the second simulation bus interface module is cross-connected with the transceiver interface of the first simulation bus interface module to achieve interface adaptation of the second simulation bus interface module; The IP source code of the FPGA communication module was analyzed and verified. The top-level module interface was extracted from the IP source code. The top-level module interface includes the clock and reset interface, the system bus interface, and the communication bus interface. Based on the extracted top-level module interfaces, the IP source code of the FPGA communication module is converted into FPGA simulation module code in C++ language. The FPGA simulation module code in C++ language provides an FPGA simulation model class containing all top-level module interfaces. Compile the C++ language FPGA simulation module code to generate the static link library of the FPGA communication module; Instantiate the FPGA communication module; For the instantiated FPGA communication module, define the data of the bus interface signals, which include the clock and reset interface, the system bus interface, and the communication bus interface. According to the operation instructions of the bus interface type of the all-digital simulation system, the data of the bus interface signal is changed to simulate the read and write operation of the bus and complete the interface adaptation of the system bus access part. Instantiate a module that is exactly the same as the FPGA communication module, as a symmetrical module; Connect the data transmitter of the FPGA communication module to the data receiver of the symmetric module, and simultaneously connect the data receiver of the FPGA communication module to the data transmitter of the symmetric module to achieve cross-connection of their transceiver interfaces. After the bus write operation is completed on the FPGA communication module, the clock delay is preset, and then according to the operation instructions of the bus interface type of the all-digital simulation system, the data bus interface of the symmetric module performs a read operation. The operation data corresponding to the bus write operation is obtained through the read operation, and the interface adaptation related to the write operation on the receiving side of the symmetric module is completed. After performing a write operation on the data bus interface of the symmetrical module according to the operation instructions of the bus interface type of the all-digital simulation system, the clock is delayed for a preset time, and then a read operation is performed on the FPGA communication module according to the bus access method, thus completing the interface adaptation of the symmetrical module receiving side write operation to the corresponding FPGA module read operation.

4. The simulation integration system for the FPGA communication module according to claim 3, characterized in that, The first simulation bus interface module includes: a simulation CPU access interface, a first clock and reset interface, and a first system bus interface; The first simulated FPGA communication module includes: a second clock and reset interface, a second system bus interface, and a first communication bus interface; The second simulated FPGA communication module includes: a third clock and reset interface, a third system bus interface, and a second communication bus interface; The second simulation bus interface module includes: a fourth clock and reset interface, a fourth system bus interface, and a UI interaction interface; The simulated CPU access interface is connected to the simulated CPU, the first clock and reset interface is connected to the second clock and reset interface, and the first system bus interface is connected to the second system bus interface; The first communication bus interface is connected to the second communication bus interface; The third clock and reset interface is connected to the fourth clock and reset interface, the third system bus interface is connected to the fourth system bus interface, and the UI interaction interface is connected to the UI interaction module.

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