A routing method and system based on timing criticality
By using a timing-critical routing method, combined with the minimum spanning tree algorithm and path merging optimization, the problem of neglecting timing-critical paths in chip design is solved, achieving dual optimization of total wiring length and timing criticality, thereby improving the chip's operating speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHAOXING XINNA TECHNOLOGY CO LTD
- Filing Date
- 2025-07-04
- Publication Date
- 2026-06-05
AI Technical Summary
The routing algorithms in existing chip designs ignore timing-critical paths, leading to frequent establishment time violations in the later stages of the design process. Furthermore, traditional methods cannot simultaneously optimize the total route length and timing-critical load nodes.
A timing-critical routing method is adopted, which iteratively expands the routing path through the minimum spanning tree algorithm and combines path merging optimization to generate a routing tree structure that satisfies the dual constraints of total cabling length and critical path timing.
It enables more accurate timing analysis, reduces overall routing costs and load node signal delays, and improves chip operating speed.
Smart Images
Figure CN120893379B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design technology, and in particular to a routing method and system based on timing criticality. Background Technology
[0002] As integrated circuit technology enters the deep submicron and nanometer era, the physical implementation of chip design faces increasingly severe timing convergence challenges. In complex high-speed digital circuit designs, interconnect delays have gradually surpassed gate delays, becoming a core factor affecting chip performance. Traditional routing algorithms are mostly based on Manhattan distance optimization or congestion control strategies, but they neglect the timing characteristics of critical paths, leading to frequent setup time violations in the later stages of design. Especially in high-performance computing chips, the coupling effect between clock networks and data paths makes the need for co-optimization of static timing analysis and physical design increasingly urgent.
[0003] In calculating routing costs, existing technologies often use two approaches: one focuses on the total length of the Net (the lines in a circuit) as the primary cost, aiming to minimize total delay. This approach ignores the setup time margin of timing-critical load nodes, which directly determine the final clock cycle size. This can lead to excessive delays in some signals, resulting in a decrease in the overall timing performance of the design. The other approach aims to optimize the routing path of timing-critical load nodes, effectively reducing their routing length. However, this approach cannot effectively balance the total routing length of the Net, leading to excessive parasitic resistance and capacitance in the routing lines, which in turn negatively impacts the overall timing performance of the load nodes.
[0004] Therefore, there is an urgent need for a routing method and system based on time-series criticality to solve the above problems. Summary of the Invention
[0005] The purpose of this invention is to provide a routing method based on time-series criticality, comprising the following steps:
[0006] S1. Based on the chip design layout results, the chip physical area is abstracted into a set of nodes, and the routing channels between adjacent areas are abstracted into a set of edges. Each node corresponds to the physical coordinates of the device, and the weight of each edge is determined by the congestion of the channel. The congestion is determined by the number of wirings that have passed through the channel and the number of signals that have passed through the channel.
[0007] S2. Generate a routing cost function for the target network, wherein the cost function is a weighted sum of the total cabling length and the critical path length;
[0008] S3. Using the driver node as the root node, the minimum spanning tree algorithm is used to iteratively expand the routing path. Each time, the node connected by the edge that minimizes the sum of the path weight and the distance to the current node is selected and added to the routing tree until all load nodes are covered. The parasitic resistance and capacitance parameters of each path are recorded. The parasitic resistance and capacitance parameters are used to calculate the timing delay from the driver node to the load node.
[0009] S4. Path merging optimization includes: traversing all load node pairs, calculating the merging cost of their overlapping paths, wherein the merging cost is the product of the overlapping path length and the sum of the temporal criticality of the two nodes, selecting the node pair with the largest product value for merging, and merging the common node on the overlapping path that is farthest from the driving node. After merging, a virtual node is generated and its temporal criticality is updated to the arithmetic mean of the criticality of the original node.
[0010] S5. Repeat steps S3 and S4 until the merged cost is lower than the preset threshold or the maximum number of iterations is reached, and output the final routing tree structure. The routing tree simultaneously satisfies the dual constraints of minimizing the total wiring length and optimizing the timing of the critical path.
[0011] Furthermore, the weighting coefficient for the total wiring length is k;
[0012] The critical path length is obtained by weighted summation of the temporal criticality of each load node. The weighting coefficient of the critical path length is 1-k, and the temporal criticality is calculated based on the establishment time margin of the load node.
[0013] Furthermore, the path merging optimization step in step S4 also includes:
[0014] S41. Calculate the merging cost of all load node pairs, where the merging cost is the product of the length of the overlapping path between the two nodes in the routing tree and their temporal criticality.
[0015] S42. Select the node pair with the highest merging value and merge them. Place the merged virtual node at the end of the overlapping path.
[0016] S43. Set the temporal criticality of the virtual node to the arithmetic mean of the criticalities of the original two nodes.
[0017] Furthermore, the generation of the routing tree in step S3 further includes:
[0018] S31. Perform shortest path search based on the edge weights, where the edge weights reflect the congestion level of the channel.
[0019] S32. Generate an initial routing tree by iteratively expanding the minimum path cost node. In each iteration, add the unconnected node closest to the driving node to the tree structure.
[0020] Furthermore, the virtual node processing method in step S5 includes:
[0021] S51. Position the physical location of the virtual node at the end node of the overlapping path;
[0022] S52. Inherit the creation time margin constraint of the original node, and take the smaller value of the two nodes as the constraint value of the virtual node.
[0023] S53. When a virtual node merges with other nodes again, the merge cost is recalculated.
[0024] This invention also discloses a routing system based on time-series criticality, comprising:
[0025] The abstract layout module is used to abstract the chip physical area into a set of nodes and the routing channels between adjacent areas into a set of edges based on the chip design layout results. Each node corresponds to the physical coordinates of the device, and the weight of each edge is determined by the congestion of the channel. The congestion is determined by the number of wirings that have passed through the channel and the number of signals that have passed through the channel.
[0026] The generation module generates a routing cost function for the target network, wherein the cost function is a weighted sum of the total cabling length and the critical path length;
[0027] The connection module is used to iteratively expand the routing path with the driver node as the root node and the minimum spanning tree algorithm. Each time, the node connected by the edge that minimizes the sum of the path weight and the distance to the current node is selected and added to the routing tree until all load nodes are covered. The parasitic resistance and capacitance parameters of each path are recorded. The parasitic resistance and capacitance parameters are used to calculate the timing delay from the driver node to the load node.
[0028] The synthesis module is used to optimize path merging. It traverses all load node pairs, calculates the merging cost of their overlapping paths, and the merging cost is the product of the overlapping path length and the sum of the temporal criticality of the two nodes. The node pair with the largest product value is selected for merging. The merging position is the common node on the overlapping path that is farthest from the driving node. After merging, a virtual node is generated and its temporal criticality is updated to the arithmetic mean of the criticality of the original node.
[0029] The execution module is used to repeatedly execute the above steps until the merged cost is lower than a preset threshold or the maximum number of iterations is reached, and outputs the final routing tree structure. The routing tree simultaneously satisfies the dual constraints of minimizing the total wiring length and optimizing the timing of the critical path.
[0030] Furthermore, the synthesis module also includes:
[0031] The calculation unit is used to calculate the merging cost of all load node pairs, wherein the merging cost is the product of the sum of the lengths of the overlapping paths of the two nodes in the routing tree and their temporal criticality.
[0032] The merging unit is used to select the node pair with the highest merging cost and merge them, placing the merged virtual node at the end of the overlapping path.
[0033] The integration unit is used to set the temporal criticality of the virtual node to the arithmetic mean of the criticalities of the original two nodes.
[0034] This application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-described method.
[0035] This application also provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the steps of the above-described method.
[0036] The beneficial effects of this application are as follows:
[0037] This invention, based on a more accurate time delay model, defines an objective function that comprehensively considers both the overall routing cost and the routing cost of time-critical load nodes, making time series analysis more accurate. Simultaneously, it designs a comprehensive routing method that optimizes both the overall routing cost and the routing cost of critical load nodes. This method first establishes an initial routing tree, then combines time criticality with a node merging approach. This reduces the overall routing cost while maximizing the reduction of signal delay at load nodes according to their criticality, thereby decreasing the clock cycle size and effectively increasing the chip's operating speed. Attached Figure Description
[0038] Figure 1 This is a schematic diagram of a method flow proposed in an embodiment of this application;
[0039] Figure 2 This is a schematic diagram of a time delay model proposed in an embodiment of this application;
[0040] Figure 3 This is an example of calculating the cost function proposed in one embodiment of this application;
[0041] Figure 4 This is a schematic diagram of the physical structure and Net node locations proposed in an embodiment of this application;
[0042] Figure 5 This is a schematic diagram of an initial routing tree proposed in an embodiment of this application;
[0043] Figure 6This is a schematic diagram illustrating the statistical analysis of all distance values based on temporal criticality, as proposed in an embodiment of this application.
[0044] Figure 7 This is a schematic diagram of node merging proposed in an embodiment of this application;
[0045] Figure 8 This is a schematic diagram of the final merging result proposed in an embodiment of this application;
[0046] Figure 9 This is a schematic diagram illustrating the result of a rerouting proposed in an embodiment of this application.
[0047] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0048] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
[0049] This application provides a routing method based on temporal criticality, including the following steps:
[0050] S1. Based on the chip design layout results, the chip physical area is abstracted into a set of nodes, and the routing channels between adjacent areas are abstracted into a set of edges. Each node corresponds to the physical coordinates of the device, and the weight of each edge is determined by the congestion of the channel. The congestion is determined by the number of wirings that have passed through the channel and the number of signals that have passed through the channel.
[0051] S2. Generate a routing cost function for the target network, wherein the cost function is a weighted sum of the total cabling length and the critical path length;
[0052] S3. Using the driver node as the root node, the minimum spanning tree algorithm is used to iteratively expand the routing path. Each time, the node connected by the edge that minimizes the sum of the path weight and the distance to the current node is selected and added to the routing tree until all load nodes are covered. The parasitic resistance and capacitance parameters of each path are recorded. The parasitic resistance and capacitance parameters are used to calculate the timing delay from the driver node to the load node.
[0053] S4. Path merging optimization includes: traversing all load node pairs, calculating the merging cost of their overlapping paths, wherein the merging cost is the product of the overlapping path length and the sum of the temporal criticality of the two nodes, selecting the node pair with the largest product value for merging, and merging the common node on the overlapping path that is farthest from the driving node. After merging, a virtual node is generated and its temporal criticality is updated to the arithmetic mean of the criticality of the original node.
[0054] S5. Repeat steps S3 and S4 until the merged cost is lower than the preset threshold or the maximum number of iterations is reached, and output the final routing tree structure. The routing tree simultaneously satisfies the dual constraints of minimizing the total wiring length and optimizing the timing of the critical path.
[0055] like Figure 2 In the time delay model shown, the cost function is defined as follows:
[0056] ;
[0057] Where no is the driving device, rd is the output resistance of the previous stage driving device, and Cno is the equivalent total capacitance looking towards Net from the output of the driving device. This capacitance is the equivalent sum of all capacitances on Net, including parasitic capacitance and the input capacitance of the output device.
[0058] ej represents the edges traversed by the path from point no to point nj, rej and Cej represent the parasitic resistance and capacitance on each edge, and Cj represents the equivalent capacitance of each edge looking backward, i.e., in the direction from n0 to ni.
[0059] like Figure 2 As shown, n1, n2, and n3 are load devices, where re0, re1, Ce0, and Ce1 are parasitic resistance and parasitic capacitance, and C1, C2, and C3 are the input resistances of the three load devices, respectively.
[0060] Therefore, to obtain T(n1), we need to decompose n0 to n1 into different edges with parasitic resistance as the dividing point according to the above formula, and look backward at the end of each edge to obtain the equivalent capacitance based on the circuit analysis results. The equivalent capacitance corresponding to re0 is the sum of the equivalent capacitances from node k to n0, n1, and n2.
[0061] According to this formula, the time delay from the driver node to a load node is related to two factors: the total route length (a longer route length results in greater parasitic capacitance and resistance) and the path length from the driver node to the load node. If the output resistance rd is larger, the former has a greater impact on the time delay; conversely, the latter has a greater impact.
[0062] Therefore, this scheme influences the routing algorithm from two perspectives simultaneously and provides a unified cost calculation function for both. The formula for calculating the cost function is as follows:
[0063] ;
[0064] Among them, D represents the combined value. It is the total route length of the Net. The time-series criticality of the corresponding load node. The route length α from the driver node to the load node is calculated as follows: The timing criticality of the load node with the minimum required time R (MinR) is assigned a value of 1, the timing criticality of the load node with the maximum required time R (MaxR) is assigned a value of 0, and the criticality of load nodes between the minimum (MinR) and maximum (MaxR) is determined based on the required time R:
[0065] (MaxR–R) / (MaxR–MinR);
[0066] For example Figure 3 As shown, the Net and routing results are displayed. The numbers on the edges represent the length, α represents the timing criticality, the circles represent nodes on the Net, S is the driver node, and the rest are load nodes.
[0067] The combined cost D = k × (2 + 3 + 3 + 4) + (1 - k)( 0.8 × (2 + 3) + 1 × (2 + 4) + 0 × (2 + 3)).
[0068] Specifically, the weighting coefficient for the total wiring length is k;
[0069] The critical path length is obtained by weighted summation of the temporal criticality of each load node. The weighting coefficient of the critical path length is 1-k, and the temporal criticality is calculated based on the establishment time margin of the load node.
[0070] The value of k is a real number greater than or equal to 0 and less than or equal to 1, and is dynamically adjusted according to the design stage;
[0071] The critical path length is obtained by weighted summation of the temporal criticality of each load node. The weighting coefficient of the critical path length is 1-k, and the temporal criticality is calculated based on the establishment time margin of the load node.
[0072] Specifically, the path merging optimization steps in step S4 further include:
[0073] S41. Calculate the merging cost of all load node pairs, where the merging cost is the product of the length of the overlapping path between the two nodes in the routing tree and their temporal criticality.
[0074] S42. Select the node pair with the highest merging value and merge them. Place the merged virtual node at the end of the overlapping path.
[0075] S43. Set the temporal criticality of the virtual node to the arithmetic mean of the criticalities of the original two nodes.
[0076] Specifically, the virtual node processing method in step S5 includes:
[0077] S51. Position the physical location of the virtual node at the end node of the overlapping path;
[0078] S52. Inherit the creation time margin constraint of the original node, and take the smaller value of the two nodes as the constraint value of the virtual node.
[0079] S53. When a virtual node merges with other nodes again, the merge cost is recalculated.
[0080] like Figure 4 As shown, after understanding the calculation formula of the cost function, it is necessary to model the physical structure diagram. The design layout results, that is, the physical location of each device in the chip, are input as known conditions. The physical regions in the chip that house the devices are abstracted as nodes, and the routing channels between the physical regions are regarded as edges, forming a physical structure diagram composed of nodes and edges. The devices in the design are all located between the above nodes. As shown in the figure below, the solid nodes in the figure represent nodes on a certain Net (in chip design and routing methods, Net refers to the electrical connection structure connecting multiple logical or physical components in the circuit, and will be referred to as Net in the following text). α represents the timing criticality of the load node. Here, it is assumed that node D is the driving node of the Net, and the other solid nodes represent the load nodes of the Net. The weight of the edge in the figure represents the congestion of the current routing channel when routing the Net. The larger the edge weight, the more severe the congestion. The weight can be determined by the number of signals that have passed through the channel.
[0081] Furthermore, the generation of the routing tree in step S3 further includes:
[0082] S31. Perform shortest path search based on the edge weights, where the edge weights reflect the congestion level of the channel.
[0083] S32. Generate an initial routing tree by iteratively expanding the minimum path cost node. In each iteration, add the unconnected node closest to the driving node to the tree structure.
[0084] Regarding the initial routing tree, a path merging method is used for Net routing. The input layout design results are used to route the Net, which means connecting the driver nodes and load nodes on the Net in the physical structure diagram. The connection routes will form a tree structure, with the root node of the tree being the driver node and the leaf nodes being the load nodes.
[0085] like Figure 5 As shown, routing a Net can be divided into the following steps:
[0086] Step 1: Starting from the driving node, initialize the distance Dis=0. Initialize the distance Dis=0 for all nodes except the driving node; set set S to empty, and set the complement of set S to S-, which is initialized to include all nodes in the physical structure graph.
[0087] Step 2: Add node D to S and remove node D from S-. Then update the distance of each node in S- that is connected to a node in S by an edge, using the method Dis_S- = Min(W + Dis_S), where Dis_S- represents the distance value of the node in S- that is connected to a node in S, W represents the weight value of the edge, Dis_S represents the distance value of the node in S that is connected to it, and Min represents the minimum value of all the above distance values.
[0088] Step 3: Take the node with the smallest Dis_S- in the previous step, and record the node with the smallest distance in S that is connected to it as its predecessor node. Add it to S and remove it from S-.
[0089] Step 4: Repeat steps 2 and 3 until all nodes in S- are empty.
[0090] Thus, the initial routing tree with the driver node as the source is obtained, as follows: Figure 5 As shown, the dashed lines represent the routing paths.
[0091] Step 5: Iterate through the load nodes and combine them in pairs. Take the corresponding overlapping path value Merged_Dis. For example, if the overlapping route range of load nodes B and F is from D to E to C, then Merged_Dis(B, F) = 1 + 2 = 3. For another example, if the overlapping route range of load nodes G and H is from D to M, then Merged_Dis(G, H) = 2.
[0092] Step 6: After calculating the Merged_Dis for all the above combinations, calculate the distance value MD based on temporal criticality. The calculation method is as follows:
[0093] MD = Merged_Dis × (α1 + α2),
[0094] Where α1 and α2 represent the timing criticality of the corresponding two load nodes.
[0095] For example, MD(B,F) = (1+2)×(0.1+0.7) = 2.4. The legend shows the calculation results for all MD values. Figure 6 As shown.
[0096] Step 7, select the pair with the largest MD value, such as Figure 6As shown, this represents a combination of nodes F and G. These two nodes are merged, and the merged node becomes the new load node, placed on the overlapping path between the two nodes, at the point furthest from the driver node. Specifically, the overlapping route range for load nodes F and G is from D to E, and node E is the furthest node on their overlapping path. The criticality α of the merged node is equal to the average criticality of the two combined nodes. The original two nodes, F and G, are then deleted. The merging process is recorded. Figure 7 As shown, the solid black nodes represent deleted nodes that have been merged, and the gray nodes at node E represent newly added load nodes.
[0097] Step 8: Repeat steps 5, 6 and 7 above until all load nodes have been merged and only driver node D remains. Figure 8 This is the final result after the merger is completed.
[0098] Step 9: Based on the recorded results of the merging process, re-route the Net. Determining the routing path is the reverse process of merging; that is, the merging node will route along the path from the merging node to the load node, as shown below. Figure 9 As shown, the new routing result is based on the previously defined cost calculation function, taking into account not only the total route length (or cost) but also the routing paths of critical load nodes according to the time sequence criticality.
[0099] Compared to existing technologies, this invention, based on a more accurate time delay model, defines an objective function that comprehensively considers both the overall routing cost and the routing cost of time-critical load nodes, resulting in more accurate time series analysis. Simultaneously, it designs a comprehensive routing method that optimizes both the overall routing cost and the routing cost of critical load nodes. This method first establishes an initial routing tree, then combines time criticality with a node merging approach. This reduces the overall routing cost while maximizing the reduction of signal delay at load nodes according to their criticality, thereby decreasing the clock cycle size and effectively increasing the chip's operating speed.
[0100] This invention also discloses a routing system based on time-series criticality, comprising:
[0101] The abstract layout module is used to abstract the chip physical area into a set of nodes and the routing channels between adjacent areas into a set of edges based on the chip design layout results. Each node corresponds to the physical coordinates of the device, and the weight of each edge is determined by the congestion of the channel. The congestion is determined by the number of wirings that have passed through the channel and the number of signals that have passed through the channel.
[0102] The generation module generates a routing cost function for the target network, wherein the cost function is a weighted sum of the total cabling length and the critical path length;
[0103] The connection module is used to iteratively expand the routing path with the driver node as the root node and the minimum spanning tree algorithm. Each time, the node connected by the edge that minimizes the sum of the path weight and the distance to the current node is selected and added to the routing tree until all load nodes are covered. The parasitic resistance and capacitance parameters of each path are recorded. The parasitic resistance and capacitance parameters are used to calculate the timing delay from the driver node to the load node.
[0104] The synthesis module is used to optimize path merging. It traverses all load node pairs, calculates the merging cost of their overlapping paths, and the merging cost is the product of the overlapping path length and the sum of the temporal criticality of the two nodes. The node pair with the largest product value is selected for merging. The merging position is the common node on the overlapping path that is farthest from the driving node. After merging, a virtual node is generated and its temporal criticality is updated to the arithmetic mean of the criticality of the original node.
[0105] The execution module is used to repeatedly execute the above steps until the merged cost is lower than a preset threshold or the maximum number of iterations is reached, and outputs the final routing tree structure. The routing tree simultaneously satisfies the dual constraints of minimizing the total wiring length and optimizing the timing of the critical path.
[0106] Furthermore, the synthesis module also includes:
[0107] The calculation unit is used to calculate the merging cost of all load node pairs, wherein the merging cost is the product of the sum of the lengths of the overlapping paths of the two nodes in the routing tree and their temporal criticality.
[0108] The merging unit is used to select the node pair with the highest merging cost and merge them, placing the merged virtual node at the end of the overlapping path.
[0109] The integration unit is used to set the temporal criticality of the virtual node to the arithmetic mean of the criticalities of the original two nodes.
[0110] This application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-described method.
[0111] This application also provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the steps of the above-described method.
[0112] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in this application and in the embodiments can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual-speed SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
[0113] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.
[0114] The above description is merely a preferred embodiment of the present invention and does not limit the scope of this application. Any equivalent results or equivalent process transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of protection of this application.
Claims
1. A routing method based on temporal criticality, characterized in that, Includes the following steps: S1. Based on the chip design layout results, the chip physical area is abstracted into a set of nodes, and the routing channels between adjacent areas are abstracted into a set of edges. Each node corresponds to the physical coordinates of the device, and the weight of each edge is determined by the congestion of the channel. The congestion is determined by the number of wirings that have passed through the channel and the number of signals that have passed through the channel. S2. Generate a routing cost function for the target network, wherein the cost function is a weighted sum of the total cabling length and the critical path length; S3. Using the driver node as the root node, the minimum spanning tree algorithm is used to iteratively expand the routing path. Each time, the node connected by the edge that minimizes the sum of the path weight and the distance to the current node is selected and added to the routing tree until all load nodes are covered. The parasitic resistance and capacitance parameters of each path are recorded. The parasitic resistance and capacitance parameters are used to calculate the timing delay from the driver node to the load node. S4. Path merging optimization includes: traversing all load node pairs, calculating the merging cost of their overlapping paths, wherein the merging cost is the product of the overlapping path length and the sum of the temporal criticality of the two nodes, selecting the node pair with the largest product value for merging, and merging the common node on the overlapping path that is farthest from the driving node. After merging, a virtual node is generated and its temporal criticality is updated to the arithmetic mean of the criticality of the original node. S5. Repeat steps S3 and S4 until the merged cost is lower than the preset threshold or the maximum number of iterations is reached, and output the final routing tree structure. The routing tree simultaneously satisfies the dual constraints of minimizing the total wiring length and optimizing the timing of the critical path.
2. The routing method based on temporal criticality according to claim 1, characterized in that, The weighting coefficient for the total wiring length is k; The critical path length is obtained by weighted summation of the temporal criticality of each load node. The weighting coefficient of the critical path length is 1-k, and the temporal criticality is calculated based on the establishment time margin of the load node.
3. The routing method based on temporal criticality according to claim 1, characterized in that, The path merging optimization steps in step S4 also include: S41. Calculate the merging cost of all load node pairs, where the merging cost is the product of the length of the overlapping path between the two nodes in the routing tree and their temporal criticality. S42. Select the node pair with the highest merging value and merge them. Place the merged virtual node at the end of the overlapping path. S43. Set the temporal criticality of the virtual node to the arithmetic mean of the criticalities of the original two nodes.
4. The routing method based on time-series criticality according to claim 1, characterized in that, The generation of the routing tree in step S3 further includes: S31. Perform shortest path search based on the edge weights, where the edge weights reflect the congestion level of the channel. S32. Generate an initial routing tree by iteratively expanding the minimum path cost node. In each iteration, add the unconnected node closest to the driving node to the tree structure.
5. The routing method based on temporal criticality according to claim 1, characterized in that, The virtual node processing method described in step S5 includes: S51. Position the physical location of the virtual node at the end node of the overlapping path; S52. Inherit the creation time margin constraint of the original node, and take the smaller value of the two nodes as the constraint value of the virtual node. S53. When a virtual node merges with other nodes again, the merge cost is recalculated.
6. A routing system based on temporal criticality, used to execute a routing method based on temporal criticality according to any one of claims 1-5, characterized in that, include: The abstract layout module is used to abstract the chip physical area into a set of nodes and the routing channels between adjacent areas into a set of edges based on the chip design layout results. Each node corresponds to the physical coordinates of the device, and the weight of each edge is determined by the congestion of the channel. The congestion is determined by the number of wirings that have passed through the channel and the number of signals that have passed through the channel. The generation module generates a routing cost function for the target network, wherein the cost function is a weighted sum of the total cabling length and the critical path length; The connection module is used to iteratively expand the routing path with the driver node as the root node and the minimum spanning tree algorithm. Each time, the node connected by the edge that minimizes the sum of the path weight and the distance to the current node is selected and added to the routing tree until all load nodes are covered. The parasitic resistance and capacitance parameters of each path are recorded. The parasitic resistance and capacitance parameters are used to calculate the timing delay from the driver node to the load node. The synthesis module is used to optimize path merging. It traverses all load node pairs, calculates the merging cost of their overlapping paths, and the merging cost is the product of the overlapping path length and the sum of the temporal criticality of the two nodes. The node pair with the largest product value is selected for merging. The merging position is the common node on the overlapping path that is farthest from the driving node. After merging, a virtual node is generated and its temporal criticality is updated to the arithmetic mean of the criticality of the original node. The execution module is used to repeatedly execute the above steps until the merged cost is lower than a preset threshold or the maximum number of iterations is reached, and outputs the final routing tree structure. The routing tree simultaneously satisfies the dual constraints of minimizing the total wiring length and optimizing the timing of the critical path.
7. A routing system based on time-series criticality according to claim 6, characterized in that, The synthesis module further includes: The calculation unit is used to calculate the merging cost of all load node pairs, wherein the merging cost is the product of the sum of the lengths of the overlapping paths of the two nodes in the routing tree and their temporal criticality. The merging unit is used to select the node pair with the highest merging cost and merge them, placing the merged virtual node at the end of the overlapping path. The integration unit is used to set the temporal criticality of the virtual node to the arithmetic mean of the criticalities of the original two nodes.
8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the routing method based on timing criticality as described in any one of claims 1-5.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the routing method based on time criticality as described in any one of claims 1-5.