Pixel circuit, display device and electronic apparatus

Abstract

The invention relates to a pixel circuit, a display device, and an electronic device. The pixel circuit includes a first transistor, a second transistor for applying a data voltage to the first transistor, a third transistor for diode connection of the first transistor, a fourth transistor for applying a first power voltage to a first electrode of the first transistor, and a fifth transistor for diode connection of the second transistor. A fifth transistor for connecting a second electrode of the first transistor and a fourth node, a sixth transistor for applying an initialization voltage, a seventh transistor, an eighth transistor for applying a data voltage to the fifth node in response to a second scan signal, a tenth transistor for applying a second power voltage to the fifth node, and a ninth transistor for applying a ninth power voltage to the ninth node in response to a ninth scan signal. A twelfth transistor for applying an initialization voltage to the fourth node; and a light emitting element. A sweep signal is applied to a control electrode of the first transistor, and the sweep signal is a global signal having the same timing across at least two pixel rows.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a pixel circuit, a display apparatus including the same, and an electronic device including the same. More particularly, embodiments of the present application relate to a pixel circuit which is driven by a pulse width modulation method, performs internal compensation of threshold voltage, and includes a small number of transistors, the pixel circuit being applicable to a display apparatus of ultra-high resolution. BACKGROUND

[0002] Generally, a display apparatus includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. The display panel driver includes a gate driver which provides a gate signal to the gate lines, a data driver which provides a data voltage to the data lines, and a driving controller which controls the gate driver and the data driver.

[0003] A conventional pixel circuit which is driven by a pulse width modulation method and performs internal compensation of threshold voltage can include 19 or more transistors and 3 or more capacitors, so that it is difficult to apply the same to a display apparatus of ultra-high resolution due to a limitation of integration. SUMMARY

[0004] Embodiments of the present application provide a pixel circuit which is driven by a pulse width modulation method, performs internal compensation of threshold voltage, and includes a small number of transistors, the pixel circuit being applicable to a display apparatus of ultra-high resolution.

[0005] Embodiments of the present application also provide a display apparatus including the pixel circuit.

[0006] According to an embodiment, the pixel circuit includes: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor configured to apply a data voltage to the second node in response to a first scan signal; a third transistor configured to connect the first node and the third node in response to the first scan signal; a fourth transistor configured to apply a first power voltage to the second node in response to an emission signal; a fifth transistor configured to connect the third node and a fourth node in response to the emission signal; a sixth transistor configured to apply an initialization voltage to the first node in response to a first initialization signal; a seventh transistor including a control electrode connected to the fourth node, a first electrode connected to a fifth node, and a second electrode connected to a sixth node, and the seventh transistor is configured to generate a drive current; an eighth transistor configured to apply the data voltage to the fifth node in response to a second scan signal; a tenth transistor configured to apply a second power voltage to the fifth node in response to the emission signal; a twelfth transistor configured to apply the initialization voltage to the fourth node in response to a second initialization signal; and a light emitting element configured to emit light based on the drive current. The first transistor and the seventh transistor are P-type transistors, and the second transistor, the third transistor, and the eighth transistor are N-type transistors. A sweep signal is applied to the first node, and the sweep signal is a global signal having the same timing across at least two pixel rows.

[0007] In an embodiment, the second scan signal, the emission signal, the first initialization signal, and the second initialization signal can be global signals.

[0008] In an embodiment, the pixel circuit can further include: a ninth transistor configured to connect the fourth node and the sixth node in response to the second scan signal; an eleventh transistor configured to connect the sixth node and the seventh node in response to the emission signal; and a thirteenth transistor configured to apply a light emitting element initialization voltage to a first electrode of the light emitting element in response to a light emitting element initialization signal.

[0009] In an embodiment, the light emitting element initialization signal can be a global signal.

[0010] In an embodiment, the light emitting element can include a first electrode connected to the seventh node and a second electrode configured to receive a third power voltage. The light emitting element initialization voltage can be lower than the third power voltage.

[0011] In an embodiment, the fourth transistor, the fifth transistor, the tenth transistor, the eleventh transistor, and the thirteenth transistor can be P-type transistors, and the sixth transistor, the ninth transistor, and the twelfth transistor can be N-type transistors.

[0012] In an embodiment, the first transistor can be turned off and the light emitting element can emit light while the seventh transistor is turned on in the emission-on period. The seventh transistor can be turned off and the light emitting element can stop emitting light when the first transistor is turned on in the emission-off period after the emission-on period.

[0013] In an embodiment, in a first period of a frame period in which the pixel circuit is driven, the first initialization signal can have an active level, the second initialization signal can have an active level and the sweep signal can have a high level, and the sixth transistor can be turned on and the twelfth transistor can be turned on.

[0014] In an embodiment, in a second period after the first period, the data voltage can have a pulse width data voltage, the first initialization signal can have a non-active level, the second initialization signal can have a non-active level, the first scan signal can have an active level, the second transistor can be turned on, and the third transistor can be turned on.

[0015] In an embodiment, in a third period after the second period, the data voltage can have a constant current voltage, the first scan signal can have a non-active level, the second scan signal can have an active level, and the eighth transistor can be turned on.

[0016] In an embodiment, in a fourth period after the third period, the emission signal can have an active level, and the sweep signal can be lowered from a high level to a low level lower than the high level.

[0017] In an embodiment, the frame period in which the pixel circuit is driven can include a write frame in which the pulse width data voltage is applied to the pixel circuit and the light emitting element emits light, and a hold frame in which the pulse width data voltage is not applied to the pixel circuit and the light emitting element emits light.

[0018] In an embodiment, in a first hold period of the hold frame, the sweep signal can have a high level, the first initialization signal can have a non-active level, the second initialization signal can have an active level, the emission signal can have a non-active level, the sixth transistor can be turned off, and the twelfth transistor can be turned on.

[0019] In an embodiment, in a second hold period after the first hold period, the second initialization signal can have a non-active level, the first scan signal can have a non-active level, and the twelfth transistor can be turned off.

[0020] In an embodiment, in a third hold period after the second hold period, the data voltage can have a constant current voltage, the second scan signal can have an active level, and the eighth transistor can be turned on.

[0021] In an embodiment, in a fourth hold period after the third hold period, the emission signal can have an active level, and the sweep signal can decrease from a high level to a low level lower than the high level.

[0022] In an embodiment, in the first to fourth hold periods, the data voltage can have a constant current voltage, and the first scan signal can have a non-active level.

[0023] In an embodiment, in the first to fourth hold periods, the first initialization signal can have a non-active level.

[0024] According to an embodiment, a display apparatus includes a display panel including a pixel circuit, a display area, a first peripheral area and a second peripheral area, a gate driver configured to apply a first scan signal to the display area, a data driver configured to apply a data voltage to the display area, a voltage generator configured to apply a global signal having a same timing across at least two pixel rows to the display area, and a driving controller configured to control the gate driver, the data driver, and the voltage generator. The pixel circuit includes a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, a second transistor configured to apply the data voltage to the second node in response to the first scan signal, a third transistor configured to connect the first node and the third node in response to the first scan signal, a fourth transistor configured to apply a first power voltage to the second node in response to an emission signal, a fifth transistor configured to connect the third node and the fourth node in response to the emission signal, a sixth transistor configured to apply an initialization voltage to the first node in response to a first initialization signal, a seventh transistor including a control electrode connected to the fourth node, a first electrode connected to a fifth node, and a second electrode connected to a sixth node, the seventh transistor being configured to generate a driving current, an eighth transistor configured to apply the data voltage to the fifth node in response to a second scan signal, a tenth transistor configured to apply a second power voltage to the fifth node in response to the emission signal, a twelfth transistor configured to apply the initialization voltage to the fourth node in response to a second initialization signal, and a light emitting element configured to emit light based on the driving current. The first transistor and the seventh transistor are P-type transistors, and the second transistor, the third transistor, and the eighth transistor are N-type transistors. The sweep signal is applied to the first node, and the sweep signal is the global signal.

[0025] In an embodiment, the voltage generator can apply a gate clock signal to the gate driver, and apply the emission signal, the first initialization signal, the second initialization signal, the second scan signal, and the sweep signal to the display area.

[0026] In an embodiment, a gate driver can be disposed in the first peripheral area. A display area can be disposed between the first peripheral area and the second peripheral area. An emission line configured to receive an emission signal, a first initialization line configured to receive a first initialization signal, a second initialization line configured to receive a second initialization signal, a second scan signal line configured to receive a second scan signal, and a sweep signal line configured to receive a sweep signal can be disposed in the second peripheral area.

[0027] According to an embodiment, a pixel circuit can include a light emitting element, a pulse width driving circuit configured to generate a pulse width signal, and a constant current driving circuit configured to control emission of the light emitting element based on the pulse width signal. The pulse width driving circuit can include a pulse driving transistor configured to generate the pulse width signal based on a sweep signal that is a global signal having a same timing across at least two pixel rows, a pulse write transistor configured to apply a data voltage to a first electrode of the pulse driving transistor in response to a first scan signal that is a line-by-line scan signal having different timings across the at least two pixel rows, a pulse emission control transistor configured to apply a first power voltage to the first electrode of the pulse driving transistor in response to an emission signal, and a first initialization transistor configured to apply an initialization voltage to a control electrode of the pulse driving transistor in response to a first initialization signal. The constant current driving circuit can include a constant current driving transistor configured to apply a driving current to the light emitting element in response to the pulse width signal, a constant current write transistor configured to apply a constant current voltage to a first electrode of the constant current driving transistor in response to a second scan signal, a constant current emission control transistor configured to apply a second power voltage to the first electrode of the constant current driving transistor in response to the emission signal, and a second initialization transistor configured to apply the initialization voltage to a control electrode of the constant current driving transistor in response to a second initialization signal. The pulse driving transistor and the constant current driving transistor can be P-type transistors, and the pulse write transistor and the constant current write transistor can be N-type transistors.

[0028] In an embodiment, the emission signal, the first initialization signal, the second initialization signal, and the second scan signal can be global signals.

[0029] In an embodiment, the pulse width driving circuit can further include a pulse compensation transistor connected to the control electrode of the pulse driving transistor and a second electrode of the pulse driving transistor. The constant current driving circuit can further include a constant current compensation transistor connected to the control electrode of the constant current driving transistor and a second electrode of the constant current driving transistor.

[0030] In an embodiment, the pulse compensation transistor and the constant current compensation transistor can be N-type transistors.

[0031] According to an embodiment, an electronic device includes a pixel circuit and a power source configured to provide power to the pixel circuit. The pixel circuit includes a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, a second transistor configured to apply a data voltage to the second node in response to a first scan signal, a third transistor configured to connect the first node and the third node in response to the first scan signal, a fourth transistor configured to apply a first power voltage to the second node in response to an emission signal, a fifth transistor configured to connect the third node and a fourth node in response to the emission signal, a sixth transistor configured to apply an initialization voltage to the first node in response to a first initialization signal, a seventh transistor including a control electrode connected to the fourth node, a first electrode connected to a fifth node, and a second electrode connected to a sixth node, and the seventh transistor is configured to generate a driving current at the second electrode, an eighth transistor configured to apply the data voltage to the fifth node in response to a second scan signal, a tenth transistor configured to apply a second power voltage to the fifth node in response to the emission signal, a twelfth transistor configured to apply the initialization voltage to the fourth node in response to a second initialization signal, and a light emitting element configured to emit light based on the driving current. The first transistor and the seventh transistor are P-type transistors, and the second transistor, the third transistor, and the eighth transistor are N-type transistors. A sweep signal is applied to the first node, and the sweep signal is a global signal having a same timing across at least two pixel rows.

[0032] As described above, the pixel circuit can include 13 transistors and 2 capacitors. The pixel circuit can be driven by pulse width modulation, perform internal compensation of a threshold voltage, and include a small number of transistors compared to a conventional pixel circuit, so that the pixel circuit can have a high integration degree. Accordingly, the pixel circuit can be applied to a display device of ultra-high resolution.

[0033] Further, some of the transistors included in the pixel circuit can be N-type transistors, so that power consumption can be effectively reduced. Accordingly, the pixel circuit can stably operate by using a low power voltage. Further, power consumption of the display device can be reduced.

[0034] Further, some of the transistors of the pixel circuit can be P-type transistors, so that mobility can be effectively improved.

[0035] Further, some of the input signals applied to the pixel circuit can be global signals, which are simultaneous signals having a same timing regardless of pixel rows, so that power consumption of the display device can be effectively reduced.

[0036] Further, the emission signal can be a global signal, so that the display apparatus can not include an emission driver. Accordingly, the degree of integration of the display apparatus can be further improved. Further, the power consumption can be further improved.

[0037] Further, the pixel circuit can be driven at a variable frequency, so that the power consumption of the display apparatus can be effectively reduced.

[0038] Further, in the hold frame, some of the input signals can have a direct current (DC) voltage, so that the power consumption of the display apparatus can be further reduced. BRIEF DESCRIPTION OF DRAWINGS

[0039] The illustrative, non-limiting embodiments will be better understood from the following detailed description with reference to the drawings, from which:

[0040] Figure 1 is a block diagram illustrating a display apparatus according to an embodiment of the present application.

[0041] Figure 2 is a circuit diagram illustrating an example of a pixel (or a pixel circuit) of the display panel of Figure 1

[0042] Figure 3 is a timing chart illustrating a timing of signals applied to the pixel circuit of Figure 2

[0043] Figure 4 is a circuit diagram illustrating an operation of the pixel circuit of Figure 2 in a first period.

[0044] Figure 5 is a circuit diagram illustrating an operation of the pixel circuit of Figure 2 in a second period.

[0045] Figure 6 is a circuit diagram illustrating an operation of the pixel circuit of Figure 2 in a third period.

[0046] Figure 7 is a circuit diagram illustrating an operation of the pixel circuit of Figure 2 in a fourth period.

[0047] Figure 8 is a circuit diagram illustrating an operation of the pixel circuit of Figure 2 in a fifth period.

[0048] Figure 9 is a conceptual diagram illustrating a driving frequency of the display panel of Figure 1

[0049] Figure 10 is a timing chart illustrating a timing applied to the pixel circuit in a write frame. ​​​

[0050] Figure 11 is a timing chart showing timing applied to the pixel circuit in the hold frame.

[0051] Figure 12 is a circuit diagram showing operation of the pixel circuit in the first hold period of Figure 2 Figure 11

[0052] Figure 13 is a circuit diagram showing operation of the pixel circuit in the third hold period of Figure 2 Figure 11

[0053] Figure 14 is a circuit diagram showing operation of the pixel circuit in the fourth hold period of Figure 2 Figure 11

[0054] Figure 15 is a circuit diagram showing operation of the pixel circuit in the fifth hold period of Figure 2 Figure 11

[0055] Figure 16 is a diagram showing an example of a position of a drive controller, a data driver, a gate driver, a voltage generator, and a display panel included in the display device of Figure 1

[0056] Figure 17 is a block diagram showing the gate driver included in the display device of Figure 1

[0057] Figure 18 is a block diagram showing an electronic device according to an embodiment of the present application.

[0058] Figure 19 is a diagram showing an example in which the electronic device in Figure 18 is implemented as a smart phone.

[0059] Figure 20 is a diagram showing an example in which the electronic device in Figure 18 is implemented as a smart watch. DETAILED DESCRIPTION

[0060] ​​​​​​​​​​The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, "a," "an," "the," and "at least one" are used interchangeably and mean one or more, unless the context clearly dictates otherwise. For example, "a member" has the same meaning as "at least one member." "At least one" should not be construed as limiting "one" or "one." "Or" means "and / or." As used herein, the term "and / or" includes any combination of one or more of the associated listed items and all combinations of the items. It will also be understood that the terms "comprise" and / or "comprising," or "contain" and / or "containing," when used in this specification, indicate the presence of the stated features, regions, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0061] It will be understood that, although the terms "first," "second," "third," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "a first component," "a first region," "a first layer," or "a first section" discussed below can be called a "second element," "a second component," "a second region," "a second layer," or "a second section." Hereinafter, the present application will be explained in detail with reference to the accompanying drawings.

[0062] Figure 1 is a block diagram illustrating a display apparatus according to an embodiment of the present application.

[0063] Referring to Figure 1 , the display apparatus includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a voltage generator 600.

[0064] The display panel 100 has a display area displaying an image and a peripheral area adjacent to the display area.

[0065] The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels PX electrically connected to the gate lines GL and the data lines DL. The gate lines GL can extend in a first direction D1, and the data lines DL can extend in a second direction D2 crossing the first direction D1. In an embodiment, the plurality of pixels PX can be arranged in a matrix form. A "pixel row" can mean pixels arranged in the same row of the matrix among the plurality of pixels PX, and the plurality of pixels PX can include several pixel rows arranged in a column direction of the matrix.

[0066] The drive controller 200 receives input image data IMG and input control signals CONT from an external device. For example, the input image data IMG can include red image data, green image data, and blue image data. The input image data IMG can include white image data. The input image data IMG can include magenta image data, cyan image data, and yellow image data. The input control signals CONT can include a main clock signal and a data enable signal. The input control signals CONT can further include a vertical synchronization signal and a horizontal synchronization signal.

[0067] The drive controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signals CONT.

[0068] The drive controller 200 generates the first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signals CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 can include a vertical start signal FLM.

[0069] In an embodiment, the gate driver 300 can receive the vertical start signal FLM, and a high voltage VGH, a low voltage VGL, and a gate clock signal from the voltage generator 600. The gate clock signal can include a first clock signal CLK1 and a second clock signal CLK2. The low voltage VGL can be lower than the high voltage VGH.

[0070] The drive controller 200 generates the second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signals CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 can include a horizontal start signal and a load signal.

[0071] The drive controller 200 generates the data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver 500.

[0072] The drive controller 200 generates a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0073] The drive controller 200 generates a fourth control signal CONT4 based on the input control signal CONT for controlling the operation of the voltage generator 600, and outputs the fourth control signal CONT4 to the voltage generator 600.

[0074] Gate driver 300 generates a gate signal for driving gate line GL in response to a first control signal CONT1 received from drive controller 200. Gate driver 300 can output the gate signal to gate line GL. For example, gate driver 300 can... Figure 2 The first scan signal SPWM[n] is sequentially output to the gate line GL.

[0075] In this embodiment, Figure 2 The first scan signal SPWM[n] can be a progressive signal, which has a different timing across each pixel row. In this paper, [n] can refer to the nth pixel row, where n is a positive integer. The receiver of the first scan signal SPWM[n]... Figure 2 The pixel circuitry can be a pixel circuitry included in the nth pixel row. For example, a progressive signal can have different timings across at least two pixel rows.

[0076] In one embodiment, the gate driver 300 may be disposed in the peripheral region. In another embodiment, the gate driver 300 may be integrated into the peripheral region. In yet another embodiment, the gate driver 300 may be located on the peripheral region.

[0077] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0078] For example, the gamma reference voltage generator 400 can be located in the drive controller 200 or in the data driver 500.

[0079] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the drive controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into a data voltage VDATA having an analog type using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage VDATA to the data line DL. In the embodiment, Figure 1 and Figure 2 The data voltage VDATA can include a pulse width data voltage VPWM and a constant current voltage VCCG. Figure 3 Figure 3

[0080] In an embodiment, the data driver 500 can be disposed in the peripheral area. In an embodiment, the data driver 500 can be integrated in the peripheral area.

[0081] The voltage generator 600 generates global signals and power voltages in response to a fourth control signal CONT4 received from the drive controller 200. The "global signals" can be simultaneous signals having the same timing regardless of the pixel row. For example, the global signals can have the same timing across at least two pixel rows. The global signals can include an emission signal EM, a second scan signal SCCG, a first initialization signal VST1, a second initialization signal VST2, and a sweep signal SWEEP. In an embodiment, the global signals can further include a light emitting element initialization signal BCB. The power voltages can include a high power voltage VDD, a third power voltage VSS, an initialization voltage VINT, and a light emitting element initialization voltage VAINT. The high power voltage VDD can include a first power voltage VDD1 and a second power voltage VDD2 different from the first power voltage VDD1. Figure 2 Figure 2 Figure 2 The third power voltage VSS can be lower than the high power voltage VDD.

[0082] Figure 2 is a circuit diagram illustrating an example of a pixel PX (or a pixel circuit PX) of the display panel 100 of Figure 1

[0083] Referring to Figure 2 ​​​​​In this embodiment, the pixel circuit PX can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, a second capacitor C2, and a light emitting element EE. For example, the pixel circuit PX can have a structure of 13T2C (thirteen transistors and two capacitors).

[0084] The first transistor T1 can include a control electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The first transistor T1 can generate a pulse width signal in response to a sweep signal SWEEP. For example, the first transistor T1 can be referred to as a “pulse driving transistor”.

[0085] The second transistor T2 can include a control electrode configured to receive a first scan signal SPWM[n], a first electrode configured to receive a data voltage VDATA, and a second electrode connected to the second node N2. The second transistor T2 can apply the data voltage VDATA to the first transistor T1 in response to the first scan signal SPWM[n]. For example, the second transistor T2 can be referred to as a “pulse writing transistor”.

[0086] The third transistor T3 can include a control electrode configured to receive the first scan signal SPWM[n], a first electrode connected to the third node N3, and a second electrode connected to the first node N1. The third transistor T3 can connect the first node N1 and the third node N3 in response to the first scan signal SPWM[n]. For example, the third transistor can diode-connect the first transistor T1 in response to the first scan signal SPWM[n]. For example, the third transistor T3 can be referred to as a “pulse compensation transistor”.

[0087] The fourth transistor T4 can include a control electrode configured to receive an emission signal EM, a first electrode configured to receive a first power voltage VDD1, and a second electrode connected to the second node N2. The fourth transistor T4 can apply the first power voltage VDD1 to the second node N2 in response to the emission signal EM. For example, the fourth transistor T4 can be referred to as a “pulse emission control transistor”.

[0088] The fifth transistor T5 can include a control electrode configured to receive an emission signal EM, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The fifth transistor T5 can connect the third node N3 and the fourth node N4 in response to the emission signal EM. For example, when the emission signal EM has an activation level and the first transistor T1 is turned on, the fifth transistor T5 can apply the first power voltage VDD1 to the fourth node N4.

[0089] The sixth transistor T6 can include a control electrode configured to receive a first initialization signal VST1, a first electrode configured to receive an initialization voltage VINT, and a second electrode connected to the first node N1. The sixth transistor T6 can apply the initialization voltage VINT to the first node N1 in response to the first initialization signal VST1. For example, the initialization voltage VINT can be a voltage that causes the first transistor T1 to be turned on. For example, the sixth transistor T6 can be referred to as a "first initialization transistor."

[0090] The seventh transistor T7 can include a control electrode connected to the fourth node N4, a first electrode connected to the fifth node N5, and a second electrode connected to the sixth node N6. The seventh transistor T7 can generate a driving current based on a constant current voltage VCCG of the constant current voltage generator 200. Figure 3 The seventh transistor T7 can output the driving current in response to a pulse width signal that is a voltage applied to the fourth node N4. For example, the seventh transistor T7 can be referred to as a "constant current driving transistor."

[0091] The eighth transistor T8 can include a control electrode configured to receive a second scan signal SCCG, a first electrode configured to receive a data voltage VDATA, and a second electrode connected to the fifth node N5. The eighth transistor T8 can apply the data voltage VDATA to the seventh transistor T7 in response to the second scan signal SCCG. For example, the eighth transistor T8 can be referred to as a "constant current writing transistor."

[0092] The ninth transistor T9 can include a control electrode configured to receive the second scan signal SCCG, a first electrode connected to the sixth node N6, and a second electrode connected to the fourth node N4. The ninth transistor T9 can connect the fourth node N4 and the sixth node N6 in response to the second scan signal SCCG. For example, the ninth transistor T9 can diode-connect the seventh transistor T7 in response to the second scan signal SCCG. For example, the ninth transistor T9 can be referred to as a "constant current compensation transistor."

[0093] The tenth transistor T10 can include a control electrode configured to receive an emission signal EM, a first electrode configured to receive a second power voltage VDD2, and a second electrode connected to the fifth node N5. The tenth transistor T10 can apply the second power voltage VDD2 to the fifth node N5 in response to the emission signal EM. For example, the tenth transistor T10 can be referred to as a "constant current emission control transistor."

[0094] The eleventh transistor T11 can include a control electrode configured to receive an emission signal EM, a first electrode connected to the sixth node N6, and a second electrode connected to the seventh node N7. The eleventh transistor T11 can connect the sixth node N6 and the seventh node N7 in response to the emission signal EM. For example, when the emission signal EM has an active level, the eleventh transistor T11 can apply a driving current to the light emitting element EE.

[0095] The twelfth transistor T12 can include a control electrode configured to receive a second initialization signal VST2, a first electrode configured to receive an initialization voltage VINT, and a second electrode connected to the fourth node N4. The twelfth transistor T12 can apply the initialization voltage VINT to the fourth node N4 in response to the second initialization signal VST2. For example, the twelfth transistor T12 can initialize the fourth node N4 in response to the second initialization signal VST2. For example, the initialization voltage VINT can be a voltage that turns on the seventh transistor T7. For example, the twelfth transistor T12 can be referred to as a "second initialization transistor."

[0096] The thirteenth transistor T13 can include a control electrode configured to receive a light emitting element initialization signal BCB, a first electrode configured to receive a light emitting element initialization voltage VAINT, and a second electrode connected to the seventh node N7. The thirteenth transistor T13 can apply the light emitting element initialization voltage VAINT to the seventh node N7 in response to the light emitting element initialization signal BCB. For example, the thirteenth transistor T13 can be referred to as a "light emitting element initialization transistor." For example, the light emitting element initialization voltage VAINT can be lower than the third power voltage VSS. When the light emitting element initialization voltage VAINT is lower than the third power voltage VSS, current leakage flowing through the light emitting element EE can be reduced. Accordingly, a black characteristic of the pixel circuit PX can be effectively improved.

[0097] The first capacitor C1 can include a first electrode configured to receive a sweep signal SWEEP and a second electrode connected to the first node N1.

[0098] The second capacitor C2 can include a first electrode configured to receive a second power voltage VDD2 and a second electrode connected to the fourth node N4.

[0099] The light emitting element EE can include a first electrode connected to the seventh node N7 and a second electrode configured to receive the third power voltage VSS. For example, the first electrode of the light emitting element EE can be an anode. For example, the second electrode of the light emitting element EE can be a cathode. The light emitting element EE can emit light based on a driving current. For example, the light emitting element EE can be a light emitting diode. In an embodiment, the light emitting element EE can be a micro light emitting diode.

[0100] In an embodiment, the pixel circuit PX can include a pulse width driving circuit and a constant current driving circuit.

[0101] The "pulse width driving circuit" can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1.

[0102] The "constant current driving circuit" can include a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a second capacitor C2.

[0103] In the present embodiment, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, and the thirteenth transistor T13 can be P-type transistors. The second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the twelfth transistor T12 can be N-type transistors. For example, the P-type transistors can be low temperature poly-silicon ("LTPS") transistors. For example, the N-type transistors can be oxide transistors.

[0104] In the present embodiment, the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the twelfth transistor T12 can be N-type transistors. Accordingly, current leakage of the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the twelfth transistor T12 is reduced, so that the pixel circuit PX can stably operate by using a low power voltage. Accordingly, by the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the twelfth transistor T12, power consumption of the display apparatus can be effectively reduced.

[0105] Figure 3 is a timing chart illustrating a timing of signals applied to Figure 2 the pixel circuit PX.

[0106] Referring to Figure 3The frame period 1 FRAME can include a first period TP1A, a second period TP2A, a third period TP3A, a fourth period TP4A, and a fifth period TP5A.

[0107] In the first period TP1A, the first initialization signal VST1 can have an active level, the second initialization signal VST2 can have an active level, the first scan signal SPWM[n] can have a non-active level, the second scan signal SCCG can have a non-active level, the emission signal EM can have a non-active level, the sweep signal SWEEP can have a high level, and the light emitting element initialization signal BCB can have an active level.

[0108] In this document, when a transistor is a P-type transistor, an active level can be a low level, and a non-active level can be a high level. Further, when a transistor is an N-type transistor, an active level is a high level, and a non-active level is a low level.

[0109] In the second period TP2A after the first period TP1A, the data voltage VDATA can have a pulse width data voltage VPWM, the first initialization signal VST1 can have a non-active level, the second initialization signal VST2 can have a non-active level, the first scan signal SPWM[n] can have an active level, the second scan signal SCCG can have a non-active level, the emission signal EM can have a non-active level, the sweep signal SWEEP can have a high level, and the light emitting element initialization signal BCB can have an active level. In the second period TP2A, the first scan signal SPWM[n] can be sequentially applied to the pixel rows.

[0110] In the third period TP3A after the second period TP2A, the data voltage VDATA can have a constant current voltage VCCG, the first initialization signal VST1 can have a non-active level, the second initialization signal VST2 can have a non-active level, the first scan signal SPWM[n] can have a non-active level, the second scan signal SCCG can have an active level, the emission signal EM can have a non-active level, the sweep signal SWEEP can have a high level, and the light emitting element initialization signal BCB can have an active level.

[0111] In a fourth period TP4A after the third period TP3A, the first initialization signal VST1 can have a non-activation level, the second initialization signal VST2 can have a non-activation level, the first scan signal SPWM[n] can have a non-activation level, the second scan signal SCCG can have a non-activation level, the emission signal EM can have an activation level, the sweep signal SWEEP can gradually decrease from a high level to a low level lower than the high level, and the light emitting element initialization signal BCB can have a non-activation level. The fourth period TP4A can be referred to as an "emission-on period".

[0112] In a fifth period TP5A after the fourth period TP4A, the first initialization signal VST1 can have a non-activation level, the second initialization signal VST2 can have a non-activation level, the first scan signal SPWM[n] can have a non-activation level, the second scan signal SCCG can have a non-activation level, the emission signal EM can have an activation level, the sweep signal SWEEP can gradually decrease to a lower low level, and the light emitting element initialization signal BCB can have a non-activation level. The fifth period TP5A can be referred to as an "emission-off period".

[0113] Figure 4 is a circuit diagram illustrating an operation of the pixel circuit PX in the first period TP1A. Figure 2

[0114] Referring to Figure 3 and Figure 4 In the first period TP1A, the sixth transistor T6 can be turned on in response to the first initialization signal VST1. Thus, the initialization voltage VINT can be applied to the first node N1. Thus, the first node N1 can be initialized. For example, the first node N1 can be initialized to the initialization voltage VINT.

[0115] In the first period TP1A, the thirteenth transistor T13 can be turned on in response to the light emitting element initialization signal BCB. Thus, the light emitting element initialization voltage VAINT can be applied to the seventh node N7. Thus, the seventh node N7 can be initialized to the light emitting element initialization voltage VAINT.

[0116] In the first period TP1A, the first transistor T1 can be turned on in response to the voltage of the first node N1. Further, the seventh transistor T7 can be turned on in response to the voltage of the fourth node N4.

[0117] Figure 5 is a circuit diagram illustrating an operation of the pixel circuit PX in the second period TP2A. Figure 2

[0118] Referring to Figure 3 and​​Figure 5 In the second period TP2A, the data voltage VDATA can have a pulse width data voltage VPWM. The pulse width data voltage VPWM can have the same or different voltage level from another pixel according to the emission intensity of each pixel. In an embodiment, the pulse width data voltage VPWM can have a pulse shape (e.g., a trapezoidal shape) that is periodically repeated during the second period TP2A.

[0119] In the second period TP2A, the second transistor T2 can be turned on in response to the first scan signal SPWM[n]. The second transistor T2 can apply the pulse width data voltage VPWM to the second node N2. In an embodiment, the first scan signal SPWM[n] can have a pulse shape (e.g., a square wave shape) that is periodically repeated during the second period TP2A and synchronized with the pulse width data voltage VPWM, such that when the second transistor T2 is turned on in response to the first scan signal SPWM[n], the second transistor T2 can apply the pulse width data voltage VPWM of a high level to the second node N2. This state of the first scan signal SPWM[n] can be considered as an "active level" of the first scan signal SPWM[n].

[0120] In the second period TP2A, the third transistor T3 can be turned on in response to the first scan signal SPWM[n]. Accordingly, the pulse width data voltage VPWM can be applied to the second node N2. Also, the first transistor T1 can be turned on in response to the voltage of the first node N1. Also, the third transistor T3 can diode-connect the first transistor T1, such that a voltage compensated for the threshold voltage of the first transistor T1 can be applied to the first node N1. For example, a pulse width compensation voltage that is the sum of the pulse width data voltage VPWM and the threshold voltage of the first transistor T1 can be applied to the first node N1.

[0121] In the second period TP2A, the thirteenth transistor T13 can be turned on in response to the light emitting element initialization signal BCB. Accordingly, the light emitting element initialization voltage VAINT can be applied to the seventh node N7.

[0122] Figure 6 is a circuit diagram illustrating an operation of the pixel circuit PX in the third period TP3A. Figure 2 is a circuit diagram illustrating an operation of the pixel circuit PX in the third period TP3A.

[0123] Referring to Figure 3 and Figure 6In the third period TP3A, the data voltage VDATA can have the constant current voltage VCCG. The constant current voltage VCCG can have the same voltage level for all pixels. Alternatively, the constant current voltage VCCG can have a first voltage level for red pixels, a second voltage level different from the first voltage level for green pixels, and a third voltage level different from the first voltage level and the second voltage level for blue pixels.

[0124] In the third period TP3A, the eighth transistor T8 can be turned on in response to the second scan signal SCCG. The eighth transistor T8 can apply the constant current voltage VCCG to the fifth node N5.

[0125] In the third period TP3A, the ninth transistor T9 can be turned on in response to the second scan signal SCCG. Accordingly, the constant current voltage VCCG can be applied to the fifth node N5. In addition, the seventh transistor T7 can be turned on in response to the voltage of the fourth node N4. Further, the ninth transistor T9 can diode-connect the seventh transistor T7 so that a voltage compensated for the threshold voltage of the seventh transistor T7 can be applied to the fourth node N4. For example, a constant current compensation voltage that is the sum of the constant current voltage VCCG and the threshold voltage of the seventh transistor T7 can be applied to the fourth node N4.

[0126] In the third period TP3A, the thirteenth transistor T13 can be turned on in response to the light emitting element initialization signal BCB. Accordingly, the light emitting element initialization voltage VAINT can be applied to the seventh node N7.

[0127] Figure 7 is a circuit diagram illustrating Figure 2 operation of the pixel circuit PX in the fourth period TP4A.

[0128] Referring to Figure 3 and Figure 7 In the fourth period TP4A, the fourth transistor T4 can be turned on in response to the emission signal EM. In the fourth period TP4A, the fifth transistor T5 can be turned on in response to the emission signal EM. In the fourth period TP4A, the tenth transistor T10 can be turned on in response to the emission signal EM. In the fourth period TP4A, the eleventh transistor T11 can be turned on in response to the emission signal EM. Further, the thirteenth transistor T13 can be turned off in response to the light emitting element initialization signal BCB. Accordingly, the drive current can be applied to the light emitting element EE. Accordingly, the light emitting element EE can emit light.

[0129] In the fourth period TP4A, the sweep signal SWEEP can gradually decrease from the high level to the low level. Accordingly, the voltage of the first node N1 can gradually decrease.

[0130] Figure 8 is a circuit diagram illustrating Figure 2 operation of the pixel circuit PX in the fifth period TP5A.

[0131] Referring to Figure 3 and Figure 8 In the fifth period TP5A, the sweep signal SWEEP can gradually decrease to a low level. The voltage of the first node N1 can gradually decrease. When the voltage of the first node N1 is lower than the threshold voltage of the first transistor T1, the first transistor T1 can be turned on. When the first transistor T1 is turned on, the first power voltage VDD1 can be applied to the fourth node N4. When the first power voltage VDD1 is applied to the fourth node N4, the seventh transistor T7 can be turned off. When the seventh transistor T7 is turned off, the light emitting element EE can stop emitting light. In the fifth period TP5A, the voltage applied to the fourth node N4 can be the pulse width signal.

[0132] The point in time at which the first transistor T1 is turned on can be determined by the pulse width data voltage VPWM applied to the control electrode of the first transistor T1.

[0133] According to the present embodiment, the pixel circuit PX can include 13 transistors and 2 capacitors. The pixel circuit PX driven by the pulse width modulation performs internal compensation of the threshold voltage, and the pixel circuit PX includes a small number of transistors, so that the integration of the pixel circuit PX can be effectively improved. Therefore, the pixel circuit PX can be suitable for a display device of ultra-high resolution.

[0134] Further, the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the twelfth transistor T12 included in the pixel circuit PX can be N-type transistors. Therefore, the pixel circuit PX can stably operate by using a low power voltage. Therefore, by the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the twelfth transistor T12, the power consumption of the display device can be effectively reduced.

[0135] Further, the first transistor T1 and the seventh transistor T7 can be P-type transistors, so that the mobility can be effectively improved.

[0136] Further, the light emitting element initialization voltage VAINT applied to the first electrode of the thirteenth transistor T13 can be lower than the third power voltage VSS applied to the cathode of the light emitting element EE, so that the black characteristics of the pixel circuit PX can be effectively improved.

[0137] Further, the sweep signal SWEEP can be a global signal, so that the power consumption of the display device can be effectively reduced. Further, the first initialization signal VST1, the second initialization signal VST2, the second scan signal SCCG, the emission signal EM, and the light emitting element initialization signal BCB can be global signals, so that the power consumption of the display device can be further improved.

[0138] Further, the emission signal EM can be a global signal, so that the display device can not include an emission driver. Thus, the integration of the display device can be further improved. Further, the power consumption can be further improved.

[0139] Figure 9 is a conceptual diagram illustrating a driving frequency of the display panel 100. Figure 1 is a timing chart illustrating a timing applied to the pixel circuit PX in a write frame. Figure 10 is a timing chart illustrating a timing applied to the pixel circuit PX in a hold frame. Figure 11 is a timing chart illustrating a timing applied to the pixel circuit PX in a hold frame.

[0140] The display panel 100 according to the present embodiment can be driven at a variable frequency, except that the display panel 100 is driven at a variable frequency. The driving timing of the display panel 100 according to the present embodiment is basically the same as that described with reference to Figure 2 to Figure 8 , so that the same reference numerals will be used, and any repetitive explanation related to the above-described elements will be omitted.

[0141] Referring to Figure 1 , Figure 9 to Figure 11 , the display panel 100 can be driven at a variable frequency. A first frame FR1 having a first frequency can include a first active period AC1 and a first blanking period BL1. A second frame FR2 having a second frequency different from the first frequency can include a second active period AC2 and a second blanking period BL2. A third frame FR3 having a third frequency different from the first frequency and the second frequency can include a third active period AC3 and a third blanking period BL3.

[0142] The length of the first active period AC1 and the length of the second active period AC2 can be the same, and the length of the first blanking period BL1 and the length of the second blanking period BL2 can be different.

[0143] The length of the second active period AC2 and the length of the third active period AC3 can be the same, and the length of the second blanking period BL2 and the length of the third blanking period BL3 can be different.

[0144] A display device supporting a variable frequency can include a write frame in which a data voltage is written to a pixel, and a hold frame in which a data voltage is not written to a pixel and only light emission is performed. The write frame can be arranged within an active period AC1, AC2, and AC3. The hold frame can be arranged within a blanking period BL1, BL2, and BL3.

[0145] For example, in the write frame, a pulse width data voltage VPWM can be applied to the first transistor T1, and the light emitting element EE can emit light. For example, in the hold frame, the pulse width data voltage VPWM can not be applied to the first transistor T1, and the light emitting element EE can emit light.

[0146] Figure 10 The driving timing of the write frame of the display device 1 can be substantially the same as the driving timing of the display device 2. Figure 3

[0147] The hold frame of the display device 1 can include a first hold period TP1B, a second hold period TP2B, a third hold period TP3B, a fourth hold period TP4B, and a fifth hold period TP5B. Figure 11 In the first hold period TP1B, the first initialization signal VST1 can have a non-activation level, the second initialization signal VST2 can have an activation level, the first scan signal SPWM[n] can have a non-activation level, the second scan signal SCCG can have a non-activation level, the emission signal EM can have a non-activation level, the sweep signal SWEEP can have a high level, and the light emitting element initialization signal BCB can have an activation level.

[0148] In the second hold period TP2B after the first hold period TP1B, the first initialization signal VST1 can have a non-activation level, the second initialization signal VST2 can have a non-activation level, the first scan signal SPWM[n] can have a non-activation level, the second scan signal SCCG can have a non-activation level, the emission signal EM can have a non-activation level, the sweep signal SWEEP can have a high level, and the light emitting element initialization signal BCB can have an activation level.

[0149] In the third hold period TP3B after the second hold period TP2B, the first initialization signal VST1 can have a non-activation level, the second initialization signal VST2 can have a non-activation level, the first scan signal SPWM[n] can have a non-activation level, the second scan signal SCCG can have an activation level, the emission signal EM can have a non-activation level, the sweep signal SWEEP can have a high level, and the light emitting element initialization signal BCB can have an activation level.

[0150]

[0151] ​In the fourth hold period TP4B after the third hold period TP3B, the first initialization signal VST1 can have the inactive level, the second initialization signal VST2 can have the inactive level, the first scan signal SPWM[n] can have the inactive level, the second scan signal SCCG can have the inactive level, the emission signal EM can have the active level, the sweep signal SWEEP can gradually decrease from the high level to the low level, and the light emitting element initialization signal BCB can have the inactive level.

[0152] In the fifth hold period TP5B after the fourth hold period TP4B, the first initialization signal VST1 can have the inactive level, the second initialization signal VST2 can have the inactive level, the first scan signal SPWM[n] can have the inactive level, the second scan signal SCCG can have the inactive level, the emission signal EM can have the active level, the sweep signal SWEEP can gradually decrease to the low level, and the light emitting element initialization signal BCB can have the inactive level.

[0153] In the hold frame, the first initialization signal VST1 and the first scan signal SPWM[n] can have the inactive level. In the hold frame, the data voltage VDATA can have the constant current voltage VCCG.

[0154] Figure 12 is a circuit diagram illustrating an operation of the pixel circuit PX in the first hold period TP1B of Figure 2 Figure 11

[0155] Referring to Figure 11 and Figure 12 In the first hold period TP1B after the write frame, the first initialization signal VST1 can have the inactive level, and the sweep signal SWEEP can have the high level. The sixth transistor T6 can be turned off in response to the first initialization signal VST1. The first capacitor C1 can couple the sweep signal SWEEP and apply a coupled voltage to the first node N1. Accordingly, the voltage of the first node N1 can be the pulse width compensation voltage of the write frame.

[0156] In the first hold period TP1B, the twelfth transistor T12 can be turned on in response to the second initialization signal VST2. Accordingly, the initialization voltage VINT can be applied to the fourth node N4.

[0157] In the first hold period TP1B, the thirteenth transistor T13 can be turned on in response to the light emitting element initialization signal BCB. Accordingly, the light emitting element initialization voltage VAINT can be applied to the seventh node N7.

[0158] Figure 13 ​​It is shown Figure 2 The pixel circuit PX in Figure 11 The circuit diagram for the operation in the third holding cycle TP3B.

[0159] Reference Figure 11 and Figure 13 In the third hold period TP3B following the first hold period TP1B, the second scan signal SCCG can have an active level. In the third hold period TP3B, the eighth transistor T8 can be turned on in response to the second scan signal SCCG. In the third hold period TP3B, the ninth transistor T9 can be turned on in response to the second scan signal SCCG. Therefore, a constant current voltage VCCG can be applied to the fourth node N4. In the third hold period TP3B, the voltage at the fourth node N4 can be a constant current voltage.

[0160] Figure 14 It is shown Figure 2 The pixel circuit PX in Figure 11 The circuit diagram for the operation in the fourth holding cycle TP4B.

[0161] Reference Figure 11 and Figure 14 During the fourth hold period TP4B, the fourth transistor T4 can be turned on in response to the emission signal EM. During the fourth hold period TP4B, the fifth transistor T5 can be turned on in response to the emission signal EM. During the fourth hold period TP4B, the tenth transistor T10 can be turned on in response to the emission signal EM. During the fourth hold period TP4B, the eleventh transistor T11 can be turned on in response to the emission signal EM. Furthermore, the thirteenth transistor T13 can be turned off in response to the light-emitting element initialization signal BCB. Therefore, a drive current can be applied to the light-emitting element EE. Therefore, the light-emitting element EE can emit light.

[0162] During the fourth hold period TP4B, the sweep signal SWEEP can gradually decrease from a high level to a low level. Therefore, the voltage of the first node N1 can gradually decrease.

[0163] Figure 15 It is shown Figure 2 The pixel circuit PX in Figure 11 The circuit diagram for the operation of TP5B in the fifth holding cycle.

[0164] Reference Figure 11 and Figure 15In the fifth holding period TP5B, the sweep signal SWEEP can gradually decrease to a low level. The voltage of the first node N1 can gradually decrease. When the voltage of the first node N1 is lower than the threshold voltage of the first transistor T1, the first transistor T1 can be turned on. When the first transistor T1 is turned on, the first power voltage VDD1 can be applied to the fourth node N4. When the first power voltage VDD1 is applied to the fourth node N4, the seventh transistor T7 can be turned off. When the seventh transistor T7 is turned off, the light emitting element EE can stop emitting light.

[0165] The point in time when the first transistor T1 is turned on can be determined by the pulse width data voltage VPWM applied to the control electrode of the first transistor T1 in the write frame.

[0166] According to the present embodiment, the pixel circuit PX can include 13 transistors and 2 capacitors. The pixel circuit PX driven by the pulse width modulation performs internal compensation of the threshold voltage, and the pixel circuit PX includes a small number of transistors, so that the integration of the pixel circuit PX can be effectively improved. Therefore, the pixel circuit PX can be suitable for a display device of ultra-high resolution.

[0167] Further, the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the twelfth transistor T12 included in the pixel circuit PX can be N-type transistors. Therefore, the pixel circuit PX can stably operate by using a low power voltage. Therefore, by the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the twelfth transistor T12, the power consumption of the display device can be effectively reduced.

[0168] Further, the first transistor T1 and the seventh transistor T7 can be P-type transistors, so that the mobility can be effectively improved.

[0169] Further, the light emitting element initialization voltage VAINT applied to the first electrode of the thirteenth transistor T13 can be lower than the third power voltage VSS applied to the cathode of the light emitting element EE, so that the black characteristics of the pixel circuit PX can be effectively improved.

[0170] Further, the sweep signal SWEEP can be a global signal, so that the power consumption of the display device can be effectively reduced. Further, the first initialization signal VST1, the second initialization signal VST2, the second scan signal SCCG, the emission signal EM, and the light emitting element initialization signal BCB can be global signals, so that the power consumption of the display device can be further improved.

[0171] Furthermore, the transmitted signal EM can be a global signal, allowing the display device to function without a transmitter driver. This further improves the integration of the display device and reduces power consumption.

[0172] Furthermore, in this embodiment, the pixel circuit PX can be driven at a variable frequency, which can effectively reduce the power consumption of the display device.

[0173] Furthermore, in this embodiment, during the hold frame, the data voltage VDATA can have a constant current voltage VCCG, and the first initialization signal VST1 and the first scan signal SPWM[n] can have an inactive level, which further reduces the power consumption of the display device.

[0174] Figure 16 It is shown that it includes Figure 1 A diagram showing an example of the positions of the drive controller 200, data driver 500, gate driver 300, voltage generator 600, and display panel 100 in a display device.

[0175] Reference Figure 1 and Figure 16 The display panel 100 may include a display area AA and a peripheral area. The peripheral area may include a first peripheral area DS1 and a second peripheral area DS2. The display panel 100 may include a vertical start signal line FLML, a first clock signal line CLK1L, a second clock signal line CLK2L, a high voltage line VGHL, a low voltage line VGLL, an emission line EML, a second scan signal line SCCGL, a first initialization line VST1L, a second initialization line VST2L, a light-emitting element initialization line BCBL, and a sweep signal line SWEEPL. The vertical start signal FLM can be applied to the vertical start signal line FLML. The first clock signal CLK1 can be applied to the first clock signal line CLK1L. The second clock signal CLK2 can be applied to the second clock signal line CLK2L. The high voltage VGH can be applied to the high voltage line VGHL. The low voltage VGL can be applied to the low voltage line VGLL. The emission signal EM can be applied to the emission line EML. The second scan signal SCCG can be applied to the second scan signal line SCCGL. The first initialization signal VST1 can be applied to the first initialization line VST1L. The second initialization signal VST2 can be applied to the second initialization line VST2L. The light-emitting element initialization signal BCB can be applied to the light-emitting element initialization line BCBL. The sweep signal SWEEP can be applied to the sweep signal line SWEEPL.

[0176] In this embodiment, the gate driver 300 can receive a vertical start signal FLM, a first clock signal CLK1, a second clock signal CLK2, a high voltage VGH, and a low voltage VGL from the voltage generator 600. The gate driver 300 can generate first scan signals SPWM[1], SPWM[2] to SPWM[n] based on the vertical start signal FLM, the first clock signal CLK1, the second clock signal CLK2, the high voltage VGH, and the low voltage VGL.

[0177] The gate driver 300 can be disposed in the first peripheral region DS1. The emitter line EML, the second scan signal line SCCGL, the first initialization line VST1L, the second initialization line VST2L, the light-emitting element initialization line BCBL, and the sweep signal line SWEEPL can be disposed in the second peripheral region DS2. Conversely, when the gate driver 300 is disposed in the second peripheral region DS2, the emitter line EML, the second scan signal line SCCGL, the first initialization line VST1L, the second initialization line VST2L, the light-emitting element initialization line BCBL, and the sweep signal line SWEEPL can be disposed in the first peripheral region DS1.

[0178] The dimensions of the first outer region DS1 and the second outer region DS2 can be changed by the user.

[0179] In this embodiment, the transmit signal EM, the sweep signal SWEEP, the second scan signal SCCG, the first initialization signal VST1, and the second initialization signal VST2 can be global signals. Therefore, the display device may not include a transmit driver and a sweep signal driver. This further reduces the power consumption of the display device.

[0180] Figure 17 It is shown that it includes Figure 1 A block diagram of the gate driver 300 in a display device.

[0181] Reference Figure 1 , Figure 16 and Figure 17 The gate driver 300 may include multiple stages STAGE 1, STAGE 2, STAGE 3, STAGE 4... In the multiple stages STAGE 1, STAGE 2, STAGE 3, STAGE 4..., it receives the vertical start signal FLM, the first clock signal CLK1 and the second clock signal CLK2, and sequentially outputs the first scan signals SPWM[1], SPWM[2], SPWM[3], SPWM[4]... to multiple pixels row by row.

[0182] The first clock signal CLK1 and the second clock signal CLK2 can be applied to the first clock terminal CLK1T and the second clock terminal CLK2T of the first stage 1, respectively. The first clock signal CLK1 and the second clock signal CLK2 can be applied to the second clock terminal CLK2T and the first clock terminal CLK1T of the second stage 2, respectively. Similarly, the first clock signal CLK1 and the second clock signal CLK2 can be applied to the first clock terminal CLK1T and the second clock terminal CLK2T of the third stage 3, respectively. The first clock signal CLK1 and the second clock signal CLK2 can be applied to the second clock terminal CLK2T and the first clock terminal CLK1T of the fourth stage 4, respectively.

[0183] Figure 18 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the present invention. Figure 19 It is shown Figure 18 The diagram shows an example of an electronic device 1000 implemented as a smartphone.

[0184] Reference Figure 18 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. In this document, the display device 1060 may be... Figure 1 The display device. In addition, the electronic device 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, other electronic devices, etc.

[0185] In an embodiment, such as Figure 19 As shown, electronic device 1000 can be implemented as a smartphone. However, electronic device 1000 is not limited to this. For example, electronic device 1000 can be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer, and head-mounted display (HMD) device, etc.

[0186] Processor 1010 can perform various computing functions or tasks. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be coupled to other components via address bus, control bus, data bus, etc. In addition, processor 1010 can be coupled to expansion buses, such as peripheral component interconnect (PCI) bus.

[0187] Processor 1010 can process input image data IMG (refer to...) Figure 1 ), application enable signal (APPON) and input control signal CONT (see reference)Figure 1 Output to Figure 1 The drive controller 200.

[0188] The memory device 1020 can store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device, etc.).

[0189] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, and CD-ROM drives, etc. I / O device 1040 may include input devices such as keyboards, keypads, mouse devices, touchpads, and touchscreens, as well as output devices such as printers and speakers. In some embodiments, display device 1060 may be included in I / O device 1040. Power supply 1050 provides power for the operation of electronic device 1000. Display device 1060 may be coupled to other components via a bus or other communication link.

[0190] Reference Figure 19 The electronic device of the present invention is shown as a smartphone, but the invention is not limited thereto. The electronic device may be a television set, a monitor, a laptop computer, or a tablet computer. Additionally, the electronic device may be an automobile.

[0191] Figure 20 It is shown Figure 18 The diagram shows an example of an electronic device implemented as a smartwatch.

[0192] Reference Figure 18 and Figure 20 The electronic device 1000 can be implemented as a smartwatch. A smartwatch can be an example of an electronic device 1000 that requires an ultra-high resolution display panel.

[0193] The display device according to the embodiment can be applied to display devices included in computers, laptops, mobile phones, smartphones, smart tablets, portable media players (PMPs), personal digital assistants (PDAs), or Motion Picture Experts Compression Standard Audio Layer 3 (MP3) players, etc.

[0194] The foregoing is illustrative of the invention and should not be construed as limiting it. Although several embodiments of the invention have been described, those skilled in the art will readily understand that many modifications are possible in the embodiments without departing from the novel teachings and advantages of the invention. Therefore, all such modifications are intended to be included within the scope of the invention as defined in the claims. In the claims, the device (or means) plus function clause is intended to cover structures described herein that perform the functions referenced, and not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of the invention and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The invention is defined by the claims, and equivalents of the claims are included therein.

Claims

1. A pixel circuit, wherein, The pixel circuit includes: The first transistor includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; The second transistor is configured to apply a data voltage to the second node in response to the first scan signal; A third transistor is configured to connect the first node and the third node in response to the first scan signal; A fourth transistor is configured to apply a first electrical voltage to the second node in response to a transmit signal; The fifth transistor is configured to connect the third node and the fourth node in response to the transmitted signal; The sixth transistor is configured to apply an initialization voltage to the first node in response to a first initialization signal; The seventh transistor includes a control electrode connected to the fourth node, a first electrode connected to the fifth node, and a second electrode connected to the sixth node, and the seventh transistor is configured to generate a drive current; The eighth transistor is configured to apply the data voltage to the fifth node in response to the second scan signal; The tenth transistor is configured to apply a second electrical voltage to the fifth node in response to the transmitted signal; The twelfth transistor is configured to apply the initialization voltage to the fourth node in response to a second initialization signal; and The light-emitting element is configured to emit light based on the driving current. Wherein, the first transistor and the seventh transistor are P-type transistors, and the second transistor, the third transistor, and the eighth transistor are N-type transistors. The sweep frequency signal is applied to the first node, and the sweep frequency signal is a global signal with the same timing across at least two pixel rows.

2. The pixel circuit according to claim 1, wherein, The second scanning signal, the transmission signal, the first initialization signal, and the second initialization signal are the global signals.

3. The pixel circuit according to claim 1, wherein, The pixel circuit also includes: The ninth transistor is configured to connect the fourth node and the sixth node in response to the second scan signal; The eleventh transistor is configured to connect the sixth and seventh nodes in response to the transmit signal; and The thirteenth transistor is configured to apply an initialization voltage to the first electrode of the light-emitting element in response to an initialization signal.

4. The pixel circuit according to claim 3, wherein, The initialization signal for the light-emitting element is the global signal.

5. The pixel circuit according to claim 3, wherein, The light-emitting element includes a first electrode connected to the seventh node and a second electrode configured to receive a third electrical voltage, and The initial voltage of the light-emitting element is lower than the third power voltage.

6. The pixel circuit according to claim 3, wherein, The fourth, fifth, tenth, eleventh, and thirteenth transistors are P-type transistors, and the sixth, ninth, and twelfth transistors are N-type transistors.

7. The pixel circuit according to claim 1, wherein, During the emission activation cycle, the first transistor is turned off, and the light-emitting element emits light simultaneously with the seventh transistor being turned on. In the emission off cycle following the emission on cycle, when the first transistor is turned on, the seventh transistor is turned off, and the light-emitting element stops emitting light.

8. The pixel circuit according to claim 1, wherein, In the first period of the frame cycle in which the pixel circuit is driven, the first initialization signal has an active level, the second initialization signal has an active level and the sweep signal has a high level, and the sixth transistor is turned on and the twelfth transistor is turned on.

9. The pixel circuit according to claim 8, wherein, In the second cycle following the first cycle, the data voltage has a pulse width data voltage, the first initialization signal has an inactive level, the second initialization signal has an inactive level, the first scan signal has an active level, the second transistor is turned on, and the third transistor is turned on.

10. The pixel circuit according to claim 9, wherein, In the third cycle following the second cycle, the data voltage has a constant current voltage, the first scan signal has an inactive level, the second scan signal has an active level, and the eighth transistor is turned on.

11. The pixel circuit according to claim 10, wherein, In the fourth cycle following the third cycle, the transmitted signal has an activation level, and the sweep signal decreases from the high level to a low level below the high level.

12. The pixel circuit according to claim 1, wherein, The frame cycle in which the pixel circuit is driven includes a write frame and a hold frame. In the write frame, a pulse width data voltage is applied to the pixel circuit and the light-emitting element emits light. In the hold frame, the pulse width data voltage is not applied to the pixel circuit and the light-emitting element emits light.

13. The pixel circuit according to claim 12, wherein, During the first hold period of the hold frame, the sweep signal is high, the first initialization signal is inactive, the second initialization signal is active, the transmit signal is inactive, the sixth transistor is off, and the twelfth transistor is on.

14. The pixel circuit according to claim 13, wherein, In the second hold period following the first hold period, the second initialization signal has an inactive level, the first scan signal has an inactive level, and the twelfth transistor is turned off.

15. The pixel circuit according to claim 14, wherein, In the third hold period following the second hold period, the data voltage has a constant current voltage, the second scan signal has an activation level, and the eighth transistor is turned on.

16. The pixel circuit according to claim 15, wherein, In the fourth hold period following the third hold period, the transmit signal has an activation level, and the sweep signal decreases from the high level to a low level below the high level.

17. The pixel circuit according to claim 16, wherein, During the first hold period to the fourth hold period, the data voltage has the constant current voltage, and the first scan signal has the inactive level.

18. The pixel circuit according to claim 16, wherein, During the first hold period to the fourth hold period, the first initialization signal has the inactive level.

19. A display device, wherein, The display device includes: The display panel includes pixel circuitry, a display area, a first peripheral area, and a second peripheral area. A gate driver is configured to apply a first scan signal to the display area; A data driver is configured to apply a data voltage to the display area; A voltage generator is configured to apply a global signal with the same timing across at least two pixel rows to the display area; and The drive controller is configured to control the gate driver, the data driver, and the voltage generator. The pixel circuit includes: The first transistor includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; The second transistor is configured to apply the data voltage to the second node in response to the first scan signal; A third transistor is configured to connect the first node and the third node in response to the first scan signal; A fourth transistor is configured to apply a first electrical voltage to the second node in response to a transmit signal; The fifth transistor is configured to connect the third node and the fourth node in response to the transmitted signal; The sixth transistor is configured to apply an initialization voltage to the first node in response to a first initialization signal; The seventh transistor includes a control electrode connected to the fourth node, a first electrode connected to the fifth node, and a second electrode connected to the sixth node, and the seventh transistor is configured to generate a drive current; The eighth transistor is configured to apply the data voltage to the fifth node in response to the second scan signal; The tenth transistor is configured to apply a second electrical voltage to the fifth node in response to the transmitted signal; The twelfth transistor is configured to apply the initialization voltage to the fourth node in response to a second initialization signal; and The light-emitting element is configured to emit light based on the driving current. Wherein, the first transistor and the seventh transistor are P-type transistors, and the second transistor, the third transistor, and the eighth transistor are N-type transistors. The frequency sweep signal is applied to the first node, and the frequency sweep signal is the global signal.

20. The display device according to claim 19, wherein, The voltage generator applies a gate clock signal to the gate driver and applies the transmit signal, the first initialization signal, the second initialization signal, the second scan signal, and the sweep signal to the display area.

21. The display device according to claim 20, wherein, The gate driver is disposed in the first peripheral region. The display area is located between the first peripheral area and the second peripheral area, and The transmitter line configured to receive the transmitter signal, the first initialization line configured to receive the first initialization signal, the second initialization line configured to receive the second initialization signal, the second scan signal line configured to receive the second scan signal, and the scan signal line configured to receive the scan signal are disposed in the second peripheral area.

22. A pixel circuit, wherein, The pixel circuit includes: Light-emitting elements; The pulse width driving circuit is configured to generate a pulse width signal; and A constant current drive circuit is configured to control the emission of the light-emitting element based on the pulse width signal. The pulse width driving circuit includes: A pulse-driven transistor is configured to generate the pulse width signal based on a sweep frequency signal, the sweep frequency signal being a global signal having the same timing across at least two pixel rows; A pulse write transistor is configured to apply a data voltage to the first electrode of the pulse drive transistor in response to a first scan signal, the first scan signal being a line-by-line signal with a different timing across the at least two pixel rows; A pulse emission control transistor is configured to apply a first electrical voltage to the first electrode of the pulse drive transistor in response to an emission signal; and A first initialization transistor is configured to apply an initialization voltage to the control electrode of the pulse-driven transistor in response to a first initialization signal. The constant current drive circuit includes: A constant current driving transistor is configured to apply a driving current to the light-emitting element in response to the pulse width signal; A constant current write transistor is configured to apply a constant current voltage to the first electrode of the constant current drive transistor in response to a second scan signal; A constant current emitter control transistor is configured to apply a second electrical voltage to the first electrode of the constant current drive transistor in response to the emitter signal; and The second initialization transistor is configured to apply the initialization voltage to the control electrode of the constant current drive transistor in response to a second initialization signal, and Wherein, the pulse drive transistor and the constant current drive transistor are P-type transistors, and the pulse write transistor and the constant current write transistor are N-type transistors.

23. The pixel circuit according to claim 22, wherein, The transmission signal, the first initialization signal, the second initialization signal, and the second scan signal are the global signals.

24. The pixel circuit according to claim 22, wherein, The pulse width driving circuit further includes a pulse compensation transistor connected to the control electrode and the second electrode of the pulse driving transistor, and The constant current driving circuit further includes a constant current compensation transistor connected to the control electrode and the second electrode of the constant current driving transistor.

25. The pixel circuit according to claim 24, wherein, The pulse compensation transistor and the constant current compensation transistor are N-type transistors.

26. An electronic device, wherein, The electronic device includes: Pixel circuits; and A power source is configured to supply power to the pixel circuitry. The pixel circuit includes: The first transistor includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; The second transistor is configured to apply a data voltage to the second node in response to the first scan signal; A third transistor is configured to connect the first node and the third node in response to the first scan signal; A fourth transistor is configured to apply a first electrical voltage to the second node in response to a transmit signal; The fifth transistor is configured to connect the third node and the fourth node in response to the transmitted signal; The sixth transistor is configured to apply an initialization voltage to the first node in response to a first initialization signal; The seventh transistor includes a control electrode connected to the fourth node, a first electrode connected to the fifth node, and a second electrode connected to the sixth node, and the seventh transistor is configured to generate a drive current; The eighth transistor is configured to apply the data voltage to the fifth node in response to the second scan signal; The tenth transistor is configured to apply a second electrical voltage to the fifth node in response to the transmitted signal; The twelfth transistor is configured to apply the initialization voltage to the fourth node in response to a second initialization signal; and The light-emitting element is configured to emit light based on the driving current. Wherein, the first transistor and the seventh transistor are P-type transistors, and the second transistor, the third transistor, and the eighth transistor are N-type transistors. The sweep frequency signal is applied to the first node, and the sweep frequency signal is a global signal with the same timing across at least two pixel rows.

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