Display panel and display device

Abstract

The invention provides a display panel and a display device.A pull-up module in a gate driving circuit is used for generating a gate signal output through a gate line of the level according to a signal of a first node of the level and a first signal of the level, and an inverting module in the gate driving circuit comprises a plurality of inverting transistors; grid electrodes of the plurality of inverting transistors are electrically connected to a plurality of to-be-inverted signal lines respectively, and each first inverting transistor is used for controlling the potential of a grid electrode signal of the level according to a to-be-inverted signal transmitted by the corresponding to-be-inverted signal line; and the total time period of the time periods of the pulses in the plurality of to-be-inverted signals covers the time period of the pulse in the signal of the first node of the current stage, so that the reliability of the gate signal of the current stage output by the gate drive circuit is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a display panel and a display device. Background Technology

[0002] To achieve higher electron mobility, oxide materials are generally chosen as the active layer material for transistors in gate drive circuits.

[0003] However, the threshold voltage of transistors made of oxide materials tends to increase indefinitely with prolonged use. In the gate drive circuit, the signal at the node controlling the gate of the transistor in the inverter has a high amplitude and a long duration when it is at its high potential. This causes the gate of the transistor in the inverter to be under high voltage for a long time, resulting in a particularly severe positive drift of the threshold voltage of the transistor, which affects the gate signal output by the gate drive circuit. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a corresponding display device to improve the problem of forward drift of the threshold voltage of transistors in an inverter.

[0005] An embodiment of the present invention provides a display panel including a plurality of pixels and a cascaded multi-stage gate driving circuit, wherein one stage of the multi-stage gate driving circuit includes:

[0006] The pull-up control module is used to control the signal of the first node in the gate drive circuit of this stage according to the frame start signal or the stage transmission signal of the previous i stages, where i is a positive integer;

[0007] A pull-up module is electrically connected to the first node and the first signal line of this stage. It is used to generate a gate signal output through the gate line of this stage based on the signal of the first node and the first signal line of this stage. The pulse in the signal of the first node of this stage is used to control the pull-up module to generate the pulse in the gate signal of this stage based on the first signal of this stage. The pulse width of the pulse in the signal of the first node of this stage is greater than the pulse width of the gate signal of this stage.

[0008] An inverting module includes multiple inverting transistors, the gates of which are electrically connected to multiple signal lines to be inverted. Each inverting transistor is used to control the potential of the gate signal of its own stage according to the signal to be inverted transmitted by the corresponding signal line to be inverted.

[0009] The total time period of the pulses in the multiple signals to be inverted covers the time period of the pulses in the signal of the first node of this level.

[0010] The embodiment of the present application also provides a display device, comprising the display panel according to any one of the above and a driving chip electrically connected to the display panel, wherein the driving chip is used for transmitting the frame start signal and the first signal to the multi-stage gate drive circuit, and is used for transmitting a data signal to the plurality of pixels.

[0011] Alternatively, the display device comprises the display panel according to any one of the above, a timing driving chip and a source driving chip electrically connected to the display panel, wherein the timing driving chip is used for transmitting the frame start signal and the first signal to the multi-stage gate drive circuit, and the source driving chip is used for transmitting a data signal to the plurality of pixels.

[0012] The gate signal and the data signal are used for controlling the display panel to display a picture.

[0013] The present application provides a display panel and a display device, comprising a plurality of pixels and a multi-stage gate drive circuit in cascade, wherein the gate drive circuit comprises: a pull-up control module, used for controlling a signal of a first node in the gate drive circuit of the present stage according to a frame start signal or a stage transmission signal of a previous i stage, wherein i is a positive integer; a pull-up module, used for generating a gate signal output through a gate line of the present stage according to the signal of the first node of the present stage and a first signal of the present stage transmitted by the first signal line of the present stage, wherein a pulse width of a pulse in the signal of the first node of the present stage is greater than a pulse width of a pulse in the gate signal of the present stage; and an inverting module, which is configured to comprise a plurality of inverting transistors, and the gate of each inverting transistor is electrically connected to a plurality of to-be-inverted signal lines respectively, each inverting transistor is used for controlling the potential of the gate signal of the present stage according to a to-be-inverted signal transmitted by the corresponding to-be-inverted signal line, and the total time period of the time periods of the pulses in the plurality of to-be-inverted signals covers the time period of the pulse in the signal of the first node of the present stage, thereby reducing the risk of positive drift of the threshold voltage of the inverting transistor, avoiding the problem of reduced driving capability caused by insufficient on-state current of the inverting transistor, and improving the reliability of the gate signal of the present stage output by the gate drive circuit. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 The architecture diagram of the display panel provided by the embodiment of the present application is shown.

[0015] Figures 2 to 4 The circuit diagram of the gate drive circuit provided by the embodiment of the present application is shown.

[0016] Figure 5 The timing diagram of part of input signals and part of node signals in the gate drive circuit provided by the embodiment of the present application is shown.

[0017] Figure 6A circuit diagram of a gate drive circuit provided for a comparative example of the present application.

[0018] Figures 7 to 9 A graph of threshold voltage change over time of a transistor provided for an embodiment of the present application.

[0019] Figure 10 and Figure 11 An architectural diagram of a display device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be apparently and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by a person skilled in the art without any creative work belong to the protection scope of the present application.

[0021] The terms "first", "second", "third", and "fourth" and the like in the present application are used to distinguish different objects, rather than to describe a particular order. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device including a series of steps or modules is not limited to the listed steps or modules, but can optionally include steps or modules not listed, or can optionally include other steps or modules inherent to the process, method, product, or device.

[0022] In this document, reference to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to one of skill in the art, embodiments described herein can be combined with other embodiments.

[0023] Embodiments of the present application provide a gate drive circuit, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0024] In an embodiment, as shown in Figure 1 The display panel 100 includes a plurality of pixels Pi and a multi-stage gate drive circuit 20 cascaded, as shown in Figures 2 to 4 One stage of the multi-stage gate drive circuit 20 includes a pull-up control module 201, a pull-up module 202, and an inverting module 203, and the specific functions are as follows:

[0025] The pull-up control module 201 is configured to control a signal q(n) of a first node Q(n) in the gate drive circuit 20 at the nth stage according to a frame start signal stv (for the gate drive circuit 20 at the first stage) or a stage transmission signal st(n-i) of the (i-1)th stage (for the gate drive circuit 20 at the nth stage, i is a positive integer, and n is a positive integer greater than i).

[0026] The pull-up module 202 is electrically connected to the first node Q(n) at the current stage and a first signal line (for example, a corresponding clock line CK) at the current stage, and is configured to generate a gate signal gate(n) output through a gate line G(n) at the current stage according to the signal q(n) of the first node Q(n) at the current stage and a first signal (that is, a corresponding clock signal ck) at the current stage transmitted by the first signal line at the current stage, in combination with Figures 2 to 5 As shown, the pulse in the signal q(n) of the first node Q(n) at the current stage is used to control the pull-up module 202 to generate a pulse in the gate signal gate(n) at the current stage according to the first signal (that is, the corresponding clock signal ck) at the current stage, and the pulse width W1 of the pulse in the signal q(n) of the first node Q(n) at the current stage is greater than the pulse width W2 of the pulse in the gate signal gate(n) at the current stage.

[0027] The inverting module 203 includes a plurality of inverting transistors, and the gates of the plurality of inverting transistors are respectively electrically connected to a plurality of to-be-inverted signal lines. Each first inverting transistor is configured to control the potential of the gate signal gate(n) at the current stage according to a to-be-inverted signal transmitted by a corresponding to-be-inverted signal line.

[0028] As can be seen from the above description, in combination with Figures 1 to 4 As shown, the gate signal gate(1) at the first stage can be generated by the gate drive circuit 20 at the first stage according to the frame start signal stv and the first signal (a corresponding clock signal ck) at the first stage, and the gate signal gate(n) at the nth stage can be generated by the gate drive circuit 20 at the nth stage according to the stage transmission signal st(n-i) of the (i-1)th stage and the first signal (a corresponding clock signal ck) at the nth stage.

[0029] For example Figures 2 to 4 As shown, i can be 6, and at this time n is greater than 7, that is, the gate signal gate(n) at the nth stage can be generated by the gate drive circuit 20 at the nth stage according to the stage transmission signal st(n-6) of the (6-1)th stage and the first signal (a corresponding clock signal ck) at the nth stage. Similarly, the gate signal gate(7) at the 7th stage to the gate signal at the last stage can be generated by the gate drive circuit 20 at the 7th stage to the gate drive circuit 20 at the last stage, respectively, with the phases being sequentially lagged.

[0030] Based on this, for the gate driving circuits 20 of the first stage to the gate driving circuits 20 of the sixth stage, all six can be acted upon by the same frame start signal stv. The pulse width of the frame start signal stv needs to be greater than the pulse width of each first signal. By differentiating the phase of the six first signals (i.e. the six corresponding clock signals ck) of the six, the six can generate gate signals gate(1) of the first stage to gate signals gate(6) of the sixth stage with phases lagging sequentially.

[0031] Of course, when the pulse width of the frame start signal stv is insufficient to cover the total pulse width of the six first signals corresponding to the above six, the number of frame start signals stv can be appropriately increased so that the total pulse width of the multiple frame start signals stv can cover the total pulse width of the six first signals corresponding to the above six. For example, the number of frame start signals stv can be two, and the two frame start signals stv are defined as the first frame start signal stv1 and the second frame start signal stv2, respectively. The first frame start signal stv1 can be applied to the gate drive circuit 20 of the first stage to the gate drive circuit 20 of the third stage, and the second frame start signal stv2 can be applied to the gate drive circuit 20 of the fourth stage to the sixth stage. The pulse width of the first frame start signal stv1 covers the total pulse width of the first signals of the first stage to the first signals of the third stage, and the pulse width of the second frame start signal stv2 covers the total pulse width of the first signals of the first stage to the first signals of the third stage.

[0032] Specifically, in combination Figures 1 to 4 As shown, the number of stages of the gate driving circuit 20 can be equal to the number of rows of pixels Pi. The pulses in the gate signal of each stage are used to control the corresponding row of pixels Pi to turn on. The multi-stage gate driving circuit 20 uses multiple pulses in the multi-stage gate signal generated by methods including but not limited to the above to be delayed sequentially, so it can control multiple rows of pixels Pi to turn on sequentially, thereby realizing the row-by-row scanning of multiple rows of pixels Pi.

[0033] like Figure 6 As shown, the comparative example is the same as that of this embodiment. Figures 2 to 4 The difference (as shown) lies at least in that the gates of both transistors T52' and T56' in its inverting module 203 are electrically connected to the first node Q(n) of this stage. The pulse width and potential of the pulse in the first node Q(n) signal q(n) are relatively large, which results in a longer conduction time for transistors T52' and T56', causing a particularly severe positive drift of their threshold voltages. As a result, their on-state current is insufficient, their driving capability is reduced, and this indirectly has an adverse effect on the potential of the gate signal gate(n) of this stage.

[0034] like Figures 2 to 4As shown, the gates of the plurality of inverting transistors in the inverting module 203 in this embodiment are respectively electrically connected to a plurality of to-be-inverted signal lines, so as to be respectively controlled by a plurality of to-be-inverted signals, and the total time period of the time periods in which the pulses (for controlling the corresponding inverting transistors to be turned on) in the plurality of to-be-inverted signals are located (i.e., the total time period in which the plurality of inverting transistors are turned on) covers the time period in which the pulse in the signal q(n) of the first node Q(n) of the current stage is located.

[0035] In the above, the "coverage" can be understood as, on the time axis, the starting time of the earliest one of the time periods in which the pulses in the plurality of to-be-inverted signals are located is the same as or earlier than the starting time of the time period in which the pulse in the signal q(n) of the first node Q(n) of the current stage is located, and the starting time of the latest one is the same as or lags behind the starting time of the time period in which the pulse in the signal q(n) of the first node Q(n) of the current stage is located.

[0036] For example, when the number of inverting transistors is only 2, as shown in FIG. 3, Figures 2 to 4 As shown, the plurality of inverting transistors include a first inverting transistor T53 and a second inverting transistor T55, and the plurality of to-be-inverted signal lines include at least a first to-be-inverted signal line L1 and a second to-be-inverted signal line L2; the gates of the first inverting transistor T53 and the second inverting transistor T55 are respectively electrically connected to the first to-be-inverted signal line and the second to-be-inverted signal line, the first inverting transistor T53 is configured to control the potential of the gate signal gate(n) of the current stage according to the first to-be-inverted signal transmitted by the first to-be-inverted signal line L1, and the second inverting transistor T55 is configured to control the potential of the gate signal gate(n) of the current stage according to the second to-be-inverted signal transmitted by the second to-be-inverted signal line L2; wherein the starting time of the time period in which the pulse in the first to-be-inverted signal is located is earlier than or the same as the starting time of the time period in which the pulse in the signal q(n) of the first node Q(n) of the current stage is located, and the ending time of the time period in which the pulse in the second to-be-inverted signal is located lags behind or is the same as the ending time of the time period in which the pulse in the signal q(n) of the first node Q(n) of the current stage is located; the time period in which the pulse in the first to-be-inverted signal is located and the time period in which the pulse in the second to-be-inverted signal is located overlap, so that there is no gap between the time period in which the pulse in the first to-be-inverted signal is located and the time period in which the pulse in the second to-be-inverted signal is located, and the total time period includes the time period in which the pulse in the signal q(n) of the first node Q(n) of the current stage is located.

[0037] For another example, when the number of inverting transistors is only 2, as shown in FIG. 4, Figures 2 to 4As shown, the plurality of inverter transistors further includes a third inverter transistor T54. Different from the above analysis, whether the time period of the pulse in the first to-be-inverted signal and the time period of the pulse in the second to-be-inverted signal overlap is not limited here. When the two time periods do not overlap, the time period of the pulse in the third to-be-inverted signal (acting on the gate of the third inverter transistor T54) located between the two time periods can overlap with both of the two time periods at the same time, and the above requirement can also be met.

[0038] It can be understood that the plurality of inverter transistors in the inverter module 203 in the embodiment can all control the potential of the gate signal gate(n) of the current stage. By setting the plurality of inverter transistors in the inverter module 203 to be controlled by different time-sharing conduction respectively, and the total time period occupied by the conduction of the two can cover the time period in which the transistor T52' and the transistor T56' are turned on by the signal q(n) of the first node Q(n) of the current stage, the inverter module 203 can maintain the control time of the potential of the gate signal gate(n) of the current stage, and compared with the comparative example, the risk of forward drift of the threshold voltage of any inverter transistor in the above process is reduced, thereby avoiding the problem of insufficient on-state current of the inverter transistor and the problem of reduced driving capability, and improving the reliability of the gate signal gate(n) of the current stage output by the gate drive circuit 20.

[0039] In some embodiments, as shown in FIG. 6, the material of the active layer of each of the plurality of inverter transistors (at least including the first inverter transistor T53 and the second inverter transistor T55) includes metal oxide. Further, the material of the active layer of each of the plurality of transistors in the gate drive circuit 20 can include metal oxide. It can be understood that the transistor made of metal oxide rather than amorphous silicon can have higher carrier mobility and lower power consumption, and the gate drive circuit 20 formed thereby can make the display panel 100 have higher resolution, better uniformity and stability. Figures 2 to 4

[0040] However, as shown in FIG. 7, the material of the active layer of each of the plurality of inverter transistors (at least including the first inverter transistor T53 and the second inverter transistor T55) includes metal oxide. Further, the material of the active layer of each of the plurality of transistors in the gate drive circuit 20 can include metal oxide. It can be understood that the transistor made of metal oxide rather than amorphous silicon can have higher carrier mobility and lower power consumption, and the gate drive circuit 20 formed thereby can make the display panel 100 have higher resolution, better uniformity and stability. Figure 7 ​As shown, the curve CL1 shows the change of threshold voltage of the transistor made of metal oxide with time of its positive bias, and the curve CL2 shows the change of threshold voltage of the transistor made of amorphous silicon with time of its positive bias. As can be seen from the two curves, the threshold voltage of the transistor made of amorphous silicon rises rapidly in the early stage, but does not rise any more after reaching a saturation value, while the threshold voltage of the transistor made of metal oxide rises slowly in the early stage, but is in an infinite rising trend. If the transistor made of metal oxide in the inverting module 203 is acted on by the first node Q(n) signal q(n) in the manner of the comparative example, the positive bias of the transistor will be particularly serious, while if the transistor made of metal oxide in the inverting module 203 is acted on by the first node Q(n) signal q(n) in the manner of the present application, the positive bias of the transistor made of metal oxide in the inverting module 203 can be greatly improved compared with the transistor made of amorphous silicon, and the reliability of the gate signal gate(n) output by the gate drive circuit 20 can be greatly improved. Figures 2 to 4 As shown, the curve CL1 shows the change of threshold voltage of the transistor made of metal oxide with time of its positive bias, and the curve CL2 shows the change of threshold voltage of the transistor made of amorphous silicon with time of its positive bias. As can be seen from the two curves, the threshold voltage of the transistor made of amorphous silicon rises rapidly in the early stage, but does not rise any more after reaching a saturation value, while the threshold voltage of the transistor made of metal oxide rises slowly in the early stage, but is in an infinite rising trend. If the transistor made of metal oxide in the inverting module 203 is acted on by the first node Q(n) signal q(n) in the manner of the comparative example, the positive bias of the transistor will be particularly serious, while if the transistor made of metal oxide in the inverting module 203 is acted on by the first node Q(n) signal q(n) in the manner of the present application, the positive bias of the transistor made of metal oxide in the inverting module 203 can be greatly improved compared with the transistor made of amorphous silicon, and the reliability of the gate signal gate(n) output by the gate drive circuit 20 can be greatly improved.

[0041] In some embodiments, as shown in Figure 1 As shown, the display panel 100 comprises a plurality of clock lines CK, each of the clock lines CK is used for transmitting a corresponding clock signal ck, the first signal line of each stage is a clock line CK, as shown in Figures 2 to 4 As shown, taking the nth stage gate drive circuit 20 as an example, the pull-up module 202 comprises a first pull-up transistor T21, a gate of the first pull-up transistor T21 is electrically connected to the first node Q(n) of the present stage, one of a source and a drain of the first pull-up transistor T21 is electrically connected to the corresponding clock line CK, and the other of the source and the drain of the first pull-up transistor T21 is electrically connected to the gate line G(n) of the present stage; wherein, in the time period of the pulse in the signal q(n) of the first node Q(n) of the present stage, the pulse of the clock signal ck is used to control the amplitude of the pulse in the signal q(n) of the first node Q(n) to reach the corresponding maximum value.

[0042] In the display panel 100, each two of the plurality of clock signals ck output by the plurality of clock lines CK have a phase difference, and each clock line CK is electrically connected to at least two stages of gate drive circuits 20 which are spaced apart. For example, the number of clock lines CK is 12, each two of the corresponding 12 clock signals ck have a phase difference, the first clock line CK can be electrically connected to the 1+12k stage gate drive circuit 20, the second clock line CK can be electrically connected to the 2+12k stage gate drive circuit 20, the third clock line CK can be electrically connected to the 3+12k stage gate drive circuit 20, and so on, and the 12th clock line CK can be electrically connected to the 12+12k stage gate drive circuit 20, k can be any positive integer starting from 0.

[0043] It can be understood that, since one of the source and the drain of the first pull-up transistor T21 is electrically connected to the corresponding clock line CK, and the other is electrically connected to the gate line G(n) of the current stage, in the period in which the pulse in the signal q(n) of the first node Q(n) of the current stage controls the first pull-up transistor T21 to be turned on, the first pull-up transistor T21 can output the corresponding clock signal ck as the gate signal gate(n) of the current stage, but the pulse of the clock signal ck needs to include its pulse in the period so that the gate signal gate(n) of the current stage also includes its pulse, and since there is a parasitic capacitance between any one of the source and the drain of the first pull-up transistor T21 and its gate, it can be considered that at least one of the rising edge of the pulse of the clock signal ck and the rising edge of the pulse of the gate signal gate(n) makes the amplitude of the pulse in the signal q(n) of the gate (i.e. the first node Q(n)) of the first pull-up transistor T21 further increase to its maximum value through the above-mentioned parasitic capacitance, so as to further increase the turn-on degree of the first pull-up transistor T21, and be more beneficial to the output of the gate signal gate(n) of the current stage.

[0044] Further, as shown in Figures 2 to 4 , the pull-up module 202 can further include a bootstrap capacitor Cbt connected between the gate of the first pull-up transistor T21 and the gate line G(n) of the current stage, and similarly, according to the above-mentioned description of the role of the parasitic capacitance, the bootstrap capacitor Cbt can further increase the turn-on degree of the first pull-up transistor T21 at the rising edge of the pulse of the gate signal gate(n).

[0045] In some embodiments, as shown in Figures 2 to 4 , the pull-up control module 201 includes a pull-up control transistor T11, a gate of the pull-up control transistor T11 is electrically connected to a frame start line STV (for the gate drive circuit 20 of the first stage) for transmitting the frame start signal stv or a stage transmission line ST(n) (for the gate drive circuit 20 of the nth stage, i is a positive integer, and n is a positive integer greater than i) of the i-th stage for transmitting the stage transmission signal st(n-i) of the i-th stage, one of the source and the drain of the pull-up control transistor T11 is electrically connected to the first node Q(n) of the current stage. Figure 2 and Figure 4 , the other of the source and the drain of the pull-up control transistor T11 is electrically connected to the gate of the pull-up control transistor T11, or as Figure 3a fourth signal line VGH electrically connected to a fourth signal for transmission; wherein the potential of the fourth signal and the potential of the stage transfer signal st(n-i) of the previous i stage when the pull-up control transistor T11 is turned on are used to pull up the potential of the signal q(n) of the first node Q(n) of the current stage.

[0046] wherein, as shown in Figure 2 and Figure 4 When the other of the source and the drain of the pull-up control transistor T11 is electrically connected to the gate of the pull-up control transistor T11, the pull-up control transistor T11 is in a diode connection and works in a saturation region, so that the voltage difference between any of the source and the drain and the gate of the pull-up control transistor T11 is close to the threshold voltage, which causes leakage current when the pull-up control transistor T11 is controlled by the frame start signal stv or the stage transfer signal st(n-i) of the previous i stage to be turned off, and the positive or negative bias of the pull-up control transistor T11 is small, and the power consumption is low.

[0047] wherein, as shown in Figure 3 When the other of the source and the drain of the pull-up control transistor T11 is electrically connected to the fourth signal line VGH, the voltage difference between the other of the source and the drain and the gate of the pull-up control transistor T11 is large, so that the pull-up control transistor T11 can be better turned on or turned off, the fourth signal can provide additional current, and the first node Q(n) can be quickly charged to improve the pre-charging ability of the first node Q(n).

[0048] As discussed above, taking the nth stage as an example, no matter whether the other of the source and the drain of the pull-up control transistor T11 is electrically connected to the gate of the pull-up control transistor T11 or the fourth signal line VGH, the stage transfer signal st(n-i) of the previous i stage acting on the gate of the pull-up control transistor T11 is used to control which stage the potential of the first node Q(n) is raised by the stage transfer signal st(n-i) of the previous i stage or the fourth signal, so as shown in Figure 5 Taking i as 6 as an example, the pulse in the signal q(n) of the first node Q(n) of the current stage at least includes the pulse of the stage transfer signal st(n-6) of the previous 6 stages, and the starting time of the former pulse is the same as that of the latter pulse.

[0049] In some embodiments, as shown in Figures 2 to 4As shown, taking the nth stage gate drive circuit 20 as an example, the pull-up module 202 is further configured to generate, according to the signal q(n) of the first node Q(n) of the current stage and the first signal (taking a corresponding clock signal ck as an example) of the current stage, the stage transmission signal st(n) of the current stage output through the stage transmission line ST(n) of the current stage, the pulse in the signal q(n) of the first node Q(n) of the current stage is used to control the pull-up module 202 to generate the pulse in the stage transmission signal st(n) of the current stage according to the first signal of the current stage, and the pulse width of the pulse in the signal q(n) of the first node Q(n) of the current stage is greater than the pulse width of the pulse in the stage transmission signal st(n) of the current stage; wherein the first to-be-inverted signal line L1 is the stage transmission line ST(n-k1) of the first k1 stages, and the second to-be-inverted signal line L2 is the stage transmission line ST(n) of the current stage or the stage transmission line ST(n+k2) of the second k2 stages (the former is taken as an example in the drawing), and k1 and k2 are both positive integers, and k1 is greater than or equal to i.

[0050] Specifically, as shown in the figure, Figures 2 to 4 As shown, the pull-up module 202 can further include a second pull-up transistor T22, a gate of the second pull-up transistor T22 is electrically connected to the first node Q(n) of the current stage, one of a source and a drain of the second pull-up transistor T22 is electrically connected to a corresponding clock line CK, and the other of the source and the drain of the second pull-up transistor T22 is electrically connected to the stage transmission line ST(n) of the current stage. As can be known from the above description about the function of the first pull-up transistor T21, the waveform (including pulse width, phase, and amplitude) of the stage transmission line ST(n) of the current stage generated by the second pull-up transistor T22 is almost the same as that of the gate signal gate(n) of the current stage, and therefore the pulse width of the pulse in the signal q(n) of the first node Q(n) of the current stage is also greater than the pulse width of the pulse in the stage transmission signal st(n) of the current stage.

[0051] In one aspect, in the embodiment, the stage transmission line ST(n-k1) of the first k1 (greater than or equal to i) stages is taken as the first to-be-inverted signal line L1, and the stage transmission line ST(n) of the current stage or the stage transmission line ST(n+k2) of the second k2 stages is taken as the second to-be-inverted signal line L2, so that the gate of the first inverting transistor T53 is acted on by the stage transmission signal st(n-k1) of the first k1 stages, and the gate of the second inverting transistor T55 is acted on by the stage transmission signal st(n) of the current stage or the stage transmission signal st(n+k2) of the second k2 stages (the former is taken as an example in the drawing). Since the pulses of the stage transmission signals of different stages are in different time periods, the first inverting transistor T53 and the second inverting transistor T55 can be turned on at different times, and the first inverting transistor T53 can be turned on at the rising edge of the pulse in the signal q(n) of the first node Q(n) at the latest, and the second inverting transistor T55 can be turned off at the falling edge of the pulse in the signal q(n) of the first node Q(n) at the earliest.

[0052] Among them, combined Figures 2 to 5 As shown, based on the working principle of the pull-up control module 201 and pull-up module 202 mentioned above, the maximum amplitude of the pulse in the signal q(n) of the first node Q(n) is reached after its amplitude reaches the amplitude of the stage transmission signal st(ni) of the previous i stage and rises again. Therefore, it can be considered that the amplitude of the pulse of the stage transmission signal of all stages is less than the maximum amplitude of the pulse in the signal q(n) of the first node Q(n). That is, the gate potential of the multiple inverting transistors in the inverting module 203 is lower than the potential in the comparative example when they are turned on.

[0053] That is, when multiple signals to be inverted are selected from several of the multi-stage transmission signals, the amplitude of the pulse in the first signal to be inverted and the amplitude of the pulse in the second signal to be inverted are both less than the maximum amplitude of the pulse in the signal q(n) of the first node Q(n). Of course, a signal can also be provided individually as multiple signals to be inverted, so that the amplitude of its pulse is also less than the maximum amplitude of the pulse in the signal q(n) of the first node Q(n).

[0054] On the other hand, since the amplitude of the pulse in the first signal to be inverted and the amplitude of the pulse in the second signal to be inverted are both less than the maximum amplitude of the pulse in the signal q(n) of the first node Q(n), the forward bias amplitude of the multiple inverting transistors is also low when they are turned on, which further reduces the risk of forward drift of the threshold voltage of the inverting transistors.

[0055] Furthermore, such as Figures 2 to 4 As shown, taking the nth stage gate drive circuit 20 as an example, the inverting module 203 further includes the aforementioned third inverting transistor T54. The gate of the third inverting transistor T54 is electrically connected to the stage transmission line ST(n-k3) of the previous k3 stages. The third inverting transistor T54 is used to control the potential of the gate signal gate(n) of this stage according to the stage transmission signal st(n-k3) transmitted by the stage transmission line ST(n-k3) of the previous k3 stages. k3 is a positive integer and k3 is less than i.

[0056] That is, the gate of the first inverter transistor T53 is acted on by the stage transfer signal st(n-k1) of the previous k1 stage, the gate of the second inverter transistor T55 is acted on by the stage transfer signal st(n) of the current stage or the stage transfer signal st(n+k2) of the next k2 stage (the former is exemplified in the figure), and the gate of the third inverter transistor T54 is acted on by the stage transfer signal st(n-k3) of the previous k3 stage. Since the pulses of the stage transfer signal st(n-k1) of the previous k1 stage, the stage transfer signal st(n-k3) of the previous k3 stage, the stage transfer signal st(n) of the current stage, and the stage transfer signal st(n+k2) of the next k2 stage are arranged in the positive direction of the time axis in sequence, the first inverter transistor T53, the third inverter transistor T54, and the second inverter transistor T55 are sequentially turned on.

[0057] Specifically, in combination with the foregoing description of the first inverter module 201, as shown in the figure, the time period t1 in which the pulse of the stage transfer signal st(n-i) of the previous k1 stage as the first to-be-inverted signal is located, and the time period t2 in which the pulse of the stage transfer signal st(n-k3) of the previous k3 stage as the third to-be-inverted signal is located overlap; the time period t2 in which the pulse of the stage transfer signal st(n-k3) of the previous k3 stage as the third to-be-inverted signal is located, and the time period t3 in which the pulse of the stage transfer signal st(n) of the current stage or the stage transfer signal st(n+k2) of the next k2 stage (the former is exemplified in the figure) as the second to-be-inverted signal is located overlap. Figures 2 to 5 For ease of description, an example in which i is 6 is described here. Since k1 is greater than or equal to 6, k2 is a positive integer, and k3 is less than 6, for example, k1 can be 8 and k3 can be 4, that is, the gate of the first inverter transistor T53, the gate of the third inverter transistor T54, and the gate of the second inverter transistor T55 can be acted on by the stage transfer signal st(n-8) of the previous 8 stage, the stage transfer signal st(n-4) of the previous 4 stage, and the stage transfer signal st(n) of the current stage respectively, so that the first inverter transistor T53, the third inverter transistor T54, and the second inverter transistor T55 are sequentially turned on in the time period t1, the time period t2, and the time period t3. Since the adjacent two of the time period t1, the time period t2, and the time period t3 overlap, the total time period in which the three inverter transistors are turned on can cover the total time period in which the transistor T52' and the transistor T56' in the comparative example are turned on, thereby avoiding the total working time of the inverter module 203 from being insufficient.

[0058] Further, in combination with the foregoing description of the first inverter module 201,

[0059] Figures 2 to 5 ​As shown, for example, when the gate of the second inverting transistor T55 is electrically connected to the stage transmission line ST(n) of this stage, the inverting module 203 may also include the aforementioned fourth inverting transistor T56. The gate of the fourth inverting transistor T56 is electrically connected to the stage transmission line ST(n+k2) of the next k2 stages to obtain the stage transmission signal st(n+k2) of the next k2 stages. k2 is a positive integer. Here, we take k2 as 3 as an example. Then, the gate of the fourth inverting transistor T56 is electrically connected to the stage transmission line ST(n+3) of the next 3 stages to be controlled by the stage transmission signal st(n+3) of the next 3 stages.

[0060] Among them, the time period t4 of the pulse of the stage transmission signal st(n+3) of the last 3 stages and the time period t3 of the pulse of the stage transmission signal st(n) of this stage can also overlap. Furthermore, since the end time of the time period t4 of the pulse of the stage transmission signal st(n+3) of the last 3 stages lags behind the falling edge of the pulse in the signal q(n) of the first node Q(n).

[0061] Taking the example of i = 6, k1 = 8, k3 = 4, and k2 = 3, the inverting module 203 is turned on at the rising edge of the pulse in the signal q(n) of the first node Q(n) for a first duration T1 (i.e., the time difference between the stage transmission signal st(n-8) of the first 8 stages and the stage transmission signal st(n-6) of the first 6 stages), and the inverting module 203 is turned on after the falling edge of the pulse in the signal q(n) of the first node Q(n) for a second duration T2 (i.e., the time difference between the stage transmission signal st(n+3) of the last 3 stages and the stage transmission signal st(n) of this stage).

[0062] like Figure 8 As shown, the diagram illustrates the curves CL1' and CL2' of the threshold voltage of a metal oxide transistor versus its forward bias time when the first node Q(n) signal q(n) is applied to the inverting module 203, based on the comparative example. (Refer to the previous text regarding...) Figure 7 As discussed earlier, because the maximum amplitude and pulse width of the first node Q(n) signal q(n) of this stage are relatively large, the threshold voltage of transistors made of amorphous silicon can be lower than the critical voltage after a long period of time, but the threshold voltage of transistors made of metal oxide is higher than the critical voltage, causing the gate signal gate(n) output by the gate drive circuit 20 to become abnormal. The critical voltage can be understood as the threshold voltage value of the gate signal gate(n) output by the gate drive circuit 20 that falls between abnormal and normal values.

[0063] like Figure 9As shown, the curve CL1' illustrates the change of threshold voltage of the transistor with time when the first node Q(n) signal q(n) acts on the inverting module 203 in the comparative example, and the curve CL2" illustrates the change of threshold voltage of the transistor with time when the signal transmitted by the above-mentioned several stages acts on the inverting module 203 in the embodiment of the present application. By comparison, it can be seen that when the signal transmitted by the above-mentioned several stages acts on the inverting module 203, the threshold voltage of the multiple inverting transistors in the inverting module 203 will not be higher than the above-mentioned critical voltage for a long time, thereby reducing the risk of abnormality of the gate signal gate(n) of the current stage output by the gate driving circuit 20.

[0064] In some embodiments, as shown in Figures 2 to 4 As shown, the inverting module 203 further comprises a first inverting control transistor T51, a gate of the first inverting control transistor T51 is electrically connected to a second signal line (for example, comprising a first sub-signal line LC1 and a second sub-signal line LC2), one of a source and a drain of the first inverting control transistor T51, one of a source and a drain of the first inverting transistor T53, and one of a source and a drain of the second inverting transistor T55 are all electrically connected to a second node K of the current stage, the first inverting control transistor T51 is used to control a signal k(n) of the second node K of the current stage according to a second signal transmitted by the second signal line, and the signal k(n) of the second node K of the current stage is used to control the gate signal gate(n) of the current stage; wherein the first inverting control transistor T51 is used to pull up the potential of the signal k(n) of the second node K of the current stage, and the first inverting transistor T53 and the second inverting transistor T55 are used to pull down the potential of the signal k(n) of the second node K of the current stage.

[0065] That is, when the first inverting control transistor T51 is turned on under the control of the second signal, the first inverting transistor T53 can pull up the potential of the signal k(n) of the second node K of the current stage, and when at least one inverting transistor is turned on under the control of the corresponding inverting signal, the inverting module 203 can pull down the potential of the signal k(n) of the second node K of the current stage.

[0066] In some embodiments, as shown in Figure 2 and Figure 3 As shown, the other one of the source and the drain of the first inverting control transistor T51 is electrically connected to the gate of the first inverting control transistor T51, or as shown in Figure 4As shown, the fourth signal line VGH for transmitting the fourth signal is electrically connected to the gate driving circuit 20. The gate driving circuit 20 further comprises a pull-down maintaining module 204 electrically connected to the second node K of the current stage and the gate line G(n) of the current stage. The potential of the fourth signal and the potential of the second signal when the first inverting control transistor T51 is turned on are both used to pull down the potential of the signal k(n) of the second node K of the current stage, so as to pull down the potential of the gate signal gate(n) of the current stage by the pull-down maintaining module 204.

[0067] Similarly, when the other of the source and the drain of the first inverting control transistor T51 is electrically connected to the gate of the first inverting control transistor T51, the first inverting control transistor T51 is in a diode connection mode; when the other of the source and the drain of the first inverting control transistor T51 is electrically connected to the fourth signal line VGH, the voltage difference between the other of the source and the drain and the gate of the first inverting control transistor T51 is larger. The advantages of the above two connection modes of the other of the source and the drain of the first inverting control transistor T51 can be referred to the above description of the above two connection modes of the pull-up control transistor T11.

[0068] Specifically, as shown in Figures 2 to 4 The pull-down maintaining module 204 is further electrically connected to the first node Q(n) of the current stage and the stage transmission line ST(n) for transmitting the stage transmission signal st(n) of the current stage. The pull-down maintaining module 204 is further used to control the potential of the signal q(n) of the first node Q(n) of the current stage and the potential of the stage transmission signal st(n) of the current stage according to the signal k(n) of the second node K of the current stage. The pull-down maintaining module 204 can comprise a first pull-down maintaining transistor T32, a second pull-down maintaining transistor T42 and a third pull-down maintaining transistor T72. The connection relationship of the three transistors can be referred to the circuit diagram.

[0069] It can be understood that no matter the other of the source and the drain of the first inverting control transistor T51 is electrically connected to the gate or the fourth signal line VGH, the following analysis is applicable:

[0070] When the first inverting control transistor T51 is controlled to conduct the second signal, it can transmit the second signal or the fourth signal to the second node K of this stage to pull up the signal k(n) of the second node K of this stage. Then, the first pull-down sustaining transistor T32, the second pull-down sustaining transistor T42, and the third pull-down sustaining transistor T72 are all turned on. The fifth signal transmitted by the fifth signal line VSSQ can pull down the potential of the signal q(n) of the first node Q(n) of this stage and the stage transmission signal st(n) of this stage through the second pull-down sustaining transistor T42 and the third pull-down sustaining transistor T72. The sixth signal transmitted by the sixth signal line VSSG can pull down the potential of the gate signal gate(n) of this stage through the first pull-down sustaining transistor T32.

[0071] When any inverting transistor is controlled to conduct the corresponding inverted signal, it can pull down the signal k(n) of the second node K of this stage to the fifth signal. As a result, the first pull-down holding transistor T32, the second pull-down holding transistor T42, and the third pull-down holding transistor T72 are all turned off and turned on. The potentials of the signal q(n) of the first node Q(n) of this stage, the stage transmission signal st(n) of this stage, and the gate signal gate(n) of this stage can be left unpulled.

[0072] In some embodiments, such as Figures 2 to 4 As shown, when the gate drive circuit 20 includes two inverting modules 203, the inverting module 203 further includes: a second inverting control transistor T52, the gate of the second inverting control transistor T52 is electrically connected to a third signal line (e.g., including a first sub-signal line LC1 and a second sub-signal line LC2), one of the source and drain of the second inverting control transistor T52 is electrically connected to one of the source and drain of the first inverting control transistor T51, and the second inverting control transistor T52 is used to pull down the potential of the signal k(n) of the second node K of this stage; wherein, the second signal line and the third signal line both include a first sub-signal line LC1 and a second sub-signal line LC2, the second signal and the third signal both include a first sub-signal transmitted by the first sub-signal line LC1 and a second sub-signal transmitted by the second sub-signal line LC2, and the phase of the first sub-signal and the phase of the second sub-signal are opposite.

[0073] In one of the two inverting modules 203, a gate of the first inverting control transistor T51 is electrically connected to the first sub-signal line LC1, and a gate of the second inverting control transistor T52 is electrically connected to the second sub-signal line LC2. In the other of the two inverting modules 203, the gate of the first inverting control transistor T51 is electrically connected to the second sub-signal line LC2, and the gate of the second inverting control transistor T52 is electrically connected to the first sub-signal line LC1.

[0074] For example Figures 2 to 4 As shown, the first inverting control transistor T51 and the second inverting control transistor T52 in the left inverting module 203 are controlled by the first sub-signal and the second sub-signal respectively, and the first inverting control transistor T51 and the second inverting control transistor T52 in the right inverting module 203 are controlled by the second sub-signal and the first sub-signal respectively, thereby having the following functions:

[0075] When the first inverting control transistor T51 in the left inverting module 203 is turned on and the second inverting control transistor T52 is turned off, the second signal or the fourth signal is transmitted to the second node K of the current stage to pull up the signal k(n) of the second node K of the current stage, so that the left inverting module 203 works. At the same time, the first inverting control transistor T51 in the right inverting module 203 is turned off and the second inverting control transistor T52 is turned on, and the fifth signal is transmitted to the second node K of the current stage to pull down the signal k(n) of the second node K of the current stage, so that the right inverting module 203 works.

[0076] Therefore, the left inverting module 203 and the right inverting module 203 work alternately to alternately realize the pull-up of the signal k(n) of the second node K of the current stage.

[0077] Correspondingly, when the gate drive circuit 20 also includes two pull-down maintaining modules 204, both of which can control the potential of the signal q(n) of the first node Q(n) of the current stage, the potential of the stage transmission signal st(n) of the current stage, and the potential of the gate signal gate(n) of the current stage according to the signal k(n) of the second node K of the current stage, or it can also be understood that the left pull-down maintaining module 204 is controlled by the left inverting module 203, and the right pull-down maintaining module 204 is controlled by the right inverting module 203.

[0078] In some embodiments, as Figures 2 to 4As shown, the gate drive circuit 20 further comprises a reset module 205, and the reset module 205 in each stage of the gate drive circuit 20 is configured to reset the potential of the signal q(n) of the first node Q(n) in the stage before the starting moment of the time period in which the pulse of the frame start signal stv is located according to a reset signal.

[0079] It can be understood that the potential of the first node Q(1) in the first stage of the gate drive circuit 20 can be reset by the reset module 205 before being pre-charged by the pull-up control module 201, and the pre-charging moment of the potential of the first node Q(1) in each stage of the gate drive circuit 20 is later than the pre-charging moment of the potential of the first node Q(1) in the previous stage of the gate drive circuit 20, so the potential of the first node in all stages can be reset by the reset signal before being pre-charged.

[0080] Further, the reset module 205 in each stage of the gate drive circuit 20 is further configured to reset the potential of the gate signal gate(n) in the stage, the potential of the stage transfer signal st(n) in the stage according to the reset signal before the starting moment of the time period in which the pulse of the frame start signal stv is located. That is, the potential of the gate signal gate(n) in all stages, the potential of the stage transfer signal st(n) can also be reset by the reset signal at the same time (the potential of the first node is reset).

[0081] Further, as shown in the figure, Figures 2 to 4 The reset signal at least comprises a first reset signal Reset1 and a second reset signal Reset2, and the phase of the first reset signal Reset1 and the phase of the second reset signal Reset2 are different.

[0082] The reset module 205 is configured to reset one of the potential of the signal q(n) of the first node Q(n) in the stage, the potential of the gate signal gate(n) in the stage, and the potential of the stage transfer signal st(n) in the stage according to the first reset signal Reset1, and the reset module 205 is further configured to reset the other two of the three according to the second reset signal Reset2; or, the reset module 205 is configured to reset two of the three according to the first reset signal Reset1, and the reset module 205 is further configured to reset the other one of the three according to the second reset signal Reset2.

[0083] The figure only takes the former as an example to illustrate, for example, the first reset signal Reset1 can reset the potential of the signal q(n) of the first node Q(n) in the stage, and the second reset signal Reset2 can reset the potential of the gate signal gate(n) in the stage, and the potential of the stage transfer signal st(n) in the stage.

[0084] Further, as shown in the figure, in the gate drive circuit 20 controlled by the stage transmission signal st(n-i) of the previous i stage, the reset module 205 comprises: a first reset module 2051, configured to reset the potential of the signal q(n) of the first node Q(n) of the current stage according to the reset signal (for details, please refer to the relevant description above); and a second reset module 2052, configured to reset the potential of the signal q(n) of the first node Q(n) of the current stage according to the frame start signal stv after the potential of the signal q(n) of the first node Q(n) is reset by the first reset module 2051. Figures 2 to 4

[0085] Among them, the first reset module 2051 can comprise a first reset transistor T34, a second reset transistor T44, and a third reset transistor T74, and the second reset module 2052 can comprise a fourth reset transistor T45 and a fifth reset transistor T46. The connection relationship of the above six reset transistors can refer to the circuit diagram.

[0086] It can be understood that, in the nth stage gate drive circuit 20 controlled by the stage transmission signal st(n-i) of the previous i stage, since the potential of the first node Q(n) of the current stage is pre-charged by the pull-up control module 201 at the same time as the rising edge of the pulse of the stage transmission signal st(n-i) of the previous i stage, and the rising edge of the pulse of the frame start signal stv is earlier than the rising edge of the pulse of the stage transmission signal st(n-i) of the previous i stage, therefore, before the potential of the first node Q(n) of the current stage is pre-charged by the stage transmission signal st(n-i) of the previous i stage, the potential of the signal q(n) of the first node Q(n) of the current stage can be reset twice in turn by the reset signal and the frame start signal stv.

[0087] Further, as shown in the figure, in the gate drive circuit 20 controlled by the stage transmission signal st(n-i) of the previous i stage, the reset module 205 comprises: a first reset module 2051, configured to reset the potential of the signal q(n) of the first node Q(n) of the current stage according to the reset signal (for details, please refer to the relevant description above); and a second reset module 2052, configured to reset the potential of the signal q(n) of the first node Q(n) of the current stage according to the frame start signal stv after the potential of the signal q(n) of the first node Q(n) is reset by the first reset module 2051. Figures 2 to 4

[0088] ​​Based on the above discussion of the first frame start signal stv1 and the second frame start signal stv2, it can be seen that the first frame start signal stv1 can be applied to the gate drive circuits 20 of the first stage to the third stage, and the second frame start signal stv2 can be applied to the gate drive circuits 20 of the fourth stage to the sixth stage. Moreover, the phase of the first frame start signal stv1 can be earlier than the phase of the second frame start signal stv2. Therefore, starting from the seventh stage gate drive circuit 20, the second reset module 2052 in each stage can perform two resets based on the first frame start signal stv1 and the second frame start signal stv2 before the potential of the signal q(n) of the first node Q(n) in this stage is pre-charged.

[0089] In some embodiments, such as Figures 2 to 4 As shown, the gate driving circuit 20 further includes a pull-down module 206, used to control the signal q(n) of the first node Q(n) of the current stage according to the stage transmission signal st(n+j) of the j-th stage, where j is a positive integer. That is, during the pulse period of the stage transmission signal st(n+j) of the j-th stage, which is also the pulse period of the gate signal gate(n+j) of the j-th stage, the pull-down module 206 can transmit the fifth signal to the first node Q(n) of the current stage, thereby pulling down the potential of the signal q(n) of the first node Q(n) so that it reaches the falling edge of the corresponding pulse, preventing the first pull-up transistor T21 from remaining on and continuing to output the next pulse of the corresponding clock signal ck.

[0090] For example, when i is 6 and the corresponding number of clock lines CK is 12, j can be 6 or 8, that is, the potential of the signal q(n) of the first node Q(n) of this stage is pulled down according to the stage transmission signal st(n+6) of the last 6 stages or the stage transmission signal st(n+8) of the last 8 stages. Furthermore, the pull-down of the potential of the signal q(n) of the first node Q(n) can be maintained by the inverting module 203 and the pull-down maintenance module 204.

[0091] It is important to note that Figure 10 In this embodiment, since the gate of the fourth inverting transistor T56 is controlled by the stage transmission signal st(n+3) of the last 3 stages, before the pulse of the stage transmission signal st(n+6) of the last 6 stages or the stage transmission signal st(n+8) of the last 8 stages arrives, due to the effect of the stage transmission signal st(n+3) of the last 3 stages, the potential of the signal q(n) of the first node Q(n) of this stage is still maintained at a smaller value after its pulse value reaches the corresponding maximum value. It can be understood that its potential is the same as the potential that was previously precharged.

[0092] Embodiments of the present invention also provide a display device, such as... Figure 11As shown, the display device 200 includes a display panel 100 as described above and a driver chip 300 electrically connected to the display panel 100. The driver chip 300 is used to transmit the frame start signal stv and the first signal to the multi-level gate driving circuit 20, and to transmit data signals to the plurality of pixels Pi; or, as shown ​ As shown, the display device 200 includes a display panel 100 as described above, a timing driver chip 301 and a source driver chip 302 electrically connected to the display panel 100. The timing driver chip 301 is used to transmit the frame start signal stv and the first signal to the multi-level gate driver circuit 20, and the source driver chip 302 is used to transmit data signals to the plurality of pixels Pi. The gate signal gate(n) and the data signals are used to control the display panel 100 to display the image.

[0093] The display panel and display device provided in the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The system includes multiple pixels and cascaded multi-stage gate driving circuits, wherein one stage of the multi-stage gate driving circuit includes: The pull-up control module is used to control the signal of the first node in the gate drive circuit of this stage according to the frame start signal or the stage transmission signal of the previous i stages, where i is a positive integer; A pull-up module is electrically connected to the first node and the first signal line of this stage. It is used to generate a gate signal output through the gate line of this stage based on the signal of the first node and the first signal line of this stage. The pulse in the signal of the first node of this stage is used to control the pull-up module to generate the pulse in the gate signal of this stage based on the first signal of this stage. The pulse width of the pulse in the signal of the first node of this stage is greater than the pulse width of the gate signal of this stage. An inverting module includes multiple inverting transistors, the gates of which are electrically connected to multiple signal lines to be inverted. Each inverting transistor is used to control the potential of the gate signal of its own stage according to the signal to be inverted transmitted by the corresponding signal line to be inverted. The total time period of the pulses in the multiple signals to be inverted covers the time period of the pulses in the signal of the first node of this level.

2. The display panel according to claim 1, characterized in that, The plurality of said inverting transistors include at least a first inverting transistor and a second inverting transistor, and the plurality of said signal lines to be inverted include at least a first signal line to be inverted and a second signal line to be inverted; The gate of the first inverting transistor and the gate of the second inverting transistor are electrically connected to the first signal line to be inverted and the second signal line to be inverted, respectively. The first inverting transistor is used to control the potential of the gate signal of this stage according to the first signal to be inverted transmitted by the first signal line to be inverted. The second inverting transistor is used to control the potential of the gate signal of this stage according to the second signal to be inverted transmitted by the second signal line to be inverted. Wherein, the start time of the pulse in the first signal to be inverted is earlier than or the same as the start time of the pulse in the signal of the first node of the same level, and the end time of the pulse in the second signal to be inverted is later than or the same as the end time of the pulse in the signal of the first node of the same level. The time period of the pulse in the first signal to be inverted overlaps with the time period of the pulse in the second signal to be inverted.

3. The display panel according to claim 1, characterized in that, The amplitude of the pulse in the first signal to be inverted and the amplitude of the pulse in the second signal to be inverted are both less than the maximum amplitude of the pulse in the signal of the first node.

4. The display panel according to claim 3, characterized in that, It includes multiple clock lines, each clock line is used to transmit a corresponding clock signal, and the first signal line of each stage is one of the clock lines; The pull-up module includes: The first pull-up transistor has its gate electrically connected to the first node of this stage, one of its source and drain electrically connected to the corresponding clock line, and the other of its source and drain electrically connected to the gate line of this stage. Specifically, during the time period of the pulse in the signal of the first node at this level, the pulse of the clock signal is used to control the amplitude of the pulse in the signal of the first node to reach the corresponding maximum value.

5. The display panel according to any one of claims 2 to 4, characterized in that, The pull-up module is also used to generate the stage transmission signal of this level through the stage transmission line based on the signal of the first node of this level and the first signal of this level. The pulse in the signal of the first node of this level is used to control the pull-up module to generate the pulse in the stage transmission signal of this level based on the first signal of this level. The pulse width of the pulse in the signal of the first node of this level is greater than the pulse width of the pulse in the stage transmission signal of this level. Wherein, the first signal line to be inverted is the stage transmission line of the previous k1 stage, the second signal line to be inverted is the stage transmission line of this stage or the stage transmission line of the next k2 stage, k1 and k2 are both positive integers, and k1 is greater than or equal to i.

6. The display panel according to claim 5, characterized in that, The inverting module further includes a third inverting transistor, the gate of which is electrically connected to the stage transmission line of the previous k3 stages. The third inverting transistor is used to control the potential of the gate signal of this stage according to the stage transmission signal transmitted by the stage transmission line of the previous k3 stages, where k3 is a positive integer and k3 is less than i.

7. The display panel according to claim 6, characterized in that, The time periods of the pulses of the stage transmission signals of the first k1th stage to be inverted signal and the time periods of the pulses of the stage transmission signals of the first k3th stage overlap. The time periods of the pulses of the stage transmission signal of the first k3 stages overlap with the time periods of the pulses of the stage transmission signal of this stage, which serves as the second phase-to-invert signal, or the pulses of the stage transmission signal of the last k2 stages.

8. The display panel according to any one of claims 2 to 4, characterized in that, The inverting module also includes: A first inverting control transistor, the gate of which is electrically connected to a second signal line, and one of the sources and drains of the first inverting control transistor, one of the sources and drains of the first inverting transistor, and one of the sources and drains of the second inverting transistor are all electrically connected to a second node of this stage. The first inverting control transistor is used to control the signal of the second node of this stage according to the second signal transmitted by the second signal line, and the signal of the second node of this stage is used to control the gate signal of this stage. Wherein, the first inverting control transistor is used to pull up the potential of the signal of the second node of this stage, and the first inverting transistor and the second inverting transistor are used to pull down the potential of the signal of the second node of this stage.

9. The display panel according to claim 8, characterized in that, The inverting module also includes: The second inverting control transistor has its gate electrically connected to the third signal line, and one of its source and drain is electrically connected to one of the source and drain of the first inverting control transistor. The second inverting control transistor is used to pull down the potential of the signal of the second node in this stage. Wherein, the second signal line and the third signal line each include a first sub-signal line and a second sub-signal line, and the second signal and the third signal each include a first sub-signal transmitted by the first sub-signal line and a second sub-signal transmitted by the second sub-signal line, wherein the phase of the first sub-signal and the phase of the second sub-signal are opposite; The gate drive circuit includes two inverting modules. In one of the two inverting modules, the gate of the first inverting control transistor is electrically connected to the first sub-signal line, and the gate of the second inverting control transistor is electrically connected to the second sub-signal line. In the other of the two inverting modules, the gate of the first inverting control transistor is electrically connected to the second sub-signal line, and the gate of the second inverting control transistor is electrically connected to the first sub-signal line.

10. The display panel according to claim 8, characterized in that, The other of the source and drain of the first inverting control transistor is electrically connected to the gate of the first inverting control transistor, or electrically connected to the fourth signal line for transmitting the fourth signal. The gate driving circuit further includes: The pull-down sustaining module is electrically connected to the second node of this stage and the gate line of this stage; The potential of the fourth signal and the potential of the second signal when the first inverting control transistor is turned on are both used to pull down the potential of the signal of the second node of this stage, so that the pull-down maintenance module pulls down the potential of the gate signal of this stage.

11. The display panel according to claim 10, characterized in that, The pull-down sustaining module is also electrically connected to the first node of this level and the stage transmission line for transmitting the stage transmission signal of this level. The pull-down sustaining module is also used to control the potential of the signal of the first node of this level and the potential of the stage transmission signal of this level according to the signal of the second node of this level.

12. The display panel according to any one of claims 1 to 4, characterized in that, The pull-up control module includes: A pull-up control transistor, wherein the gate of the pull-up control transistor is electrically connected to a frame start line for transmitting the frame start signal or a stage transmission line for transmitting the stage transmission signal of the previous stage, and one of the source and drain of the pull-up control transistor is electrically connected to the first node of the current stage. The other of the source and drain of the pull-up control transistor is electrically connected to the gate of the pull-up control transistor, or electrically connected to the fourth signal line for transmitting the fourth signal. Wherein, the potential of the fourth signal and the potential of the stage transmission signal of the first i stage when the pull-up control transistor is turned on are both used to pull up the potential of the signal of the first node of this stage.

13. The display panel according to any one of claims 1 to 4, characterized in that, The gate driving circuit further includes a reset module. The reset modules in the multi-stage gate driving circuit are all used to reset the potential of the signal of the first node of the multi-stage circuit before the start time of the pulse of the frame start signal according to the reset signal.

14. The display panel according to claim 13, characterized in that, The reset module in the multi-stage gate drive circuit is also used to reset the potential of the gate signal and the potential of the stage transmission signal of the current stage before the start time of the pulse of the frame start signal according to the reset signal. The reset signal includes at least a first reset signal and a second reset signal, wherein the phases of the first reset signal and the second reset signal are different; The reset module is used to reset one of the potential of the signal of the first node of the current stage, the potential of the gate signal of the current stage, and the potential of the stage transmission signal of the current stage according to the first reset signal. The reset module is also used to reset the other two of the three according to the second reset signal. Alternatively, the reset module is used to reset two of the three components according to the first reset signal, and the reset module is also used to reset the third of the three components according to the second reset signal.

15. The display panel according to claim 13, characterized in that, In the gate drive circuit controlled by the stage transmission signal of the preceding i-th stage, the reset module includes: The first reset module is used to reset the potential of the signal of the first node of this stage according to the reset signal; The second reset module is used to reset the potential of the first node's signal at this level according to the frame start signal after the potential of the first node's signal has been reset by the first reset module.

16. The display panel according to claim 15, characterized in that, The frame start signal includes at least a first frame start signal and a second frame start signal with a phase difference. The pull-up control module is used to control the signal of the first node of the current stage according to one of the first frame start signal, the second frame start signal, and the stage transmission signal of the previous i stages. In the gate drive circuit controlled by the stage transmission signal of the previous i stage, the second reset module is used to reset the potential of the signal of the first node of the current stage in sequence according to the first frame start signal and the second frame start signal.

17. The display panel according to any one of claims 1 to 4, characterized in that, The gate driving circuit further includes: The drop-down module is used to control the signal of the first node in this level according to the transmission signal of the next j level, where j is a positive integer.

18. The display panel according to claim 17, characterized in that, The first signal line is a clock line, the first signal is a clock signal, and there are 12 first signal lines. Each pair of the 12 clock signals has a phase difference. Where i is 6 and j is 6 or 8.

19. The display panel according to any one of claims 1 to 4, characterized in that, The active layer of each of the plurality of said inverting transistors is made of a metal oxide.

20. A display device, characterized in that, The device includes a display panel as described in any one of claims 1 to 19 and a driver chip electrically connected to the display panel, the driver chip being used to transmit the frame start signal and the first signal to the multi-level gate driving circuit, and to transmit data signals to the plurality of pixels; Alternatively, the display device includes a display panel as described in any one of claims 1 to 19, a timing driver chip electrically connected to the display panel, and a source driver chip, wherein the timing driver chip is used to transmit the frame start signal and the first signal to the multi-level gate driving circuit, and the source driver chip is used to transmit data signals to the plurality of pixels. The gate signal and the data signal are used to control the display panel to display the image.

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