Display device

Abstract

The invention discloses a display device. The display device includes: a substrate; a first insulating layer disposed on the substrate and including an inorganic insulating material; an oxide semiconductor layer disposed on the first insulating layer; a second insulating layer disposed on the oxide semiconductor layer and including an inorganic insulating material; and a third insulating layer disposed on the gate electrode and including an inorganic insulating material, the gate electrode disposed on the second insulating layer. The oxide semiconductor layer includes a first conductive region, a second conductive region, and a channel region between the first conductive region and the second conductive region, and a value of HC in the channel region of the oxide semiconductor layer is less than 30% according to equation (1).

Description

[0001] Divisional Explanation

[0002] This application is a divisional application of the application patent application with the application date of August 19, 2020, the national application number of 202010836192.5, and the invention name of "Display device and method of manufacturing display device".

[0003] Cross Reference to Related Applications

[0004] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0108938, filed on September 3, 2019, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by this reference. TECHNICAL FIELD

[0005] One or more embodiments relate to a display device and a method of manufacturing a display device. BACKGROUND

[0006] The purpose of display devices is diversifying. In addition, as display devices have become thinner and lighter, their range of use has gradually extended. In particular, as the demand for high-resolution and large-area display devices increases, there is a need for high-quality thin film transistors that can be miniaturized and are not affected by pressure drop. SUMMARY

[0007] One or more embodiments include a display device including a transistor including an oxide semiconductor layer and a method of manufacturing a display device.

[0008] According to one or more embodiments, a display device includes a substrate, a first insulating layer provided over the substrate and including an inorganic insulating material, an oxide semiconductor layer provided over the first insulating layer, a second insulating layer provided over the oxide semiconductor layer and including an inorganic insulating material, a gate electrode provided over the second insulating layer, and a third insulating layer provided over the gate electrode and including an inorganic insulating material. The oxide semiconductor layer includes a first conductive region, a second conductive region, and a channel region between the first conductive region and the second conductive region. The hydrogen concentration of the oxide semiconductor layer is about 5 x 10 20 atoms / cm 3 to about 2 x 10 21 atoms / cm 3the value of HC in the channel region of the oxide semiconductor layer is less than 30% according to Equation (1): HC = (Max - Min) / Avg x 100% — Equation (1), where Max represents the maximum hydrogen concentration value detected from a plurality of points within the channel region, Min represents the minimum hydrogen concentration value detected from a plurality of points within the channel region, and Avg represents the average hydrogen concentration value detected from a plurality of points within the channel region.

[0009] The hydrogen concentration of the channel region can be in a range of about 1 x 1019 atoms / cm3 to about 2 x 1020 atoms / cm3. 21 3 The hydrogen concentration of the channel region can be in a range of about 1 x 1019 atoms / cm3 to about 2 x 1020 atoms / cm3. 21 3 The hydrogen concentration of the channel region can be in a range of about 1 x 1019 atoms / cm3 to about 2 x 1020 atoms / cm3.

[0010] The second insulating layer can include a silicon oxide layer.

[0011] At least one of the first insulating layer and the third insulating layer can include a silicon oxide layer or a silicon nitride layer.

[0012] The display device can further include a metal layer interposed between the substrate and the first insulating layer.

[0013] The oxide semiconductor layer can contain fluorine and the concentration of fluorine of the oxide semiconductor layer can be in a range of about 5 x 1019 atoms / cm3 to about 5 x 1020 atoms / cm3. 17 3 The oxide semiconductor layer can contain fluorine and the concentration of fluorine of the oxide semiconductor layer can be in a range of about 5 x 1019 atoms / cm3 to about 5 x 1020 atoms / cm3. 18 3 The oxide semiconductor layer can contain fluorine and the concentration of fluorine of the oxide semiconductor layer can be in a range of about 5 x 1019 atoms / cm3 to about 5 x 1020 atoms / cm3.

[0014] The metal layer can include a bottom gate electrode.

[0015] According to one or more embodiments, a display device includes: a substrate; first and second transistors each disposed on the substrate, wherein one of the first and second transistors includes an oxide semiconductor layer including a channel region, a first conductive region, and a second conductive region, wherein the first and second conductive regions are located on two opposite sides of the channel region, respectively; a first insulating layer interposed between the substrate and the oxide semiconductor layer; a gate electrode overlapping with the channel region of the oxide semiconductor layer; a second insulating layer interposed between the oxide semiconductor layer and the gate electrode; and a third insulating layer disposed on the second insulating layer and covering the gate electrode. The hydrogen concentration of the oxide semiconductor layer is in a range of about 5 x 1019 atoms / cm3 to about 2 x 1020 atoms / cm3. 20 3 The hydrogen concentration of the channel region can be in a range of about 1 x 1019 atoms / cm3 to about 2 x 1020 atoms / cm3. 21 3 ​​​​​​Within the range, and according to equation (1), the HC value in the channel region of the oxide semiconductor layer is less than 30%: HC=(Max-Min) / Avg×100%------Equation (1), where Max represents the maximum hydrogen concentration value detected from multiple points in the channel region, Min represents the minimum hydrogen concentration value detected from multiple points in the channel region, and Avg represents the average hydrogen concentration value detected from multiple points in the channel region.

[0016] The hydrogen concentration in the channel region can be approximately 1 × 10⁻⁶. 21 atoms / cm 3 Approximately 2×10 21 atoms / cm 3 Within the range.

[0017] The second insulating layer includes a silicon oxide layer. At least one of the first and third insulating layers includes a silicon oxide layer or a silicon nitride layer.

[0018] The display device may further include a metal layer between the substrate and the first insulating layer.

[0019] The metal layer can have the same voltage level as the gate electrode.

[0020] The other of the first and second transistors may be a silicon transistor.

[0021] According to one or more embodiments, a method of manufacturing a display device includes: forming a first insulating layer comprising an inorganic insulating material on a substrate; forming an oxide semiconductor layer on the first insulating layer; forming a second insulating layer comprising an inorganic insulating material on the oxide semiconductor layer; forming a gate electrode on the second insulating layer; and forming a third insulating layer comprising an inorganic insulating material on the gate electrode. The third insulating layer is formed by ammonia-free chemical vapor deposition. The oxide semiconductor layer includes a first conductive region, a second conductive region, and a channel region located between the first conductive region and the second conductive region, and according to equation (1), the HC value in the channel region of the oxide semiconductor layer is less than 30%: HC=(Max-Min) / Avg×100%------Equation (1), where Max represents the maximum hydrogen concentration value detected from multiple points in the channel region, Min represents the minimum hydrogen concentration value detected from multiple points in the channel region, and Avg represents the average hydrogen concentration value detected from multiple points in the channel region.

[0022] The hydrogen concentration in the channel region can be approximately 1 × 10⁻⁶. 21 atoms / cm 3 Approximately 2×10 21 atoms / cm 3 Within the range.

[0023] The second insulating layer can include a silicon oxide layer, and the silicon oxide layer can cover the channel region, at least a portion of the first conductive region, and at least a portion of the second conductive region.

[0024] The method can further include applying heat to the first insulating layer before forming the oxide semiconductor layer.

[0025] The method can further include forming a metal layer on the substrate before forming the first insulating layer.

[0026] Forming the metal layer can include forming an initial layer including a metal, and etching the initial layer so that the metal layer overlaps the channel region of the oxide semiconductor layer, and the etching the initial layer can include using a gas including fluorine.

[0027] The oxide semiconductor layer can include fluorine, and a concentration of the fluorine can be in a range of about 5 x 10 17 atoms / cm 3 to about 5 x 10 18 atoms / cm 3 .

[0028] The above and other aspects and features of certain embodiments of the present disclosure will be more apparent from the following description, taken in conjunction with the accompanying drawings, in which: BRIEF DESCRIPTION OF DRAWINGS

[0029] Figures 1 to 9 A process of forming an oxide transistor of a display device according to an embodiment is illustrated.

[0030] Figure 10 A plan view of an oxide semiconductor layer of an oxide transistor according to an embodiment is illustrated.

[0031] Figure 11 A secondary ion mass spectrometry apparatus for measuring a concentration of hydrogen or fluorine of an oxide transistor according to an embodiment is illustrated.

[0032] Figure 12 An equivalent circuit diagram of one pixel of a display device according to an embodiment is illustrated.

[0033] Figure 13 A cross-sectional view of a display device according to an embodiment is illustrated.

[0034] Figure 14 A graph of a secondary ion mass spectrometry (SIMS) detection result of an oxide transistor of a display device according to an embodiment and a graph of an analysis result of some materials of the oxide transistor are illustrated.

[0035] Figure 15 A graph of a hydrogen concentration in an oxide semiconductor layer of an oxide transistor of a display device according to an embodiment is illustrated. DETAILED DESCRIPTION

[0036] Reference will now be made in detail embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals can refer to like elements throughout. In this regard, embodiments can have different forms and should not be construed as limited to the descriptions set forth herein.

[0037] Embodiments are described in detail below with reference to the accompanying drawings. In the drawings, like reference numerals can refer to like elements throughout, and a repeated description can be omitted.

[0038] Herein, when one value is described as approximately equal to another value, for example, "the width can be about 0.1 mm to about 1 mm", it should be understood that the values are equal to each other within a measurement error, or if not equal in measurement, the values are close enough to be functionally equal to each other, as would be understood by one of ordinary skill in the art.

[0039] It should be understood that when a layer, region, or component is referred to as being "formed on" another layer, region, or component, it can be "directly formed on" the other layer, region, or component or "indirectly formed on" the other layer, region, or component, with another layer, region, or component intervening therebetween.

[0040] For ease of explanation, the size of elements in the drawings can be exaggerated.

[0041] It should be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, it can be "directly connected" to the other layer, region, or component and / or can be "indirectly connected" to the other layer, region, or component, with other layers, regions, or components intervening therebetween.

[0042] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system, and can be interpreted in a broader sense.

[0043] For ease of description, although the display device according to the embodiments is described as an organic light emitting display device as an example, the display device according to the present disclosure is not limited thereto. For example, the display device can be an inorganic light emitting display.

[0044] Figures 1 to 9 A process of forming an oxide transistor of a display device according to an embodiment is illustrated.

[0045] Referring to Figure 1 According to an embodiment, a metal layer 105 is formed on a substrate 100. The substrate 100 can include a glass material or a polymer resin. For example, the substrate 100 includes a glass material including SiO2 as a main component.

[0046] According to embodiments, the metal layer 105 has a predetermined width and a predetermined length, and is formed by forming an initial metal layer and etching the initial metal layer. An example, non-limiting etching process is dry etching. The etching uses a gas including fluorine. In embodiments, the metal layer 105 can include a single layer or multiple layers, and include one or more of aluminum (Al), molybdenum (Mo), copper (Cu), and titanium (Ti). The metal layer 105 is formed by forming an initial metal layer including the above-described materials on the substrate 100 and then etching the initial metal layer. For example, the metal layer 105 can be patterned by dry etching using sulfur hexafluoride (SF6).

[0047] According to embodiments, the metal layer 105 will overlap at least a portion of the oxide semiconductor layer 120 formed during the processes to be described below. Figure 4 In embodiments, although the metal layer 105 is shown as completely overlapping the oxide semiconductor layer 120 in Figure 4 In another embodiment, however, the metal layer 105 overlaps or covers a portion of the oxide semiconductor layer 120, such as a channel region of the oxide semiconductor layer 120. The metal layer 105 blocks light incident to the oxide semiconductor layer 120, or functions as a gate electrode of the oxide semiconductor layer 120 by having a predetermined voltage, such as a gate voltage.

[0048] Referring to Figure 2 According to embodiments, a bottom (or lower) insulating layer 110 is formed on the substrate 100. The bottom insulating layer 110 includes an inorganic insulating material and is formed by chemical vapor deposition (CVD). For example, the bottom insulating layer 110 is deposited by plasma enhanced chemical vapor deposition (PECVD). Alternatively, in other embodiments, the bottom insulating layer 110 can be deposited by various other deposition methods, such as atmospheric pressure CVD (APCVD) or low pressure CVD (LPCVD).

[0049] According to embodiments, the bottom insulating layer 110 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. The bottom insulating layer 110 can have a single layer structure or a multi-layer structure including the above-described materials. For example, the bottom insulating layer 110 can have a two-layer structure of a silicon nitride layer and a silicon oxide layer.

[0050] Compared to a silicon oxide layer, according to embodiments, a silicon nitride layer is an insulating layer having a relatively high hydrogen content. Processes according to embodiments of forming a silicon nitride layer by using PECVD are described below.

[0051] According to an embodiment, a substrate 100 is inserted into a chamber and a plasma atmosphere is formed, the substrate 100 being the object on which deposition is performed. A silicon nitride layer is formed by using silane (SiH4) and ammonia (NH3). In an embodiment, the layer formation gas for forming the silicon nitride layer includes nitrogen molecules (N2), silane and ammonia. Silane is decomposed into silicon (Si) and hydrogen (H) by plasma, and ammonia is decomposed into nitrogen (N) and hydrogen (H). When each decomposed atom falls on the substrate 100 and each fallen atom reacts based on the surface temperature of the substrate 100, a silicon nitride layer is formed on the substrate 100.

[0052] According to an embodiment, a silicon oxide layer is formed by PECVD using silane and nitrous oxide (N2O). In this case, the silicon oxide layer includes hydrogen (H). Alternatively, in another embodiment, a silicon oxide layer is formed using a layer formation gas including silicon fluoride and oxygen. For silicon fluoride, for example, silicon tetrafluoride (SiF4) and disilicon hexafluoride (Si2F6) are used. In the case where a layer formation gas including silicon fluoride is used, the silicon oxide layer includes fluorine (F).

[0053] In an embodiment, the silicon oxide layer formed by using silane and nitrous oxide (N2O) also includes hydrogen (H) and fluorine (F). In this case, fluorine (F) originates from sulfur hexafluoride (SF6) gas used when etching the metal layer 105, or from a cleaning process or a drying process of the chamber during the PECVD process.

[0054] Reference is made to Figure 3 According to an embodiment, after the bottom insulating layer 110 is formed, a heat treatment process is performed. The bottom insulating layer 110 includes hydrogen (H). Since hydrogen, hydroxyl or moisture can affect the oxide semiconductor layer described below, its concentration is reduced in advance by the heat treatment process.

[0055] According to an embodiment, by the heat treatment process, hydrogen (H) or fluorine (F) in the bottom insulating layer 110 is removed. The heat treatment process is performed at a temperature higher than about 400 °C, for example, at about 460 °C for about 1 hour. By the heat treatment process, the hydrogen (H) concentration or the fluorine (F) concentration in the bottom insulating layer 110 is reduced.

[0056] Reference is made to Figure 4According to the embodiment, the oxide semiconductor layer 120 is formed over the bottom insulating layer 110. The oxide semiconductor layer 120 includes one of a Zn oxide, an In-Zn oxide, and a Ga-In-Zn oxide as a Zn oxide-based material. The oxide semiconductor layer 120 includes a semiconductor including a Zn oxide-based material containing a metal such as In, Ga, and / or Sn. For example, the oxide semiconductor layer 120 can include one of an IGZO (In-Ga-Zn-O) semiconductor, an ITZO (In-Sn-Zn-O) semiconductor, and an IGTZO (In-Ga-Sn-Zn-O) semiconductor.

[0057] In the embodiment, the oxide semiconductor layer 120 is formed by a sputtering method using an In-Ga-Zn-O-based oxide target. For example, the oxide semiconductor layer 120 is formed by a sputtering method in an inert gas (such as argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere including an inert gas and oxygen.

[0058] Reference is made to Figure 5 According to the embodiment, the intermediate insulating layer 130 is formed over the oxide semiconductor layer 120. The intermediate insulating layer 130 includes an inorganic insulating material. The intermediate insulating layer 130 functions as a gate insulating layer interposed between the gate electrode described below and the oxide semiconductor layer 120.

[0059] According to the embodiment, the intermediate insulating layer 130 completely covers the substrate 100. For example, Figure 3 The top surface of the oxide semiconductor layer 120 shown is completely covered with the intermediate insulating layer 130. When the intermediate insulating layer 130 includes silicon nitride, because the silicon nitride already includes a relatively high hydrogen content as described above, the oxide semiconductor layer 120 under the intermediate insulating layer 130 becomes completely conductive during the process of forming the intermediate insulating layer 130. In this case, the oxide semiconductor layer 120 can not function as an active layer of a transistor. Therefore, the intermediate insulating layer 130 is formed to include silicon oxide.

[0060] According to the embodiment, the intermediate insulating layer 130 is formed by a CVD process such as PECVD, APCVD, or LPCVD, and the like, as with the process of forming the bottom insulating layer 110 described with reference to Figure 2 The specific formation process is the same as the formation process described above.

[0061] Reference is made to Figure 6 According to the embodiment, the gate electrode 140 is formed over the intermediate insulating layer 130. The gate electrode 140 can include a single layer or a plurality of layers containing one or more of aluminum (Al), molybdenum (Mo), copper (Cu), and titanium (Ti). The gate electrode 140 overlaps with a portion of the oxide semiconductor layer 120.

[0062] With reference to Figure 7 According to an embodiment, a top (or upper) insulating layer 150 is formed over the gate electrode 140. The top insulating layer 150 includes an inorganic insulating material. The top insulating layer 150 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. The top insulating layer 150 can be a single-layer structure or a multi-layer structure including the above-described materials. For example, the top insulating layer 150 is a bi-layer structure of a silicon nitride layer and a silicon oxide layer.

[0063] According to an embodiment, the top insulating layer 150 is formed by a CVD process, such as PECVD, APCVD, or LPCVD, etc., as with the process described with reference to Figure 2

[0064] Hydrogen originating from the gas used during the process of forming the top insulating layer 150, such as those used in PECVD, can contribute to make a portion of the oxide semiconductor layer 120 conductive. For example, according to an embodiment, a portion of the oxide semiconductor layer 120 that does not overlap with the gate electrode 140 can become conductive by the above-described hydrogen, and the oxide semiconductor layer 120 will include a channel region 121, a first conductive region 122, and a second conductive region 123. The first conductive region 122 and the second conductive region 123 are on two opposite sides of the channel region 121.

[0065] According to an embodiment, when a large amount of hydrogen is generated during the process of forming the top insulating layer 150, the area of the oxide semiconductor layer 120 that becomes conductive by the hydrogen increases, and thus the length of the channel region 121 is reduced.

[0066] To prevent this from happening, according to an embodiment, a silicon nitride layer is formed as the top insulating layer 150 by PECVD that does not contain ammonia (NH3). In this case, the silicon nitride layer is formed by using silane and nitrogen gas (N2). Because PECVD that does not contain ammonia (NH3) includes a small amount of hydrogen compared to the above-described PECVD, the hydrogen concentration in the silicon nitride layer formed by PECVD that does not contain ammonia (NH3) is relatively low, which prevents the length of the channel region from being reduced.

[0067] With reference to Figure 8 According to an embodiment, after forming the contact hole CNT that exposes a conductive region of the oxide semiconductor layer 120, such as one or both of the first conductive region 122 and the second conductive region 123, an annealing process is performed. In an embodiment, the annealing process is performed at a temperature of about 350 °C or higher, or about 400 °C or higher.

[0068] ​According to an embodiment, the conductorization of the oxide semiconductor layer 120 is induced by an annealing process. The hydrogen concentration of the first conductive region 122 and the second conductive region 123 changes before and after the annealing process. For example, the hydrogen concentration of the first conductive region 122 and the second conductive region 123 after the annealing process is higher than the hydrogen concentration of the first conductive region 122 and the second conductive region 123 before the annealing process. One of the first conductive region 122 and the second conductive region 123 corresponds to a source region, and the other of the first conductive region 122 and the second conductive region 123 corresponds to a drain region.

[0069] Referring to Figure 9 , according to an embodiment, an electrode layer is formed connected to at least one of the first conductive region 122 and the second conductive region 123. In an embodiment, Figure 9 A first electrode layer 161 and a second electrode layer 162 are shown connected to the first conductive region 122 and the second conductive region 123, respectively. One of the first electrode layer 161 and the second electrode layer 162 corresponds to a source electrode of the transistor, and the other of the first electrode layer 161 and the second electrode layer 162 corresponds to a drain electrode of the transistor.

[0070] According to an embodiment, the first electrode layer 161 and the second electrode layer 162 are each a single-layer structure or a multi-layer structure including one or more of aluminum (Al), molybdenum (Mo), copper (Cu), and titanium (Ti). The first electrode layer 161 and the second electrode layer 162 are patterned after forming a layer including the above-mentioned materials by a process such as dry etching.

[0071] Figure 10 A plan view of an oxide semiconductor layer of an oxide transistor according to an embodiment.

[0072] Referring to Figure 10 , according to an embodiment, the oxide semiconductor layer 120 includes a channel region 121, a first conductive region 122 on a first side of the channel region 121, and a second conductive region 123 on a second side of the channel region 121. The oxide semiconductor layer 120 includes a Zn-oxide-based material. The Zn-oxide-based material includes one or more of Zn-oxide, In-Zn-oxide, and Ga-In-Zn-oxide, etc. The oxide semiconductor layer 120 includes a semiconductor including a Zn-oxide-based material including a metal such as one or more of In, Ga, and Sn. For example, the oxide semiconductor layer 120 includes one of an IGZO (In-Ga-Zn-O) semiconductor, an ITZO (In-Sn-Zn-O) semiconductor, and an IGTZO (In-Ga-Sn-Zn-O) semiconductor.

[0073] According to the embodiment, the hydrogen concentration in the first conductive region 122 and the second conductive region 123 is higher than the hydrogen concentration in the channel region 121. Because by referring to... Figures 1 to 9 One or both of the processes described for forming the top insulating layer 150 and the annealing process introduce hydrogen into the first conductive region 122 and the second conductive region 123, so that the hydrogen concentration in the first conductive region 122 and the second conductive region 123 is higher than the hydrogen concentration in the channel region 121.

[0074] According to the embodiment, the typical hydrogen concentration of the oxide semiconductor layer 120 is about 5 × 10⁻⁶. 20 atoms / cm 3 Approximately 2×10 21 atoms / cm 3 Within a certain range. The hydrogen concentration in the channel region 121 of the oxide semiconductor layer 120 is approximately 1 × 10⁻⁶. 21 atoms / cm 3 Approximately 2×10 21 atoms / cm 3 Within the range.

[0075] According to the embodiment, when the difference in hydrogen concentration at each measurement point in the channel region 121 is large, the driving performance of the display device including the oxide semiconductor layer deteriorates, and the display quality of the display device also deteriorates. Conversely, in the channel region 121 of the oxide semiconductor layer 120 manufactured according to the above process, the hydrogen concentration value HC in the following equation (1) is less than 30%.

[0076] HC=(Max-Min) / Avg×100%-------Equation (1),

[0077] Where Max represents the maximum hydrogen concentration value detected from multiple points within channel region 121, Min represents the minimum hydrogen concentration value detected from multiple points within channel region 121, and Avg represents the average hydrogen concentration value detected from multiple points within channel region 121. When the above conditions are not met, the channel length of channel region 121 cannot be sufficiently ensured, and the display quality of the display device may not be guaranteed due to, for example, the occurrence of leakage current. More appropriately, the HC value according to equation (1) may be 20% or less.

[0078] According to an embodiment, the hydrogen concentration of the channel region 121 is measured in an effective region 121VR defined inward from the edge of the channel region 121. Assuming W is the width of the channel region 121 in the width direction, and L is the length of the channel region 121 between the first conductive region 122 and the second conductive region 123, the edge region of the channel region 121, having a width and length of approximately 0.15% × L and 0.15% × W, is where noise occurs when measuring the hydrogen concentration. Therefore, the area separated from the edge of the channel region by approximately 0.15% × L and 0.15% × W... Figure 10The hydrogen concentration is measured in a region indicated by a mark (hereinafter referred to as an effective region 121VR). In an embodiment, Figure 10 The effective region 121VR is shown to have a quadrangular shape. In an embodiment, the effective region 121VR has a curved shape or a serpentine shape. The effective region 121VR spaced apart from the edge of the channel region 121 has a length corresponding to about 99.7% x L and a width corresponding to about 99.7% x W. In an embodiment, the length L of the channel region 121 is about 10 pm or less.

[0079] In an embodiment, the hydrogen concentration of the effective region 121VR of the channel region 121 is in a range from about 5 x 1019atoms / cm3to about 2 x 1020atoms / cm3, and the hydrogen concentration at any first point within the effective region 121VR is less than twice the hydrogen concentration at a second point. For example, the hydrogen concentration of the effective region 121VR of the channel region 121 can be in a range from about 1 x 1019atoms / cm3to about 2 x 1020atoms / cm3. 20 3 21 3 21 3 21 3

[0080] According to an embodiment, the oxide semiconductor layer 120 includes fluorine obtained by a process of forming the metal layer 105 described with reference to Figure 1 For example, the fluorine concentration of the channel region 121 of the oxide semiconductor layer 120 is less than the fluorine concentration of the first conductive region 122 or the second conductive region 123. In an embodiment, the fluorine concentration of the channel region 121 is in a range from about 5 x 1019atoms / cm3to about 5 x 1020atoms / cm3. 17 3 18 3

[0081] According to an embodiment, the hydrogen concentration and the fluorine concentration can be measured by secondary ion mass spectrometry (SIMS).

[0082] Figure 11 A secondary ion mass spectrometry apparatus for measuring the concentration of hydrogen or fluorine of an oxide transistor according to an embodiment is illustrated.

[0083] Referring to Figure 11 , the SIMS apparatus includes a chamber 1100, a primary ion source 1200, an electron generation source 1300, and a secondary ion optical system 1400.

[0084] ​​​​​​​​​​​​According to embodiments, the primary ion source 1200 generates and emits an ion beam. The primary ion source 1200 emits the primary ion beam PB1 toward an oxide semiconductor layer OS on a sample, such as a substrate Sub, placed inside the chamber 1100. The chamber 1100 is in a vacuum state.

[0085] According to embodiments, the primary ion source 1200 emits the primary ion beam PB1 including cesium ions (Cs + ). After the primary ion beam PB1 is irradiated onto the sample, secondary ions SB2 emitted from the sample propagate to the secondary ion optical system 1400 by a sputtering phenomenon. The primary ion beam PB1 moves in a direction perpendicular to the sample, such as the oxide semiconductor layer OS, and the secondary ions SB2 propagate in a direction perpendicular to the sample (e.g., the oxide semiconductor layer OS). For example, a passage of the primary ion beam PB1 and a passage of the secondary ions SB2 are on the same axis.

[0086] According to embodiments, the electron generation source 1300 includes an electron gun that emits an electron beam to prevent the sample from being charged by sputtering ions.

[0087] According to embodiments, Figure 11 The SIMS apparatus shown in FIG. 10 applies a predetermined voltage to a substrate Sub, such as a glass substrate. Because the glass substrate has a low conductivity compared to a wafer, there is a limitation in preventing charging even when the electron generation source 1300 is provided, and the ion propagation path can be distorted.

[0088] According to embodiments, to prevent distortion of the path, first to fourth wire portions 1501, 1502, 1503, and 1504 are provided outside the chamber 1100 to generate an electromagnetic field. The electromagnetic field is formed in the X-axis direction (or the Y-axis direction) and the Z-axis direction. The deformation of the ion beam path, such as the primary ion beam PB1 or the secondary ions SB2, can be prevented by the electromagnetic field. In embodiments, the first to fourth wire portions 1501, 1502, 1503, and 1504 include enameled wires.

[0089] According to embodiments, although charging is prevented by using the electron generation source 1300 and the beam path is corrected by using the first to fourth wire portions 1501, 1502, 1503, and 1504, when the substrate Sub includes a glass substrate, a high voltage applied to the substrate Sub can cause a crack in the glass. In addition, charging occurring on the surface of the test piece can distort the detected image. Therefore, a method in which the acceleration voltage of the instrument source is reduced is used. For example, the absolute value of the power supply voltage supplied to the SIMS apparatus is about 4 kV. The voltage applied to the test piece, such as a glass substrate, is about -4 kV, and the voltage applied to the primary ion source 1200 is about +4 kV.

[0090] Figure 12 Equivalent circuit diagram of one pixel of the display device according to the embodiment.

[0091] Reference Figure 12 According to the embodiment, the pixel PX of the display device includes a pixel circuit PC and a light emitting diode, such as an organic light emitting diode OLED, electrically connected to the pixel circuit PC.

[0092] According to the embodiment, the pixel PX includes a plurality of first to seventh transistors T1, T2, T3, T4, T5, T6, and T7; a first capacitor Cst; a second capacitor Cbt; an organic light emitting diode OLED as a display element; signal lines SL1, SL2, SL3, SL4, EL, and DL; an initialization voltage line VIL; and a power voltage line PL connected to the initialization voltage line VIL. In another embodiment, at least one of the signal lines SL1, SL2, SL3, SL4, EL, and DL; the initialization voltage line VIL or the power voltage line PL can be shared by adjacent pixels. In Figure 12 In the embodiment, the third transistor T3 and the fourth transistor T4 are provided as n-channel metal oxide semiconductor (NMOS) field effect transistors, and the remaining transistors are provided as p-channel metal oxide semiconductor (PMOS) field effect transistors.

[0093] According to the embodiment, the signal lines include a plurality of data lines DL, a plurality of first scan lines SL1, a plurality of second scan lines SL2, a plurality of third scan lines SL3, a plurality of fourth scan lines SL4, and a plurality of emission control lines EL. In the embodiment, the second scan lines SL2 are connected to the first scan lines SL1. In this case, the first scan signal GP1 is the second scan signal GP2.

[0094] According to the embodiment, the power voltage line PL transmits a first power voltage ELVDD to the first transistor T1, and the initialization voltage line VIL transmits an initialization voltage Vint to the pixel PX, wherein the initialization voltage Vint initializes the first transistor T1 and the organic light emitting diode OLED.

[0095] According to the embodiment, during a process of forming the signal lines, the power voltage line PL, and the initialization voltage line VIL on the substrate, the first scan lines SL1, the second scan lines SL2, the third scan lines SL3, the fourth scan lines SL4, the emission control lines EL, and the initialization voltage line VIL extend in a first direction and are spaced apart from each other. The data lines DL and the power voltage line PL extend in a second direction intersecting the first direction and are spaced apart from each other.

[0096] According to an embodiment, the first transistor T1 is connected to the power voltage line PL through the fifth transistor T5 and is electrically connected to the organic light emitting diode OLED through the sixth transistor T6. The first transistor T1 functions as a driving transistor, receives a data signal DATA according to a switching operation of the second transistor T2 and supplies a driving current I OLED to the organic light emitting diode OLED.

[0097] According to an embodiment, the second transistor T2 is connected to the first scan line SL1 and the data line DL and is connected to the power voltage line PL through the fifth transistor T5. The second transistor T2 is turned on in response to a first scan signal GP1 received through the first scan line SL1 and performs a switching operation of transferring a data signal DATA received through the data line DL to the node N.

[0098] According to an embodiment, the third transistor T3 is connected to the fourth scan line SL4 and is electrically connected to the organic light emitting diode OLED through the sixth transistor T6. The third transistor T3 is turned on in response to a fourth scan signal GN2 received through the fourth scan line SL4 and is diode-connected to the first transistor T1.

[0099] According to an embodiment, the fourth transistor T4 is connected to the third scan line SL3 and the initialization voltage line VIL, is turned on in response to a third scan signal GN1 received through the third scan line SL3, and transfers an initialization voltage Vint from the initialization voltage line VIL to a gate electrode of the first transistor T1, thereby initializing the voltage of the gate electrode of the first transistor T1.

[0100] According to an embodiment, the fifth transistor T5 and the sixth transistor T6 are connected to the emission control line EL, are simultaneously turned on in response to an emission control signal EM received through the emission control line EL, and constitute a current path so that a driving current I OLED flows from the power voltage line PL to the organic light emitting diode OLED.

[0101] According to an embodiment, the seventh transistor T7 is connected to the second scan line SL2 and the initialization voltage line VIL, is turned on in response to a second scan signal GP2 received through the second scan line SL2, transfers an initialization voltage Vint from the initialization voltage line VIL to the organic light emitting diode OLED, thereby initializing the organic light emitting diode OLED. In some embodiments, the seventh transistor T7 is omitted.

[0102] According to an embodiment, the first capacitor Cst includes a first electrode CE1 and a second electrode CE2. The first electrode CE1 is connected to the gate electrode of the first transistor T1, and the second electrode CE2 is connected to the power supply voltage line PL. The first capacitor Cst is a storage capacitor. The first capacitor Cst stores and holds a voltage corresponding to a difference between two opposite end portions of the power supply voltage line PL and the gate electrode of the first transistor T1, thereby holding a voltage applied to the gate electrode of the first transistor T1.

[0103] According to an embodiment, the second capacitor Cbt includes a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 is connected to the first scan line SL1 and the gate electrode of the second transistor T2. The fourth electrode CE4 is connected to the gate electrode of the first transistor T1 and the first electrode CE1 of the first capacitor Cst. The second capacitor Cbt is a boost capacitor. When the first scan signal GP1 of the first scan line SL1 is a voltage that turns off the second transistor T2, the second capacitor Cbt raises the voltage of the node N and reduces a black voltage that displays black.

[0104] According to an embodiment, an organic light emitting diode OLED is electrically connected to a pixel circuit PC including transistors and capacitors. The organic light emitting diode OLED includes a pixel electrode and an opposite electrode. The opposite electrode receives a second power supply voltage ELVSS. The organic light emitting diode OLED emits light to display an image by receiving a driving current I OLED from the first transistor T1.

[0105] In this embodiment, at least one of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 includes an oxide semiconductor layer, and the remaining transistors include a silicon semiconductor layer. Specifically, the first transistor T1, which directly affects the luminance of the display device, includes a semiconductor layer including highly reliable polysilicon, and a high-resolution display device can be implemented by this configuration.

[0106] According to an embodiment, because the oxide semiconductor layer has high carrier mobility and low leakage current, the voltage drop is not large even when the driving time is long. That is, because the image color change corresponding to the voltage drop is not large even during low frequency driving, the display device can be driven at a low frequency. Because the oxide semiconductor layer has low leakage current, at least one of the fourth transistor T4 and the third transistor T3 connected to the gate electrode of the first transistor T1 can include an oxide semiconductor layer, and thus leakage current that can flow to the gate electrode of the first transistor T1 is prevented, and at the same time, power consumption is reduced.

[0107] Figure 13 A cross-sectional view of a display device according to an embodiment. Figure 13A partial area of ​​the display device is shown, and a substrate 200, a first transistor T1 and a sixth transistor T6 including a silicon semiconductor, a fourth transistor T4 including an oxide semiconductor layer, a first capacitor Cst and a second capacitor Cbt are also shown.

[0108] According to an embodiment, the substrate 200 includes one of glass, ceramic, metal, and flexible or bendable materials. When the substrate 200 includes a flexible or bendable material, the substrate 200 includes a polymer resin, such as polyethersulfone (PES), polyarylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

[0109] According to the embodiment, the buffer layer 210 is disposed on the substrate 200 to increase the flatness of the top surface of the substrate 200, and includes an inorganic insulating material, such as silicon oxide, silicon nitride or silicon oxynitride.

[0110] According to an embodiment, the first semiconductor layer AS1 of the first transistor T1 and the sixth semiconductor layer AS6 of the sixth transistor T6 are disposed on the buffer layer 210. The first semiconductor layer AS1 and the sixth semiconductor layer AS6 comprise silicon semiconductors. In this embodiment, Figure 13 The diagram shows a first high-concentration impurity region B1 and a channel region A1 in a first semiconductor layer AS1, and a first high-concentration impurity region B6, a second high-concentration impurity region C6, and a channel region A6 in a sixth semiconductor layer AS6. The first high-concentration impurity region B1 is doped with impurities and is conductive, and the first high-concentration impurity region B6 and the second high-concentration impurity region C6 are also doped with impurities and are conductive.

[0111] According to the embodiment, the first gate electrode G1 of the first transistor T1 and the sixth gate electrode G6 of the sixth transistor T6 are respectively located on the first semiconductor layer AS1 and the sixth semiconductor layer AS6. The first insulating layer 211 is disposed between the first semiconductor layer AS1 and the first gate electrode G1, and is disposed between the sixth semiconductor layer AS6 and the sixth gate electrode G6.

[0112] According to an embodiment, the first insulating layer 211 comprises an inorganic material containing one or more of oxides and nitrides. For example, the first insulating layer 211 comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide.

[0113] According to an embodiment, the first gate electrode G1 overlaps with the channel region A1 of the first semiconductor layer AS1, and the sixth gate electrode G6 overlaps with the channel region A6 of the sixth semiconductor layer AS6. The first gate electrode G1 and the sixth gate electrode G6 may each comprise a single layer or multiple layers containing one or more of molybdenum (Mo), copper (Cu), and titanium (Ti).

[0114] According to an embodiment, the first electrode CE1 of the first capacitor Cst and the third electrode CE3 of the second capacitor Cbt are disposed on the same layer as the first gate electrode G1 and the sixth gate electrode G6. The first electrode CE1 of the first capacitor Cst and the third electrode CE3 of the second capacitor Cbt are made of the same material as the first gate electrode G1 and the sixth gate electrode G6.

[0115] According to an embodiment, a second insulating layer 212 is disposed on the first gate electrode G1 and the sixth gate electrode G6. The second insulating layer 212 comprises an inorganic material containing one or more of oxides and nitrides. For example, the second insulating layer 212 comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide.

[0116] According to an embodiment, the second electrode CE2 of the first capacitor Cst is disposed on the second insulating layer 212 and overlaps with the first electrode CE1 of the first capacitor Cst. The second electrode CE2 may have a single-layer structure or a multi-layer structure including one or more of molybdenum (Mo), copper (Cu), and titanium (Ti).

[0117] According to an embodiment, a third insulating layer 213 is disposed on the second electrode CE2 of the first capacitor Cst. The third insulating layer 213 comprises an inorganic material containing oxides or nitrides. For example, the third insulating layer 213 comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide.

[0118] According to the implementation, the first capacitor Cst overlaps with the first transistor T1. For example, the first gate electrode G1 of the first transistor T1 is used as the first electrode CE1 of the first capacitor Cst.

[0119] According to an embodiment, the fourth semiconductor layer AO4 of the fourth transistor T4 includes an oxide semiconductor layer and is disposed on the third insulating layer 213. The fourth semiconductor layer AO4 includes a first conductive region B4 and a second conductive region C4, and a channel region A4 between the first conductive region B4 and the second conductive region C4. The first conductive region B4 and the second conductive region C4 are conductive and spaced apart from each other. The fourth semiconductor layer AO4 includes Zn oxide, In-Zn oxide, or Ga-In-Zn oxide, etc.

[0120] According to an embodiment, the fourth transistor T4 includes dual gate electrodes. For example, a first gate electrode G41 is disposed above the fourth semiconductor layer AO4 of the fourth transistor T4, and a second gate electrode G42 is disposed below the fourth semiconductor layer AO4. The first gate electrode G41 and the second gate electrode G42 overlap with the channel region A4 of the fourth semiconductor layer AO4.

[0121] According to an embodiment, a fourth insulating layer 214 is disposed on the third insulating layer 213 and covers the fourth semiconductor layer AO4, and includes an inorganic material comprising oxides or nitrides. For example, the fourth insulating layer 214 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide.

[0122] According to the embodiments, the first gate electrode G41 and the second gate electrode G42 include a single-layer structure or a multi-layer structure containing one or more of molybdenum (Mo), copper (Cu) and titanium (Ti).

[0123] According to an embodiment, a fifth insulating layer 215 is disposed on the fourth insulating layer 214 and covers the fourth transistor T4. A power supply voltage line PL, a first connection electrode 267, and a connection line 166 are disposed on the fifth insulating layer 215. The fifth insulating layer 215 comprises an inorganic material containing oxides or nitrides. For example, the fifth insulating layer 215 comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide.

[0124] According to an embodiment, the power supply voltage line PL and the first connection electrode 267 comprise a relatively highly conductive material. The power supply voltage line PL and the first connection electrode 267 may have a single-layer or multi-layer structure comprising one or more of aluminum (Al), copper (Cu), and titanium (Ti). In an embodiment, the power supply voltage line PL and the first connection electrode 267 have a stacked structure of three sequentially stacked Ti / Al / Ti layers. The first connection electrode 267 is connected to the sixth semiconductor layer AS6 via contact holes. A connection line 166 connects the first gate electrode G1 of the first transistor T1 (or the first electrode CE1 of the first capacitor Cst) to the fourth electrode CE4 of the second capacitor Cbt via contact holes in the second insulating layer 212, the third insulating layer 213, the fourth insulating layer 214, and the fifth insulating layer 215. The connection line 166 is formed of a conductive material.

[0125] According to one embodiment, a sixth insulating layer 216, serving as a planarization layer, is disposed on the fifth insulating layer 215 and covers the power supply voltage line PL, the first connection electrode 267, and the connection line 166. The sixth insulating layer 216 comprises an organic material, such as benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). Optionally, in other embodiments, the sixth insulating layer 216 comprises an inorganic material. The sixth insulating layer 216 serves as a protective layer covering the first transistor T1, the sixth transistor T6, and the fourth transistor T4. The top portion of the sixth insulating layer 216 is planar. The sixth insulating layer 216 may have a single-layer structure or a multi-layer structure.

[0126] According to one embodiment, a data line DL and a second connection electrode 277 are disposed on a sixth insulating layer 216. The data line DL partially overlaps with the power supply voltage line PL. The second connection electrode 277 is connected to a first connection electrode 267 through a contact hole formed in the sixth insulating layer 216. The data line DL and the second connection electrode 277 comprise conductive materials, such as metals or conductive oxides. For example, the data line DL and the second connection electrode 277 may have a single-layer structure or a multi-layer structure comprising one or more of aluminum (Al), copper (Cu), and titanium (Ti). In one embodiment, the data line DL and the second connection electrode 277 have a stacked structure of three sequentially stacked Ti / Al / Ti layers. A seventh insulating layer 217 is disposed on the sixth insulating layer 216 and covers the data line DL and the second connection electrode 277.

[0127] According to one embodiment, an organic light-emitting diode (OLED) is disposed on a seventh insulating layer 217. The OLED includes a pixel electrode 310, a counter electrode 330, and an intermediate layer 320 including an emission layer between the pixel electrode 310 and the counter electrode 330.

[0128] According to the embodiment, the pixel electrode 310 is connected to the second connection electrode 277 through a contact hole formed in the seventh insulating layer 217, and is connected to the sixth transistor T6 through the second connection electrode 277 and the first connection electrode 267.

[0129] According to the embodiment, an eighth insulating layer 218, which functions as a pixel defining layer, is disposed on the seventh insulating layer 217. The eighth insulating layer 218 defines the emission region of the pixel by including an opening 218OP corresponding to each pixel. Furthermore, the eighth insulating layer 218 can prevent arcing or the like at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the opposing electrode 330 above the pixel electrode 310. The eighth insulating layer 218 comprises an organic material including, for example, polyimide or HMDSO.

[0130] According to one embodiment, the pixel electrode 310 is disposed on the seventh insulating layer 217 and includes one or more conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In another embodiment, the pixel electrode 310 includes a reflective layer comprising one or more of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and compounds thereof. In another embodiment, the pixel electrode 310 further includes a layer comprising ITO, IZO, ZnO, or In2O3 on or below the reflective layer.

[0131] According to an embodiment, the intermediate layer 320 of an organic light-emitting diode (OLED) includes an emission layer. The emission layer comprises a polymeric organic material or a low-molecular-weight organic material that emits light of a predetermined color. The emission layer is one of a red emission layer, a green emission layer, and a blue emission layer. Optionally, in another embodiment, the emission layer has a multilayer structure in which the red, green, and blue emission layers are stacked to emit white light, or has a single-layer structure comprising red, green, and blue emitting materials. In an embodiment, the intermediate layer 320 includes one or more of a first functional layer below the emission layer and a second functional layer on the emission layer. The first and second functional layers may each be a single layer covering a plurality of pixel electrodes 310 or a layer patterned to correspond to each of the plurality of pixel electrodes 310.

[0132] According to embodiments, the first functional layer has a single-layer structure or a multi-layer structure. For example, when the first functional layer comprises a polymer material, the first functional layer is a hole transport layer (HTL) with a single-layer structure. The first functional layer comprises poly(3,4)-ethylene-dihydroxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer comprises a low molecular weight material, the first functional layer comprises a hole injection layer (HIL) and a hole transport layer (HTL).

[0133] According to one embodiment, when the first functional layer and the emitter layer comprise polymer materials, a second functional layer is formed to improve the characteristics of the organic light-emitting diode (OLED). The second functional layer may have a single-layer structure or a multi-layer structure. The second functional layer includes one or more of an electron transport layer (ETL) and an electron injection layer (EIL). According to another embodiment, the second functional layer is omitted.

[0134] According to one embodiment, the counter electrode 330 faces the pixel electrode 310, and the intermediate layer 320 is located between the counter electrode 330 and the pixel electrode 310. The counter electrode 330 comprises a conductive material with low work function. For example, the counter electrode 330 comprises a (semi-)transparent layer containing one or more of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), and alloys thereof. Optionally, in another embodiment, the counter electrode 330 further comprises a layer including ITO, IZO, ZnO, or In2O3 on or below the (semi-)transparent layer containing the above-described material. The counter electrode 330 is disposed on the intermediate layer 320 and the eighth insulating layer 218. The counter electrode 330 may be integrally formed covering multiple organic light-emitting diodes (OLEDs) in the display area and may be a common electrode facing multiple pixel electrodes 310.

[0135] According to an embodiment, a thin-film encapsulation layer or encapsulation substrate is disposed on an organic light-emitting diode (OLED) to cover and protect the OLED. The thin-film encapsulation layer covers the display area and extends beyond the display area. The thin-film encapsulation layer includes an inorganic encapsulation layer containing at least one inorganic material and an organic encapsulation layer containing at least one organic material. In an embodiment, the thin-film encapsulation layer has a structure in which a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer are sequentially stacked. The encapsulation substrate faces the substrate 100 and is bonded to the substrate 100 using a sealing member, such as a sealant or a melt.

[0136] According to the implementation method, Figure 13 The fourth transistor T4 shown in the image is referenced. Figures 1 to 9 The described process is used to form the fourth transistor T4. The second gate electrode G42 corresponds to... Figure 9 The metal layer 105, the first gate electrode G41 of the fourth transistor T4 corresponds to Figure 9 The gate electrode 140, and the insulating layer between the second gate electrode G42 and the first gate electrode G41 of the fourth transistor T4 respectively correspond to the reference. Figure 9 Described insulating layer. Specific process and reference for forming the fourth transistor T4. Figures 1 to 9 The processes described are the same.

[0137] Figure 14 It is a graph showing the SIMS test results of the oxide transistors included in the display device according to the embodiment and the analysis results of some materials of the oxide transistors.

[0138] like Figure 9 or Figure 13As shown in the diagram, according to an embodiment, insulating layers are formed on and below the oxide semiconductor layer of the oxide transistor, respectively. When SIMS is performed on a test piece including insulating layers formed on and below the oxide semiconductor layer, respectively, results are obtained. Figure 14 The graph shown in the image.

[0139] Figure 14 The graph shows the results of SIMS performed on a test specimen (which includes silicon insulating layers formed on and below an IGZO oxide semiconductor layer, respectively), and displays the ionization intensity of secondary ions as a function of sputtering time. Since SIMS is performed in the depth direction of the test specimen, the interface of the test specimen is determined by the ionization intensity of secondary ions as a function of sputtering time.

[0140] refer to Figure 14 According to the embodiment, the metal oxide of the oxide semiconductor layer, such as gallium oxide (GaO) or indium oxide (InO), exhibits high intensity in the regions corresponding to the oxide semiconductor layer. Conversely, since the insulating layers formed on and below the oxide semiconductor layer respectively include silicon, the regions with high silicon intensity correspond to the regions of the insulating layer.

[0141] According to the implementation, because SIMS is performed on a test piece (which includes an oxide semiconductor layer and an insulating layer formed on and below the oxide semiconductor), the region corresponding to the oxide semiconductor layer corresponds to... Figure 14 The curve shown in the figure represents the half-width value of GaO, and the relevant region ( Figure 14 The two opposite sides around the IGZO correspond to the insulating layer ILU disposed above the oxide semiconductor layer and the insulating layer ILO disposed below the oxide semiconductor layer, respectively.

[0142] exist Figure 14 In one approach, the region corresponding to the half-width value of GaO corresponds to an oxide semiconductor layer, but in another approach, the region corresponding to the half-width value of InO corresponds to an oxide semiconductor layer.

[0143] Figure 15 A graph showing the hydrogen concentration in the oxide semiconductor layer of the oxide transistor of the display device according to an embodiment. Figure 15 The "improved H concentration distribution" corresponds to an embodiment of the present invention, and Figure 15 The “H concentration distribution before improvement” corresponds to the comparative example.

[0144] Figure 15 The implementation method is through reference Figures 1 to 9The described process is essentially the same as the process formed, and is similar to... Figures 1 to 9 The difference lies in the formation of a contact hole exposing one of the first and second conductive regions. An oxide semiconductor layer of the embodiment formed by the above process has been fabricated to include IGZO, and the specific shape of the oxide semiconductor layer is consistent with the reference. Figure 13 The fourth transistor described has the same shape.

[0145] refer to Figure 15 According to an embodiment, it is shown that the hydrogen concentration of the oxide semiconductor layer including IGZO manufactured according to the embodiment has a relatively constant value in the channel region. Figure 15 This shows that the hydrogen concentration in the channel region is approximately 1 × 10⁻⁶. 21 atoms / cm 3 Approximately 2×10 21 atoms / cm 3 Within that range. Specifically, Figure 15 The graph shows approximately 1.5 × 10 21 atoms / cm 3 Approximately 2×10 21 atoms / cm 3 The range. It is known that the HC value in the channel region is less than 30% according to equation (1). Specifically, Figure 15 The graph shows (Max-Min) / Avg×100% < 15%.

[0146] As a comparative example, see reference Figure 15 The "improved H concentration distribution" refers to a process that differs from the process described in this disclosure, for example, when a reference is omitted. Figure 2 The described process, and in reference Figure 6 During the process of forming the top insulating layer 150, when the third insulating layer is formed using a layer forming gas including ammonia, the difference in hydrogen concentration in the channel region is (Max-Min) / Avg×100%>30%, and because the effective channel length in the channel region is reduced in the oxide semiconductor layer according to the comparative example, it is not possible to ensure sufficient specifications for driving the display device.

[0147] According to the implementation, the effective channel length in the channel region of the oxide semiconductor layer is fully ensured, and thus the operating characteristics of the pixel circuit of the light-emitting diode electrically connected to the display device are improved, and thus high-quality images can be provided.

[0148] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and are not intended for limiting purposes. The description of features or aspects in each embodiment should generally be considered as other similar features or aspects that may be used in other embodiments. Although one or more embodiments have been described with reference to the figures, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device, the display device comprising: substrate; A first insulating layer is disposed on the substrate; An oxide semiconductor layer, wherein the oxide semiconductor layer is disposed on the first insulating layer; A second insulating layer is disposed on the oxide semiconductor layer; A gate electrode, wherein the gate electrode is disposed on the second insulating layer; as well as A third insulating layer is disposed on the gate electrode. The oxide semiconductor layer includes a first conductive region, a second conductive region, and a channel region located between the first conductive region and the second conductive region. The channel region comprises hydrogen, and The hydrogen concentration is measured in the effective region of the channel region, which is separated from the edge of the channel region by 0.15% multiplied by the length L of the channel region and 0.15% multiplied by the width W of the channel region.

2. The display device according to claim 1, wherein the hydrogen concentration of the oxide semiconductor layer is 5 × 10⁻⁶. 20 atoms / cm 3 Up to 2×10 21 atoms / cm 3 Within the range.

3. The display device according to claim 1, wherein the hydrogen concentration in the channel region is 1 × 10⁻⁶. 21 atoms / cm 3 Up to 2×10 21 atoms / cm 3 Within the range.

4. The display device according to claim 1, wherein, according to equation (1), the HC value in the channel region of the oxide semiconductor layer is less than 30%: HC=(Max-Min) / Avg×100%------Equation (1), where Max represents the maximum hydrogen concentration value detected from multiple points within the channel region. Min represents the minimum hydrogen concentration value detected from multiple points within the channel region, and Avg represents the average hydrogen concentration value detected from multiple points within the channel region, and The hydrogen concentration is measured in the effective region of the channel region, which is separated from the edge of the channel region by 0.15% multiplied by the length L of the channel region and 0.15% multiplied by the width W of the channel region.

5. The display device according to claim 1, wherein the oxide semiconductor layer comprises fluorine, and The concentration of fluorine in the oxide semiconductor layer is 5 × 10⁻⁶. 17 atoms / cm 3 Up to 5×10 18 atoms / cm 3 Within the range.

6. The display device according to claim 1, wherein each of the first insulating layer and the second insulating layer comprises an inorganic insulating material.

7. The display device according to claim 1, further comprising: The metal layer between the substrate and the first insulating layer, The metal layer overlaps with the oxide semiconductor layer.

8. A display device, the display device comprising: substrate; A first transistor, the first transistor including a first semiconductor layer and a first gate electrode on the first semiconductor layer; A second transistor is electrically connected to the first transistor and includes a second semiconductor layer and a second gate electrode on the second semiconductor layer, wherein the second semiconductor layer is electrically connected to a data line and the second gate electrode is electrically connected to a scan line; A first insulating layer is disposed on the first gate electrode and the second gate electrode; and A third transistor, comprising an oxide semiconductor layer and a gate electrode on the oxide semiconductor layer. The oxide semiconductor layer includes a first conductive region, a second conductive region, and a channel region between the first conductive region and the second conductive region. The channel region comprises hydrogen, and The hydrogen concentration is measured in the effective region of the channel region, which is separated from the edge of the channel region by 0.15% multiplied by the length L of the channel region and 0.15% multiplied by the width W of the channel region.

9. The display device according to claim 8, wherein the hydrogen concentration of the oxide semiconductor layer is 5 × 10⁻⁶. 20 atoms / cm 3 Up to 2×10 21 atoms / cm 3 Within the range.

10. The display device according to claim 8, wherein the hydrogen concentration in the channel region is 1 × 10⁻⁶. 21 atoms / cm 3 Up to 2×10 21 atoms / cm 3 Within the range.

11. The display device according to claim 8, wherein, according to equation (1), the HC value in the channel region of the oxide semiconductor layer is less than 30%: HC=(Max-Min) / Avg×100%------Equation (1), where Max represents the maximum hydrogen concentration value detected from multiple points within the channel region. Min represents the minimum hydrogen concentration value detected from multiple points within the channel region, and Avg represents the average hydrogen concentration value detected from multiple points within the channel region, and The hydrogen concentration is measured in the effective region of the channel region, which is separated from the edge of the channel region by 0.15% multiplied by the length L of the channel region and 0.15% multiplied by the width W of the channel region.

12. The display device of claim 8, wherein the oxide semiconductor layer comprises fluorine, and The concentration of fluorine in the oxide semiconductor layer is 5 × 10⁻⁶. 17 atoms / cm 3 Up to 5×10 18 atoms / cm 3 Within the range.

13. The display device according to claim 8, wherein the first insulating layer comprises an inorganic insulating material.

14. The display device according to claim 8, further comprising: A metal layer inserted between the substrate and the first insulating layer. The metal layer overlaps with the channel region of the oxide semiconductor layer.

15. The display device according to claim 14, further comprising: An electrode disposed on and overlapping the first gate electrode; The metal layer and the electrode are made of the same material.

16. The display device of claim 8, wherein each of the first semiconductor layer and the second semiconductor layer comprises polycrystalline silicon.

Images