Array substrate, manufacturing method thereof and display device

Abstract

The invention provides an array substrate, a manufacturing method thereof and a display device. The array substrate comprises a substrate structure; an active layer on the substrate structure; the first insulating layer is patterned on one side, far away from the substrate structure, of the active layer, and the first insulating layer is provided with a first through hole exposing a part of the active layer; a first conductive layer in the first via and in contact with the active layer; and a first connector on a side of the first insulating layer away from the substrate structure, the first connector being in contact with the first conductive layer, the first connector covering a first portion of the first conductive layer and not covering a second portion of the first conductive layer. According to the array substrate, the possibility of missing parts of the active layer can be reduced, and the performance of the array substrate and the performance of the display device formed by the array substrate are improved.

Description

[0001] The present application is a divisional application of the original application (application number 202210590935.4, with the application date of May 27, 2022, and the invention name: Array substrate and manufacturing method thereof, display device). TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof, and a display device. BACKGROUND

[0003] Currently, OLED (Organic Light-Emitting Diode) technology is becoming more and more mature. In some OLED display panels, the array substrate can adopt a 5-mask (which can be referred to as 5Mask) process. In the process of manufacturing the array substrate, TFT (Thin Film Transistor) transistors need to be manufactured. SUMMARY

[0004] One of the technical problems solved by the present disclosure is that in the related art, in the process of forming TFT of the array substrate, in the lap area of the source or drain and the active layer, since the active layer is etched twice, which causes the active layer to have a missing part, and reduces the performance of the display device.

[0005] According to one aspect of the present disclosure, an array substrate is provided, comprising: a substrate structure; an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first via exposing a portion of the active layer; a first conductive layer in the first via and in contact with the active layer; and a first connecting piece on a side of the first insulating layer away from the substrate structure, the first connecting piece being in contact with the first conductive layer, the first connecting piece covering a first portion of the first conductive layer and not covering a second portion of the first conductive layer.

[0006] In some embodiments, the first insulating layer also has a second via exposing another portion of the active layer; the array substrate further comprises: a second conductive layer in the second via; a second connecting piece electrically connected to the second conductive layer; and a gate electrode located on a side of the first insulating layer away from the active layer; wherein the second connecting piece is in the same layer as the gate electrode, and the first connecting piece and the second connecting piece are both isolated from the gate electrode.

[0007] In some embodiments, the substrate structure comprises: a substrate substrate; a light-shielding layer and a third conductive layer on the substrate substrate, a projection of the light-shielding layer on the substrate substrate at least partially overlaps with a projection of the active layer on the substrate substrate, wherein the third conductive layer is covered on the light-shielding layer, or the light-shielding layer is covered on the third conductive layer; and a buffer layer between the third conductive layer and the active layer.

[0008] In some embodiments, a projection of the first conductive layer on the substrate substrate at least partially overlaps with a projection of the light-shielding layer on the substrate substrate.

[0009] In some embodiments, the second via further exposes a portion of the buffer layer; the second conductive layer comprises: a third portion on a surface of the active layer and a fourth portion on a surface of the buffer layer.

[0010] In some embodiments, the materials of the first conductive layer, the second conductive layer and the third conductive layer all comprise transparent conductive materials.

[0011] In some embodiments, the thickness of the third conductive layer is greater than the thickness of the second conductive layer, and the thickness of the second conductive layer is equal to the thickness of the first conductive layer.

[0012] In some embodiments, the thickness of the first conductive layer is greater than the thickness of the active layer.

[0013] In some embodiments, the area of the overlapping portion of the first connecting member and the first conductive layer is less than the area of the overlapping portion of the second connecting member and the second conductive layer.

[0014] In some embodiments, the first insulating layer comprises a gate insulating layer under the gate; the active layer comprises: a first conductorized region electrically connected to the first connecting member, a second conductorized region electrically connected to the second connecting member, and a channel region between the first conductorized region and the second conductorized region, the channel region is flush with the edge of the gate insulating layer.

[0015] In some embodiments, the width of the overlapping portion of the first connecting member and the first conductive layer in the direction from the first connecting member to the gate is less than the distance between the edge of the first conductive layer and the channel region.

[0016] In some embodiments, the area of the first conductive layer is greater than the area of the overlapping portion of the first connecting member and the first conductive layer.

[0017] In some embodiments, the area of the first conductive layer is less than the area of the channel region.

[0018] In some embodiments, a width of an overlapping portion of the first conductive layer and the active layer in a direction from the first connection to the gate is less than a width of an overlapping portion of the second conductive layer and the active layer in the direction from the first connection to the gate.

[0019] In some embodiments, a distance between the first conductive layer and the gate is greater than a width of an overlapping portion of the first connection and the first conductive layer in a direction from the first connection to the gate, and the width of the overlapping portion of the first connection and the first conductive layer in the direction from the first connection to the gate is greater than a width of a second portion of the first conductive layer in the direction from the first connection to the gate.

[0020] In some embodiments, the array substrate further comprises: a second insulating layer covering the first connection, the second connection, and the gate; a planarization layer on a side of the second insulating layer distal to the substrate structure; a first electrode layer and a pixel defining layer on a side of the planarization layer distal to the substrate structure, the first electrode layer electrically connected to the second connection, the pixel defining layer having a first opening exposing at least a portion of the first electrode layer; a light emitting layer located at least in the first opening; and a second electrode layer electrically connected to the light emitting layer.

[0021] In some embodiments, a width of an overlapping portion between a footprint of the second conductive layer on the substrate substrate and a footprint of the third conductive layer on the substrate substrate in a direction from the first connection to the gate is less than a width of an overlapping portion between the footprint of the second conductive layer on the substrate substrate and a footprint of the first electrode layer on the substrate substrate in the direction from the first connection to the gate.

[0022] In some embodiments, a width of an overlapping portion between a footprint of the second conductive layer on the substrate substrate and a footprint of the third conductive layer on the substrate substrate in a direction from the first connection to the gate is less than a width of an overlapping portion between the footprint of the third conductive layer on the substrate substrate and a footprint of the first electrode layer on the substrate substrate in the direction from the first connection to the gate.

[0023] According to another aspect of the present disclosure, there is provided an array substrate, comprising: a substrate structure; and a thin film transistor on the substrate structure, the thin film transistor comprising: an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer distal to the substrate structure, the first insulating layer having a first via exposing a portion of the active layer; a first conductive layer in the first via and in contact with the active layer; and a first connection, a second connection, and a gate on a side of the first insulating layer distal to the substrate structure, wherein the first connection is in contact with the first conductive layer, the first connection, the second connection, and the gate are in the same layer and are isolated from each other, and the gate is between the first connection and the second connection; wherein the active layer comprises a first conductorized region electrically connected to the first connection, a second conductorized region electrically connected to the second connection, and a channel region between the first conductorized region and the second conductorized region, the channel region being below the gate; the first conductive layer comprises a first portion distal to the gate and a second portion proximal to the gate, the first portion is completely covered by the first connection, the second portion is not covered by the first connection, and a footprint of the first conductive layer on the substrate structure is inside a footprint of the active layer on the substrate structure.

[0024] In some embodiments, a width of the second portion along a direction from the first connection to the gate is less than a width of the first portion along the direction from the first connection to the gate.

[0025] In some embodiments, a width of the second portion along a direction from the first connection to the gate is less than a width of the channel region along the direction from the first connection to the gate.

[0026] In some embodiments, a thickness of the second portion is less than a thickness of the first portion.

[0027] In some embodiments, a width of the first portion is 2 to 5 times a width of the second portion.

[0028] In some embodiments, the active layer further comprises a semiconductor region on a side of the first conductorized region distal to the channel region; wherein a width of the second portion along a direction from the first connection to the gate is less than a width of the semiconductor region along the direction from the first connection to the gate.

[0029] According to another aspect of the present disclosure, there is provided a display device, comprising: the array substrate as previously described.

[0030] According to another aspect of the present disclosure, a method for manufacturing an array substrate is provided, comprising: forming an active layer on a substrate structure; forming a patterned first insulating layer on a side of the active layer distal to the substrate structure, the first insulating layer having a first via exposing a portion of the active layer; performing a first conductorization process on the portion of the active layer exposed; forming a first conductive layer in the first via and in contact with the active layer; forming a connection material layer on a side of the first insulating layer distal to the substrate structure by a deposition process; patterning the connection material layer using a patterned mask layer to form a first connection, the first connection being in contact with the first conductive layer, the first connection covering a first portion of the first conductive layer and not covering a second portion of the first conductive layer; etching the first insulating layer to enlarge the first via by a self-alignment process using the mask layer, wherein the enlarged first via exposes another portion of the active layer; and performing a second conductorization process on the another portion of the active layer exposed.

[0031] The array substrate described above comprises: a substrate structure; an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer distal to the substrate structure, the first insulating layer having a first via exposing a portion of the active layer; a first conductive layer in the first via and in contact with the active layer; and a first connection on a side of the first insulating layer distal to the substrate structure, the first connection being in contact with the first conductive layer, the first connection covering a first portion of the first conductive layer and not covering a second portion of the first conductive layer. Since the first conductive layer is formed in the first via of the first insulating layer, the first conductive layer can protect the portion of the active layer underneath to some extent during the manufacturing process, thereby reducing the possibility of missing portion of the active layer and improving the performance of the array substrate and the display device formed therefrom.

[0032] Other features of the present disclosure, and their advantages, will become apparent from the following detailed description of exemplary embodiments with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and together with the description, serve to explain the principles of the present disclosure.

[0034] The present disclosure can be understood more readily by reference to the following detailed description, taken in connection with the accompanying drawings, in which:

[0035] FIG. 1 is a cross-sectional schematic view showing an array substrate according to one embodiment of the present disclosure;

[0036] FIG. 2 is a cross-sectional schematic view showing an array substrate according to another embodiment of the present disclosure;

[0037] FIG. 3 is a schematic diagram illustrating an enlarged view of the array substrate in FIG. 1 at block 201;

[0038] FIG. 4 is a plan view schematically illustrating a partial structure of an array substrate according to one embodiment of the present disclosure;

[0039] FIG. 5 is a flowchart illustrating a manufacturing method of an array substrate according to one embodiment of the present disclosure;

[0040] FIGS. 6A-6I is a cross-sectional schematic diagram illustrating structures at several stages in a manufacturing process of an array substrate according to some embodiments of the present disclosure;

[0041] FIG. 7 is a cross-sectional schematic diagram illustrating a structure at one stage in a manufacturing process of an array substrate according to another embodiment of the present disclosure;

[0042] FIG. 8 is a cross-sectional schematic diagram illustrating a structure at one stage in a manufacturing process of an array substrate according to another embodiment of the present disclosure;

[0043] FIGS. 9A-9C is a cross-sectional schematic diagram illustrating structures at several stages in a manufacturing process of an array substrate according to some embodiments of the present disclosure;

[0044] FIGS. 10A-10C is a cross-sectional schematic diagram illustrating structures at several stages in a manufacturing process of an array substrate according to some embodiments of the present disclosure.

[0045] It should be understood that the same or like reference numerals indicate the same or like elements. DETAILED DESCRIPTION

[0046] Various exemplary embodiments of the present disclosure will now be described in detail herein with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative in nature and is in no way intended to limit the disclosure, its application or uses, except as described by the appended claims. The present disclosure can be implemented in numerous different forms, as will be apparent to one of ordinary skill in the art. The embodiments provided are in the nature of a best mode of the disclosure and are provided to give a full and enabling disclosure as required by the patent laws, and to fully and completely convey the full scope of the disclosure to those skilled in the art. Note that the relative arrangement of the components and steps illustrated in these embodiments, the composition of the materials, the numerical expressions, and numerical values set forth in these embodiments are all intended to be exemplary only and are in no way to be construed as limiting unless otherwise specifically indicated.

[0047] The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different parts. The terms "include", "comprise", and similar terms mean that the elements before the terms encompass the elements listed after the terms, and do not exclude the possibility of also encompassing other elements. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0048] In the present disclosure, when it is described that a specific device is located between a first device and a second device, there can be an intervening device between the specific device and the first device or the second device, or there can be no intervening device. When it is described that a specific device is connected to another device, the specific device can be directly connected to the other device without an intervening device, or can not be directly connected to the other device with an intervening device.

[0049] All terms used in the present disclosure, including technical terms or scientific terms, have the same meanings as those understood by a person of ordinary skill in the art to which the present disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in a generally used dictionary should be interpreted to have meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formalized sense, unless otherwise clearly defined herein.

[0050] Techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail, but should be considered as part of the specification where appropriate.

[0051] The inventors of the present disclosure found that, in the related art, in the process of forming a TFT of an array substrate, in the overlap area of the source or drain and the active layer, the active layer is subjected to 2 times of etching, which causes the active layer to have a missing part. This makes the conduction path of the overlap area of the source or drain and the active layer very short, which can limit the current flow capacity, easily cause poor contact, and affect the performance of the display product.

[0052] In view of this, an embodiment of the present disclosure provides an array substrate to reduce the possibility of the active layer having a missing part.

[0053] FIG. 1 is a schematic cross-sectional view showing an array substrate according to an embodiment of the present disclosure.

[0054] As shown in FIG. 1 , the array substrate includes a substrate structure 110.

[0055] As shown in FIG. 1As shown, the array substrate further includes an active layer 120 on the substrate structure 110. For example, the material of the active layer includes a semiconductor material such as IGZO (Indium Gallium Zinc Oxide).

[0056] As shown, the array substrate further includes a patterned first insulating layer 130 on a side of the active layer 120 distal from the substrate structure. The first insulating layer 130 has a first via 141 exposing a portion of the active layer 120. The first insulating layer 130 covers the active layer 120. For example, the material of the first insulating layer includes an inorganic insulating material (e.g., silicon dioxide or silicon nitride, etc.). FIG. 1 As shown, the array substrate further includes a first conductive layer 151 in the first via 141 and in contact with the active layer 120. In some embodiments, the material of the first conductive layer includes a metallic material. For example, the material of the first conductive layer includes a transparent conductive material. For example, the transparent conductive material includes ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), etc. Here, the first conductive layer employs a transparent conductive material, which can improve the light transmittance of the array substrate.

[0057] FIG. 1 As shown, the array substrate further includes a first connecting member 161 on a side of the first insulating layer 130 distal from the substrate structure 110. The first connecting member 161 is in contact with the first conductive layer 151. The material of the first connecting member 161 includes a metallic material such as copper, etc. For example, the first connecting member can be a source electrode or a drain electrode. The first connecting member 161 covers a first portion of the first conductive layer 151 and does not cover a second portion of the first conductive layer 151 (to be described later in connection with FIG. 2).

[0058] As shown, the array substrate further includes a first conductive layer 151 in the first via 141 and in contact with the active layer 120. In some embodiments, the material of the first conductive layer includes a metallic material. For example, the material of the first conductive layer includes a transparent conductive material. For example, the transparent conductive material includes ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), etc. Here, the first conductive layer employs a transparent conductive material, which can improve the light transmittance of the array substrate. FIG. 1 FIG. 3 As shown, the array substrate further includes a first connecting member 161 on a side of the first insulating layer 130 distal from the substrate structure 110. The first connecting member 161 is in contact with the first conductive layer 151. The material of the first connecting member 161 includes a metallic material such as copper, etc. For example, the first connecting member can be a source electrode or a drain electrode. The first connecting member 161 covers a first portion of the first conductive layer 151 and does not cover a second portion of the first conductive layer 151 (to be described later in connection with FIG. 2).

[0059] So far, the array substrate according to some embodiments of the present disclosure is provided. The array substrate includes: a substrate structure; an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer distal from the substrate structure, the first insulating layer having a first via exposing a portion of the active layer; a first conductive layer in the first via and in contact with the active layer; and a first connecting member on a side of the first insulating layer distal from the substrate structure, the first connecting member being in contact with the first conductive layer, the first connecting member covering a first portion of the first conductive layer and not covering a second portion of the first conductive layer. In this embodiment, since the first conductive layer is formed in the first via of the first insulating layer, the first conductive layer can protect a portion of the active layer thereunder to some extent during the manufacturing process, thereby reducing the possibility of missing portion of the active layer and improving the performance of the array substrate and the display device formed therefrom.

[0060] As​​FIG. 1 As shown, the first insulating layer 130 also has a second via hole 142 exposing another portion of the active layer 120.

[0061] In some embodiments, as shown in FIG. 1C, the array substrate further includes a first conductive layer 151 in the first via hole 141. The first conductive layer 151 fills the first via hole 141. For example, the material of the first conductive layer 151 includes a transparent conductive material. For example, the transparent conductive material includes ITO, IZO, or the like. Here, the first conductive layer 151 employs a transparent conductive material, which can improve the light transmittance of the array substrate. FIG. 1

[0062] Similar to the first conductive layer, the second conductive layer can protect a portion of the active layer underneath, thereby reducing the possibility of the active layer having a missing portion, and further improving the performance of the array substrate and the display device formed therefrom.

[0063] In some embodiments, as shown in FIG. 1C, the first conductive layer 151 and the overlapping portion of the active layer 120 in the direction from the first connecting member 151 to the gate 163 has a width smaller than the second conductive layer 152 and the overlapping portion of the active layer 120 in the direction from the first connecting member 151 to the gate 163. In other words, the second conductive layer 152 is made larger. For example, the area or width (i.e., the lateral dimension shown in the cross-sectional view) of the second conductive layer 152 is larger than that of the first conductive layer 151. In this way, the second conductive layer 152 can also serve as one electrode plate of a capacitor. This is conducive to forming a transparent capacitor structure, and improving the capacitance and conductive capacity. FIG. 1 In some embodiments, as shown in FIG. 1C, the array substrate further includes a second connecting member 162 electrically connected to the second conductive layer 152. The second connecting member 162 is in contact with the second conductive layer 152. The material of the second connecting member 162 includes a metal material such as copper or the like. The second connecting member can be a source electrode or a drain electrode. For example, the first connecting member 161 is a source electrode, and the second connecting member 162 is a drain electrode. For another example, the first connecting member 161 is a drain electrode, and the second connecting member 162 is a source electrode.

[0064] FIG. 1 In some embodiments, as shown in FIG. 1C, the array substrate further includes a gate 163 on the side of the first insulating layer 130 away from the active layer 120. The material of the gate 163 includes a metal material such as copper or the like.

[0065] In some embodiments, as shown in FIG. 1C, the array substrate further includes a gate 163 on the side of the first insulating layer 130 away from the active layer 120. The material of the gate 163 includes a metal material such as copper or the like. FIG. 1 As shown in FIG. 1C, the array substrate further includes a gate 163 on the side of the first insulating layer 130 away from the active layer 120. The material of the gate 163 includes a metal material such as copper or the like.

[0066] FIG. 1 ​​​As shown, the second connecting member 162 is in the same layer as the gate 163. The first connecting member 161 is also in the same layer as the gate 163. The first connecting member 161 and the second connecting member 162 are both isolated from the gate 163. The gate 163 is between the first connecting member 161 and the second connecting member 162.

[0067] It should be noted that the "same layer" refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then patterning the film layer by using the same mask plate through a one-time patterning process. For example, two structure layers in the same layer can be located on the same structure layer, or can be located on different structure layers. Two structure layers in the same layer can be at different heights or have different thicknesses.

[0068] In some embodiments, as shown in FIG. 1A, the substrate structure 110 includes a substrate base plate 111. The substrate base plate includes a rigid base plate or a flexible base plate, etc. For example, the substrate base plate can include a glass base plate, etc. FIG. 1

[0069] As shown in FIG. 1A, the substrate structure 110 further includes a light shielding layer 112 on the substrate base plate 111. The light shielding layer 112 is at least partially overlapped with the active layer 120 on the substrate base plate 111. For example, the material of the light shielding layer 112 includes a metal material such as aluminum, molybdenum or copper, etc. FIG. 1

[0070] As shown in FIG. 1A, the substrate structure 110 further includes a third conductive layer 113 covering the light shielding layer 112. The third conductive layer 113 can extend from the light shielding layer 112 to the substrate base plate 111. The third conductive layer 113 can serve as another electrode plate of the capacitor. FIG. 1 It should be noted that in other embodiments, the positions of the light shielding layer 112 and the third conductive layer 113 can be interchanged. For example, the third conductive layer 113 can be located on the substrate base plate 111, and the light shielding layer 112 is located on the side of the third conductive layer 113 away from the substrate base plate, i.e., the light shielding layer 112 covers the third conductive layer 113.

[0071] In some embodiments, the material of the third conductive layer 113 includes a transparent conductive material. For example, the transparent conductive material includes ITO or IZO, etc. Here, the third conductive layer adopts a transparent conductive material, which can improve the light transmittance of the array substrate.

[0072] As shown in FIG. 1A, the substrate structure 110 further includes a fourth conductive layer 114 on the substrate base plate 111. The fourth conductive layer 114 can extend from the third conductive layer 113 to the substrate base plate 111. The fourth conductive layer 114 can serve as another electrode plate of the capacitor.

[0073] FIG. 1 ​​​As shown, the substrate structure 110 also includes a buffer layer 114 between the third conductive layer 113 and the active layer 120. For example, the buffer layer 114 may include an inorganic insulating material such as silicon dioxide. The buffer layer 114 covers the third conductive layer 113 and the substrate 111, etc.

[0074] In some embodiments, such as FIG. 1 As shown, the substrate 110 may further include a trace 115. A first connector 161 can be electrically connected to the trace 115 via a third via (as a conductive via) 143 passing through the first insulating layer 130 and the buffer layer 114. The trace 115 may be on the same layer as the light-shielding layer 112. For example, the material of the trace 115 may be the same as the material of the light-shielding layer 112. The trace 115 is isolated from the light-shielding layer 112.

[0075] In some embodiments, the orthographic projection of the first conductive layer 151 onto the substrate 111 at least partially overlaps with the orthographic projection of the light-shielding layer 112 onto the substrate 111. The light-shielding layer 112 can serve to block light.

[0076] In some embodiments, the thickness of the third conductive layer 113 is greater than the thickness of the second conductive layer 152. The thickness of the second conductive layer 152 is equal to the thickness of the first conductive layer 151. This makes the second conductive layer 152 relatively thin, thereby further improving the light transmittance of the array substrate. In addition, the relatively thick third conductive layer 113 can reduce resistance.

[0077] For example, the thickness of the third conductive layer 113 is 3,000 to 5,000 angstroms. For example, the thickness of the second conductive layer 152 (or the first conductive layer 151) is 500 to 1,000 angstroms.

[0078] In some embodiments, the thickness of the first conductive layer 151 is greater than the thickness of the active layer 120. For example, the thickness of the active layer 120 is 300 to 500 angstroms.

[0079] In some embodiments, the area of ​​the overlap between the first connector 161 and the first conductive layer 151 is smaller than the area of ​​the overlap between the second connector 162 and the second conductive layer 151. Here, the area of ​​the overlap between the second connector 162 and the second conductive layer 151 is relatively large, which can reduce the contact resistance.

[0080] In some embodiments, such as FIG. 3 As shown, the first insulating layer 130 includes a gate insulating layer 131 located below the gate 163.

[0081] like FIG. 3As shown, the active layer 120 includes a first conductive region 121 electrically connected with the first connecting member 161, a second conductive region 122 electrically connected with the second connecting member 162, and a channel region 123 between the first conductive region 121 and the second conductive region 122. For example, the channel region 123 is flush with the edge of the gate insulating layer 131. Here, the first conductive layer 151 is in contact with the first conductive region 121, and the second conductive layer 152 is in contact with the second conductive region 122. By conductivizing the portions on both sides of the channel region 123 of the active layer 120, the contact resistance between the first conductive layer 151 and the active layer 120 and the contact resistance between the second conductive layer 152 and the active layer 120 can be reduced, facilitating the transmission of current and improving the performance of the array substrate and the display device formed therefrom.

[0082] FIG. 3 is a schematic view of the array substrate in the display device 100 at block 201. FIG. 3 is a schematic view of the array substrate in the display device 100 at block 201.

[0083] As shown in FIG. 2A, the first conductive layer 151 includes a first portion 1511 away from the gate 163 and a second portion 1512 close to the gate 163. The first portion 1511 is completely covered by the first connecting member 161, and the second portion 1512 is not covered by the first connecting member 161. FIG. 3 In some embodiments, as shown in FIG. 2B, the width d1 of the overlapping portion of the first connecting member 161 and the first conductive layer 151 in the direction from the first connecting member 161 to the gate 163 is less than the distance d4 between the edge of the first conductive layer 151 and the channel region 123.

[0084] FIG. 1 In some embodiments, the area of the first conductive layer 151 is greater than the area of the overlapping portion of the first connecting member 161 and the first conductive layer 151 (i.e., the portion corresponding to the width d1). This facilitates sufficient contact between the first connecting member 161 and the first conductive layer 151, preventing the problem of poor contact.

[0085] In some embodiments, the area of the first conductive layer 151 is less than the area of the channel region 123. The relatively large area of the channel region 123 facilitates improved performance of the thin film transistor.

[0086] It should be noted that the “area” referred to in the present disclosure refers to the area of the surface of a structural layer parallel to the plane in which the substrate 111 lies. For example, the area can be the area of the upper surface of the structural layer. For example, the area of the first conductive layer 151 is the area of the upper surface of the first conductive layer 151; the area of the channel region 123 is the area of the upper surface of the channel region 123, and so on.

[0087] It should be noted that the “area” referred to in the present disclosure refers to the area of the surface of a structural layer parallel to the plane in which the substrate 111 lies. For example, the area can be the area of the upper surface of the structural layer. For example, the area of the first conductive layer 151 is the area of the upper surface of the first conductive layer 151; the area of the channel region 123 is the area of the upper surface of the channel region 123, and so on.

[0088] ​In some embodiments, the distance d3 between the first conductive layer 151 and the gate 163 is greater than the width d1 of the overlapping portion of the first connector 161 and the first conductive layer 151 along the direction from the first connector 161 to the gate 163, and the width d1 of the overlapping portion of the first connector 161 and the first conductive layer 151 along the direction from the first connector 161 to the gate 163 is greater than the width d2 of the second portion (i.e., the portion not covered by the first connector 161) 1512 of the first conductive layer 151 along the direction from the first connector 161 to the gate 163. That is, d3>d1>d2. This dimensional design is beneficial for improving the performance of the thin-film transistor, thereby improving the performance of the array substrate and the display device formed therefrom.

[0089] In addition, such as FIG. 3 As shown, there is a gap 301 between the first conductive layer 151 and the gate insulating layer 131.

[0090] Back FIG. 2 In some embodiments, the array substrate further includes a second insulating layer 171 covering the first connector 161, the second connector 162, and the gate 163. For example, the material of the second insulating layer 171 includes at least one of silicon dioxide or silicon nitride.

[0091] like FIG. 2 As shown, the array substrate also includes a planarization layer 172 on the side of the second insulating layer 171 away from the substrate structure 110. For example, the material of the planarization layer 172 includes an organic insulating material such as resin.

[0092] like FIG. 1 As shown, the array substrate also includes a first electrode layer 181 and a pixel defining layer 174 on the side of the planarization layer 172 away from the substrate structure 110. The first electrode layer 181 is electrically connected to the second connector 162 (e.g., through a conductive via). The pixel defining layer 174 has a first opening 1742 exposing at least a portion of the first electrode layer 181. For example, the first electrode layer 181 is an anode layer. For example, the material of the first electrode layer 181 includes metals such as copper, silver, aluminum, or aluminum alloys, or transparent conductive materials such as ITO or IZO.

[0093] like FIG. 1 As shown, the array substrate also includes a light-emitting layer 180 located at least in the first opening 1742. The light-emitting layer 180 may include: a light-emitting layer for emitting red light, a light-emitting layer for emitting green light, or a light-emitting layer for emitting blue light.

[0094] like FIG. 2As shown, the array substrate further includes a second electrode layer 182 electrically connected to the light-emitting layer 180. The second electrode layer 182 covers the pixel defining layer 174 and the light-emitting layer 180. The second electrode layer 182 can be a cathode layer. For example, the material of the second electrode layer 182 includes a metal such as copper, silver, aluminum, or an aluminum alloy, or a transparent conductive material such as ITO or IZO.

[0095] In some embodiments, the array substrate can further include other functional layers between the first electrode layer 181 and the second electrode layer 182, for example, an electron transport layer, a hole transport layer, an electron blocking layer, or a hole blocking layer, etc. Therefore, the scope of the present disclosure is not limited to this.

[0096] In some embodiments, as shown in FIG. 1A, the second conductive layer 152 is electrically connected to the first electrode layer 181. For example, the second conductive layer 152 is directly connected to the first electrode layer 181. In some embodiments, as shown in FIG. 1B, the second conductive layer 152 is electrically connected to the first electrode layer 181 through a via hole 151. In some embodiments, as shown in FIG. 1C, the second conductive layer 152 is electrically connected to the first electrode layer 181 through a via hole 151 and a via hole 152. FIG. 2 As shown in FIG. 1A, the width of the overlapping portion between the orthographic projection of the second conductive layer 152 on the substrate 111 and the orthographic projection of the third conductive layer 113 on the substrate 111 in the direction from the first connecting piece 161 to the gate 163 is less than the width of the overlapping portion between the orthographic projection of the second conductive layer 152 on the substrate 111 and the orthographic projection of the first electrode layer 181 on the substrate 111 in the direction from the first connecting piece 161 to the gate 163. This is advantageous for improving the light transmittance of the array substrate.

[0097] In some embodiments, as shown in FIG. 1A, the second conductive layer 152 is electrically connected to the first electrode layer 181. For example, the second conductive layer 152 is directly connected to the first electrode layer 181. In some embodiments, as shown in FIG. 1B, the second conductive layer 152 is electrically connected to the first electrode layer 181 through a via hole 151. In some embodiments, as shown in FIG. 1C, the second conductive layer 152 is electrically connected to the first electrode layer 181 through a via hole 151 and a via hole 152. FIG. 1 As shown in FIG. 1A, the width of the overlapping portion between the orthographic projection of the second conductive layer 152 on the substrate 111 and the orthographic projection of the third conductive layer 113 on the substrate 111 in the direction from the first connecting piece 161 to the gate 163 is less than the width of the overlapping portion between the orthographic projection of the second conductive layer 152 on the substrate 111 and the orthographic projection of the first electrode layer 181 on the substrate 111 in the direction from the first connecting piece 161 to the gate 163. This is advantageous for improving the light transmittance of the array substrate.

[0098] The present disclosure provides an array substrate. As shown in FIG. 1A, the array substrate includes a substrate structure 110 and a thin film transistor on the substrate structure 110. FIG. 1

[0099] ​The thin-film transistor includes an active layer 120 on a substrate structure 110. The thin-film transistor also includes a patterned first insulating layer 130 on the side of the active layer 120 away from the substrate structure 110. The first insulating layer 130 has a first via 141 exposing a portion of the active layer 120. The thin-film transistor also includes a first conductive layer 151 in the first via 141 and in contact with the active layer 120. The thin-film transistor also includes a first connector 161, a second connector 162, and a gate 163 on the side of the first insulating layer 130 away from the substrate structure 110. The first connector 161 is in contact with the first conductive layer 151. The first connector 161, the second connector 162, and the gate 163 are on the same layer and isolated from each other. The gate 163 is located between the first connector 161 and the second connector 162.

[0100] like FIG. 2 and FIG. 4 As shown, the active layer 120 includes: a first conductive region 121 electrically connected to the first connector 161, a second conductive region 122 electrically connected to the second connector 162, and a channel region 123 between the first conductive region 121 and the second conductive region 122. The channel region 123 is located below the gate 163.

[0101] like FIG. 4 As shown, the first conductive layer 151 includes a first portion 1511 away from the gate 163 and a second portion 1512 close to the gate 163. The first portion 1511 is completely covered by the first connector 161, while the second portion 1512 is not covered by the first connector 161. The orthographic projection of the first conductive layer 151 onto the substrate structure 110 lies inside the orthographic projection of the active layer 120 onto the substrate structure 110.

[0102] In the above embodiments, since a first conductive layer is formed in the first through-hole of the first insulating layer, the first conductive layer can protect a portion of the active layer below it to a certain extent during the manufacturing process, thereby reducing the possibility of missing parts of the active layer and improving the performance of the array substrate and the display device formed therefrom.

[0103] In some embodiments, such as FIG. 4 As shown, the width d2 of the second portion 1512 along the direction from the first connector 161 to the gate 163 is smaller than the width d1 of the first portion 1511 along the direction from the first connector 161 to the gate 163. Here, the width of the first portion 1511 is equal to the width of the overlapping portion of the first connector 161 and the first conductive layer 151, both being d1.

[0104] For example, the width d1 of the first part 1511 is 2 to 5 times the width d2 of the second part 1512.

[0105] In some embodiments, as shown in FIG. 15B, the width d2 of the second portion 1512 in the direction from the first connection to the gate is smaller than the width d5 of the channel region 123 in the direction from the first connection to the gate. FIG. 1 In some embodiments, as shown in FIG. 15B, the width d2 of the second portion 1512 in the direction from the first connection to the gate is smaller than the width d5 of the channel region 123 in the direction from the first connection to the gate.

[0106] In some embodiments, as shown in FIG. 15B, the thickness H2 of the second portion 1512 is smaller than the thickness H1 of the first portion 1511. FIG. 2 In some embodiments, as shown in FIG. 15B, the thickness H2 of the second portion 1512 is smaller than the thickness H1 of the first portion 1511.

[0107] In some embodiments, as shown in FIG. 15B, the width d2 of the second portion 1512 in the direction from the first connection to the gate is smaller than the width d5 of the channel region 123 in the direction from the first connection to the gate. FIG. 5 In some embodiments, as shown in FIG. 15B, the width d2 of the second portion 1512 in the direction from the first connection to the gate is smaller than the width d5 of the channel region 123 in the direction from the first connection to the gate. FIG. 5 In some embodiments, as shown in FIG. 15B, the width d2 of the second portion 1512 in the direction from the first connection to the gate is smaller than the width d5 of the channel region 123 in the direction from the first connection to the gate. In some embodiments, as shown in FIG. 15B, the width d2 of the second portion 1512 in the direction from the first connection to the gate is smaller than the width d5 of the channel region 123 in the direction from the first connection to the gate.

[0108] In some embodiments, as shown in FIG. 15B, the width d2 of the second portion 1512 in the direction from the first connection to the gate is smaller than the width d5 of the channel region 123 in the direction from the first connection to the gate. In some embodiments, as shown in FIG. 15B, the width d2 of the second portion 1512 in the direction from the first connection to the gate is smaller than the width d5 of the channel region 123 in the direction from the first connection to the gate.

[0109] In some embodiments, as shown in FIG. 15B, the width d2 of the second portion 1512 in the direction from the first connection to the gate is smaller than the width d5 of the channel region 123 in the direction from the first connection to the gate. FIGS. 6A-6I FIG. 16 is a cross-sectional schematic view showing an array substrate according to another embodiment of the present disclosure.

[0110] The structure of the array substrate shown in FIG. 16 is similar to the structure of the array substrate shown in FIG. 15B. Unlike the structure of the array substrate shown in FIG. 15B, in the array substrate shown in FIG. 16, the second via hole 142 also exposes a portion of the buffer layer 114, and the second conductive layer 152 includes a third portion 1521 on the surface of the active layer 120 and a fourth portion 1522 on the surface of the buffer layer 114. FIGS. 9A-9C In the structure shown in FIG. 16, the lateral dimension of the active layer 120 is smaller than the lateral dimension of the active layer 120 in FIG. 15B, and the area of the third portion 1521 of the second conductive layer 152 is smaller than the area of the overlapping portion of the second conductive layer 152 and the active layer 120 in FIG. 15B. Therefore, in the array substrate shown in FIG. 16, the area of the overlapping portion of the second conductive layer 152 and the active layer 120 is reduced, which can improve the light transmittance of the array substrate. FIG. 5 In the structure shown in FIG. 16, the lateral dimension of the active layer 120 is smaller than the lateral dimension of the active layer 120 in FIG. 15B, and the area of the third portion 1521 of the second conductive layer 152 is smaller than the area of the overlapping portion of the second conductive layer 152 and the active layer 120 in FIG. 15B. Therefore, in the array substrate shown in FIG. 16, the area of the overlapping portion of the second conductive layer 152 and the active layer 120 is reduced, which can improve the light transmittance of the array substrate. FIGS. 6A-6F In the structure shown in FIG. 16, the lateral dimension of the active layer 120 is smaller than the lateral dimension of the active layer 120 in FIG. 15B, and the area of the third portion 1521 of the second conductive layer 152 is smaller than the area of the overlapping portion of the second conductive layer 152 and the active layer 120 in FIG. 15B. Therefore, in the array substrate shown in FIG. 16, the area of the overlapping portion of the second conductive layer 152 and the active layer 120 is reduced, which can improve the light transmittance of the array substrate. FIG. 6A In the structure shown in FIG. 16, the lateral dimension of the active layer 120 is smaller than the lateral dimension of the active layer 120 in FIG. 15B, and the area of the third portion 1521 of the second conductive layer 152 is smaller than the area of the overlapping portion of the second conductive layer 152 and the active layer 120 in FIG. 15B. Therefore, in the array substrate shown in FIG. 16, the area of the overlapping portion of the second conductive layer 152 and the active layer 120 is reduced, which can improve the light transmittance of the array substrate. FIG. 6B In the structure shown in FIG. 16, the lateral dimension of the active layer 120 is smaller than the lateral dimension of the active layer 120 in FIG. 15B, and the area of the third portion 1521 of the second conductive layer 152 is smaller than the area of the overlapping portion of the second conductive layer 152 and the active layer 120 in FIG. 15B. Therefore, in the array substrate shown in FIG. 16, the area of the overlapping portion of the second conductive layer 152 and the active layer 120 is reduced, which can improve the light transmittance of the array substrate. FIG. 6B In the structure shown in FIG. 16, the lateral dimension of the active layer 120 is smaller than the lateral dimension of the active layer 120 in FIG. 15B, and the area of the third portion 1521 of the second conductive layer 152 is smaller than the area of the overlapping portion of the second conductive layer 152 and the active layer 120 in FIG. 15B. Therefore, in the array substrate shown in FIG. 16, the area of the overlapping portion of the second conductive layer 152 and the active layer 120 is reduced, which can improve the light transmittance of the array substrate. FIG. 6C In the structure shown in FIG. 16, the lateral dimension of the active layer 120 is smaller than the lateral dimension of the active layer 120 in FIG. 15B, and the area of the third portion 1521 of the second conductive layer 152 is smaller than the area of the overlapping portion of the second conductive layer 152 and the active layer 120 in FIG. 15B. Therefore, in the array substrate shown in FIG. 16, the area of the overlapping portion of the second conductive layer 152 and the active layer 120 is reduced, which can improve the light transmittance of the array substrate. FIG. 6D In the structure shown in FIG. 16, the lateral dimension of the active layer 120 is smaller than the lateral dimension of the active layer 120 in FIG. 15B, and the area of the third portion 1521 of the second conductive layer 152 is smaller than the area of the overlapping portion of the second conductive layer 152 and the active layer 120 in FIG. 15B. Therefore, in the array substrate shown in FIG. 16, the area of the overlapping portion of the second conductive layer 152 and the active layer 120 is reduced, which can improve the light transmittance of the array substrate.

[0111] FIG. 6Eis a top view schematically showing a partial structure of an array substrate according to one embodiment of the present disclosure.

[0112] For the convenience of illustration, FIG. 5 The first conductorized region 121, the first conductive layer 151 and the first connecting member 161 of the active layer 120 of the array substrate are shown in FIG. 6E As shown, due to the presence of the first conductive layer 151, the first conductorized region 121 does not have missing parts, thus, the current can flow through the first conductorized region 121 more uniformly from the first connecting member 161, providing the signal transmission capability of the array substrate.

[0113] In some embodiments of the present disclosure, a display device is also provided, comprising an array substrate as previously described, for example, FIG. 6F or FIG. 5 the array substrate as shown. For example, the display device can be: a display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. any product or component with display function.

[0114] FIGS. 6G-6I is a flow chart showing a manufacturing method of an array substrate according to one embodiment of the present disclosure. As shown, FIG. 6G the manufacturing method comprises steps S502 to S508. FIG. 6H is a cross-sectional schematic view showing the structure of several stages in the manufacturing process of an array substrate according to some embodiments of the present disclosure. FIG. 6H is a cross-sectional schematic view showing the structure of several stages in the manufacturing process of an array substrate according to some other embodiments of the present disclosure. The manufacturing process of the array substrate according to some embodiments of the present disclosure will be described in detail below in combination with FIG. 6H , FIG. 6I and FIG. 6I .

[0115] As shown, FIG. 5 in step S502, an active layer is formed on a substrate structure.

[0116] For example, as shown, FIG. 9A for example, the active layer 120 is formed on the substrate structure 110 by a deposition process. The specific structure of the substrate structure 110 has been described in detail previously, and will not be repeated here.

[0117] Returning to FIG. 5 in step S504, a patterned first insulating layer is formed on the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a part of the active layer.

[0118] For example, the process of forming the patterned first insulating layer can be described in detail with reference to FIG. 9A .

[0119] like FIG. 9B As shown, for example, a first insulating layer 130 is formed on the side of the active layer 120 away from the substrate structure 110 by a deposition process.

[0120] Next, as FIG. 5 As shown, a first mask layer 610 is formed on the side of the first insulating layer 130 away from the substrate structure 110. For example, the material of the first mask layer is a positive photoresist.

[0121] Next, as FIG. 9C and FIG. 5 As shown, for example, by exposure and development techniques, the first mask layer 610 is patterned using a patterned first mask template 621 to form a patterned first mask layer 610, such that the patterned first mask layer has a second opening 6102 that exposes a portion of the first insulating layer 130.

[0122] Next, as FIG. 9C and FIG. 7 As shown, using a patterned first mask layer 610, a portion of the first insulating layer 130 exposed by the second opening 6102 is removed by an etching process (e.g., dry etching) to form a first via 141, thereby forming a patterned first insulating layer 130. The first via 141 exposes a portion of the active layer 120.

[0123] Back FIG. 7 In step S506, a first conductorization process is performed on the portion of the active layer that is exposed.

[0124] For example, such as FIG. 7 As shown, a first conductor-enhancing process can be performed on the portion of the active layer 120 that is exposed. For example, a dry etching process and He gas (helium gas) can be used to perform the first conductor-enhancing process.

[0125] Next, as FIG. 6E As shown, the first mask layer 610 is removed.

[0126] Back FIG. 6I In step S508, a first conductive layer in contact with the active layer is formed in the first through hole.

[0127] For example, you can refer to FIG. 8 Describe in detail the process of forming the first conductive layer.

[0128] For example, such as FIG. 8 As shown, a first conductive layer 151 is formed on the side of the patterned first insulating layer 130 away from the substrate structure 110 and in the first via 141 by a deposition process. For example, the material of the first conductive layer 151 includes a transparent conductive material.

[0129] Next, as shown in FIG. 6B, a second mask layer 612 is formed on the side of the first conductive layer 151 away from the substrate structure 110, and the second mask layer 612 is exposed and developed using the first mask plate 621 described above, thereby forming the structure of the second mask layer 612 as shown in FIG. 6C. For example, the material of the second mask layer is a negative photoresist. FIG. 8 FIG. 6F Next, as shown in FIG. 6D, the first conductive layer 151 is etched to remove the portion of the first conductive layer 151 not covered by the second mask layer 612, and to retain the portion of the first conductive layer 151 covered by the second mask layer 612, thereby forming the structure as shown in FIG. 6E.

[0130] Next, as shown in FIG. 6F, the second mask layer 612 is removed. FIG. 6I FIG. 8

[0131] Next, as shown in FIG. 6F, the second mask layer 612 is removed. FIG. 8 By this point, the patterned first conductive layer 151 is formed, which can protect the active layer 120 underneath as much as possible from being etched.

[0132] Returning to FIG. 5, at step S510, a connection material layer is formed on the side of the first insulating layer away from the substrate structure by a deposition process.

[0133] FIGS. 10A-10C For example, as shown in FIG. 6G, a connection material layer 160 is formed on the side of the first insulating layer 130 away from the substrate structure 110 by a deposition process. The material of the connection material layer 160 includes a metal such as copper.

[0134] Returning to FIG. 5, at step S512, the connection material layer is patterned using a patterned mask layer to form a first connection, which is in contact with the first conductive layer, the first connection covering a first portion of the first conductive layer and not covering a second portion of the first conductive layer. FIGS. 10A-10C For example, as shown in FIG. 6H, a patterned mask layer (which can be referred to as a third mask layer) 637 is formed on the side of the connection material layer away from the substrate structure 110. For example, the material of the third mask layer is a photoresist.

[0135] FIG. 1 Next, as shown in FIG. 6I, the first connection is formed by etching the connection material layer 160 using the third mask layer 637 as a mask.

[0136] Next, as shown in FIG. 6I, the first connection is formed by etching the connection material layer 160 using the third mask layer 637 as a mask. FIG. 10A Next, as shown in FIG. 6I, the first connection is formed by etching the connection material layer 160 using the third mask layer 637 as a mask.

[0137] FIG. 10A ​​​​​​As shown, for example, a first connector 161 is formed by patterning the connection material layer 160 using a third mask layer 637 through a wet etching process. Additionally, a second connector 162 and a gate 163 may also be formed during this process. During this wet etching process, the etching solution may etch a portion of the connection material layer below the edge of the third mask layer, thus causing the formed first connector to be recessed inwards.

[0138] This forms the first connector.

[0139] Back FIG. 10A In step S514, the first insulating layer is etched using a mask layer and a self-aligned process to enlarge the first via, wherein the enlarged first via exposes another part of the active layer.

[0140] For example, such as FIG. 10A As shown, using a patterned mask layer (i.e., the third mask layer) 637, the first insulating layer 130 is etched through a self-aligned process to enlarge the first via 141, wherein the enlarged first via 141 exposes another portion of the active layer 120. For example, this etching is a dry etching process. Here, the entire surface of the first insulating layer is etched, forming a gap between the first conductive layer and the gate insulating layer, namely the gap 301 mentioned above.

[0141] Back FIG. 10B In step S516, the exposed portion of the active layer is subjected to a second conductor treatment.

[0142] For example, such as FIG. 10B As shown, a second conductiveing ​​process is performed on the exposed portion of the active layer 120. For example, a dry etching process and helium gas can be used to perform the second conductiveing ​​process. During this process, the portion of the active layer directly beneath the first conductive layer 151 is protected from etching due to the presence of the first conductive layer 151.

[0143] Next, remove the third mask layer 637.

[0144] So far, the manufacturing method of the array substrate of some embodiments of the present disclosure is provided. The manufacturing method comprises: forming an active layer on a substrate structure; forming a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first via exposing a portion of the active layer; performing a first conductorization process on the portion of the active layer exposed; forming a first conductive layer in contact with the active layer in the first via; forming a connection material layer on the side of the first insulating layer away from the substrate structure by a deposition process; patterning the connection material layer by using a patterned mask layer to form a first connection, the first connection being in contact with the first conductive layer, the first connection covering a first portion of the first conductive layer and not covering a second portion of the first conductive layer; etching the first insulating layer by using the mask layer to expand the first via by a self-alignment process, wherein the expanded first via exposes another portion of the active layer; and performing a second conductorization process on the another portion of the active layer exposed. The manufacturing method can reduce the possibility of missing portions of the active layer, thereby improving the performance of the array substrate and the display device formed therefrom.

[0145] Further, in the manufacturing process described above, the second mask layer uses a negative photoresist, so that the first mask template described above can be used for exposure and development, without the need for additional mask template manufacturing, thereby reducing the process complexity.

[0146] FIG. 10C is a cross-sectional schematic view showing a structure at a stage in the manufacturing process of an array substrate according to another embodiment of the present disclosure. The FIG. 10C is a cross-sectional schematic view showing a structure at a stage in the process of forming a first conductive layer according to some embodiments.

[0147] For example, as FIG. 10C shown, after forming the structure shown in FIG. 1 , a first conductive layer 151 is formed on the patterned first mask layer 610 and in the first via 141 of the first insulating layer 130 by a deposition process.

[0148] Next, the first mask layer 610 and the portion of the first conductive layer 151 on the first mask layer 610 are removed by a lift-off process, leaving the portion of the first conductive layer 151 in the first via 141, thereby forming a structure as shown in FIG. 1 .

[0149] In this embodiment, the lift-off process is used, without the need for additional mask processes, further reducing the process complexity.

[0150] ​ is a cross-sectional schematic view showing a structure at a stage in the manufacturing process of an array substrate according to another embodiment of the present disclosure. The ​Fig. 6 shows a cross-sectional schematic view of a structure at one stage of a process of forming the first conductive layer according to some embodiments.

[0151] For example, as shown in Fig. 6, after forming the structure shown in Fig. 5, a first conductive layer 151 is formed in the first via 141 of the first insulating layer 130 by using a patterned second mask 630 and by using an evaporation process, i.e., a structure shown in Fig. 6 is formed. ​ ​ For example, as shown in Fig. 6, after forming the structure shown in Fig. 5, a first conductive layer 151 is formed in the first via 141 of the first insulating layer 130 by using a patterned second mask 630 and by using an evaporation process, i.e., a structure shown in Fig. 6 is formed. ​ ​ For example, as shown in Fig. 6, after forming the structure shown in Fig. 5, a first conductive layer 151 is formed in the first via 141 of the first insulating layer 130 by using a patterned second mask 630 and by using an evaporation process, i.e., a structure shown in Fig. 6 is formed. ​ For example, as shown in Fig. 6, after forming the structure shown in Fig. 5, a first conductive layer 151 is formed in the first via 141 of the first insulating layer 130 by using a patterned second mask 630 and by using an evaporation process, i.e., a structure shown in Fig. 6 is formed.

[0152] In this embodiment, the first conductive layer is formed by using an evaporation process, which can reduce the process complexity.

[0153] ​ Fig. 7 shows a cross-sectional schematic view of a structure at one stage of a process of manufacturing an array substrate according to some embodiments. ​ ​ The process of manufacturing the array substrate according to some embodiments of the present disclosure is described in detail below with reference to Figs. 7 to 10.

[0154] First, as shown in Fig. 7, a substrate structure is provided. The step of providing the substrate structure includes the following steps. ​ For example, as shown in Fig. 7, the light-blocking layer 112 is formed on the substrate 111 by using a deposition and patterning process. In addition, the trace 115 is also formed.

[0155] ​ Next, as shown in Fig. 7, the third conductive layer 113 is formed on the light-blocking layer 112 by using a deposition and patterning process.

[0156] In some embodiments, the third conductive layer 113 is formed on the substrate 111 by using a deposition and patterning process first; then, the light-blocking layer 112 is formed on the third conductive layer 113 by using a deposition and patterning process. ​ Next, as shown in Fig. 7, the buffer layer 114 is formed on the third conductive layer 113 by using a deposition process.

[0157] By now, the substrate structure 110 is formed.

[0158] ​ Next, as shown in Fig. 7, the buffer layer 114 is formed on the third conductive layer 113 by using a deposition process.

[0159] By now, the substrate structure 110 is formed.

[0160] ​​​​​Next, as ​ As shown, the active layer 120, the first insulating layer 130, the first via 141, the first conductive layer 151, and the first connector 161 are formed using the process described above. Here, the second via 142, the third via 143, the second conductive layer 152, the second connector 162, and the gate 163 are also formed.

[0161] It should be noted that the second conductive layer 152 is formed together with the first conductive layer 151 using the same process, and the second connector 162 and the gate 163 are formed with the first connector 161 using the same patterning process. Further details will not be provided here.

[0162] It should also be noted that, while forming the first through hole 141, a second through hole 142 and a third through hole 143 can also be formed. The formation process of the second through hole 142 and the third through hole 143 is similar to that of the first through hole 141, and will not be described in detail here.

[0163] Next, as ​ As shown, a second insulating layer 171 is formed by a deposition process, covering the first connector 161, the second connector 162, and the gate 163.

[0164] Next, as ​ As shown, a planarization layer 172 is formed on the side of the second insulating layer 171 away from the substrate structure 110.

[0165] Next, as ​ As shown, a first electrode layer 181 electrically connected to the second connector 162 is formed on the side of the planarization layer 172 away from the substrate structure 110.

[0166] Next, as ​ As shown, a pixel defining layer 174 is formed on the side of the planarization layer 172 away from the substrate structure 110. The pixel defining layer 174 has a first opening 1742 that exposes at least a portion of the first electrode layer 181.

[0167] Next, as ​ As shown, a light-emitting layer 180 is formed at least in the first opening 1742.

[0168] Next, as ​ As shown, a second electrode layer 182 electrically connected to the light-emitting layer 180 is formed by a deposition process.

[0169] Thus, a method for manufacturing an array substrate according to some embodiments of the present disclosure is provided. This manufacturing method can reduce the possibility of missing portions in the active layer, thereby improving the performance of the array substrate and the display device formed therefrom.

[0170] So far, the embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein according to the above description.

[0171] Although some specific embodiments of the present disclosure have been described in detail through examples, those skilled in the art should understand that the above examples are only for illustration, not for limiting the scope of the present disclosure. Those skilled in the art should understand that the above embodiments can be modified or some technical features can be replaced equivalently without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. An array substrate, comprising: Substrate structure; The active layer on the substrate structure; A patterned first insulating layer on the side of the active layer away from the substrate structure, the first insulating layer having a first through-hole; The first conductive layer in contact with the active layer; and A first connector on the side of the first insulating layer away from the substrate structure, the first connector being in contact with the first conductive layer through the first through-hole, the first connector covering a first portion of the first conductive layer but not covering a second portion of the first conductive layer, the second portion being in contact with the active layer.

2. The array substrate according to claim 1, wherein: The first insulating layer also has a second through hole; The array substrate further includes: A second conductive layer in contact with the active layer; A second connector electrically connected to the second conductive layer through the second through-hole; and The gate located on the side of the first insulating layer away from the active layer; The second connector is on the same layer as the gate, and both the first connector and the second connector are isolated from the gate.

3. The array substrate according to claim 2, further comprising: A second insulating layer covers the first connector, the second connector, the first conductive layer, and the gate.

4. The array substrate according to claim 2, wherein the active layer includes a channel region, and on the side near the channel region, the minimum distance from the second conductive layer to the channel region is less than the width of the portion of the second conductive layer between the gate and the second connector that is not covered by the second connector.

5. The array substrate according to claim 2, wherein the active layer includes a channel region, and on the side near the channel region, the minimum distance from the first conductive layer to the channel region is not equal to the width of the portion of the first conductive layer between the gate and the first connector that is not covered by the first connector.

6. The array substrate according to claim 2, wherein, The second portion is located between the first connector and the gate.

7. The array substrate according to claim 2, further comprising: A capacitor includes a first electrode plate and a second electrode plate, wherein the first electrode plate includes a second conductive layer, and the second conductive layer is in the same layer as the first conductive layer.

8. The array substrate according to claim 6, wherein, The first electrode plate also includes a portion of the active layer.

9. The array substrate according to claim 2, wherein, The thickness of the second conductive layer is less than the thickness of the active layer.

10. The array substrate according to claim 1, wherein, The first conductive layer is made of a transparent conductive material.

11. The array substrate according to claim 10, wherein, The transparent conductive material includes indium tin oxide or indium zinc oxide.

12. The array substrate according to claim 1, wherein, The array substrate further includes a gate located on the side of the first insulating layer away from the active layer, wherein the width of the second portion along the direction from the first connector to the gate is smaller than the width of the first portion along the direction from the first connector to the gate.

13. The array substrate according to claim 1, wherein, The array substrate further includes a gate located on the side of the first insulating layer away from the active layer, the active layer including a channel region, the second portion having a width along the direction from the first connector to the gate that is smaller than the width of the channel region along the direction from the first connector to the gate.

14. The array substrate according to claim 1, wherein, The thickness of the second part is less than the thickness of the first part.

15. The array substrate according to claim 12, wherein, The width of the first part is 2 to 5 times the width of the second part.

16. The array substrate according to claim 2, wherein: The active layer includes: a first conductive region electrically connected to the first connector, a second conductive region electrically connected to the second connector, and a channel region between the first conductive region and the second conductive region, the channel region being below the gate. The active layer further includes a semiconductor region located on the side of the first conductor region away from the channel region; Wherein, the width of the second portion along the direction from the first connector to the gate is smaller than the width of the semiconductor region along the direction from the first connector to the gate.

17. The array substrate according to claim 2, wherein, The substrate structure includes: Substrate; A light-shielding layer and a third conductive layer are disposed on the substrate, wherein the orthographic projection of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate, wherein the third conductive layer covers the light-shielding layer, or the light-shielding layer covers the third conductive layer; and A buffer layer between the third conductive layer and the active layer.

18. The array substrate according to claim 17, wherein, The orthographic projection of the first conductive layer on the substrate overlaps at least partially with the orthographic projection of the light-shielding layer on the substrate.

19. The array substrate according to claim 17, wherein, The second through-hole also exposes a portion of the buffer layer; The second conductive layer includes a third portion located on the surface of the active layer and a fourth portion located on the surface of the buffer layer.

20. The array substrate according to claim 17, wherein, The materials of both the second conductive layer and the third conductive layer include transparent conductive materials.

21. The array substrate according to claim 17, wherein, The thickness of the third conductive layer is greater than the thickness of the second conductive layer, and / or the thickness of the second conductive layer is equal to the thickness of the first conductive layer.

22. The array substrate according to claim 1, wherein, The thickness of the first conductive layer is greater than the thickness of the active layer.

23. The array substrate according to claim 2, wherein, The area of ​​the overlap between the first connector and the first conductive layer is smaller than the area of ​​the overlap between the second connector and the second conductive layer.

24. The array substrate according to claim 2, wherein: The first insulating layer includes a gate insulating layer located below the gate; The active layer includes: a first conductive region electrically connected to the first connector, a second conductive region electrically connected to the second connector, and a channel region between the first conductive region and the second conductive region, the channel region being flush with the edge of the gate insulating layer.

25. The array substrate according to claim 24, wherein, The width of the overlapping portion of the first connector and the first conductive layer along the direction from the first connector to the gate is less than the distance between the edge of the first conductive layer and the channel region.

26. The array substrate according to claim 1, wherein, The area of ​​the first conductive layer is larger than the area of ​​the contact portion between the first connector and the first conductive layer.

27. The array substrate according to claim 24, wherein, The area of ​​the first conductive layer is smaller than the area of ​​the channel region.

28. The array substrate according to claim 2, wherein, The width of the overlap between the first conductive layer and the active layer along the direction from the first connector to the gate is smaller than the width of the overlap between the second conductive layer and the active layer along the direction from the first connector to the gate.

29. The array substrate according to claim 2, wherein, The distance between the first conductive layer and the gate is greater than the width of the overlapping portion of the first connector and the first conductive layer along the direction from the first connector to the gate, and the width of the overlapping portion of the first connector and the first conductive layer along the direction from the first connector to the gate is greater than the width of the second portion of the first conductive layer along the direction from the first connector to the gate.

30. The array substrate according to claim 2, further comprising: A second insulating layer covers the first connector, the second connector, the first conductive layer, and the gate. A planarization layer on the side of the second insulating layer away from the substrate structure; A first electrode layer and a pixel defining layer are provided on the side of the planarization layer away from the substrate structure. The first electrode layer is electrically connected to the second connector. The pixel defining layer has a first opening that exposes at least a portion of the first electrode layer. At least the light-emitting layer located in the first opening; and A second electrode layer electrically connected to the light-emitting layer.

31. The array substrate according to claim 17, wherein, The width of the overlap between the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the third conductive layer on the substrate, along the direction from the first connector to the gate, is less than the width of the overlap between the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the first electrode layer on the substrate, along the direction from the first connector to the gate.

32. The array substrate according to claim 17, wherein, The width of the overlap between the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the third conductive layer on the substrate along the direction from the first connector to the gate is less than the width of the overlap between the orthographic projection of the third conductive layer on the substrate and the orthographic projection of the first electrode layer on the substrate along the direction from the first connector to the gate.

33. A display device, comprising: The array substrate as described in any one of claims 1 to 32.

34. A method for manufacturing an array substrate, comprising: An active layer is formed on the substrate structure; A patterned first insulating layer is formed on the side of the active layer away from the substrate structure, the first insulating layer having a first via exposing a portion of the active layer; A first conductor-enhancing process is performed on the portion of the active layer that is exposed; A first conductive layer is formed in contact with the active layer; A bonding material layer is formed on the side of the first insulating layer away from the substrate structure by a deposition process; The connecting material layer is patterned using a patterned mask layer to form a first connector. The first connector contacts the first conductive layer through the first through-hole. The first connector covers a first portion of the first conductive layer but does not cover a second portion of the first conductive layer. The second portion contacts the active layer. Using the mask layer, the first insulating layer is etched through a self-aligned process to enlarge the first via, wherein the enlarged first via exposes another part of the active layer; and The exposed portion of the active layer is subjected to a second conductor treatment.

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