Light emitting element and display device including the same

Abstract

A light-emitting element according to an embodiment includes: a first semiconductor layer, an active layer, and a second semiconductor layer arranged in this order in one direction; a first insulating film surrounding outer peripheral surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer and containing an M1xOy-type oxide; a second insulating film surrounding the first insulating film and containing an M22xO (2y-1) type oxide; a third insulating film surrounding the second insulating film and containing an M3xOy-type oxide; and a fourth insulating film surrounding the third insulating film, where M1, M2, and M3 may each be a metal material, and x and y may each be a natural number.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a light emitting element and a display device including the same. BACKGROUND

[0002] With the development of multimedia, display devices are becoming increasingly important. Accordingly, various display devices, such as liquid crystal display devices and organic light emitting display devices, are being developed. SUMMARY

[0003] [PROBLEMS TO BE SOLVED]

[0004] The present disclosure is to provide a light emitting element and a display device including the same having improved reliability.

[0005] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] [TECHNICAL SOLUTION]

[0007] The light emitting element according to an embodiment can include: a first semiconductor layer, an active layer, and a second semiconductor layer arranged in sequence in one direction; a first insulating film surrounding an outer peripheral surface of the first semiconductor layer, the active layer, and the second semiconductor layer and including M1O2-type oxide; a second insulating film surrounding the first insulating film and including M22O3-type oxide; a third insulating film surrounding the second insulating film and including M3O2-type oxide; and a fourth insulating film surrounding the third insulating film. Each of M1, M2, and M3 can be a metal material, and x and y can each be a natural number. x O y 2x O (2y-1) x O y

[0008] The sum of the thickness of the first insulating film, the thickness of the second insulating film, and the thickness of the third insulating film can be 10 nm or less.

[0009] The fourth insulating film can have a thickness greater than the sum of the thickness of the first insulating film, the thickness of the second insulating film, and the thickness of the third insulating film.

[0010] The thickness of the first insulating film can be greater than the thickness of the second insulating film.

[0011] The thickness of the third insulating film can be equal to or greater than the thickness of the second insulating film.

[0012] The first insulating film can include M1O2-type oxide, the second insulating film can include M22O3-type oxide, and the third insulating film can include M3O2-type oxide.

[0013] ​​​The first insulating film may include at least one of SiO2, ZrO2, HfO2, GeO2, TiO2 and TeO2, and the second insulating film may include at least one of Al2O3, Y2O3, La2O3, Ce2O3, Lu2O3, Sc2O3 and Yb2O3.

[0014] The third insulating film may include at least one of SiO2, ZrO2, HfO2, GeO2, TiO2 and TeO2.

[0015] The first insulating film may include ZrO2, the second insulating film may include Al2O3, and the third insulating film may include ZrO2.

[0016] The light-emitting element may further include: a fifth insulating film surrounding the fourth insulating film and having a thickness greater than that of the fourth insulating film.

[0017] The fourth insulating film may be an inorganic film comprising oxides, and the fifth insulating film may be an inorganic film comprising oxides of a different material than the fourth insulating film.

[0018] The light-emitting element according to the embodiment may include: a first semiconductor layer, an active layer, and a second semiconductor layer arranged sequentially in one direction; and a first insulating film surrounding the outer peripheral surface of the first semiconductor layer, the active layer, and the second semiconductor layer and including M1. x O y Type oxide; second insulating film, surrounding the first insulating film and containing M2 2x O (2y-1) Type oxide; third insulating film, surrounding the second insulating film and including M3 x O y Type oxide. Each of M1, M2 and M3 can be a metallic material, x and y can each be a natural number, the thickness of the first insulating film can be greater than the thickness of the second insulating film, and the thickness of the third insulating film can be equal to or greater than the thickness of the second insulating film.

[0019] The sum of the thicknesses of the first insulating film, the second insulating film, and the third insulating film can be 10 nm or less.

[0020] The first insulating film may include M1O2 type oxide, the second insulating film may include M22O3 type oxide, and the third insulating film may include M3O2 type oxide.

[0021] The first insulating film may include at least one of SiO2, ZrO2, HfO2, GeO2, TiO2 and TeO2, and the second insulating film may include at least one of Al2O3, Y2O3, La2O3, Ce2O3, Lu2O3, Sc2O3 and Yb2O3.

[0022] The third insulating film can include at least one of SiO2, ZrO2, HfO2, GeO2, TiO2, and TeO2.

[0023] The first insulating film can include ZrO2, the second insulating film can include Al2O3, and the third insulating film can include ZrO2.

[0024] The light emitting element can further include a fourth insulating film surrounding the third insulating film and having a thickness greater than a sum of a thickness of the first insulating film, a thickness of the second insulating film, and a thickness of the third insulating film.

[0025] The light emitting element can further include a fifth insulating film surrounding the fourth insulating film and having a thickness greater than a thickness of the fourth insulating film.

[0026] A display device according to an embodiment can include a pixel including a first electrode and a second electrode spaced apart from each other, and a light emitting element electrically connected between the first electrode and the second electrode. The light emitting element can include a first semiconductor layer, an active layer, and a second semiconductor layer arranged in this order in one direction, a first insulating film surrounding an outer circumferential surface of the first semiconductor layer, the active layer, and the second semiconductor layer and including M1O2-type oxide, a second insulating film surrounding the first insulating film and including M2O3-type oxide, a third insulating film surrounding the second insulating film and including M3O2-type oxide, and a fourth insulating film surrounding the third insulating film. Each of M1, M2, and M3 can be a metal material, and x and y can each be a natural number. x O y 2x O (2y-1) x O y

[0027] A sum of a thickness of the first insulating film, a thickness of the second insulating film, and a thickness of the third insulating film can be 10 nm or less.

[0028] The fourth insulating film can have a thickness greater than a sum of a thickness of the first insulating film, a thickness of the second insulating film, and a thickness of the third insulating film.

[0029] The thickness of the first insulating film can be greater than the thickness of the second insulating film, and the thickness of the third insulating film can be equal to or greater than the thickness of the second insulating film.

[0030] The first insulating film can include M1O2-type oxide, the second insulating film can include M22O3-type oxide, and the third insulating film can include M3O2-type oxide.

[0031] ​​​The first insulating film can include at least one of SiO2, ZrO2, HfO2, GeO2, TiO2, and TeO2, and the second insulating film can include at least one of Al2O3, Y2O3, La2O3, Ce2O3, Lu2O3, Sc2O3, and Yb2O3.

[0032] The third insulating film can include at least one of SiO2, ZrO2, HfO2, GeO2, TiO2, and TeO2.

[0033] The first insulating film can include ZrO2, the second insulating film can include Al2O3, and the third insulating film can include ZrO2.

[0034] The display device can further include a fifth insulating film surrounding the fourth insulating film and having a thickness greater than a thickness of the fourth insulating film.

[0035] The fourth insulating film can be an inorganic film including an oxide, and the fifth insulating film can be an inorganic film including an oxide different from a material of the fourth insulating film.

[0036] The pixel can further include a first alignment electrode and a second alignment electrode positioned below the light emitting element and spaced apart from each other.

[0037] Further details of implementations are included in the detailed description and the accompanying drawings.

[0038] [Effects of the Invention]

[0039] The light emitting element according to the implementation can include a multi-layer oxide insulating film surrounding the first semiconductor layer, the active layer, and the second semiconductor layer. The multi-layer oxide insulating film can include a first insulating film including an oxide containing M1 x O y a second insulating film including an oxide containing M2 2x O (2y-1) and a third insulating film including an oxide containing M3 x O y .

[0040] According to the implementation, oxygen flowing into the light emitting element can be trapped by oxygen vacancies formed at interfaces of the first insulating film, the second insulating film, and the third insulating film. Accordingly, reliability of the light emitting element can be increased.

[0041] The display device according to the implementation can include a pixel including the light emitting element. Accordingly, reliability of the display device can be increased.

[0042] However, effects of the implementation are not limited to the foregoing effects, and various other effects are included in the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 A schematic perspective view of a light-emitting element according to an embodiment;

[0044] Figure 2 A schematic cross-sectional view of a light-emitting element according to an embodiment;

[0045] Figure 3 A cross-sectional view of a light-emitting element according to an embodiment;

[0046] Figure 4 A cross-sectional view of a light-emitting element according to an embodiment;

[0047] Figure 5 A diagram illustrating an interface reaction occurring in a multilayer oxide insulating film according to an embodiment and oxygen vacancies formed therefrom;

[0048] Figure 6 A graph showing a luminance maintenance rate of a light-emitting element with respect to a material forming a multilayer oxide insulating film;

[0049] Figure 7 A graph showing a luminance maintenance rate of a light-emitting element with respect to a thickness of a first insulating film;

[0050] Figure 8 A graph showing a luminance maintenance rate of a light-emitting element with respect to a thickness of a second insulating film;

[0051] Figure 9 A graph showing a luminance maintenance rate of a light-emitting element with respect to a thickness of a third insulating film;

[0052] Figure 10 A plan view of a display device according to an embodiment;

[0053] Figure 11 A circuit diagram of a pixel according to an embodiment;

[0054] Figure 12 A circuit diagram of a pixel according to an embodiment;

[0055] Figure 13 A plan view of a pixel according to an embodiment;

[0056] Figure 14 A cross-sectional view of a display device according to an embodiment;

[0057] Figure 15 A Figure 14 An enlarged view of a region of a pixel illustrated in FIG. 20B;

[0058] Figure 16 A Figure 15 An enlarged view of a region of a light-emitting element illustrated in FIG. 21B; and

[0059] Figure 17 For Figure 15 An enlarged view of a region of the light-emitting element illustrated in DETAILED DESCRIPTION

[0060] The advantages and features of the present disclosure and a method of accomplishing the same can be understood more readily by reference to the following detailed description of embodiments and the accompanying drawings. The present disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the present disclosure to those skilled in the art, and the present disclosure will only be defined by the claims.

[0061] It will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on another element or layer or intervening elements or layers can be present. In the description of embodiments, the same drawing reference numerals are used throughout the several views and the same reference numerals in different drawings signify the same or similar elements. The shapes, sizes, proportions, angles, numbers, and the like that are disclosed in the drawings for describing the embodiments are merely examples and the present disclosure is not limited to the illustrated details.

[0062] The features of various embodiments of the present disclosure can be partially or wholly combined or combined with each other, and can be technically inter-operable and drivable in various ways. The embodiments can be implemented independently of each other or together in an interdependent relationship.

[0063] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0064] Figure 1 is a schematic perspective view of a light-emitting element LD according to an embodiment. Figure 2 is a schematic cross-sectional view of a light-emitting element LD according to an embodiment. For example, Figure 2 is schematically illustrated Figure 1 a cross-section of the light-emitting element LD.

[0065] Referring to Figure 1 and Figure 2 , the light-emitting element LD can include a light-emitting stack LES, a multilayer oxide insulating film MLO, and a protective film PRL. In an embodiment, the light-emitting element LD can be provided in a rod shape. In the description of the embodiment, the rod shape can include various rod shapes or bar shapes including a cylindrical shape or a polygonal column shape, and the shape of a cross-section of the light-emitting element LD is not particularly limited. In an embodiment, the length L of the light-emitting element LD can be greater than the diameter D (or the width of the cross-section) of the light-emitting element LD.

[0066] The light-emitting stack LES (also referred to as "light emitter" or "light-emitting structure") can include semiconductor layers of different conductive types and an active layer between the semiconductor layers. The light-emitting stack LES can optionally further include at least one electrode layer.

[0067] The multilayer oxide insulating film MLO can surround the outer peripheral surface of the light-emitting stack LES (e.g., the side surface of the rod-shaped light-emitting stack LES). The multilayer oxide insulating film MLO can expose both ends of the light-emitting stack LES (e.g., both bases of the rod-shaped light-emitting stack LES). The multilayer oxide insulating film MLO can include two or more insulating films containing different oxides. The two or more insulating films can be thin films having a small thickness. For example, the multilayer oxide insulating film MLO can include insulating films whose total thickness is 10 nm or less. Because the thickness of the multilayer oxide insulating film MLO is limited to 10 nm or less, the influence of the multilayer oxide insulating film MLO on the characteristics of the light-emitting stack LES can be prevented or reduced.

[0068] The protective film PRL can surround the multilayer oxide insulating film MLO and expose both ends of the light-emitting stack LES (e.g., both bases of the rod-shaped light-emitting stack LES). The protective film PRL can be a single insulating film, or can include two or more insulating films.

[0069] The protective film PRL can be formed to stably protect the light-emitting stack LES and the multilayer oxide insulating film MLO in the process of manufacturing the light-emitting element LD and / or in other subsequent processes (e.g., a pixel process for forming a pixel of a display device using the light-emitting element LD). For example, the protective film PRL can be formed to have a thickness that enables it to remain on the surface of the light-emitting element LD even when etched by a certain thickness due to over-etching, which can occur in a process of etching the upper surface of the multilayer oxide insulating film MLO and the protective film PRL during the process of manufacturing the light-emitting element LD and / or a pixel process for forming a pixel of a display device using the light-emitting element LD (e.g., an etching process for forming a pixel electrode connected to both ends of the light-emitting element LD).

[0070] For example, the protective film PRL can be formed to have a thickness including a margin for over-etching that can occur in a subsequent process, so that the protective film PRL can stably cover the light-emitting stack LES and the multilayer oxide insulating film MLO. In an embodiment, the protective film PRL can include at least one insulating film having a thickness equal to or greater than the thickness of the multilayer oxide insulating film MLO (e.g., a thickness of about 10 nm or more).

[0071] In an embodiment, the light-emitting element LD can have a small size in the range of nanometers to micrometers. For example, the light-emitting element LD can have a diameter D (or a width of a cross section) and / or a length L in the range of nanometers to micrometers. For example, the light-emitting element LD can have a diameter D and / or a length L in the range of about tens of nanometers to tens of micrometers.

[0072] The structure, shape, size, and / or type of the light-emitting element (LD) can vary depending on the implementation method. For example, the structure, shape, size, and / or type of the light-emitting element (LD) can be modified in various ways depending on the design conditions of the light-emitting device using the LD or the light-emitting characteristics to be ensured.

[0073] Light-emitting devices, including light-emitting elements (LDs), can be used in various types of devices that require a light source. For example, an LD can be placed in the pixels of a display device and can be used as the light source for the pixels. LDs can also be used in other types of devices that require a light source, such as lighting devices.

[0074] In this implementation, the light-emitting element (LD) can be surface-treated with a hydrophobic material. Accordingly, when the LD is supplied to each emission area (e.g., the emission area of ​​each pixel and / or subpixel) using methods such as inkjet printing, aggregation of the LD can be prevented.

[0075] Figure 3 This is a cross-sectional view of a light-emitting element (LD) according to an embodiment. For example, Figure 3 Showing with Figure 1 An implementation of the cross section (e.g., longitudinal section) of the light-emitting element LD corresponding to line I-I'.

[0076] Figure 4 This is a cross-sectional view of a light-emitting element (LD) according to an embodiment. For example, Figure 4 Showing with Figure 1 Another embodiment of the cross-section of the light-emitting element LD corresponding to line I-I'. With Figure 3 Compared to the implementation method, in Figure 4 In one embodiment, the light-emitting element LD further includes a fifth insulating film INF5.

[0077] Apart from Figure 1 and Figure 2 In addition to referencing Figure 3 and Figure 4 The light-emitting element (LD) may include a light-emitting stack LES comprising a first semiconductor layer SCL1, an active layer ACT (also referred to as the "light-emitting layer"), and a second semiconductor layer SCL2 arranged and / or stacked sequentially along one direction (e.g., the longitudinal or height direction). The light-emitting stack LES may optionally further include an electrode layer ETL. The light-emitting element (LD) may further include a multilayer oxide insulating film MLO and a protective film PRL surrounding the light-emitting stack LES.

[0078] The light emitting element LD can include a first end EP1 and a second end EP2. In an embodiment, the first end EP1 and the second end EP2 can be opposite to each other. For example, the light emitting element LD can include the first end EP1 and the second end EP2 at both ends in a longitudinal direction (or a height direction). The first end EP1 of the light emitting element LD can include a first base (e.g., an upper surface) of the light emitting element LD and / or a region around the first base. The second end EP2 of the light emitting element LD can include a second base (e.g., a lower surface) of the light emitting element LD and / or a region around the second base.

[0079] In an embodiment, the first semiconductor layer SCL1, the active layer ACT, the second semiconductor layer SCL2, and the electrode layer ETL can be sequentially arranged in a direction from the second end EP2 toward the first end EP1 of the light emitting element LD. For example, the electrode layer ETL (or the second semiconductor layer SCL2) can be located at the first end EP1 of the light emitting element LD, and the first semiconductor layer SCL1 (or another electrode layer adjacent to and electrically connected to the first semiconductor layer SCL1) can be located at the second end EP2 of the light emitting element LD.

[0080] In Figure 3 In an embodiment, the electrode layer ETL is described as included in the light emitting stack LES. However, embodiments are not limited to this case. For example, the electrode layer ETL can also be formed separately from the light emitting stack LES and then placed on the light emitting stack LES.

[0081] In an embodiment, the light emitting stack LES (or the light emitting element LD including the light emitting stack LES) can further include at least one other semiconductor layer (e.g., at least one other semiconductor layer located above and / or below the active layer ACT) and / or at least one other electrode layer (e.g., an additional electrode layer located around the first semiconductor layer SCL1).

[0082] The first semiconductor layer SCL1 can include a first-conductivity-type semiconductor layer containing a first-conductivity-type dopant. For example, the first semiconductor layer SCL1 can be an N-type semiconductor layer containing an N-type dopant.

[0083] In an embodiment, the first semiconductor layer SCL1 can contain a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the first semiconductor layer SCL1 can contain a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide-based semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The first semiconductor layer SCL1 can also contain other materials.

[0084] In embodiments, the first semiconductor layer SCL1 can contain an N-type dopant such as Si, Ge, or Sn. The first semiconductor layer SCL1 can also contain other dopants.

[0085] An active layer ACT (also referred to as a "light-emitting layer") can be located on the first semiconductor layer SCL1. The active layer ACT can include a single or multiple quantum well (QW) structure. When a voltage equal to or higher than a threshold voltage is applied across the light-emitting element LD, electron-hole pairs can recombine in the active layer ACT. Accordingly, light can be emitted from the light-emitting element LD.

[0086] In embodiments, the active layer ACT can emit light in a visible wavelength band, e.g., a wavelength band of about 400 nm to 900 nm. For example, the active layer ACT can emit blue light having a peak wavelength in a range of about 440 nm to 480 nm, green light having a peak wavelength in a range of about 510 nm to 550 nm, or red light having a peak wavelength in a range of about 610 nm to 650 nm. The active layer ACT can also emit light in other colors and / or wavelength bands in addition to the colors and / or wavelength bands exemplified above.

[0087] In embodiments, the active layer ACT can contain a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the active layer ACT can contain a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, InGaAlN, AlN, InN, and AlInN, or a phosphide-based semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The active layer ACT can also contain other materials.

[0088] The second semiconductor layer SCL2 can be located on the active layer ACT. The second semiconductor layer SCL2 can include a second-conductivity-type semiconductor layer containing a second-conductivity-type dopant. For example, the second semiconductor layer SCL2 can be a P-type semiconductor layer containing a P-type dopant.

[0089] In embodiments, the second semiconductor layer SCL2 can contain a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the second semiconductor layer SCL2 can contain a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide-based semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The second semiconductor layer SCL2 can also contain other materials.

[0090] In embodiments, the second semiconductor layer SCL2 can contain a P-type dopant such as Mg. The second semiconductor layer SCL2 can also contain other dopants.

[0091] In an embodiment, the first semiconductor layer SCL1 and the second semiconductor layer SCL2 can contain the same semiconductor material (e.g., the same nitride-based semiconductor material), but can contain dopants of different conductivity types. In another embodiment, the first semiconductor layer SCL1 and the second semiconductor layer SCL2 can contain different semiconductor materials, and can contain dopants of different conductivity types.

[0092] In an embodiment, the first semiconductor layer SCL1 and the second semiconductor layer SCL2 can have different lengths (or thicknesses) in the longitudinal direction of the light-emitting element LD. For example, along the longitudinal direction of the light-emitting element LD, the first semiconductor layer SCL1 can have a length longer than that of the second semiconductor layer SCL2 (or can have a thickness thicker than that of the second semiconductor layer SCL2). Accordingly, the active layer ACT is closer to the first end EP1 (e.g., the P-type end) than to the second end EP2 (e.g., the N-type end).

[0093] The electrode layer ETL can be located on the second semiconductor layer SCL2. The electrode layer ETL can be an electrode for protecting the second semiconductor layer SCL2 and smoothly connecting the second semiconductor layer SCL2 to at least one circuit element, electrode, and / or wiring. For example, the electrode layer ETL can be an ohmic contact electrode or a Schottky contact electrode.

[0094] According to an embodiment, the electrode layer ETL can contain a metal or a metal oxide. For example, the electrode layer ETL can be formed by using a metal such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), or copper (Cu), an oxide or an alloy thereof, or a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), or indium oxide (In2O3) alone or in combination. The electrode layer ETL can further contain other materials.

[0095] In an embodiment, the electrode layer ETL can be substantially transparent. Accordingly, light generated by the light-emitting element LD can pass through the electrode layer ETL.

[0096] The multilayer oxide insulating film MLO can surround the light-emitting stack LES. For example, the multilayer oxide insulating film MLO can surround at least the outer peripheral surfaces (e.g., side surfaces) of the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2. In an embodiment in which the light-emitting element LD further includes the electrode layer ETL, the multilayer oxide insulating film MLO can selectively surround the electrode layer ETL. For example, the multilayer oxide insulating film MLO can partially or completely surround the outer peripheral surfaces (e.g., side surfaces) of the electrode layer ETL or can not surround the electrode layer ETL.

[0097] The multilayer oxide insulating film (MLO) can expose the electrode layer (ETL) (or the second semiconductor layer (SCL2)) and the first semiconductor layer (SCL1) (or provide another electrode layer at the second end EP2 of the light-emitting element LD) at the first end EP1 and the second end EP2, respectively. For example, the MLO may not be provided on the two substrates (e.g., the upper and lower surfaces of the light-emitting element LD) corresponding to the first end EP1 and the second end EP2 of the light-emitting element LD. Accordingly, electrical signals (e.g., drive signals and / or power supply voltages) can be applied to the light-emitting element LD through the first end EP1 and the second end EP2.

[0098] Multilayer oxide insulating film (MLO) can be provided on the surface of the light-emitting layer (LES) to ensure the electrical stability of the light-emitting element (LD). Additionally, the MLO can mitigate the degradation of the LD and increase its reliability by blocking or reducing oxygen inflow into the LES. For example, the MLO may include oxygen vacancies formed at the interfaces between insulating films containing different oxides (e.g., Figure 5 oxygen vacancy V O Because oxygen is captured by oxygen vacancies, it can block or reduce the inflow of oxygen into the light-emitting LES stack.

[0099] The multilayer oxide insulating film MLO may include a first insulating film INF1, a second insulating film INF2, and a third insulating film INF3.

[0100] The first insulating film INF1 may surround the light-emitting stack LES. For example, the first insulating film INF1 may surround the outer peripheral surface (e.g., the side surface) of the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2. In an embodiment, the first insulating film INF1 may further surround at least a portion of the electrode layer ETL (e.g., at least a portion of the side surface).

[0101] The second insulating film INF2 may surround the first insulating film INF1. For example, the second insulating film INF2 may surround the outer peripheral surface (e.g., the side surface) of the first insulating film INF1.

[0102] The third insulating film INF3 may surround the second insulating film INF2. For example, the third insulating film INF3 may surround the outer peripheral surface (e.g., the side surface) of the second insulating film INF2.

[0103] The first insulating film INF1, the second insulating film INF2, and the third insulating film INF3 may contain oxides that can generate oxygen vacancies at their interfaces sufficient to improve the degradation of the light-emitting element LD, while reducing or minimizing defects in the light-emitting element LD. For example, the first insulating film INF1 may contain M1 xO y type (or M x O y type) oxide (e.g., M1 x O y type metal oxide), the third insulating film INF3 can contain M3 x O y type (or M x O y type) oxide (e.g., M3 x O y type metal oxide), and the second insulating film INF2 can contain M2 2x O (2y-1) type (or M 2x O (2y-1) type) oxide (e.g., M2 2x O (2y-1) type metal oxide). Here, M or M1, M2, and M3 can each be a material (e.g., a metal material (or a metal ion)) bonded to oxygen (or an oxygen ion), and x and y can each be a natural number. At least two of M1, M2, and M3 can be the same material, or M1, M2, and M3 can be different materials. For example, M1 and M3 can be the same material, and M2 can be a material different from M1 and M3, but the embodiment is not limited to this example.

[0104] In the embodiment, the oxides used to form the first insulating film INF1, the second insulating film INF2, and the third insulating film INF3 can be selected as materials that generate oxygen vacancies at their interfaces sufficient to improve deterioration of the light-emitting element LD while reducing or minimizing defects in the light-emitting element LD. For example, the first insulating film INF1 and the third insulating film INF3 can contain M1O2 type oxide and M3O2 type oxide, respectively, and the second insulating film INF2 can contain M22O3 type oxide.

[0105] In the embodiment, each of the first insulating film INF1 and the third insulating film INF3 can contain at least one of silicon oxide, zirconium oxide, hafnium oxide, germanium oxide, titanium oxide, and tellurium oxide. For example, each of the first insulating film INF1 and the third insulating film INF3 can contain at least one of SiO2, ZrO2, HfO2, GeO2, TiO2, and TeO2. The first insulating film INF1 and the third insulating film INF3 can contain the same oxide or different oxides.

[0106] In the embodiment, the second insulating film INF2 can contain at least one of aluminum oxide, yttrium oxide, lanthanum oxide, cerium oxide, lutetium oxide, scandium oxide, and ytterbium oxide. For example, the second insulating film INF2 can contain at least one of Al2O3, Y2O3, La2O3, Ce2O3, Lu2O3, Sc2O3, and Yb2O3.

[0107] In an embodiment, the first insulating film INF1 can be an oxide insulating film containing Zr02, the second insulating film INF2 can be an oxide insulating film containing Al203, and the third insulating film INF3 can be an oxide insulating film containing Zr02. In this case, oxygen vacancies for improving deterioration can be ensured while reducing or minimizing defects in the light-emitting element LD. The oxide used for forming the first insulating film INF1, the second insulating film INF2, and the third insulating film INF3 is not limited to the above examples, and can be changed depending on the embodiment.

[0108] In an embodiment, the first insulating film INF1, the second insulating film INF2, and the third insulating film INF3 can be formed into thin films, so that their influence on the light-emitting stack LES can be reduced or minimized. For example, the sum of the thickness of the first insulating film INF1, the thickness of the second insulating film INF2, and the thickness of the third insulating film INF3 can be 10 nm or less. In addition, the first insulating film INF1, the second insulating film INF2, and the third insulating film INF3 can be formed into a limited thickness, so that an interface reaction for smoothly inducing generation of oxygen vacancies sufficient for improving deterioration of the light-emitting element LD at their interfaces can be induced while reducing or minimizing defects in the light-emitting element LD.

[0109] For example, the second insulating film INF2 can be formed into, but is not limited to, a thickness of 2 nm or less (e.g., a thickness of about 1 nm to 2 nm) to smoothly induce an interface reaction. The first insulating film INF1 can be formed into a thickness greater than that of the second insulating film INF2 to prevent defects from occurring in a region too close to the light-emitting stack LES (e.g., to ensure a certain distance or a greater distance between the interface of the first insulating film INF1 and the second insulating film INF2 and the light-emitting stack LES), but can be formed into a limited thickness to reduce or minimize its influence on the light-emitting stack LES. For example, the first insulating film INF1 can be formed into, but is not limited to, a thickness of 3 nm or less (e.g., a thickness of about 2 nm to 3 nm). The third insulating film INF3 can be formed into a thickness equal to or greater than that of the second insulating film INF2 to enable a relatively uniform interface reaction to occur at the interface between the first insulating film INF1 and the second insulating film INF2 and at the interface between the second insulating film INF2 and the third insulating film INF3 (e.g., to prevent the interface reaction from being concentrated at the interface between the first insulating film INF1 and the second insulating film INF2). For example, the third insulating film INF3 can be formed into, but is not limited to, a thickness of 2 nm or 3 nm or less (e.g., a thickness of about 1 nm to 3 nm). Accordingly, the deterioration characteristics of the light-emitting element LD can be improved while reducing or minimizing defects in the light-emitting element LD. As a result, the reliability of the light-emitting element LD can be increased.

[0110] The protective film PRL can surround the multilayer oxide insulating film MLO. For example, the protective film PRL can surround the third insulating film INF3 and expose the first end EP1 and the second end EP2 of the light emitting element LD.

[0111] The protective film PRL can include at least one insulating film. For example, the protective film PRL can include a fourth insulating film INF4 (or a first protective film).

[0112] The fourth insulating film INF4 can surround the multilayer oxide insulating film MLO. For example, the fourth insulating film INF4 can surround the outer peripheral surface (e.g., side surface) of the third insulating film INF3.

[0113] In an embodiment, the protective film PRL can include only the fourth insulating film INF4 as in the embodiment of Figure 3 In an embodiment, the fourth insulating film INF4 can be formed to have a material and / or a thickness that can stably protect the light emitting stack LES and the multilayer oxide insulating film MLO in a process of manufacturing the light emitting element LD and / or in other subsequent processes (e.g., an etching process included in a pixel process of a display device using the light emitting element LD). For example, the fourth insulating film INF4 can be an inorganic film containing an oxide (e.g., an inorganic film containing silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide), and can have a thickness greater than the sum of the thickness of the first insulating film INF1, the thickness of the second insulating film INF2, and the thickness of the third insulating film INF3 (e.g., a thickness of about 10 nm or more). For example, the fourth insulating film INF4 can be an inorganic film containing SiO2 or other oxides, and can have a thickness of about 10 nm to 200 nm, but embodiments are not limited to this example.

[0114] In an embodiment, the protective film PRL can include two insulating films including the fourth insulating film INF4 as in the embodiment of Figure 4

[0115] The fifth insulating film INF5 can surround the fourth insulating film INF4. For example, the fifth insulating film INF5 can surround the outer peripheral surface (e.g., side surface) of the fourth insulating film INF4.

[0116] ​The fifth insulating film INF5 can protect the light-emitting stack LES and the multilayer oxide insulating film MLO together with the fourth insulating film INF4. For example, the fifth insulating film INF5 can be formed to have a material and / or a thickness that can stably protect the light-emitting stack LES and the multilayer oxide insulating film MLO in a process of manufacturing the light-emitting element LD and / or in other subsequent processes (e.g., an etching process for forming a pixel electrode over the light-emitting element LD). For example, the fifth insulating film INF5 can be an inorganic film containing an oxide different from that of the fourth insulating film INF4 (e.g., an inorganic film containing silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide), and can have a thickness greater than that of the fourth insulating film INF4. For example, the fifth insulating film INF5 can be an inorganic film containing Al2O3 or another oxide, and can have a thickness of about 10 nm to 200 nm, although the embodiment is not limited to this example.

[0117] The structure, material, and / or thickness of the protective film PRL are not limited to the above-described embodiment. For example, the protective film PRL can further include three or more insulating films including one or more additional insulating films in addition to the fourth insulating film INF4 and the fifth insulating film INF5.

[0118] In the case where the protective film PRL is formed to have two or more insulating films including the fourth insulating film INF4 and the fifth insulating film INF5, the thickness of each insulating film constituting the protective film PRL can be reduced. Accordingly, the process time for forming the protective film PRL can be reduced, and the process efficiency can be increased. For example, when the protective film PRL is formed using an atomic layer deposition (ALD) process technique, the ALD process time can be reduced by reducing the thickness of each insulating film constituting the protective film PRL.

[0119] Figure 5 To explain the interface reaction occurring in the multilayer oxide insulating film MLO according to the embodiment and the oxygen vacancy V O formed therefrom, FIG. 1 is shown. For example, Figure 5 An interface reaction occurring in a multilayer oxide insulating film MLO including a first insulating film INF1 containing ZrO2, a second insulating film INF2 containing Al2O3, and a third insulating film INF3 containing ZrO2, and the resulting oxygen vacancy V O is shown.

[0120] In addition to Figure 1 to Figure 4 reference is made to Figure 5 , the oxygen vacancy V OFor example, at the interface above, Al2O3 of the second insulating film INF2 can react with ZrO2 of the first insulating film INF1 and ZrO2 of the third insulating film INF3 to form oxygen vacancies V O .

[0121] For example, at the interface above, aluminum (Al) and zirconium (Zr) can be substituted for each other, and oxygen (O) can be substituted for each other. For example, at the interface between the second insulating film INF2 and the first insulating film INF1 and at the interface between the second insulating film INF2 and the third insulating film INF3, as disclosed in the chemical formulae of Figure 5 , Al2O3 of the second insulating film INF2 can react with ZrO2 of the first insulating film INF1 and ZrO2 of the third insulating film INF3 (ZrO2 of the first insulating film INF1 and ZrO2 of the third insulating film INF3). Therefore, zirconium (Zr) can be substituted for aluminum (Al), and oxygen (O) can be substituted for each other.

[0122] Figure 5 The chemical formulae disclosed in the above describe defects occurring at the interface in terms of Kroger-Vink notation, in which a subscript indicates a site of a defect, and a superscript indicates a quantity of an electric charge. For example, Zr Al represents a zirconium (Zr) ion located at an aluminum (Al) lattice site, with a single positive electric charge, and V ″ O represents an oxygen vacancy V O located at an oxygen (O) site, with a double negative electric charge. Three oxygen (O) ions occupy three of four oxygen (O) sites, and one oxygen (O) site is vacant to become the oxygen vacancy V O . X O The superscript X in the above indicates that the relative electric charge is zero.

[0123] For example, at the interface between the second insulating film INF2 and the first insulating film INF1 and at the interface between the second insulating film INF2 and the third insulating film INF3, the ratio of oxygen (O) ions of the first insulating film INF1 and the third insulating film INF3 to oxygen (O) ions of the second insulating film INF2 is 4:3. Therefore, oxygen vacancies V O may be formed at the interface. The oxygen vacancies V O formed by the interface reaction are defects fixed to adjacent atoms, and do not move even when the light-emitting element LD is driven.

[0124] The oxygen vacancies V O formed at the interface can serve as trapping sites that trap oxygen (O) flowing into the light-emitting element LD, thereby suppressing diffusion of oxygen. Accordingly, deterioration of the light-emitting element LD can be reduced or minimized, and the reliability of the light-emitting element LD can be increased.

[0125] Figure 6 A graph showing the brightness retention rate of a light-emitting element (LD) relative to the material forming the multilayer oxide insulating film (MLO). For example, Figure 6 The brightness maintenance rate of a light-emitting element LD comprising a multilayer oxide insulating film MLO, the multilayer oxide insulating film MLO comprising a first insulating film INF1 containing ZrO2, a second insulating film INF2 containing Al2O3 and a third insulating film INF3 containing ZrO2 is shown, and the brightness maintenance rate of a light-emitting element LD comprising multilayer oxide insulating films MLO_R1 and MLO_R2 (where the material of the second insulating film INF2 is changed to an oxide other than M2O3 type oxide) is shown.

[0126] Apart from Figure 1 to Figure 5 In addition to referencing Figure 6 Light-emitting elements (LDs) comprising a multilayer oxide insulating film MLO (insulated by an insulating film containing ZrO2) can maintain a high brightness retention rate even over time. This MLO includes a first insulating film INF1 containing ZrO2, a second insulating film INF2 containing Al2O3, and a third insulating film INF3 containing ZrO2. On the other hand, LDs comprising a multilayer oxide insulating film MLO_R1 (where the second insulating film INF2 is replaced with an insulating film containing MO2-type oxides (e.g., SiO2)) exhibit a slightly lower brightness retention rate. Furthermore, LDs comprising a multilayer oxide insulating film MLO_R2 (where the second insulating film INF2 is replaced with an insulating film containing M2O5-type oxides (e.g., Ta2O5)) exhibit a significantly lower brightness retention rate.

[0127] As described above, the brightness retention rate of the light-emitting element (LD) can vary depending on the material forming the multilayer oxide insulating film MLO. Accordingly, in the embodiment, the first insulating film INF1 and the third insulating film INF3 can each use M... x O y Type oxides (e.g., M1O2 type oxide and M3O2 type oxide, respectively) are formed, and the second insulating film INF2 can be made using M 2x O (2y-1) Type oxides (e.g., M22O3 type oxides) are formed to improve the degradation characteristics of the light-emitting element LD and ensure reliability.

[0128] Figure 7 A graph showing the brightness retention rate of the light-emitting element (LD) relative to the thickness of the first insulating film INF1. For example, Figure 7The brightness maintenance rate of a light-emitting element LD comprising a multilayer oxide insulating film MLO_1a is shown. The multilayer oxide insulating film MLO_1a comprises a first insulating film INF1 containing ZrO2 and having a thickness of 2 nm, a second insulating film INF2 containing Al2O3 and having a thickness of 1 nm, and a third insulating film INF3 containing ZrO2 and having a thickness of 1 nm. The brightness maintenance rate of a light-emitting element LD comprising multilayer oxide insulating films MLO_2 and MLO_3 (where the thickness of the first insulating film INF1 is changed) is also shown.

[0129] Apart from Figure 1 to Figure 5 In addition to referencing Figure 7 The brightness maintenance rate of the light-emitting element (LD) can vary depending on the thickness of the first insulating film INF1. For example, the brightness maintenance rate of an LD comprising a multilayer oxide insulating film MLO_1a (which includes a first insulating film INF1 (ZrO2 insulating film) with a thickness of 2 nm), the brightness maintenance rate of an LD comprising a multilayer oxide insulating film MLO_2 (which includes a first insulating film INF1 (ZrO2 insulating film) with a thickness of 3 nm), and the brightness maintenance rate of an LD comprising a multilayer oxide insulating film MLO_3 (which includes a first insulating film INF1 (ZrO2 insulating film) with a thickness of 2.5 nm) can be different. Therefore, by appropriately adjusting the thickness of the first insulating film INF1, the brightness maintenance rate of the LD can be controlled or improved.

[0130] Figure 8 A graph showing the brightness retention rate of the light-emitting element (LD) relative to the thickness of the second insulating film INF2. For example, Figure 8 The brightness maintenance rate of a light-emitting element LD comprising a multilayer oxide insulating film MLO_1b, which includes a first insulating film INF1 containing ZrO2 and having a thickness of 2 nm, a second insulating film INF2 containing Al2O3 and having a thickness of 1 nm, and a third insulating film INF3 containing ZrO2 and having a thickness of 1 nm, is shown. The brightness maintenance rate of a light-emitting element LD comprising a multilayer oxide insulating film MLO_4 (in which the thickness of the second insulating film INF2 is changed) is also shown.

[0131] Apart from Figure 1 to Figure 5 In addition to referencing Figure 8The luminance maintenance rate of the light emitting element LD can vary depending on the thickness of the second insulating film INF2. For example, the luminance maintenance rate of the light emitting element LD including the multilayer oxide insulating film MLO Ib including the second insulating film INF2 (Al203 insulating film) having a thickness of 1 nm and the luminance maintenance rate of the light emitting element LD including the multilayer oxide insulating film MLO 4 including the second insulating film INF2 (Al203 insulating film) having a thickness of 2 nm can be different. Therefore, by appropriately adjusting the thickness of the second insulating film INF2, the luminance maintenance rate of the light emitting element LD can be controlled or improved.

[0132] Figure 9 A graph showing the luminance maintenance rate of the light emitting element LD with respect to the thickness of the third insulating film INF3 is shown. Figure 9 The luminance maintenance rate of the light emitting element LD including the multilayer oxide insulating film MLO Ic including the first insulating film INF1 containing Zr02 and having a thickness of 2 nm, the second insulating film INF2 containing Al203 and having a thickness of 1 nm, and the third insulating film INF3 containing Zr02 and having a thickness of 1 nm, and the luminance maintenance rate of the light emitting element LD including the multilayer oxide insulating film MLO 5 in which the thickness of the third insulating film INF3 is changed are shown.

[0133] In addition to Figure 1 to Figure 5 Reference is also made to Figure 9 The luminance maintenance rate of the light emitting element LD can vary depending on the thickness of the third insulating film INF3. For example, the luminance maintenance rate of the light emitting element LD including the multilayer oxide insulating film MLO Ic including the third insulating film INF3 (Zr02 insulating film) having a thickness of 1 nm and the luminance maintenance rate of the light emitting element LD including the multilayer oxide insulating film MLO 5 including the third insulating film INF3 (Zr02 insulating film) having a thickness of 2 nm can be different. Therefore, by appropriately adjusting the thickness of the third insulating film INF3, the luminance maintenance rate of the light emitting element LD can be controlled or improved.

[0134] As described above, the light emitting element LD can exhibit different characteristics (e.g., different luminance maintenance rates) depending on the thickness of the first insulating film INF1, the thickness of the second insulating film INF2, and the thickness of the third insulating film INF3. Therefore, the thickness of the first insulating film INF1, the thickness of the second insulating film INF2, and the thickness of the third insulating film INF3 can be appropriately adjusted in consideration of the characteristics exhibited by the light emitting element LD.

[0135] In Figure 7 to Figure 9In the present embodiment, the light emitting element LD used in each experiment for confirming the luminance maintenance rate of the light emitting element LD according to the thickness of the first insulating film INF, the thickness of the second insulating film INF2, and the thickness of the third insulating film INF3 can be a different light emitting element LD. For example, even in the case of a light emitting element LD including the multilayer oxide insulating film MLO_1a, MLO_1b, MLO_1c having the same thickness condition, depending on the difference in the characteristics of the light emitting element LD, the experimental values can be different.

[0136] Figure 10 A plan view of a display device DD according to an embodiment. Figure 10 The structure of a display device DD centered on a display panel DP including a display area DA is schematically illustrated. The display device DD can further include a driving circuit (e.g., a scan driver, a data driver, and a timing controller) for driving the pixels PXL.

[0137] Reference Figure 10 The display device DD can include a base layer BSL and pixels PXL located on the base layer BSL. The base layer BSL and the display device DD including the base layer BSL can be provided in various shapes. For example, the base layer BSL and the display device DD can be provided in the form of a plate having a substantially quadrilateral shape in a plan view, and can include portions with angled or rounded corners. The shape of the base layer BSL and the display device DD can vary. For example, the base layer BSL and the display device DD can also have other polygonal shapes such as a hexagonal or octagonal shape in a plan view, or can have a shape including a curved perimeter such as a circular or elliptical shape. In Figure 10 In the present embodiment, the display device DD is illustrated as having a quadrilateral plate shape.

[0138] In Figure 10 In the present embodiment, a first direction DR1, a second direction DR2, and a third direction DR3 are shown. In an embodiment, the first direction DR1 can be a width direction (e.g., a row direction or a horizontal direction) of the display device DD, and the second direction DR2 can be a length direction (e.g., a column direction or a vertical direction) of the display device DD. The third direction DR3 can be a direction intersecting the first direction DR1 and the second direction DR2, and can be, for example, a thickness direction or a height direction of the display device DD.

[0139] The base layer BSL can be a base member for forming the display device DD. For example, the base layer BSL can form a base surface of the display device DD. The base layer BSL and the display device DD including the base layer BSL can include a display area DA and a non-display area NA.

[0140] The display area DA can be the area in which pixels PXL are arranged and the area in which an image is displayed. In an embodiment, the display area DA can be located in the central region of the substrate layer BSL and the display device DD.

[0141] The display area DA can have various shapes. For example, the display area DA can have various shapes, including rectangular, circular, and elliptical. In one embodiment, the display area DA can have a shape corresponding to the shape of the base layer BSL, but the embodiment is not limited to this.

[0142] The non-display area NA can be an area other than the display area DA, and can be located around the display area DA. In an embodiment, the non-display area NA can be located in the edge region of the substrate layer BSL and the display device DD, surrounding the display area DA. The non-display area NA can include the pad area where the pad P is located.

[0143] Pixel PXL may be located within the display area DA. For example, the display area DA may include the pixel region where each pixel PXL is located.

[0144] In this implementation, at least two types of pixels PXL can be arranged in the display area DA to emit light of different colors (or light of different wavelength bands). For example, a first-color pixel PXL1, a second-color pixel PXL2, and a third-color pixel PXL3 can be arranged in the display area DA. At least one first-color pixel PXL1, at least one second-color pixel PXL2, and at least one third-color pixel PXL3 located adjacent to each other can form a pixel group PXG. Each pixel group PXG can emit light of various colors by individually controlling the brightness of the first, second, and third-color pixels PXL1, PXL2, and PXL3.

[0145] exist Figure 10 In one embodiment, a first color pixel PXL1, a second color pixel PXL2, and a third color pixel PXL3 arranged sequentially along the first direction DR1 can constitute a pixel group PXG. However, the number, type, and / or arrangement of pixels PXL constituting each pixel group PXG may vary depending on the embodiment.

[0146] In this implementation, the first color pixel PXL1 can be a red pixel for emitting red light, and the second color pixel PXL2 can be a green pixel for emitting green light. Additionally, the third color pixel PXL3 can be a blue pixel for emitting blue light. The color of the light emitted from each pixel PXL can also be varied.

[0147] In this implementation, each pixel PXL may include at least one light-emitting element (LD). For example, pixel PXL may include elements according to a reference. Figure 1 to Figure 9Light-emitting element LD of at least one of the described implementations. For example, a pixel PXL can include a light-emitting element LD, and the light-emitting element LD can include: a light-emitting stack LES including at least a first semiconductor layer SCL1, an active layer ACT, and a second semiconductor layer SCL2; a multi-layer oxide insulating film MLO including first, second, and third insulating films INF1, INF2, and INF3; and a protective film PRL including at least a fourth insulating film INF4. The number, type, structure, and / or size of the light-emitting element LD provided in each pixel PXL can vary depending on the implementation.

[0148] In an implementation, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 can include a light-emitting element LD of a first color, a light-emitting element LD of a second color, and a light-emitting element LD of a third color, respectively, as their light sources. Accordingly, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 can emit light of a first color, light of a second color, and light of a third color, respectively.

[0149] In another implementation, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 can include light-emitting elements LD that emit light of the same color, and a light conversion layer including wavelength conversion particles (also referred to as “wavelength converters”) such as quantum dots, quantum rods, or phosphors that convert the color and / or wavelength of light can be placed in the emission area of the first color pixel PXL1, the second color pixel PXL2, and / or the third color pixel PXL3. Accordingly, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 can emit light of a first color, light of a second color, and light of a third color, respectively.

[0150] For example, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 can include blue light-emitting elements. In this case, a light conversion layer including wavelength conversion particles of a first color (e.g., quantum dots that convert incident light to red light) can be placed in the emission area of the first color pixel PXL1, and a light conversion layer including wavelength conversion particles of a second color (e.g., quantum dots that convert incident light to green light) can be placed in the emission area of the second color pixel PXL2. Accordingly, the first color pixel PXL1 can emit light of a first color (e.g., red light), and the second color pixel PXL2 can emit light of a second color (e.g., green light).

[0151] The pixel PXL can have a structure according to at least one of the embodiments described below. For example, the pixel PXL can have a structure to which any one of the embodiments described below is applied, or a structure to which a combination of at least two embodiments is applied. However, the structure and type of the pixel PXL are not limited to the embodiments disclosed below.

[0152] In an embodiment, the pixel PXL can be an active pixel. However, the embodiment is not limited to this case. For example, the pixel PXL can also be a passive pixel.

[0153] The wiring and / or built-in circuitry connected to the pixel PXL of the display region DA can be located in the non-display region NA. In addition, the pad P can be located in a portion (for example, a pad region) of the non-display region NA. The pad P can include a signal pad and a power pad to which a driving signal and a power voltage required to drive the pixel PXL are applied.

[0154] Figure 11 is a circuit diagram of the pixel PXL according to an embodiment. Figure 12 is a circuit diagram of the pixel PXL according to an embodiment. For example, Figure 11 and Figure 12 shows a pixel PXL including an emission unit EMU having a different structure.

[0155] Figure 11 and Figure 12 Each of the pixels PXL illustrated in Figure 6 may be any one of the pixels PXL located in the display region DA of

[0156] In addition to Figure 1 to Figure 10 , reference is made to Figure 11 and Figure 12 , the pixel PXL can be connected to a scan line SL (also referred to as a "first scan line"), a data line DL, a first power line PL1, and a second power line PL2. In addition, the pixel PXL can be further connected to at least one other power line and / or signal line. For example, the pixel PXL can be further connected to a sensing line SENL (also referred to as an "initialization power line") and / or a control line SSL (also referred to as a "second scan line").

[0157] The pixel PXL can include an emission unit EMU for generating light of a luminance corresponding to each data signal. In addition, the pixel PXL can further include a pixel circuit PXC for driving the emission unit EMU.

[0158] The pixel circuit PXC can be connected to the scan line SL and the data line DL, and can also be connected between the first power line PL1 and the transmitter unit EMU. For example, the pixel circuit PXC can be electrically connected to the scan line SL that supplies the first scan signal, the data line DL that supplies the data signal, the first power line PL1 that applies the voltage of the first power supply VDD, and the transmitter unit EMU.

[0159] The pixel circuit PXC may optionally be further connected to a control line SSL supplying the second scan signal and a sensing line SENL connected to a reference power supply (or initialization power supply) or sensing circuit in response to a display period or a sensing period. In an embodiment, the second scan signal may be the same as or different from the first scan signal. When the second scan signal is the same as the first scan signal, the control line SSL may be combined with the scan line SL.

[0160] A pixel circuit (PXC) may include at least one transistor M and a capacitor Cst. For example, a pixel circuit (PXC) may include a first transistor M1, a second transistor M2, a third transistor M3, and a capacitor Cst.

[0161] A first transistor M1 may be connected between a first power line PL1 and a second node N2. The second node N2 may be a node connecting the pixel circuit PXC and the emitter unit EMU. For example, the second node N2 may be a node where the electrodes of the first transistor M1 (e.g., the source electrode) and the electrodes of the emitter unit EMU (e.g., the first pixel electrode ELT1) are electrically connected to each other. The gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may be a drive transistor that controls the drive current supplied to the emitter unit EMU according to the voltage of the first node N1.

[0162] In one embodiment, the first transistor M1 may further include a bottom metal layer BML (also referred to as a "back gate electrode" or "second gate electrode"). In another embodiment, the bottom metal layer BML may be connected to an electrode (e.g., a source electrode) of the first transistor M1.

[0163] The bottom metal layer BML may be located on a semiconductor pattern forming the channel of the first transistor M1 (e.g., Figure 14 Below the semiconductor pattern (SCP). In this case, the bottom metal layer BML blocks light from entering the semiconductor pattern, thereby stabilizing the operating characteristics of the first transistor M1.

[0164] The second transistor M2 can be connected between the data line DL and the first node N1. Additionally, the gate electrode of the second transistor M2 can be connected to the scan line SL. When a first scan signal with a gate turn-on voltage (e.g., a logic high voltage or a high-level voltage) is supplied from the scan line SL, the second transistor M2 can be turned on and connected to the data line DL and the first node N1.

[0165] During each frame period of the display period, a data signal of a corresponding frame can be supplied to the data line DL. During a period in which a gate-on voltage of the first scan signal is supplied, the data signal can be transmitted to the first node N1 through the second transistor M2.

[0166] The capacitor Cst can be connected between the first node N1 and the second node N2. The capacitor Cst can be charged with a voltage corresponding to the data signal supplied to the first node N1.

[0167] The third transistor M3 can be connected between the second node N2 and the sensing line SENL. Also, a gate electrode of the third transistor M3 can be connected to the control line SSL (or the scan line SL). When a second scan signal (or a first scan signal) of a gate-on voltage (e.g., a logic high voltage or a high level voltage) is supplied from the control line SSL, the third transistor M3 can be turned on, and can transmit a reference voltage or an initialization voltage supplied to the sensing line SENL to the second node N2, or transmit a voltage of the second node N2 to the sensing line SENL. In an embodiment, the voltage of the second node N2 can be transmitted to a sensing circuit through the sensing line SENL, and can be provided to a driving circuit (e.g., a timing controller), and used to compensate for a difference in characteristics of the pixels PXL.

[0168] Although Figure 11 and Figure 12 all of the transistors M included in the pixel circuit PXC in Embodiments 1 and 2 are N-type transistors, embodiments are not limited to this case. For example, at least one of the first, second, and third transistors M1, M2, and M3 can be changed to a P-type transistor. Also, the structure and driving method of the pixel PXL can vary depending on embodiments.

[0169] The emission unit EMU can include at least one light emitting element LD connected (e.g., forward connected) between the first power source VDD and the second power source VSS. The at least one light emitting element LD can be a light source of the pixel PXL.

[0170] In an embodiment, the emission unit EMU can include a single light emitting element LD forward connected between the first power source VDD and the second power source VSS. In another embodiment, the emission unit EMU can include at least two light emitting elements LD forward connected between the first power source VDD and the second power source VSS.

[0171] In an embodiment, the emission unit EMU can include at least one light emitting element LD connected (e.g., forward connected) between the first power source VDD and the second power source VSS. The at least one light emitting element LD can be a light source of the pixel PXL. Figure 11The light emitting element LD can be connected in series between the pixel circuit PXC and the second power supply line PL2 in an embodiment as such. For example, the light emitting element LD can be arranged and / or connected to at least two series terminals between the pixel circuit PXC and the second power supply line PL2, and each series terminal can include at least one light emitting element LD connected in forward direction between the first power supply VDD and the second power supply VSS. For example, the emission unit EMU can include at least one light emitting element LD connected between the first pixel electrode ELT1 and the third pixel electrode ELT3 (e.g., at least one light emitting element LD connected in forward direction to a first series terminal) and at least one light emitting element LD connected between the third pixel electrode ELT3 and the second pixel electrode ELT2 (e.g., at least one light emitting element LD connected in forward direction to a second series terminal). The third pixel electrode ELT3 can be an intermediate electrode connecting the first series terminal and the second series terminal.

[0172] The type, number, and / or structure of the light emitting element LD constituting the emission unit EMU of the pixel PXL can vary depending on the embodiment. In addition, the arrangement and / or connection structure of the light emitting element LD can vary depending on the embodiment.

[0173] In an embodiment, the emission unit EMU can include at least one light emitting element LD connected in forward direction between the first pixel electrode ELT1 and the third pixel electrode ELT3 and at least one light emitting element LD connected in forward direction between the third pixel electrode ELT3 and the second pixel electrode ELT2. Figure 12 The light emitting element LD can be connected in series and in parallel between the pixel circuit PXC and the second power supply line PL2 in an embodiment as such. For example, the light emitting element LD can be arranged and / or connected to at least two series terminals between the pixel circuit PXC and the second power supply line PL2, and each series terminal can include at least one light emitting element LD connected in forward direction between the first power supply VDD and the second power supply VSS. For example, the emission unit EMU can include at least one light emitting element LD connected between the first pixel electrode ELT1 and the third pixel electrode ELT3 (e.g., at least one light emitting element LD connected in forward direction to a first series terminal) and at least one light emitting element LD connected between the third pixel electrode ELT3 and the second pixel electrode ELT2 (e.g., at least one light emitting element LD connected in forward direction to a second series terminal). The third pixel electrode ELT3 can be an intermediate electrode connecting the first series terminal and the second series terminal.

[0174] The first power supply VDD and the second power supply VSS can have different potentials. For example, the first power supply VDD can be a high-potential pixel power supply, and the second power supply VSS can be a low-potential pixel power supply.

[0175] The light emitting element LD can emit light having a luminance corresponding to a driving current supplied by the pixel circuit PXC. During each frame period of a display period, the pixel circuit PXC can supply the emission unit EMU with a driving current corresponding to a data signal. The light emitting element LD can emit light having a luminance corresponding to the driving current.

[0176] Figure 13 A plan view of a pixel PXL according to an embodiment. For example, Figure 13 The structure of the pixel PXL centered on the emission unit EMU is illustrated, and an embodiment of the emission unit EMU including at least one light emitting element LD connected in forward direction between the first pixel electrode ELT1 and the third pixel electrode ELT3 and at least one light emitting element LD connected in forward direction between the third pixel electrode ELT3 and the second pixel electrode ELT2 is shown. Figure 12The light emitting elements LD connected in series and in parallel with each other as in the embodiment.

[0177] In addition to Figure 1 to Figure 12 reference is made to Figure 13 The pixel PXL can include an emission area EA in which at least one light emitting element LD is disposed. In an embodiment, the emission area EA can include at least two light emitting elements LD and an electrode electrically connected to the light emitting elements LD. In an embodiment, the electrode can include an alignment electrode ALE and a pixel electrode ELT (also referred to as a "contact electrode"). In addition, the pixel PXL can further include a bank pattern BNP located under the alignment electrode ALE.

[0178] The alignment electrodes ALE can have various shapes and can be spaced apart from each other. In an embodiment, the alignment electrodes ALE can be spaced apart from each other along the first direction DR1 and can each have a shape (e.g., a bar shape) extending along the second direction DR2.

[0179] The shape, size, number, position, and / or arrangement of the alignment electrodes ALE can vary depending on the embodiment. In addition, the alignment electrodes ALE can have similar or identical shapes and / or sizes, or can have different shapes and sizes.

[0180] The alignment electrodes ALE can include at least two electrodes spaced apart from each other. For example, the alignment electrodes ALE can include a first alignment electrode ALE1, a second alignment electrode ALE2, and a third alignment electrode ALE3.

[0181] In an embodiment, the first alignment electrode ALE1 can be located at the center of the emission area EA, and the second alignment electrode ALE2 and the third alignment electrode ALE3 can be located on both sides of the first alignment electrode ALE1. For example, the second alignment electrode ALE2 can be located on the right side of the first alignment electrode ALE1, and the third alignment electrode ALE3 can be located on the left side of the first alignment electrode ALE1.

[0182] In the operation of aligning the light emitting elements LD, an alignment signal required to align the light emitting elements LD can be supplied to the alignment electrodes ALE (or an alignment wiring before being separated into the alignment electrodes ALE of each pixel PXL). Accordingly, the light emitting elements LD can be aligned and / or disposed between the alignment electrodes ALE. When the light emitting elements LD are aligned and / or disposed between the alignment electrodes ALE, it can mean that at least a portion of each light emitting element LD is located between the alignment electrodes ALE.

[0183] For example, in the operation of aligning the light emitting element LD, a first alignment signal, a second alignment signal, and a third alignment signal can be supplied to the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 (or a first alignment wiring to which the first alignment electrode ALE1 of the pixel PXL is connected, a second alignment wiring to which the second alignment electrode ALE2 of the pixel PXL is connected, and a third alignment wiring to which the third alignment electrode ALE3 of the pixel PXL is connected), respectively. The first alignment signal and the second alignment signal can have different waveforms, potentials, and / or phases, and the first alignment signal and the third alignment signal can have different waveforms, potentials, and / or phases. The third alignment signal can be the same as or different from the second alignment signal. Accordingly, the light emitting element LD can be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2 and between the first alignment electrode ALE1 and the third alignment electrode ALE3.

[0184] The alignment electrode ALE can be arranged in the emission region EA of each pixel PXL. In an embodiment, the alignment electrode ALE can extend through the non-emission region NEA around the emission region EA to the separation region SPA. The separation region SPA can be a region in which each alignment wiring (e.g., the first alignment wiring, the second alignment wiring, or the third alignment wiring) is separated into the alignment electrode ALE (e.g., the first alignment electrode ALE1, the second alignment electrode ALE2, or the third alignment electrode ALE3) of the pixel PXL after the alignment of the light emitting element LD is completed. The separation region SPA can be located at least one side of each emission region EA.

[0185] For example, each pixel PXL can include at least one separation region SPA (e.g., two separation regions SPA located above and below each emission region EA) located around the emission region EA. A terminal of at least one electrode constituting the emission unit EMU (e.g., a terminal of the alignment electrode ALE) can be located in each separation region SPA.

[0186] In an embodiment, each alignment electrode ALE can have a separate pattern for each pixel PXL. For example, the first, second, and third alignment electrodes ALE1, ALE2, and ALE3 of each pixel PXL can each be a separate separation pattern. However, embodiments are not limited to this example. For example, the alignment electrodes ALE connected to the second power supply line PL2 (e.g., the third alignment electrodes ALE3 of the pixels PXL) can be integrally formed with each other.

[0187] In an embodiment, the first alignment electrode ALE1 can be electrically connected to the pixel circuit PXC (e.g., the pixel circuit PXC of the corresponding pixel PXL) and / or the circuit layer (e.g., the circuit layer of the corresponding pixel PXL) through the first contact portion CNT1. Figure 14The first alignment signal can be supplied to the first alignment electrode ALE1 (or the first alignment wiring) through at least one wiring (e.g., the first power line PL1) located in the circuit layer PCL. In this case, the first alignment signal can be supplied to the first alignment electrode ALE1 (or the first alignment wiring) through at least one wiring located in the circuit layer.

[0188] The first contact portion CNT1 can include at least one contact hole and / or a via. In an embodiment, the first contact portion CNT1 can be located in the non-emission area NEA surrounding each emission area EA, but the location of the first contact portion CNT1 can be changed.

[0189] The second alignment electrode ALE2 can be electrically connected to the second power line PL2 located in the circuit layer PCL through the second contact portion CNT2. In this case, the second alignment signal can be supplied to the second alignment electrode ALE2 (or the second alignment wiring) through the second power line PL2.

[0190] The third alignment electrode ALE3 can be electrically connected to the second power line PL2 located in the circuit layer PCL through the third contact portion CNT3. In this case, the second alignment signal can also be supplied to the third alignment electrode ALE3 (or the third alignment wiring) through the second power line PL2.

[0191] Each of the second contact portion CNT2 and the third contact portion CNT3 can include at least one contact hole and / or a via. In an embodiment, the second contact portion CNT2 and the third contact portion CNT3 can be located in the non-emission area NEA, but the location of the second contact portion CNT2 and the third contact portion CNT3 can be changed.

[0192] The at least one first light emitting element LD1 can be located between the first alignment electrode ALE1 and the second alignment electrode ALE2. For example, a plurality of first light emitting elements LD1 can be arranged between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0193] Each first light emitting element LD1 can or can not overlap the first alignment electrode ALE1 and / or the second alignment electrode ALE2. A first end EP1 of the first light emitting element LD1 can be adjacent to the first alignment electrode ALE1, and a second end EP2 of the first light emitting element LD1 can be adjacent to the second alignment electrode ALE2.

[0194] The first end EP1 of the first light emitting element LD1 can be electrically connected to the first pixel electrode ELT1 (also referred to as a "first electrode"). In an embodiment, the first end EP1 of the first light emitting element LD1 can be electrically connected to the first alignment electrode ALE1 through the first pixel electrode ELT1, and can be electrically connected to the pixel circuit PXC and / or the first power line PL1 through the first alignment electrode ALE1. In another embodiment, the first end EP1 of the first light emitting element LD1 and the first pixel electrode ELT1 can be electrically connected to the pixel circuit PXC and / or the first power line PL1 without passing through the first alignment electrode ALE1.

[0195] The second end EP2 of the first light emitting element LD1 can be electrically connected to the third pixel electrode ELT3 (also referred to as a "third electrode") and / or the second pixel electrode ELT2 (also referred to as a "second electrode"). In an embodiment, the second end EP2 of the first light emitting element LD1 can be electrically connected to the third pixel electrode ELT3. In addition, the second end EP2 of the first light emitting element LD1 can be electrically connected to the second power line PL2 in sequence through the third pixel electrode ELT3, at least one second light emitting element LD2, the second pixel electrode ELT2, and the third alignment electrode ALE3.

[0196] The at least one second light emitting element LD2 can be located between the first alignment electrode ALE1 and the third alignment electrode ALE3. For example, a plurality of second light emitting elements LD2 can be arranged between the first alignment electrode ALE1 and the third alignment electrode ALE3.

[0197] Each of the second light emitting elements LD2 can or can not overlap with the first alignment electrode ALE1 and / or the third alignment electrode ALE3. The first end EP1 of the second light emitting element LD2 can be adjacent to the first alignment electrode ALE1, and the second end EP2 of the second light emitting element LD2 can be adjacent to the third alignment electrode ALE3.

[0198] The first end EP1 of the second light emitting element LD2 can be electrically connected to the third pixel electrode ELT3. The second end EP2 of the second light emitting element LD2 can be electrically connected to the second pixel electrode ELT2. In an embodiment, the second end EP2 of the second light emitting element LD2 can be electrically connected to the third alignment electrode ALE3 through the second pixel electrode ELT2, and can be electrically connected to the second power line PL2 through the third alignment electrode ALE3. In another embodiment, the second end EP2 of the second light emitting element LD2 and the second pixel electrode ELT2 can be electrically connected to the second power line PL2 without passing through the third alignment electrode ALE3.

[0199] For example, each light emitting element LD (e.g., each first light emitting element LD1 or each second light emitting element LD2) can include a first end EP1 electrically connected to the first pixel electrode ELT1 and a second end EP2 electrically connected to the second pixel electrode ELT2. In an embodiment, each light emitting element LD can be a super small (e.g., having a small size in the range of nanometers to micrometers) inorganic light emitting element using a material having an inorganic crystal structure. For example, each light emitting element LD can be an inorganic light emitting element according to reference Figure 1 to Figure 9 The light emitting element LD of at least one of the described embodiments.

[0200] The light emitting element LD can be supplied to each emission area EA by an inkjet method or a slot coating method. The light emitting element LD can be aligned between the alignment electrodes ALE by an alignment signal applied to the alignment electrodes ALE (or alignment wiring), and then can be fixed at the alignment position.

[0201] The first pixel electrode ELT1 can be located on the first end EP1 of the first light emitting element LD1 and can be electrically connected to the first end EP1 of the first light emitting element LD1. For example, the first pixel electrode ELT1 can be directly placed on the first end EP1 of the first light emitting element LD1 to contact the first end EP1 of the first light emitting element LD1.

[0202] In an embodiment, the first pixel electrode ELT1 can overlap the first alignment electrode ALE1 and can be electrically connected to the first alignment electrode ALE1 through the fourth contact portion CNT4. In addition, the first pixel electrode ELT1 can be electrically connected to the pixel circuit PXC and / or the first power supply line PL1 through the first alignment electrode ALE1. In another embodiment, the first pixel electrode ELT1 can be electrically connected to the pixel circuit PXC and / or the first power supply line PL1 without passing through the first alignment electrode ALE1.

[0203] The third pixel electrode ELT3 can be located on the second end EP2 of the first light emitting element LD1 and the first end EP1 of the second light emitting element LD2 and can be electrically connected to the second end EP2 of the first light emitting element LD1 and the first end EP1 of the second light emitting element LD2. For example, the third pixel electrode ELT3 can be directly placed on the second end EP2 of the first light emitting element LD1 and the first end EP1 of the second light emitting element LD2 to contact the second end EP2 of the first light emitting element LD1 and the first end EP1 of the second light emitting element LD2. The third pixel electrode ELT3 can electrically connect the first light emitting element LD1 and the second light emitting element LD2. In an embodiment, the third pixel electrode ELT3 can overlap a portion of each of the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0204] The second pixel electrode ELT2 (also referred to as a "second electrode") can be located on the second end EP2 of the second light emitting element LD2 and can be electrically connected to the second end EP2 of the second light emitting element LD2. For example, the second pixel electrode ELT2 can be directly placed on the second end EP2 of the second light emitting element LD2 to contact the second end EP2 of the second light emitting element LD2.

[0205] In an embodiment, the second pixel electrode ELT2 can overlap the third alignment electrode ALE3 and can be electrically connected to the third alignment electrode ALE3 through the fifth contact part CNT5. In addition, the second pixel electrode ELT2 can be electrically connected to the second power line PL2 through the third alignment electrode ALE3. In another embodiment, the second pixel electrode ELT2 can be electrically connected to the second power line PL2 without passing through the third alignment electrode ALE3.

[0206] The pixel electrodes ELT can be formed to be separated from each other in each emission area EA. In an embodiment, at least one pixel electrode ELT can extend from each emission area EA to the non-emission area NEA and / or the separation area SPA. For example, the first pixel electrode ELT1 and the second pixel electrode ELT2 can extend from each emission area EA to the non-emission area NEA and the separation area SPA and can be electrically connected to the first alignment electrode ALE1 and the third alignment electrode ALE3 in the separation area SPA, respectively. The third pixel electrode ELT3 can be formed only in each emission area EA, or a part of the third pixel electrode ELT3 can be located in the non-emission area NEA. The position, size, shape, and arrangement structure of the pixel electrodes ELT and / or the position of the fourth contact part CNT4 and the fifth contact part CNT5 can vary depending on the embodiment.

[0207] The bank pattern BNP (also referred to as a "pattern" or a "wall pattern") can be located under the alignment electrode ALE to partially overlap the alignment electrode ALE. For example, the bank pattern BNP can include a first bank pattern BNP1, a second bank pattern BNP2, and a third bank pattern BNP3 that partially overlap the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3, respectively.

[0208] Due to the bank pattern BNP, a part of each alignment electrode ALE can protrude toward the upper direction (e.g., the third direction DR3) of the pixel PXL. Accordingly, it can be easy to control the area in which the light emitting element LD is aligned. In addition, because the light emitted from the light emitting element LD at a low angle toward the bank pattern BNP is reflected toward the upper direction of the pixel PXL, the light efficiency of the pixel PXL can be increased.

[0209] In an embodiment, at least two adjacent pixels PXL can share at least one bank pattern BNP. For example, a second bank pattern BNP2 can be integrally formed with a third bank pattern BNP3 of an adjacent pixel PXL (e.g., a right-side adjacent pixel) in the first direction DR1. The third bank pattern BNP2 can be integrally formed with a second bank pattern BNP2 of another adjacent pixel (e.g., a left-side adjacent pixel) in the first direction DR1. The location, structure, number, size, and / or shape of the bank pattern BNP can vary depending on the embodiment.

[0210] A non-emission area NEA can be located around each emission area EA and / or each separation area SPA. The first bank BNK1 can be located in the non-emission area NEA.

[0211] The first bank BNK1 can include a first opening OPA1 corresponding to each emission area EA, and can surround the emission area EA. In an embodiment, the first bank BNK1 can further include a second opening OPA2 corresponding to the separation area SPA, and can surround the separation area SPA. For example, the first bank BNK1 can include an opening OPA corresponding to each emission area EA and each separation area SPA. The first bank BNK1 can define each emission area EA in which the light emitting element LD should be supplied in operation of supplying the light emitting element LD to each pixel PXL.

[0212] In an embodiment, the first bank BNK1 can include a hydrophobic surface. For example, the first bank BNK1 itself can be formed as a hydrophobic pattern using a hydrophobic material, or a hydrophobic film containing a hydrophobic material can be formed on the first bank BNK1. For example, the first bank BNK1 can be formed using a hydrophobic organic insulating material (such as a polyacrylate) having a large contact angle. Accordingly, the light emitting element LD can be smoothly supplied to the emission area EA.

[0213] Figure 14 is a cross-sectional view of a display device DD according to an embodiment. For example, Figure 14 is a cross-sectional view of a portion of a display device DD, showing a cross-section of a pixel PXL corresponding to line II-II’ of Figure 13

[0214] In addition to Figure 1 to Figure 13 reference is made to Figure 14 , the display device DD can include a base layer BSL, a circuit layer PCL, and a display layer DPL. The circuit layer PCL and the display layer DPL can be provided on the base layer BSL to overlap each other. For example, the circuit layer PCL and the display layer DPL can be arranged in sequence on a surface of the base layer BSL.

[0215] ​The display device DD can further include a color filter layer CFL and / or an encapsulation layer ENC (or a protective layer) on the display layer DPL. In an embodiment, the color filter layer CFL and / or the encapsulation layer ENC can be directly formed on a surface of the base layer BSL on which the circuit layer PCL and the display layer DPL are formed, but embodiments are not limited to this case.

[0216] The base layer BSL can be a substrate or a film containing a rigid material or a flexible material. In an embodiment, the base layer BSL can be an insulating substrate, and can have a single layer structure or a multi-layer structure.

[0217] The circuit layer PCL can be provided on a surface of the base layer BSL. The circuit layer PCL can include circuit elements constituting a pixel circuit PXC of each pixel PXL. For example, a plurality of circuit elements (e.g., a transistor M and a capacitor Cst constituting each pixel circuit PXC) can be formed in each pixel region of the circuit layer PCL.

[0218] In the Figure 14 In the

[0219] The circuit layer PCL can further include signal lines and power lines connected to the pixels PXL. For example, the circuit layer PCL can include scan lines SL, control lines SSL, data lines DL, sensing lines SENL, and / or first and second power lines PL1 and PL2 connected to the pixels PXL. In Figure 14 In the

[0220] The circuit layer PCL can further include an insulating layer. For example, the circuit layer PCL can include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and / or a passivation layer PSV arranged in order on a surface of the base layer BSL.

[0221] The circuit layer PCL can include a first conductive layer of a bottom metal layer BML including the first transistor M1 on the base layer BSL. For example, the first conductive layer can be located between the base layer BSL and the buffer layer BFL, and can include the bottom metal layer BML of the first transistor M1 provided in each pixel circuit PXC. The bottom metal layer BML of the first transistor M1 can overlap the semiconductor pattern SCP of the first transistor M1.

[0222] The first conductive layer can further include at least one wiring line LI (or a portion of at least one wiring line LI). For example, the first conductive layer can include at least some wiring lines LI extending in the second direction DR2 in the display region DA.

[0223] The buffer layer BFL can be located on a surface of the base layer BSL including the first conductive layer. The buffer layer BFL can prevent impurities from diffusing into each circuit element.

[0224] The semiconductor layer can be located on the buffer layer BFL. The semiconductor layer can include a semiconductor pattern SCP of each transistor M. The semiconductor pattern SCP can include a channel region overlapping the gate electrode GE of the corresponding transistor M and first and second conductive regions (e.g., source and drain regions) located on both sides of the channel region. The semiconductor pattern SCP can be a semiconductor pattern containing polysilicon, amorphous silicon, or an oxide semiconductor.

[0225] The gate insulating layer GI can be located on the semiconductor layer. The second conductive layer can be located on the gate insulating layer GI.

[0226] The second conductive layer can include the gate electrode GE of each transistor M. In addition, the second conductive layer can further include one electrode of the capacitor Cst provided in the pixel circuit PXC and / or a bridge pattern. In addition, when at least one power line and / or signal line located in the display region DA is configured as a plurality of layers, the second conductive layer can further include at least one wiring line (or a portion of at least one wiring line).

[0227] The interlayer insulating layer ILD can be located on the second conductive layer. The third conductive layer can be located on the interlayer insulating layer ILD.

[0228] The third conductive layer can include the source electrode SE and the drain electrode DE of each transistor M. The source electrode SE can be connected to a region (e.g., a source region) of the semiconductor pattern SCP included in the corresponding transistor M through at least one contact hole CH, and the drain electrode DE can be connected to another region (e.g., a drain region) of the semiconductor pattern SCP included in the corresponding transistor M through at least one other contact hole CH. In another embodiment, the source electrode SE and / or the drain electrode DE of at least one transistor M can not be located in the third conductive layer, but can be implemented as a source region and / or a drain region of the semiconductor pattern SCP.

[0229] In an embodiment, the third conductive layer can further include the other electrode of the capacitor Cst provided in the pixel circuit PXC, at least one wiring line, and / or a bridge pattern. For example, the third conductive layer can include at least some wiring lines extending in the first direction DR1 in the display region DA.

[0230] Each of the electrodes, conductive patterns (e.g., bridge patterns), and / or wirings constituting the first to third conductive layers can have conductivity by containing a conductive material, and a material thereof is not particularly limited. For example, each of the electrodes, conductive patterns, and / or wirings constituting the first to third conductive layers can contain one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), or can include other conductive materials.

[0231] A passivation layer PSV can be located on the third conductive layer. Each of the buffer layer BFL, the gate insulating layer GI, the interlayer insulating layer ILD, and the passivation layer PSV can be a single layer or multiple layers, and can contain an inorganic insulating material and / or an organic insulating material. In an embodiment, each of the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD can contain silicon nitride, silicon oxide, silicon oxynitride, or other inorganic insulating materials. In an embodiment, the passivation layer PSV can include at least one organic insulating layer containing an organic insulating material. In an embodiment, the passivation layer PSV can planarize a surface of the circuit layer PCL.

[0232] A display layer DPL can be located on the passivation layer PSV.

[0233] The display layer DPL can include an emission unit EMU of each pixel PXL. For example, the display layer DPL can include an alignment electrode ALE, at least one light emitting element LD, and a pixel electrode ELT located in an emission area EA of each pixel PXL. In an embodiment, each emission unit EMU can include a plurality of light emitting elements LD.

[0234] The display layer DPL can further include an insulating pattern and / or an insulating layer arranged in sequence on a surface of the base layer BSL on which the circuit layer PCL is formed. For example, the display layer DPL can include a bank pattern BNP, a first insulating layer INS1, a first bank BNK1, a second insulating layer INS2, a third insulating layer INS3, a second bank BNK2, a fourth insulating layer INS4, a fifth insulating layer INS5, and / or a sixth insulating layer INS6. The display layer DPL can optionally further include a color conversion layer CCL.

[0235] The bank pattern BNP can be located on the passivation layer PSV. The bank pattern BNP can be located under the alignment electrode ALE to overlap a portion of each alignment electrode ALE.

[0236] Due to the bank pattern BNP, the alignment electrode ALE can protrude around the light emitting element LD toward an upper direction (e.g., the third direction DR3) of the pixel PXL. The bank pattern BNP and the alignment electrode ALE on the bank pattern BNP can form a reflection protruding pattern around the light emitting element LD. Accordingly, light efficiency of the pixel PXL can be improved.

[0237] The bank pattern BNP can be a single-layered insulating pattern or a multi-layered insulating pattern containing an inorganic insulating material and / or an organic insulating material. The alignment electrode ALE can be located on the bank pattern BNP.

[0238] The alignment electrode ALE can contain an electrically conductive material. For example, each alignment electrode ALE can contain at least one electrically conductive material selected from at least one of various metal materials (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), and copper (Cu)), alloys thereof; electrically conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), or fluorine-doped tin oxide (FTO)); and electrically conductive polymers (such as PEDOT), or other electrically conductive materials. The alignment electrode ALE can contain the same or different electrically conductive materials.

[0239] Each alignment electrode ALE can be single-layered or multi-layered. In an embodiment, each alignment electrode ALE can include a reflection electrode layer containing a reflection electrically conductive material (e.g., a metal).

[0240] The first insulating layer INS1 can be located on the alignment electrode ALE. In an embodiment, the first insulating layer INS1 can include a contact hole for connecting at least one of the alignment electrodes ALE to any one of the pixel electrodes ELT. For example, the first insulating layer INS1 can include contact holes for forming the fourth contact portion CNT4 and the fifth contact portion CNT5 of the fourth pixel electrode ELT4 and the fifth pixel electrode ELT5. Figure 13 In another embodiment, the first insulating layer INS1 can be more widely opened in the emission area EA to expose at least one of the alignment electrodes ALE, and each pixel electrode ELT can be directly located on each exposed alignment electrode ALE.

[0241] The first insulating layer INS1 can be single-layered or multi-layered. The first insulating layer INS1 can contain silicon nitride, silicon oxide, silicon oxynitride, or other insulating materials.

[0242] The first bank BNK1 can be located in a display area DA in which the alignment electrodes ALE and the first insulating layer INS1 are formed. The first bank BNK1 can be located in a non-emission area NEA to surround the emission area EA of each pixel PXL.

[0243] The light emitting elements LD can be placed in each emission area EA surrounded by the first bank BNK1. The light emitting elements LD can be aligned between the alignment electrodes ALE. For example, at least one first light emitting element LD1 can be aligned or arranged between the first alignment electrode ALE1 and the second alignment electrode ALE2, and at least one second light emitting element LD2 can be aligned or arranged between the first alignment electrode ALE1 and the third alignment electrode ALE3.

[0244] The second insulating layer INS2 can be located on a portion of each light emitting element LD. In an embodiment, the second insulating layer INS2 can be located locally on a portion including a central portion of each light emitting element LD, thereby exposing the first end EP1 and the second end EP2 of each light emitting element LD. In another embodiment, the second insulating layer INS2 can be formed throughout the entire display area DA including a plurality of pixel areas, and can include contact holes exposing the first end EP1 and the second end EP2 of the light emitting element LD. The light emitting element LD can be stably fixed by the second insulating layer INS2.

[0245] The second insulating layer INS2 can be a single layer or a plurality of layers. The second insulating layer INS2 can contain silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, a photoresist material, or other insulating materials.

[0246] Different pixel electrodes ELT can be placed and / or formed on the first end EP1 and the second end EP2 of the light emitting element LD. For example, a first pixel electrode ELT1 can be placed on the first end EP1 of the first light emitting element LD1, and a portion of a third pixel electrode ELT3 can be placed on the second end EP2 of the first light emitting element LD1. Another portion of the third pixel electrode ELT3 can be placed on the first end EP1 of the second light emitting element LD2, and a second pixel electrode ELT2 can be placed on the second end EP2 of the second light emitting element LD2.

[0247] In an embodiment, the first pixel electrode ELT1 can be electrically connected to the first alignment electrode ALE1 through at least one contact portion (e.g., a fourth contact portion CNT4 of Figure 13 The second pixel electrode ELT2 can be electrically connected to the third alignment electrode ALE3 through at least one contact portion (e.g., a fifth contact portion CNT5 of Figure 13 The third pixel electrode ELT3 can electrically connect the at least one first light emitting element LD1 and the at least one second light emitting element LD2 to each other.

[0248] In an embodiment, the first alignment electrode ALE1 of each pixel PXL can be electrically connected to the first transistor M1 of the respective pixel PXL through at least one contact portion (e.g., a first contact portion CNT1 of the first alignment electrode ALE1). Figure 13 Similarly, each of the second and third alignment electrodes ALE2, ALE3 can be electrically connected to the second power line PL2 through at least one contact portion (e.g., a second contact portion CNT2 or a third contact portion CNT3 of the second or third alignment electrode ALE2, ALE3). Figure 13

[0249] The first pixel electrode ELT1 can overlap with a portion of the first alignment electrode ALE1, and the second pixel electrode ELT2 can overlap with a portion of the third alignment electrode ALE3. The third pixel electrode ELT3 can overlap with another portion of the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0250] The first pixel electrode ELT1 can be electrically connected to the first end EP1 of the first light emitting element LD1, and the second pixel electrode ELT2 can be electrically connected to the second end EP2 of the second light emitting element LD2. The third pixel electrode ELT3 can be electrically connected to the second end EP2 of the first light emitting element LD1 and the first end EP1 of the second light emitting element LD2.

[0251] In an embodiment, as shown in FIG. 1A, the first pixel electrode ELT1, the second pixel electrode ELT2, and the third pixel electrode ELT3 can be located in the same layer. In another embodiment, some of the pixel electrodes ELT (e.g., the first pixel electrode ELT1 and the second pixel electrode ELT2) and the rest can be located in different layers. In this case, an insulating layer can be disposed between the pixel electrodes ELT located in different layers. Figure 14

[0252] In the case where each pixel PXL includes an emission unit EMU having a parallel structure as in the embodiment of FIG. 1A, or when each pixel PXL includes a single light emitting element LD, the pixel PXL can not include the third pixel electrode ELT3. In this case, the first pixel electrode ELT1 can be placed on the first end EP1 of the light emitting element LD, and the second pixel electrode ELT2 can be placed on the second end EP2 of the light emitting element LD. Figure 11

[0253] The pixel electrode ELT can contain at least one electrically conductive material. In an embodiment, the pixel electrode ELT can contain a transparent electrically conductive material to transmit light emitted from the light emitting element LD.

[0254] ​​​The third insulating layer INS3 can be located on the pixel electrode ELT. The third insulating layer INS3 can be a single layer or multiple layers. The third insulating layer INS3 can contain silicon nitride, silicon oxide, silicon oxynitride, or other insulating materials.

[0255] In an embodiment, the display device DD can include a light conversion layer CCL located on the emission unit EMU of each pixel PXL. For example, the light conversion layer CCL can be provided in each emission area EA to be located over the light emitting element LD of each pixel PXL.

[0256] The display device DD can further include a second bank BNK2 located in the non-emission area NEA to overlap the first bank BNK1. The second bank BNK2 can define (or delimit) each emission area EA in which the light conversion layer CCL is to be formed. The second bank BNK2 can also be integral with the first bank BNK1.

[0257] The second bank BNK2 can contain a light-blocking material and / or a reflective material, such as a black matrix material. The second bank BNK2 can contain the same or different materials as the first bank BNK1.

[0258] The light conversion layer CCL can include at least one of wavelength conversion particles (or color conversion particles) for converting the color and / or wavelength of light emitted from the light emitting element LD and light scattering particles SCT for scattering light emitted from the light emitting element LD to increase the light output efficiency of the pixel PXL. For example, each light conversion layer CCL can be located on each emission unit EMU. Each light conversion layer CCL can include wavelength conversion particles, such as at least one type of wavelength conversion particles WS for converting incident light into a specific color of light (e.g., quantum dots corresponding to red, green, and / or blue) and / or light scattering particles SCT. The wavelength conversion particles WS and / or the light scattering particles SCT can be dispersed within a base resin BS of the light conversion layer CCL.

[0259] For example, when any one pixel PXL is set as a red (or green) pixel and a blue light emitting element LD is provided in the emission unit EMU of the pixel PXL, a light conversion layer CCL including red (or green) wavelength conversion particles WS for converting blue light into red (or green) light can be placed on the emission unit EMU of the pixel PXL. In addition, the light conversion layer CCL can further include light scattering particles SCT. In an embodiment, when any one pixel PXL is set as a blue pixel and a blue light emitting element LD is provided in the emission unit EMU of the pixel PXL, a light conversion layer CCL including light scattering particles SCT can be placed on the emission unit EMU of the pixel PXL.

[0260] At least one of the fourth, fifth, and sixth insulating layers INS4, INS5, and INS6 can be formed on a surface of the base layer BSL including the emission unit EMU and / or the light conversion layer CCL of the pixel PXL.

[0261] The fourth insulating layer INS4 can cover the emission unit EMU and / or the light conversion layer CCL to protect the emission unit EMU and / or the light conversion layer CCL of the pixel PXL. The fourth insulating layer INS4 can be a single layer or multiple layers. The fourth insulating layer INS4 can contain silicon nitride, silicon oxide, silicon oxynitride, or other insulating materials.

[0262] The fifth insulating layer INS5 can be located on the fourth insulating layer INS4. In an embodiment, the fifth insulating layer INS5 can be an overcoat layer including at least one organic insulating layer. The fifth insulating layer INS5 can substantially planarize a surface of the display layer DPL.

[0263] The sixth insulating layer INS6 can be located on the fifth insulating layer INS5. The sixth insulating layer INS6 can be a cap layer containing silicon nitride, silicon oxide, silicon oxynitride, or other insulating materials.

[0264] The color filter layer CFL can be located on the display layer DPL.

[0265] The color filter layer CFL can include color filters CF corresponding to colors of the pixels PXL. For example, the color filter layer CFL can include a first color filter CF1 located in the emission area EA of the first color pixel PXL1, a second color filter CF2 located in the emission area EA of the second color pixel PXL2, and a third color filter CF3 located in the emission area EA of the third color pixel PXL3. Each color filter CF can be provided on the sixth insulating layer INS6 to overlap with the emission unit EMU of the corresponding pixel PXL.

[0266] The first color filter CF1 can selectively transmit light of the first color. The second color filter CF2 can selectively transmit light of the second color. The third color filter CF3 can selectively transmit light of the third color.

[0267] In an embodiment, the first, second, and third color filters CF1, CF2, and CF3 can overlap with each other in the non-emission area NEA and can function as a light blocking pattern. In another embodiment, the first, second, and third color filters CF1, CF2, and CF3 can be formed separately from each other above the emission area EA of each pixel PXL, and separate light blocking patterns can be placed between the first, second, and third color filters CF1, CF2, and CF3.

[0268] The encapsulation layer ENC can be located on the color filter layer CFL. The encapsulation layer ENC can include a seventh insulating layer INS7.

[0269] The seventh insulating layer INS7 can be a single layer or multiple layers. In an embodiment, the seventh insulating layer INS7 can include at least one inorganic film to prevent penetration of oxygen or moisture. In an embodiment, the seventh insulating layer INS7 can include at least one organic film to planarize a surface of the display device DD.

[0270] Figure 15 is an enlarged view of a region of the pixel PXL illustrated in Figure 14 For example, Figure 15 is an enlarged sectional view of a region AR1 of the pixel PXL illustrated in Figure 14 In an embodiment, the light emitting elements LD included in the pixel PXL can be substantially the same or similar type and / or structure of light emitting elements LD. For example, the second light emitting element LD2 can be a light emitting element LD of the same type and / or structure as the first light emitting element LD1.

[0271] Figure 16 is an enlarged view of a region of the light emitting element LD illustrated in Figure 15 For example, Figure 16 shows a region AR2 of the light emitting element LD illustrated in Figure 15 wherein Figure 14 and Figure 15 the pixel PXL of Figure 3 includes the light emitting element LD of

[0272] Figure 17 is an enlarged view of a region of the light emitting element LD illustrated in Figure 15 For example, Figure 17 shows a region AR2 of the light emitting element LD illustrated in Figure 15 wherein Figure 14 and Figure 15 the pixel PXL of Figure 4 includes the light emitting element LD of

[0273] In addition to Figure 1 to Figure 14 with reference to Figure 15 to Figure 17 , the pixel PXL of the display device DD can include at least two pixel electrodes ELT spaced apart from each other and at least one light emitting element LD electrically connected between the pixel electrodes ELT. Each light emitting element LD can include a first semiconductor layer SCL1, an active layer ACT, and a second semiconductor layer SCL2 arranged in sequence along one direction, and can optionally further include an electrode layer ETL. Each light emitting element LD can further include a multi-layer oxide insulating film MLO and a protective film PRL surrounding at least an outer peripheral surface of the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2.

[0274] The multilayer oxide insulating film MLO can include a first insulating film INF1 surrounding at least an outer periphery surface of the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2, a second insulating film INF2 surrounding the first insulating film INF1, and a third insulating film INF3 surrounding the second insulating film INF2. The first insulating film INF1 can contain M1 x O y oxide (e.g., M1O2-type oxide). The second insulating film INF2 can contain M2 2x O (2y-1) oxide (e.g., M22O3-type oxide). The third insulating film INF3 can contain M3 x O y oxide (e.g., M3O2-type oxide).

[0275] The protective film PRL can include at least one of a fourth insulating film INF4 and a fifth insulating film INF5 surrounding the third insulating film INF3. For example, the protective film PRL can include only the fourth insulating film INF4 as illustrated in Figure 16 , or can include the fourth insulating film INF4 and the fifth insulating film INF5 as illustrated in Figure 17 . The protective film PRL can also be three or more multilayer films further including one or more insulating films.

[0276] As described above, the light-emitting element LD according to the embodiment can include a first insulating film INF1 containing M1 x O y oxide, a second insulating film INF2 containing M2 2x O (2y-1) oxide, and a third insulating film INF3 containing M3 x O y oxide. Oxygen vacancies V O may be formed at interfaces of the first, second, and third insulating films INF1, INF2, and INF3.

[0277] According to the embodiment, the oxygen vacancies V O formed at the interfaces of the first, second, and third insulating films INF1, INF2, and INF3 can block or reduce the inflow of oxygen into the light-emitting stack LES. Accordingly, the deterioration characteristics of the light-emitting element LD can be improved, and the reliability of the light-emitting element LD can be increased.

[0278] The display device DD according to the embodiment can include a pixel PXL including the light-emitting element LD. Accordingly, the deterioration characteristics of the display device DD can be improved, and the reliability of the display device DD can be increased.

[0279] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the disclosure as defined by the claims. The embodiments are to be considered in all respects as illustrative and not restrictive.

Claims

1. A light-emitting element, comprising: A first semiconductor layer, an active layer, and a second semiconductor layer are arranged sequentially in one direction; A first insulating film surrounds the outer peripheral surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer and contains M1. x O y Type oxides; A second insulating film surrounds the first insulating film and contains M2. 2x O (2y-1) Type oxides; A third insulating film surrounds the second insulating film and contains M3. x O y Type oxides; and A fourth insulating film surrounds the third insulating film. M1, M2, and M3 are each metallic materials, and x and y are each natural numbers.

2. The light-emitting element according to claim 1, wherein the sum of the thickness of the first insulating film, the thickness of the second insulating film, and the thickness of the third insulating film is 10 nm or less.

3. The light-emitting element according to claim 2, wherein the fourth insulating film has a thickness greater than the sum of the thickness of the first insulating film, the thickness of the second insulating film, and the thickness of the third insulating film.

4. The light-emitting element according to claim 1, wherein the thickness of the first insulating film is greater than the thickness of the second insulating film.

5. The light-emitting element according to claim 4, wherein the thickness of the third insulating film is equal to or greater than the thickness of the second insulating film.

6. The light-emitting element according to claim 1, wherein the first insulating film contains M1O2 type oxide, the second insulating film contains M22O3 type oxide, and the third insulating film contains M3O2 type oxide.

7. The light-emitting element according to claim 6, wherein the first insulating film contains at least one of SiO2, ZrO2, HfO2, GeO2, TiO2 and TeO2, and the second insulating film contains at least one of Al2O3, Y2O3, La2O3, Ce2O3, Lu2O3, Sc2O3 and Yb2O3.

8. The light-emitting element according to claim 7, wherein the third insulating film contains at least one of SiO2, ZrO2, HfO2, GeO2, TiO2 and TeO2.

9. The light-emitting element according to claim 8, wherein the first insulating film contains ZrO2, the second insulating film contains Al2O3, and the third insulating film contains ZrO2.

10. The light-emitting element according to claim 1, further comprising: A fifth insulating film surrounds the fourth insulating film and has a thickness greater than that of the fourth insulating film.

11. The light-emitting element according to claim 10, wherein the fourth insulating film is an inorganic film containing oxides, and the fifth insulating film is an inorganic film containing oxides of a material different from that of the fourth insulating film.

12. A light-emitting element, comprising: A first semiconductor layer, an active layer, and a second semiconductor layer are arranged sequentially in one direction; A first insulating film surrounds the outer peripheral surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer and contains M1. x O y Type oxides; A second insulating film surrounds the first insulating film and contains M2. 2x O (2y-1) Type oxides; A third insulating film surrounds the second insulating film and contains M3. x O y Type oxide, Where M1, M2, and M3 are each metallic materials, x and y are each natural numbers, the thickness of the first insulating film is greater than the thickness of the second insulating film, and the thickness of the third insulating film is equal to or greater than the thickness of the second insulating film.

13. The light-emitting element according to claim 12, wherein the sum of the thickness of the first insulating film, the thickness of the second insulating film, and the thickness of the third insulating film is 10 nm or less.

14. The light-emitting element according to claim 12, wherein the first insulating film contains an M1O2 type oxide, the second insulating film contains an M22O3 type oxide, and the third insulating film contains an M3O2 type oxide.

15. The light-emitting element according to claim 14, wherein the first insulating film contains at least one of SiO2, ZrO2, HfO2, GeO2, TiO2 and TeO2, and the second insulating film contains at least one of Al2O3, Y2O3, La2O3, Ce2O3, Lu2O3, Sc2O3 and Yb2O3.

16. The light-emitting element according to claim 15, wherein the third insulating film contains at least one of SiO2, ZrO2, HfO2, GeO2, TiO2 and TeO2.

17. The light-emitting element according to claim 16, wherein the first insulating film contains ZrO2, the second insulating film contains Al2O3, and the third insulating film contains ZrO2.

18. The light-emitting element of claim 12, further comprising a fourth insulating film surrounding the third insulating film and having a thickness greater than the sum of the thickness of the first insulating film, the thickness of the second insulating film, and the thickness of the third insulating film.

19. The light-emitting element according to claim 18, further comprising: A fifth insulating film surrounds the fourth insulating film and has a thickness greater than that of the fourth insulating film.

20. A display device comprising pixels, the pixels comprising: The first and second electrodes are spaced apart from each other; and a light-emitting element electrically connected between the first electrode and the second electrode, wherein the light-emitting element includes: A first semiconductor layer, an active layer, and a second semiconductor layer are arranged sequentially in one direction; A first insulating film surrounds the outer peripheral surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer and contains M1. x O y Type oxides; A second insulating film surrounds the first insulating film and contains M2. 2x O (2y-1) Type oxides; A third insulating film surrounds the second insulating film and contains M3. x O y Type oxides; and A fourth insulating film surrounds the third insulating film. M1 and M2 are both metallic materials, and x and y are both natural numbers.

21. The display device according to claim 20, wherein the sum of the thickness of the first insulating film, the thickness of the second insulating film, and the thickness of the third insulating film is 10 nm or less.

22. The display device of claim 21, wherein the fourth insulating film has a thickness greater than the sum of the thickness of the first insulating film, the thickness of the second insulating film, and the thickness of the third insulating film.

23. The display device of claim 20, wherein the thickness of the first insulating film is greater than the thickness of the second insulating film, and the thickness of the third insulating film is equal to or greater than the thickness of the second insulating film.

24. The display device according to claim 20, wherein the first insulating film contains an M1O2 type oxide, the second insulating film contains an M22O3 type oxide, and the third insulating film contains an M3O2 type oxide.

25. The display device according to claim 24, wherein the first insulating film contains at least one of SiO2, ZrO2, HfO2, GeO2, TiO2 and TeO2, and the second insulating film contains at least one of Al2O3, Y2O3, La2O3, Ce2O3, Lu2O3, Sc2O3 and Yb2O3.

26. The display device according to claim 25, wherein the third insulating film contains at least one of SiO2, ZrO2, HfO2, GeO2, TiO2 and TeO2.

27. The display device according to claim 26, wherein the first insulating film contains ZrO2, the second insulating film contains Al2O3, and the third insulating film contains ZrO2.

28. The display device according to claim 20, further comprising: A fifth insulating film surrounds the fourth insulating film and has a thickness greater than that of the fourth insulating film.

29. The display device according to claim 28, wherein the fourth insulating film is an inorganic film containing oxides, and the fifth insulating film is an inorganic film containing oxides of a material different from that of the fourth insulating film.

30. The display device of claim 20, wherein the pixel further comprises a first alignment electrode and a second alignment electrode located below the light-emitting element and spaced apart from each other.

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