Vibration acceleration test system based on ARM and FPGA dual-core architecture

Abstract

The invention discloses a vibration acceleration test system based on an ARM (Advanced RISC Machines) and FPGA (Field Programmable Gate Array) dual-core architecture, which comprises an acceleration sensor, a signal conditioning module, an analog-to-digital conversion module, an FPGA control core, an ARM control core, a power management module, a clock management module, an SDRAM (Synchronous Dynamic Random Access Memory) storage unit and a communication interface. The advantages of the ARM in the aspects of real-time logic control and the advantages of the FPGA in the aspects of parallel signal processing and the like are fully exerted, synchronous sampling of 16-bit resolution, 200kHz sampling rate and 8-channel vibration acceleration signals is realized, the FIR filter adopts a time division multiplexing mechanism to perform filtering processing on sampling signals of each channel, occupation of hardware resources is effectively reduced, and the signal-to-noise ratio of test data is improved. The functional requirements of logic control, signal acquisition, data processing and the like are met, and meanwhile, the design elements of low cost, portability, expandability and the like are also considered.

Description

TECHNICAL FIELD

[0001] The application relates to a vibration acceleration test system based on an ARM and FPGA dual-core architecture and belongs to the technical field of vibration acceleration test. BACKGROUND

[0002] Vibration state monitoring refers to a process of converting a vibration signal into an electric signal through a sensor, and with the aid of data analysis and signal processing technology, precise perception of equipment operation faults, structural health conditions and environmental safety situations can be achieved, and the vibration state monitoring has become a core monitoring technology in the fields of machinery, transportation and energy. As the most important parameter for representing the vibration state of an object, vibration acceleration has been widely concerned in the fields of experimental research on explosion mechanics, structural health monitoring of buildings and mechanical equipment fault diagnosis, and accurate and reliable acceleration measurement data are of important application value for carrying out the above research.

[0003] At present, commonly used data acquisition systems are mainly divided into two categories: one is a data acquisition system based on GPIB, PCI, PXI and other parallel bus technologies, which has the advantages of high sampling rate, fast data transmission and high integration degree, and is suitable for large-scale high-speed data acquisition application scenarios, but also has the disadvantages of high development cost and low deployment flexibility; the other is a data acquisition system based on DSP, ARM and FPGA embedded platforms, which has the advantages of low development cost, strong expansibility and high deployment flexibility, and is suitable for distributed industrial field data acquisition, but the acquisition device based on a single embedded platform is difficult to meet the requirements of high-speed and high-precision data acquisition and control due to limited hardware resources. SUMMARY

[0004] The technical problem to be solved by the application is to overcome the defects of the prior art and provide a vibration acceleration test system based on an ARM and FPGA dual-core architecture. The ARM control core is good at logical control and task management, and the FPGA control core focuses on high-speed data acquisition and parallel signal processing. Through heterogeneous collaborative design, the functional requirements of the test system in terms of sampling rate, clock synchronization, signal processing and data transmission are met, and design elements such as low cost, portability and expandability are also considered, thereby providing a high-performance solution for vibration acceleration measurement in the fields of explosion mechanics experiment, structural health monitoring and mechanical fault diagnosis.

[0005] Preferably, the application provides a vibration acceleration test system based on an ARM and FPGA dual-core architecture, which comprises an acceleration sensor, a signal conditioning module, an analog-to-digital conversion module, an FPGA control core, an ARM control core, a power management module, a clock management module, an SDRAM storage unit and a communication interface,

[0006] The output end of the acceleration sensor is connected to the input end of the signal conditioning module, the output end of the signal conditioning module is connected to the input end of the analog-digital conversion module, the analog-digital conversion module is connected to the FPGA control core, the FPGA control core is connected to the ARM control core, the clock management module is connected to the analog-digital conversion module, the FPGA control core and the ARM control core, the SDRAM storage unit is connected to the FPGA control core, the FPGA control core and the ARM control core are connected to the communication interface, and the power management module is connected to the acceleration sensor, the signal conditioning module, the analog-digital conversion module, the FPGA control core, the ARM control core, the clock management module and the SDRAM storage unit.

[0007] The working process of the vibration acceleration test system based on the ARM and FPGA dual-core architecture is as follows: the signal conditioning module provides constant current excitation for the acceleration sensor and amplifies the output signal of the acceleration sensor; the analog-digital conversion module synchronously performs AD conversion on the analog signal, the FPGA control core reads the AD-converted analog signal and performs FIR digital filtering processing, and the filtered data is written into the SDRAM storage unit; when the data amount reaches the set threshold value, the SDRAM storage unit sends the buffered data to the FIFO queue of the FPGA chip; and the ARM control core reads the data in the FIFO queue.

[0008] Preferably, the communication interface comprises an expansion peripheral interface, a USB_OTG interface, an Ethernet interface and a Micro SD interface, the FPGA control core is connected to the expansion peripheral interface, and the ARM control core is connected to the USB_OTG interface, the Ethernet interface and the Micro SD interface.

[0009] Preferably, the signal conditioning module comprises an LM334SM chip and an AD8422ARZ chip, and the analog-digital conversion module comprises an AD7606BSTZ chip.

[0010] Preferably, the signal conditioning module further comprises a potentiometer RP2, a potentiometer RP3, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14 and a diode D1, the R pin of the LM334SM chip is connected to the signal input end of the acceleration sensor in series with the resistor R10, the R pin of the LM334SM chip is connected to the signal input end of the acceleration sensor in series with the diode D1, the R pin of the LM334SM chip is connected to the V- pin of the LM334SM chip in series with the resistor R9, the -IN pin of the AD8422ARZ chip is grounded in series with the resistor R5, the -IN pin of the AD8422ARZ chip is grounded in series with the capacitor C9, the -IN pin of the AD8422ARZ chip is connected to the +IN pin of the AD8422ARZ chip in series with the capacitor C11, the RG1 pin of the AD8422ARZ chip is connected to the RG2 pin of the AD8422ARZ chip in series with the potentiometer RP2, the +IN pin of the AD8422ARZ chip is connected to the signal input end of the acceleration sensor in series with the resistor R7 and the capacitor C12, the +IN pin of the AD8422ARZ chip is grounded in series with the capacitor C14, the Vout pin of the AD8422ARZ chip is grounded in series with the resistor R6 and the capacitor C10, the Vout pin of the AD8422ARZ chip is connected to the output end of the signal conditioning module in series with the resistor R6, the REF pin of the AD8422ARZ chip is grounded in series with the capacitor C13, the REF pin of the AD8422ARZ chip is connected to the resistor R8 and the potentiometer RP3, the two ends of the potentiometer RP3 are connected to +5V voltage and -5V voltage respectively, the -Vs pin of the AD8422ARZ chip is connected to -5V voltage, and the +Vs pin of the AD8422ARZ chip is connected to +5V voltage.

[0011] Preferably, the analog-to-digital conversion module further comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor C23, a capacitor C24, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R11, a resistor R12, a resistor R13 and a resistor R14,

[0012] The first pin AVcc of the AD7606BSTZ chip is connected to +5V, the first pin AVcc of the AD7606BSTZ chip is connected to ground through a capacitor C15, the capacitor C15 is connected in parallel with a capacitor C16, the PAR / SER / BYTE SEL pin of the AD7606BSTZ chip is connected to ground, the STBY pin of the AD7606BSTZ chip is connected to +3.3V, the VDRIVE pin of the AD7606BSTZ chip is connected to +3.3V, the second pin AGND of the AD7606BSTZ chip is connected to ground, the REF SELECT pin of the AD7606BSTZ chip is connected to +3.3V, the 35th pin AGND of the AD7606BSTZ chip, the 38th pin AVcc of the AD7606BSTZ chip, the 40th pin AGND of the AD7606BSTZ chip, the 41st pin AGND of the AD7606BSTZ chip, the 43rd pin REFGND of the AD7606BSTZ chip, the 46th pin REFGND of the AD7606BSTZ chip and the 47th pin AGND of the AD7606BSTZ chip are all connected to ground, the 36th pin REGCAP of the AD7606BSTZ chip is connected to ground through a capacitor C22, the 37th pin AVcc of the AD7606BSTZ chip is connected to +5V, the 37th pin AVcc of the AD7606BSTZ chip is connected to ground through a capacitor C23, the capacitor C23 is connected in parallel with a capacitor C24, the 39th pin REGCAP of the AD7606BSTZ chip is connected to ground through a capacitor C21, the 42nd pin REFIN / REFOUT of the AD7606BSTZ chip is connected to ground through a capacitor C20, the REF CAPA pin of the AD7606BSTZ chip is connected to the REF CAPB pin of the AD7606BSTZ chip, the REF CAPB pin of the AD7606BSTZ chip is connected to ground through a capacitor C19, the 48th pin AVcc of the AD7606BSTZ chip is connected to +5V, the 48th pin AVcc of the AD7606BSTZ chip is connected to ground through a capacitor C17, and the capacitor C17 is connected in parallel with a capacitor C18.

[0013] Preferably, the data is stored into the local Micro SD card through the Micro SD interface in the offline mode.

[0014] Preferably, the ARM control core is a processor STM32F407 with a Cortex-M4 core, and the FPGA control core is an EP4CE10F17 device of an Altera Cyclone IV series.

[0015] Preferably, the FIR digital filter adopts a time division multiplexing mode to filter the sampling signals of the channels.

[0016] Preferably, the acceleration sensor is an IEPE type acceleration sensor.

[0017] Preferably, the FPGA control core communicates with the ARM control core through an FSMC bus.

[0018] The present application has the following beneficial effects:

[0019] (1) The present application adopts a cooperative control mode of ARM and FPGA dual-core architecture, fully utilizes the advantages of ARM in real-time logic control and FPGA in parallel signal processing, and realizes synchronous sampling of 16-bit resolution, 200KHz sampling rate and 8-channel vibration acceleration signal, thereby providing a high-performance solution for vibration acceleration measurement.

[0020] (2) The present application realizes high-speed parallel bidirectional communication between the ARM and FPGA dual-core architecture through an FSMC bus, realizes parallel bidirectional communication of ARM logic control instructions and FPGA parallel sampling data through combination of 16-bit data lines and 10-bit address lines, and guarantees the rapidity and real-time of data interaction between the two.

[0021] (3) The present application realizes construction of a FIR filter with the aid of MATLAB and Quartus II software platforms, completes design of filter amplitude-frequency characteristics with the FDATool toolbox of MATLAB, realizes parameterized configuration of the filter with a FIR IP core provided by Quartus II, and realizes digital filter processing of multi-channel sampling signals in a time-division multiplexing mode.

[0022] (4) The present application designs two communication interfaces of Ethernet interface and Micro SD interface at the ARM control end, realizes real-time data transmission between the system and the host computer in networking mode, stores test data into the local Micro SD card in offline mode, and utilizes the two communication modes to improve the flexibility of system layout and guarantee the integrity of test data. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the present application, the drawings needed in the embodiments will be briefly introduced as follows, and obviously, other drawings can be obtained by those skilled in the art without creative labor on the premise of these drawings.

[0024] Figure 1 is a principle diagram of the present application;

[0025] Figure 2 is a circuit principle diagram of the signal conditioning module of the present application;

[0026] Figure 3This is a circuit schematic diagram of the AD7606 analog-to-digital converter module of the present invention;

[0027] Figure 4 This is a timing diagram of synchronous sampling of the AD7606 analog-to-digital converter module in parallel mode according to the present invention;

[0028] Figure 5 This is a schematic diagram of the FSMC communication interface between the ARM and FPGA dual-core architectures in this invention;

[0029] Figure 6 This is a graph showing the amplitude-frequency response of the FIR filter of the present invention; Detailed Implementation

[0030] Example 1

[0031] like Figure 1 As shown, a vibration acceleration testing system based on a dual-core ARM and FPGA architecture includes an accelerometer, a signal conditioning module, an analog-to-digital converter (ADC), an FPGA control core, an ARM control core, a power management module, a clock management module, an SDRAM storage unit, and a communication interface. The communication interface includes a USB interface, an Ethernet interface, and a Micro SD card interface. The output of the accelerometer is connected to the input of the signal conditioning module, which in turn is connected to the input of the ADC. The ADC is connected to the FPGA control core, which is connected to the ARM control core. The clock management module is connected to the ADC, the FPGA control core, and the ARM control core. The SDRAM storage unit is connected to the FPGA control core. The FPGA and ARM control cores are connected to the communication interface. The power management module is connected to the accelerometer, signal conditioning module, ADC, FPGA control core, ARM control core, clock management module, and SDRAM storage unit.

[0032] The system workflow is as follows: After system initialization, the signal conditioning module provides constant current excitation to the accelerometer and amplifies its output signal to ensure its voltage range meets the input requirements of the analog-to-digital converter (ADC). The ADC synchronously performs AD conversion on eight analog signals. The FPGA control core reads the converted data and performs FIR digital filtering on it. The filtered data is then written to the SDRAM memory unit connected to the FPGA control core. When the data volume reaches a set threshold, the SDRAM memory unit sends the buffered data to the FIFO queue of the FPGA control core. The ARM control core reads the data from the FIFO queue via the FSMC bus and sends it to the host computer via the Ethernet interface. As an alternative data storage method, in offline mode, data can be stored on a local Micro SD card via the Micro SD interface to ensure the integrity of the test data.

[0033] Example 2

[0034] The circuit schematic of the signal conditioning module described in this invention is as follows: Figure 2 As shown, the circuit mainly includes a constant current source circuit and an amplifier circuit. The constant current source circuit includes a three-terminal adjustable constant current source device LM334. This device has a wide adjustable output current range, and its output current can be adjusted simply by changing the external resistor value. Simultaneously, to eliminate the influence of temperature effects on the output current, a diode and a matching resistor are added around the device to ensure a constant output current. Experimental verification shows that when R9 is 33Ω and R10 is 330Ω, the device outputs a constant current of 4mA, which meets the constant current excitation requirements of the IEPE type accelerometer. The amplifier circuit consists of an AD8422 instrumentation amplifier, a high-precision, low-noise rail-to-rail amplifier. The gain can be set from 1 to 1000 using a single gain adjustment resistor. In this invention, the sensor output signal is filtered by a DC blocking capacitor C12 to remove DC bias before being input to the amplifier. A potentiometer RP2 is selected as the gain adjustment resistor and connected between the RG pins of the amplifier. By adjusting the resistance value of RP2, the amplifier gain is changed, so that the voltage amplitude of the amplified signal matches the input voltage range of the AD converter.

[0035] Furthermore, the communication interfaces include a JTAG debug port, an extended peripheral interface, a USB_OTG interface, an Ethernet interface, an SWD debug port, and a Micro SD interface. The FPGA control core is connected to the JTAG debug port and the extended peripheral interface, while the ARM control core is connected to the USB_OTG interface, the Ethernet interface, the SWD debug port, and the Micro SD interface.

[0036] Furthermore, the signal conditioning module includes an LM334SM chip and an AD8422ARZ chip, and the analog-to-digital conversion module includes an AD7606BSTZ chip.

[0037] Further, the signal conditioning module further comprises potentiometer RP2, potentiometer RP3, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, capacitor C9, capacitor C10, capacitor C11, capacitor C12, capacitor C13, capacitor C14 and diode D1, the R pin of the LM334SM chip is connected to the signal input end of the acceleration sensor in series with resistor R10, the R pin of the LM334SM chip is connected to the signal input end of the acceleration sensor in series with diode D1, the R pin of the LM334SM chip is connected to the V- pin of the LM334SM chip in series with resistor R9, the -IN pin of the AD8422ARZ chip is grounded in series with resistor R5, the -IN pin of the AD8422ARZ chip is grounded in series with capacitor C9, the -IN pin of the AD8422ARZ chip is connected to the +IN pin of the AD8422ARZ chip in series with capacitor C11, the RG1 pin of the AD8422ARZ chip is connected to the RG2 pin of the AD8422ARZ chip in series with potentiometer RP2, the +IN pin of the AD8422ARZ chip is connected to the signal input end of the acceleration sensor in series with resistor R7 and capacitor C12, the +IN pin of the AD8422ARZ chip is grounded in series with capacitor C14, the Vout pin of the AD8422ARZ chip is grounded in series with resistor R6 and capacitor C10, the Vout pin of the AD8422ARZ chip is connected to the output end of the signal conditioning module in series with resistor R6, the REF pin of the AD8422ARZ chip is grounded in series with capacitor C13, the REF pin of the AD8422ARZ chip is connected to resistor R8 and potentiometer RP3, the two ends of the potentiometer RP3 are connected to +5V voltage and -5V voltage respectively, the -Vs pin of the AD8422ARZ chip is connected to -5V voltage, and the +Vs pin of the AD8422ARZ chip is connected to +5V voltage.

[0038] Example 3

[0039] As Figure 3 shown in the circuit principle diagram of the AD7606 analog-digital conversion module, the analog-digital conversion module further comprises capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C15, capacitor C16, capacitor C17, capacitor C18, capacitor C19, capacitor C20, capacitor C21, capacitor C22, capacitor C23, capacitor C24, resistor R1, resistor R2, resistor R3, resistor R4, resistor R11, resistor R12, resistor R13 and resistor R14,

[0040] The first pin AVcc of the AD7606BSTZ chip is connected to +5V, the first pin AVcc of the AD7606BSTZ chip is connected to ground through a capacitor C15, the capacitor C15 is connected in parallel with a capacitor C16, the PAR / SER / BYTE SEL pin of the AD7606BSTZ chip is connected to ground, the STBY pin of the AD7606BSTZ chip is connected to +3.3V, the VDRIVE pin of the AD7606BSTZ chip is connected to +3.3V, the second pin AGND of the AD7606BSTZ chip is connected to ground, the REF SELECT pin of the AD7606BSTZ chip is connected to +3.3V, the 35th pin AGND of the AD7606BSTZ chip, the 38th pin AVcc of the AD7606BSTZ chip, the 40th pin AGND of the AD7606BSTZ chip, the 41st pin AGND of the AD7606BSTZ chip, the 43rd pin REFGND of the AD7606BSTZ chip, the 46th pin REFGND of the AD7606BSTZ chip, and the 47th pin AGND of the AD7606BSTZ chip are all connected to ground, the 36th pin REGCAP of the AD7606BSTZ chip is connected to ground through a capacitor C22, the 37th pin AVcc of the AD7606BSTZ chip is connected to +5V, the 37th pin AVcc of the AD7606BSTZ chip is connected to ground through a capacitor C23, the capacitor C23 is connected in parallel with a capacitor C24, the 39th pin REGCAP of the AD7606BSTZ chip is connected to ground through a capacitor C21, the 42nd pin REFIN / REFOUT of the AD7606BSTZ chip is connected to ground through a capacitor C20, the REF CAPA pin of the AD7606BSTZ chip is connected to the REF CAPB pin of the AD7606BSTZ chip, the REF CAPB pin of the AD7606BSTZ chip is connected to ground through a capacitor C19, the 48th pin AVcc of the AD7606BSTZ chip is connected to +5V, the 48th pin AVcc of the AD7606BSTZ chip is connected to ground through a capacitor C17, and the capacitor C17 is connected in parallel with a capacitor C18.

[0041] The configuration mode of important pins of the chip and the connection mode with the FPGA are described as follows: (1) the polarity of the RANGE pin determines the voltage range of the analog input channel, in the application, the pin is connected to a logic low level, and the analog input range of all channels is set to ±5V; (2) the PAR / SER / BYTE SEL pin is a parallel / serial / byte interface selection pin, and the logic low level state of the pin corresponds to selecting a parallel interface to output sample data. In the application, the pin is connected to the ground, and the parallel interface mode is selected to output conversion data of 8 channels in time; (3) the REF SELECT pin is an internal / external reference voltage selection pin, when the pin is connected to a logic high level, the internal reference voltage mode is selected and enabled; otherwise, the internal reference voltage is disabled, and an external reference voltage is applied to the REFIN / REFOUT pin. In the application, the pin is connected to a 3.3V logic high level to enable the internal reference voltage; (4) the CONVSTA and CONVST B pins respectively provide conversion enable signals for V1-V4 channels and V5-V8 channels, in the application, the two pins are respectively connected to I / O ports of the FPGA, and according to the actual demand of the number of sampling channels, 4 / 8 channel flexible configuration is realized; (5) the +5V analog power supply is connected to the 4 AV CC power supply pins through a decoupling capacitor, the VDRIVE pin is connected to the +3.3V power supply of the FPGA, and the compatibility of the interface levels of the two is ensured; V1-V8 are respectively 8 analog signal input pins, and the 16-bit digital signals converted and output are connected to the corresponding I / O ports of the FPGA through the DB[15:0] pin.

[0042] The synchronous sampling timing sequence of the AD7606 analog-digital conversion module in the parallel mode is shown in Figure 4 Firstly, the FPGA control core inputs a high level pulse signal with a width greater than 50ns to the AD7606 through the RESET pin to reset the AD7606. After the reset is completed, the CONVSTA and CONVST B pins enable the corresponding 4 analog input channels respectively under the driving of the rising edge signal, so that the AD conversion is performed synchronously, and the conversion duration is t CONVDuring conversion, the AD7606 feeds back a high level to the FPGA through the BUSY pin, indicating its current working state. After all channels complete conversion, the BUSY pin is reset to a low level, and the sample-and-hold amplifier in the device resumes the tracking mode, at which time the 8-way conversion data is latched to the output data register. During data reading, the chip select pin CS of the AD7606 is set to a low level, and 8 low level pulse signals are sequentially input to the parallel data reading control pin RD, enabling the parallel output port DB[15:0], and the FPGA control core sequentially reads the conversion data of 8 channels through the port. While the AD7606 outputs the conversion value of the V1 channel, the FRSTDATA pin feeds back a high level signal, informing the FPGA control core of the current data reading state. After the data reading of all channels is completed, the chip select pin CS of the AD7606 is reset to a high level, completing the data conversion and reading process.

[0043] Example 4

[0044] In the present application, the FSMC bus is used to realize high-speed parallel bidirectional communication between the ARM and FPGA dual-core architecture, Figure 5 The FSMC communication interface is shown in the figure. FSMC (Flexible Static Memory Controller), that is, a variable static memory controller, is a new type of memory expansion technology for Cortex-M4 core, which not only has high data transmission rate, but also can flexibly expand large-capacity external storage devices. In the present application, the FPGA control core is mounted as an external SRAM device in the Bank1 region of the FSMC bus, the selection of the storage region is realized through the FSMC_NE1 chip selection signal, and the read and write operations of the FPGA are realized by using the shared data, address and control bus. In the data reading process, the FSMC sends the address to be accessed through the address bus A[25:16], and sets the read enable signal line FSMC_NOE to a low level, under the driving of the clock signal FSMC_CLK, the data information in the corresponding address is read through the data bus D[15:0]. During data writing operation, the write enable signal line FSMC_NWE is set to a low level, triggering the FPGA to receive data from the data bus D[15:0] and write the data into the specified memory address.

[0045] Example 5

[0046] In order to eliminate the interference noise introduced in the signal acquisition process, and further improve the signal-to-noise ratio of the test data, the FIR filter is used for filtering processing of each channel signal in the application. The FIR filter can be designed into any amplitude-frequency characteristic, and has strict linear phase, and is widely used in digital signal processing. The filter design method is as follows: (1) the built-in FDATool toolbox of MATLAB is used to complete the filter design, the window function design method is selected in the application, the sampling frequency is set to 10kHz, the cutoff frequency is set to 1kHz, the filter order is set to 30, and the Kaiser window is selected. The amplitude-frequency characteristic curve of the filter generated by the design is as shown in Figure 6 The amplitude attenuation at the cutoff frequency is about-5.5dB, and the 3dB bandwidth is about 920Hz. (2) the filter coefficients generated by the design are quantized into 16-bit fixed-point data, the filter coefficients are imported in the IP core configuration tool of Quartus II software, and the parameterization setting of the FIR IP core is realized; (3) in order to reduce the hardware resources occupied by the filter, the time-sharing multiplexing mode is used in the application, and the FIR filter function module is called in the main program in sequence to realize the digital filtering processing of the multiple signals. It should be noted that the filter parameters involved in the above description are only examples of the design method, and the filter parameters can be reasonably adjusted according to the specific situation in actual application.

[0047] Each embodiment in the specification is described in a progressive manner, and the same and similar parts between each embodiment can be referred to each other, and each embodiment mainly describes the difference from other embodiments.

[0048] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains or the patents issued thereon to the extent permitted by applicable laws.

[0049] The above specific embodiments further detail the purposes, technical solutions and beneficial effects of the application, and it should be understood that the above is only a specific embodiment of the application, and is not used to limit the protection scope of the application, and any modification, equivalent replacement, improvement, etc. made on the basis of the technical solutions of the application should be included in the protection scope of the application.

Claims

1. A vibration acceleration test system based on an ARM and FPGA dual-core architecture, characterized in that, The acceleration sensor, a signal conditioning module, an analog-digital conversion module, an FPGA control core, an ARM control core, a power management module, a clock management module, an SDRAM storage unit and a communication interface are connected in series, The output end of the acceleration sensor is connected with the input end of the signal conditioning module, the output end of the signal conditioning module is connected with the input end of the analog-digital conversion module, the analog-digital conversion module is connected with the FPGA control core, the FPGA control core is connected with the ARM control core, the clock management module is connected with the analog-digital conversion module, the FPGA control core and the ARM control core, the SDRAM storage unit is connected with the FPGA control core, the FPGA control core and the ARM control core are connected with the communication interface, and the power management module is connected with the acceleration sensor, the signal conditioning module, the analog-digital conversion module, the FPGA control core, the ARM control core, the clock management module and the SDRAM storage unit. The working process of the vibration acceleration test system based on the ARM and FPGA dual-core architecture is as follows: the signal conditioning module provides constant current excitation for the acceleration sensor and amplifies the output signal of the acceleration sensor; the analog-digital conversion module synchronously converts the analog signal, the FPGA control core reads the converted analog signal and performs FIR digital filtering processing, and the filtered data is written into the SDRAM storage unit; when the data amount reaches the set threshold, the SDRAM storage unit sends the buffered data to the FIFO queue of the FPGA chip; The ARM control core reads the data in the FIFO queue. 2.The vibration acceleration test system based on the dual-core architecture of ARM and FPGA according to claim 1, wherein, The communication interface includes an expansion peripheral interface, a USB_OTG interface, an Ethernet interface and a Micro SD interface, the FPGA control core is connected with the expansion peripheral interface, and the ARM control core is connected with the USB_OTG interface, the Ethernet interface and the Micro SD interface. 3.The vibration acceleration test system based on the dual-core architecture of ARM and FPGA of claim 1, wherein, The signal conditioning module includes an LM334SM chip and an AD8422ARZ chip, and the analog-digital conversion module includes an AD7606BSTZ chip.

4. The vibration acceleration test system based on the dual-core architecture of ARM and FPGA of claim 3, wherein, The signal conditioning module further comprises potentiometer RP2, potentiometer RP3, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, capacitor C9, capacitor C10, capacitor C11, capacitor C12, capacitor C13, capacitor C14 and diode D1, the R pin of the LM334SM chip is connected to the signal input end of the acceleration sensor after being connected in series with resistor R10, the R pin of the LM334SM chip is connected to the signal input end of the acceleration sensor after being connected in series with diode D1, the R pin of the LM334SM chip is connected to the V- pin of the LM334SM chip after being connected in series with resistor R9, the -IN pin of the AD8422ARZ chip is connected to ground after being connected in series with resistor R5, the -IN pin of the AD8422ARZ chip is connected to ground after being connected in series with capacitor C9, the -IN pin of the AD8422ARZ chip is connected to the +IN pin of the AD8422ARZ chip after being connected in series with capacitor C11, the RG1 pin of the AD8422ARZ chip is connected to the RG2 pin of the AD8422ARZ chip after being connected in series with potentiometer RP2, the +IN pin of the AD8422ARZ chip is connected to the signal input end of the acceleration sensor after being connected in series with resistor R7 and capacitor C12, the +IN pin of the AD8422ARZ chip is connected to ground after being connected in series with capacitor C14, the Vout pin of the AD8422ARZ chip is connected to ground after being connected in series with resistor R6 and capacitor C10, the Vout pin of the AD8422ARZ chip is connected to the output end of the signal conditioning module after being connected in series with resistor R6, the REF pin of the AD8422ARZ chip is connected to ground after being connected in series with capacitor C13, the REF pin of the AD8422ARZ chip is connected in series with resistor R8 and potentiometer RP3, the two ends of the potentiometer RP3 are connected to +5V voltage and -5V voltage respectively, the -Vs pin of the AD8422ARZ chip is connected to -5V voltage, and the +Vs pin of the AD8422ARZ chip is connected to +5V voltage.

5. The vibration acceleration test system based on ARM and FPGA dual-core architecture according to claim 3, characterized in that, The analog-to-digital conversion module further comprises capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8, capacitor C15, capacitor C16, capacitor C17, capacitor C18, capacitor C19, capacitor C20, capacitor C21, capacitor C22, capacitor C23, capacitor C24, resistor R1, resistor R2, resistor R3, resistor R4, resistor R11, resistor R12, resistor R13 and resistor R14, The first pin AVcc of the AD7606BSTZ chip is connected with +5V, the first pin AVcc of the AD7606BSTZ chip is connected with the ground through the capacitor C15, the capacitor C15 is connected with the capacitor C16 in parallel, the PAR / SER / BYTE SEL pin of the AD7606BSTZ chip is connected with the ground, the STBY pin of the AD7606BSTZ chip is connected with +3.3V, the VDRIVE pin of the AD7606BSTZ chip is connected with +3.3V, the second pin AGND of the AD7606BSTZ chip is connected with the ground, the REF SELECT pin of the AD7606BSTZ chip is connected with +3.3V, the 35th pin AGND of the AD7606BSTZ chip, the 38th pin AVcc of the AD7606BSTZ chip, the 40th pin AGND of the AD7606BSTZ chip, the 41th pin AGND of the AD7606BSTZ chip, the 43th pin REFGND of the AD7606BSTZ chip, the 46th pin REFGND of the AD7606BSTZ chip and the 47th pin AGND of the AD7606BSTZ chip are all connected with the ground, the 36th pin REGCAP of the AD7606BSTZ chip is connected with the ground through the capacitor C22, the 37th pin AVcc of the AD7606BSTZ chip is connected with +5V, the 37th pin AVcc of the AD7606BSTZ chip is connected with the ground through the capacitor C23, the capacitor C23 is connected with the capacitor C24 in parallel, the 39th pin REGCAP of the AD7606BSTZ chip is connected with the ground through the capacitor C21, the 42th pin REFIN / REFOUT of the AD7606BSTZ chip is connected with the ground through the capacitor C20, the REF CAPA pin of the AD7606BSTZ chip is connected with the REF CAPB pin of the AD7606BSTZ chip, the REF CAPB pin of the AD7606BSTZ chip is connected with the ground through the capacitor C19, the 48th pin AVcc of the AD7606BSTZ chip is connected with +5V, the 48th pin AVcc of the AD7606BSTZ chip is connected with the ground through the capacitor C17, and the capacitor C17 is connected with the capacitor C18 in parallel.

6. The vibration acceleration test system based on ARM and FPGA dual-core architecture according to claim 1, characterized in that, In the offline mode, data is stored into the local Micro SD card through the Micro SD interface.

7. The vibration acceleration test system based on ARM and FPGA dual-core architecture according to claim 1, characterized in that, The ARM control core is a processor STM32F407 with a Cortex-M4 core, and the FPGA control core is an EP4CE10F17 device of an Altera Cyclone IV series. 8.The vibration acceleration test system based on ARM and FPGA dual-core architecture of claim 1, wherein, The FIR digital filter adopts a time division multiplexing mode to filter the sampling signals of the channels.

9. The vibration acceleration test system based on ARM and FPGA dual-core architecture according to claim 1, characterized in that, The acceleration sensor is an IEPE type acceleration sensor.

10. The vibration acceleration test system based on ARM and FPGA dual-core architecture according to claim 1, characterized in that, The FPGA control core communicates with the ARM control core through an FSMC bus.

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