Method and system for optimizing power consumption of storage chip

Abstract

The invention provides a power consumption optimization method and system for a storage chip, and relates to the technical field of chip design, and the method comprises the steps: constructing a directed application core graph based on a calculation task of the storage chip; according to the directed application core graph, mapping the calculation task into a core of a storage chip, and determining an initial mapping scheme; obtaining related parameters of the storage chip; establishing a total power consumption model, a communication cost model and a temperature prediction model according to the related parameters; according to the total power consumption model and the communication cost model, by taking minimization of the total power consumption and the communication cost of the storage chip as a target, constructing a target function; constructing constraint conditions according to the temperature model; under the constraint of the constraint condition, optimizing the mapping scheme by adopting an optimization algorithm by taking minimization of the target function as a target, and determining an optimal mapping scheme; and executing the optimal mapping scheme to complete power consumption optimization of the storage chip. The overall performance and energy efficiency of the chip can be improved, the power consumption of the chip is reduced, and efficient operation of the chip is maintained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, in particular to a power consumption optimization method and system of a storage chip. BACKGROUND

[0002] The power consumption optimization method of a storage chip is a technical method for minimizing power consumption, communication cost and temperature by reasonably allocating and scheduling computing tasks and managing chip resources, mainly applied to a multi-core chip system to realize efficient operation of the chip.

[0003] In the rapid development of modern integrated circuit technology, power consumption management of a chip has become a key problem in design. With the increase of chip size and the improvement of processing capacity, the power consumption and temperature of the chip increase rapidly, leading to overheating of the system, performance degradation and even hardware damage. Therefore, an effective power consumption optimization method is essential.

[0004] However, the traditional power consumption optimization method is static in task mapping, which cannot dynamically adapt to different load changes and communication requirements, causing some cores to be overloaded, low utilization efficiency of communication links, unnecessary power consumption and delay, and unable to fully balance the relationship between computing resources and communication resources in the task mapping process, leading to high communication delay and bandwidth consumption, thereby affecting the overall system efficiency, and not considering temperature management of the chip when optimizing power consumption, which not only affects the performance of the chip, but also may cause hardware damage. SUMMARY

[0005] In view of the above problems of the prior art, the purpose of the embodiments of the present application is to provide a power consumption optimization method of a storage chip, which can solve the technical problems that the traditional power consumption optimization method is static in task mapping, cannot dynamically adapt to different load changes and communication requirements, causes some cores to be overloaded, the utilization efficiency of communication links is low, leads to unnecessary power consumption and delay, and cannot fully balance the relationship between computing resources and communication resources in the task mapping process, leading to high communication delay and bandwidth consumption, thereby affecting the overall system efficiency, and not considering temperature management of the chip when optimizing power consumption, which not only affects the performance of the chip, but also may cause hardware damage.

[0006] The first aspect of the embodiments of the present application provides a power consumption optimization method of a storage chip, comprising:

[0007] S1: constructing a directed application core graph based on computing tasks of a storage chip;

[0008] S2: mapping the computing tasks to cores of the storage chip according to the directed application core graph to determine an initial mapping scheme;

[0009] S3: obtaining relevant parameters of the storage chip;

[0010] S4: constructing a total power consumption model, a communication cost model and a temperature prediction model according to the relevant parameters;

[0011] S5: constructing a target function aiming at minimizing the total power consumption and communication cost of the storage chip according to the total power consumption model and the communication cost model;

[0012] S6: constructing a constraint condition according to the temperature prediction model;

[0013] S7: optimizing the initial mapping scheme by using an optimization algorithm under the constraint of the constraint condition and aiming at minimizing the function value of the target function, to determine an optimal mapping scheme;

[0014] S8: executing the optimal mapping scheme to complete the power consumption optimization of the storage chip.

[0015] The second aspect of the embodiment of the application provides a power consumption optimization system of a storage chip, which comprises a processor and a memory.

[0016] The memory stores programs or instructions executable on the processor, and the programs or instructions are executed by the processor to implement the steps of the power consumption optimization method of the storage chip according to the first aspect.

[0017] The third aspect of the embodiment of the application provides a readable storage medium, which stores programs or instructions, and the programs or instructions are executed by a processor to implement the steps of the power consumption optimization method of the storage chip according to the first aspect.

[0018] The technical scheme provided by the embodiment of the application has at least the following beneficial effects:

[0019] In the embodiment of the application, the directed application core graph is constructed, and the computing task is mapped to the computing core, so that the task dependency relationship and the communication demand in the system can be dynamically adapted, the communication delay and bandwidth consumption can be reduced, the load distribution of the computing core can be optimized, the core overload can be avoided, the overall performance and energy efficiency of the chip can be improved, the temperature prediction model and the temperature constraint condition are established, so that all task mappings meet the temperature limit of the chip, and the overheating problem is avoided, thereby improving the stability and long-term reliability of the chip, the target function is constructed, the balance between the computing resource and the communication resource is realized, the total power consumption and the communication cost can be reduced while meeting the performance requirement, the optimization algorithm is used for dynamic scheduling, the task mapping scheme is optimized, the real-time response capability and adaptability of the system in the running process are ensured, the task allocation can be automatically adjusted when the load changes or the system state changes, so that the power consumption of the chip is reduced, and the efficient operation of the chip is maintained. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:

[0021] Figure 1 is a flow diagram of a power consumption optimization method of a storage chip provided by an embodiment of the application;

[0022] Figure 2 is a structural diagram of a power consumption optimization system of a storage chip provided by an embodiment of the application. DETAILED DESCRIPTION

[0023] In order for those skilled in the art to better understand the technical solutions in the embodiments of the application, the technical solutions of the application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the application, rather than all the embodiments of the application. It should be understood that these descriptions are only exemplary, and are not used to limit the scope of the application. Based on the embodiments of the application, all other embodiments obtained by those of ordinary skill in the art without creative labor should fall within the scope of protection of the application.

[0024] The power consumption optimization method of a storage chip provided by an embodiment of the application will be described in detail below with reference to the drawings, specific embodiments and application scenarios.

[0025] Reference is made to the accompanying drawings Figure 1 , which shows a flow diagram of a power consumption optimization method of a storage chip provided by an embodiment of the application.

[0026] The power consumption optimization method of a storage chip provided by an embodiment of the application can include the following steps:

[0027] S1: Based on the computing task of the storage chip, a directed application core graph is constructed.

[0028] The storage chip is an important component in electronic devices, mainly used for data storage and reading, and can store different types of data such as operating systems, applications, pictures, videos, etc. The computing task refers to a specific operation or process that needs to be performed on the storage chip. These tasks may involve data storage, reading and writing, compression, encryption, calculation or other processing. Each computing task may have a dependency relationship with other tasks and needs to be executed in a specific order. The directed application core graph (DACG) is a graph theory model used to represent the dependency relationship and communication requirements between computing tasks (cores). In the DACG, computing tasks are cores in the graph, and data dependency relationships and communication traffic between tasks are directed edges. The weight of the edge usually represents the communication overhead or bandwidth requirement.

[0029] It should be noted that the construction of the directed application core graph is to optimize the task mapping process by analyzing the dependency relationship and communication requirement between tasks, which can clearly show the dependency and data exchange requirement between different computing tasks, clarify the relationship between tasks, effectively map tasks to appropriate cores, reduce communication delay, reduce power consumption, and improve the utilization efficiency of chip resources, thereby optimizing the overall system performance.

[0030] In one possible implementation, S1 specifically includes:

[0031] S101: According to the computing task, define the core set of the directed application core graph.

[0032] In the directed application core graph, the core set is a set of nodes in the graph, where each node represents a computing task, and the cores are connected by directed edges, representing the dependency relationship and communication requirement between tasks.

[0033] S102: According to the core set, define the edge set of the directed application core graph.

[0034] The edge set represents the dependency relationship between the core nodes in the graph, i.e. the data flow between tasks. Each directed edge points from one task node to another, indicating the execution order and data transfer direction between tasks.

[0035] S103: Define the weight of each edge in the edge set to determine the edge weight set.

[0036] The weight of the edge represents the communication requirement between tasks, i.e. the data transmission volume or bandwidth requirement between two tasks. The edge weight usually reflects the strength of data exchange between tasks and is used to represent the communication overhead between tasks.

[0037] S104: Construct the directed application core graph by combining the core set, edge set and edge weight set.

[0038] Specifically, by explicitly defining the core set, edge set and edge weight set, a comprehensive directed application core graph is constructed, which can clearly show the dependency relationship and communication demand between tasks, and provide a basis for subsequent task mapping and resource optimization. In the process of constructing the graph, not only the execution order of the tasks is considered, but also the communication cost between the tasks is evaluated, which provides an effective framework for optimizing task scheduling, communication traffic and power consumption management.

[0039] S2: According to the directed application core graph, map the computing tasks to the cores of the storage chip, and determine an initial mapping scheme.

[0040] It should be noted that by mapping the computing tasks according to the directed application core graph (DACG), the tasks can be reasonably allocated to different cores of the chip. By considering the dependency relationship and communication demand between tasks, the initial mapping scheme can optimize task scheduling and resource allocation, effectively reduce communication delay and bandwidth consumption between tasks, and at the same time ensure that the computing load and power consumption of each task are evenly distributed.

[0041] It should be noted that by mapping the computing tasks according to the directed application core graph (DACG), the tasks can be reasonably allocated to different cores of the chip. By considering the dependency relationship and communication demand between tasks, the initial mapping scheme can optimize task scheduling and resource allocation, effectively reduce communication delay and bandwidth consumption between tasks, and at the same time ensure that the computing load and power consumption of each task are evenly distributed.

[0042] In one possible implementation, S2 specifically includes:

[0043] S201: Select a plurality of initial mapping cores in the core set of the directed application core graph.

[0044]

[0045] Wherein, Rand( ) represents a random selection function, V represents a core set in the directed application core graph, v i represents the i-th initial mapping core.

[0046] Specifically, by randomly selecting the initial mapping core, the allocation position of the task can be intelligently selected according to the computing load, communication demand and other factors, providing a good starting point for subsequent optimization.

[0047] S202: Identify the direct connection relationship of each initial mapping core, and determine the adjacency matrix.

[0048]

[0049] Wherein, D represents the adjacency matrix, v j represents the j-th initial mapping core, e ij represents the edge between the i-th initial mapping core and the j-th initial mapping core, and E represents the edge set.

[0050] S203: Calculate the weight and communication cost of each initial mapping core.

[0051] The weight is specifically:

[0052]

[0053] wherein, W i represents the weight of the i-th initial mapping core, w ij represents the weight of the edge e ij , that is, the weight between the i-th initial mapping core and the j-th initial mapping core.

[0054] The communication cost is specifically:

[0055]

[0056] wherein, A i represents the communication cost of the i-th initial mapping core, N(v i ) represents the neighbor set of the i-th initial mapping core.

[0057] Specifically, the weight and communication cost of the computing task can be understood as the resource consumption and communication overhead of each task, ensuring that tasks with high power consumption or high communication demand can be reasonably allocated to suitable computing cores, avoiding resource waste and bottleneck problems.

[0058] S204: Determine the hop matrix between each initial mapping core.

[0059] The hop matrix is specifically:

[0060]

[0061] wherein, H ij represents the hop matrix from the i-th initial mapping core to the j-th initial mapping core, Min represents minimization, represents the hop set of the path (v i , v j ).

[0062] Specifically, through the hop matrix, the communication delay between tasks can be quantified, so that when mapping tasks, a path with low communication delay can be selected.

[0063] S205: According to the adjacency matrix, weight, communication cost and hop matrix, the computing task is mapped to the core of the storage chip through the shared K-nearest neighbor clustering algorithm, and the initial mapping scheme is determined.

[0064] Specifically, using a shared K-neighbor clustering algorithm, by synthesizing the adjacency matrix, weight, communication cost and hop matrix, the task cluster is intelligently divided, the tasks with close dependence are mapped to adjacent cores, thereby reducing communication delay and bandwidth consumption.

[0065] In a possible implementation, S205 specifically includes:

[0066] S2051: According to the adjacency matrix, weight, communication cost and hop matrix, determine the K-neighbor list of each initial mapping core.

[0067] Specifically, by determining the K-neighbor list of each initial mapping core according to the adjacency matrix, weight, communication cost and hop matrix, the core with the strongest task relevance can be effectively identified and selected, and by mapping the task to the core that is physically close, the communication delay and bandwidth consumption can be significantly reduced, and the data transmission between tasks is optimized.

[0068] S2052: According to the K-neighbor list, calculate the edge strength of each initial mapping core.

[0069] The edge strength is specifically:

[0070]

[0071] Wherein, str(v i ,v j ) represents the edge strength between the initial mapping core v i and the initial mapping core v j , K represents the size of the neighbor list, o represents the position of the shared neighbor in the K-neighbor list of the initial mapping core v i , p represents the position of the shared neighbor in the K-neighbor list of the initial mapping core v j , represents the oth neighbor of the initial mapping core v i , represents the pth neighbor of the initial mapping core v j , represents the conclusion.

[0072] v i and v j There is an edge between the conditions: if and only if v i and v j are in the K nearest neighbor list closest to each other.

[0073] S2053: According to the edge strength, divide the directed application core graph into multiple clusters.

[0074] S2054: Map each cluster after division to determine the mapping scheme.

[0075] Specifically, by mapping the divided task clusters, tasks closely related to each other can be mapped to adjacent computing cores, thereby effectively reducing the communication delay and bandwidth consumption between tasks, improving the data transmission efficiency, reducing the power consumption of the system, and improving the load balancing and overall performance of the system.

[0076] In a possible implementation, after S2, the method further includes:

[0077] determining a mapping quality score of the initial mapping scheme, and determining a quality level of the initial mapping scheme according to the mapping quality score, wherein the quality level includes excellent quality, medium quality, and poor quality.

[0078] The mapping quality score is calculated by a load balancing degree, an estimated communication overhead, and a core utilization rate, the load balancing degree is determined by the load of the core, the estimated communication overhead is determined by the distance between the cores after mapping, and the core utilization rate is determined by the core load, the total number of cores, and the average core performance.

[0079] When the quality level of the initial mapping scheme is excellent quality, the initial mapping scheme is executed to complete the power consumption optimization of the storage chip.

[0080] When the quality level of the initial mapping scheme is medium quality, step S3 is entered.

[0081] When the quality level of the initial mapping scheme is medium quality, the initial mapping scheme is regenerated.

[0082] Specifically, by introducing the mapping quality score and the quality level evaluation mechanism, the advantages and disadvantages of the initial mapping scheme can be effectively judged, so that the scheme can be optimized accordingly. If the quality is good, the optimization is directly executed to improve the efficiency. If the quality is poor, the scheme is adjusted for further optimization to ensure the best power consumption control and performance balance. This hierarchical management mode enhances the flexibility and accuracy of scheme optimization.

[0083] S3: Obtain related parameters of the storage chip.

[0084] In a possible implementation, the related parameters include performance parameters and physical parameters.

[0085] The performance parameters specifically include communication traffic, communication delay, communication bandwidth demand between tasks, and communication bandwidth demand between tasks. The physical parameters specifically include thermal capacitance, thermal conductivity, and chip temperature.

[0086] S4: According to the related parameters, a total power consumption model, a communication cost model, and a temperature prediction model are constructed.

[0087] It should be noted that the total power consumption model, the communication cost model and the temperature prediction model constructed based on the related parameters can comprehensively evaluate the energy efficiency, communication efficiency and temperature control demand of the chip, accurately predict and optimize the task mapping scheme, ensure that the task meets the performance demand when being executed, effectively reduce power consumption, reduce communication delay, and avoid overheating, realize efficient and stable chip operation, and improve the energy efficiency and reliability of the overall system.

[0088] In a possible implementation, S4 specifically comprises:

[0089] S401: establishing a total power consumption model and a communication cost model according to a performance parameter.

[0090] The total power consumption model is specifically:

[0091]

[0092] wherein, P Tot represents the total power consumption of the power consumption chip, λ ij represents the initial mapping core v i , and the communication flow between the initial mapping core v j , i,j=1,2,…,n, n represents the total number of initial mapping cores.

[0093] The communication cost model is specifically:

[0094]

[0095]

[0096]

[0097] wherein, C h represents the horizontal communication cost, hc ij,x represents the number of hops in the x direction between the initial mapping core v i and the initial mapping core v j , hc ij,y represents the number of hops in the y direction between the initial mapping core v i and the initial mapping core v j , hc ij,z represents the number of hops in the z direction between the initial mapping core v i and the initial mapping core v j , C v represents the vertical communication cost, C T represents the total communication cost, Source( ) represents the originating core of data transmission, Sink( ) represents the receiving core of data transmission, and δ represents an adjustment parameter.

[0098] S402: Construct a temperature prediction model according to the physical parameters.

[0099] In one possible implementation, S402 specifically includes:

[0100] S4021: Construct a thermal dynamics model.

[0101] The thermal dynamics modeling specifically refers to:

[0102]

[0103] wherein R t represents the thermal capacitance at time t, G t represents the thermal conductance at time t, and T(t) represents the temperature vector of the storage chip at time t.

[0104] wherein the thermal dynamics modeling is a mathematical model used to describe and predict the heat generated by the chip during operation and how the heat propagates within the chip.

[0105] Specifically, the thermal dynamics modeling can accurately predict the temperature distribution and heat propagation of the chip, thereby helping to optimize the heat dissipation design and power consumption management of the chip.

[0106] S4022: Discretize the thermal dynamics model to construct a temperature prediction model.

[0107] The temperature model specifically refers to:

[0108]

[0109] wherein T[k+1] represents the temperature vector of the storage chip at time k+1, I represents the unit matrix, T s represents the thermal sensitivity coefficient of the storage chip, C t represents, T[k] represents the temperature vector of the storage chip at time k, P[k] represents the power consumption vector at time k, A s represents the temperature propagation matrix, B s represents the power consumption influence matrix, T[k+m] represents the temperature vector of the storage chip at time k+m, a=0,1,…,m-1, m represents the total number of time steps of temperature prediction, and P[k+m-a-1] represents the power consumption vector at time k+m-a-1.

[0110] S5: According to the total power consumption model and the communication cost model, construct a target function with the goal of minimizing the total power consumption and communication cost of the storage chip.

[0111] Specifically, by combining the total power consumption model and the communication cost model to construct the objective function, the power consumption and the communication cost can be considered at the same time, providing a comprehensive optimization decision framework for chip design, effectively reducing the total power consumption and communication cost of the chip when executing tasks, maximizing the energy efficiency of the chip while meeting the system performance requirements, and reducing resource waste.

[0112] The objective function is specifically:

[0113]

[0114] Wherein, F represents the objective function, min represents minimization, ω P represents the control factor of the total power consumption, ω C represents the control factor of the communication cost.

[0115] S6: According to the temperature prediction model, a constraint condition is constructed.

[0116] The constraint condition is specifically:

[0117]

[0118] Wherein, max represents maximization, A s,q represents the temperature propagation matrix of the qth hot spot of the storage chip, B s,q represents the power consumption influence matrix of the qth hot spot of the storage chip, T max represents the maximum allowed temperature of the storage chip, and Q represents the total number of hot spots of the storage chip.

[0119] S7: Under the constraint of the constraint condition, the initial mapping scheme is optimized by using an optimization algorithm to minimize the objective function, to determine the optimal mapping scheme.

[0120] It should be noted that by minimizing the objective function under the constraint condition and further optimizing the initial mapping scheme using the optimization algorithm, the optimal mapping scheme can be found under the premise of multiple constraints such as power consumption, communication cost and temperature limit, which can dynamically adjust the mapping and scheduling of tasks, not only meet the system performance requirements, but also optimize the resource allocation, improve the energy efficiency and stability of the chip.

[0121] In one possible implementation, the optimization algorithm is specifically: chicken swarm optimization algorithm.

[0122] The chicken swarm optimization algorithm is a swarm intelligence optimization algorithm based on the behavior of chicken flocks in nature. It simulates the different roles (such as roosters, hens and chicks) in the process of finding food in the chicken flock through hierarchical behavior of mutual cooperation and learning, and the algorithm guides the optimal solution by the rooster, and the hens and chicks explore and learn in the group, so as to find the optimal solution in the complex search space.

[0123] Specifically, the chicken swarm optimization algorithm can simulate the behavior of chicken swarms in nature, combine the guidance of roosters and the learning of chicks, and perform efficient search and optimization in multi-dimensional complex problems. It can dynamically adjust the parameters and strategies in the search process to cope with changing optimization objectives and constraint conditions. In dealing with multi-objective optimization problems of power consumption optimization, communication cost and temperature control, the chicken swarm optimization algorithm can balance different objectives, ensure global optimal solution, and avoid falling into local optimal solution, thereby effectively improving the efficiency and stability of the mapping scheme.

[0124] In a possible implementation, S7 specifically includes:

[0125] S701: initialize a population.

[0126] Each individual in the population represents a possible mapping scheme.

[0127] S702: calculate the fitness values of all individuals in the population by taking the objective function as the fitness function.

[0128] S703: divide the population into roosters, hens and chicks according to the fitness values.

[0129] S704: update the speeds of the roosters, hens and chicks.

[0130] The speed of the updated rooster is specifically:

[0131]

[0132] wherein, represents the speed of the dth individual at the g+1th iteration when the dth individual is a rooster, represents the lower bound of the rooster speed at the gth iteration when the dth individual is a rooster, and rand0 represents a random number between [1, 0], represents the upper bound of the rooster speed at the gth iteration when the dth individual is a rooster, represents the speed of the dth individual at the gth iteration when the dth individual is a rooster, represents the first learning rate.

[0133] The speed of the updated hen is specifically:

[0134]

[0135] wherein, represents the speed of the dth individual at the g+1th iteration when the dth individual is a hen, represents the lower bound of the hen speed at the gth iteration when the dth individual is a hen, and rand1 represents a random number between [1, 0], an upper bound of the speed of the gth iteration rooster when the dth individual is a hen, an upper bound of the speed of the gth iteration rooster when the dth individual is a hen, denotes the second learning rate.

[0136] The speed of the updated chick is specifically:

[0137]

[0138] wherein, an upper bound of the speed of the gth iteration rooster when the dth individual is a hen, an upper bound of the speed of the gth iteration rooster when the dth individual is a hen, denotes the speed of the hen referenced by the dth chick in the gth iteration, and η denotes a population control factor, denotes a step length for updating the position of the chick according to the position of the hen, and L denotes a knowledge factor, i.e., the chick learns the experience of the rooster to update its own position.

[0139] S705: generating an optimized population according to the updated speed.

[0140] S706: determining whether the maximum number of iterations is reached. If yes, outputting an optimal mapping scheme according to the optimized population. Otherwise, returning to step S702.

[0141] S8: executing the optimal mapping scheme to complete the power consumption optimization of the storage chip.

[0142] It should be noted that after executing the optimal mapping scheme, the tasks can be actually allocated to the calculation cores of the chip, the power consumption optimization is realized, the inter-task communication in the execution process of the chip is minimized, the power consumption distribution is more uniform through reasonable core scheduling and load balancing, the burden of the core with excessively high power consumption is reduced, so that the overall power consumption is reduced. In addition, through this optimization, the performance degradation caused by overheating can be effectively avoided, the stability and long-term running efficiency of the system are improved, and it is ensured that the system can stably and efficiently run under low power consumption.

[0143] The technical scheme provided by the embodiments of the present application has at least the following beneficial effects:

[0144] In the embodiment of the present application, by constructing a directed application core graph and mapping the computing tasks to the computing cores, the task dependency relationship and communication demand in the system can be dynamically adapted, the communication delay and bandwidth consumption can be reduced, the load distribution of the computing cores can be optimized, the core overload can be avoided, the overall performance and energy efficiency of the chip can be improved, by establishing a temperature prediction model and temperature constraint condition, it is ensured that all task mappings meet the temperature limit of the chip, the overheating problem is avoided, thereby the stability and long-term reliability of the chip are improved, by constructing an objective function, the balance between the computing resources and the communication resources is realized, the total power consumption and communication cost can be reduced while meeting the performance requirements, the optimization algorithm is used for dynamic scheduling, the task mapping scheme is optimized, the real-time response capability and adaptability of the system in the running process are ensured, the task allocation can be automatically adjusted when the load changes or the system state changes, thereby the power consumption of the chip is reduced and the efficient operation of the chip is maintained.

[0145] Reference is made to the accompanying drawings Figure 2 , which shows a structural schematic diagram of a power consumption optimization system of a storage chip provided by an embodiment of the present application.

[0146] An embodiment of the present application provides a power consumption optimization system 20 of a storage chip, which comprises a processor 201 and a memory 202.

[0147] The memory 202 stores programs or instructions which can run on the processor 201, the programs or instructions are executed by the processor 201 to realize the steps of the power consumption optimization method of the storage chip and achieve the same technical effects, to avoid repetition, the present application will not be described again.

[0148] It should be understood that the processor 201 in the embodiment of the present application can be a central processing unit (CPU), and the processor can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), ready-to-program gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0149] It is also to be understood that the memory 202 in embodiments of the present application can be volatile or nonvolatile memory, or can include both volatile and nonvolatile memory. Nonvolatile memory can be read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), used as external cache. By way of example, and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0150] The above-described embodiments can be implemented in whole or in part by software, hardware (e.g., circuitry), firmware, or any combination of the three. When implemented in software, the above-described embodiments can be implemented in the form of one or more computer programs that are stored in a computer-readable storage medium. The computer-readable storage medium stores one or more computer instructions or computer programs that, when loaded into a computer, cause the computer to perform the processes or functions described in the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, such as from a website, a computer, a server, or a data center to another website, computer, server, or data center, via a wired (e.g., infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more collections of available media. The available media can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium can be a solid-state disk.

[0151] It should be understood that the size of the sequence number of each process described above in various embodiments of the present application does not mean the order of execution, and the execution order of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0152] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0153] Those of ordinary skill in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the devices, apparatuses and units described above can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0154] In several embodiments provided by the present application, the disclosed devices, apparatuses and methods can be implemented in other manners. For example, the apparatus embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation. For example, a plurality of units or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0155] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0156] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can be physically present separately, or two or more units can be integrated into one unit.

[0157] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the present application that essentially contribute to the prior art or the parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0158] The embodiment of the present application provides a readable storage medium, which includes: a program or instructions stored on the readable storage medium, the program or instructions are executed by a processor to realize the steps of the power consumption optimization method of the storage chip, and the same technical effects can be achieved. To avoid repetition, the present application will not be described again.

[0159] It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, but not to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. Any changes or replacements that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered within the protection scope of the present application.

Claims

1. A method for power consumption optimization of a memory chip, the method comprising: The method comprises the following steps: S1: constructing a directed application core graph based on a computing task of a memory chip; S2: mapping the computing task to cores of the memory chip according to the directed application core graph to determine an initial mapping scheme; S3: obtaining relevant parameters of the memory chip; S4: constructing a total power consumption model, a communication cost model, and a temperature prediction model according to the relevant parameters; S5: constructing an objective function aiming at minimizing the total power consumption and communication cost of the memory chip according to the total power consumption model and the communication cost model; S6: constructing a constraint condition according to the temperature prediction model; S7: optimizing the initial mapping scheme under the constraint of the constraint condition aiming at minimizing the function value of the objective function to determine an optimal mapping scheme; S8: executing the optimal mapping scheme to complete the power consumption optimization of the memory chip.

2. The power consumption optimization method of memory chips according to claim 1, wherein, The S1 specifically comprises the following steps: S101: defining a core set of the directed application core graph according to the computing task; S102: defining an edge set of the directed application core graph according to the core set; S103: defining the weight of each edge in the edge set to determine an edge weight set; S104: constructing the directed application core graph in combination with the core set, the edge set, and the edge weight set.

3. The method of power consumption optimization of a memory chip according to claim 1, wherein, The S2 specifically comprises the following steps: S201: selecting multiple initial mapping cores in the core set of the directed application core graph; S202: identifying the direct connection relationship of each initial mapping core to determine an adjacency matrix; S203: calculating the weight and communication cost of each initial mapping core; S204: determining a hop matrix between each initial mapping core; S205: mapping the computing task to the cores of the memory chip according to the adjacency matrix, the weight, the communication cost, and the hop matrix by a shared K-nearest neighbor clustering algorithm to determine the initial mapping scheme.

4. The power consumption optimization method of memory chips according to claim 3, wherein, The S205 specifically comprises the following steps: S2051: determining the K-nearest neighbor list of each initial mapping core according to the adjacency matrix, the weight, the communication cost, and the hop matrix; S2052: calculating the edge strength of each initial mapping core according to the K-nearest neighbor list; S2053: dividing the directed application core graph into multiple clusters according to the edge strength; S2054: mapping each divided cluster to determine the initial mapping scheme.

5. The method of power consumption optimization of a memory chip according to claim 1, wherein, After the S2, the following steps are further included: determining a mapping quality score of the initial mapping scheme and determining the quality level of the initial mapping scheme according to the mapping quality score, wherein the quality level comprises excellent quality, medium quality, and poor quality; when the quality level of the initial mapping scheme is the excellent quality, executing the initial mapping scheme to complete the power consumption optimization of the memory chip; when the quality level of the initial mapping scheme is the medium quality, entering step S3; when the quality level of the initial mapping scheme is the medium quality, regenerating an initial mapping scheme.

6. The method of power consumption optimization of a memory chip according to claim 1, wherein, The related parameters include performance parameters and physical parameters.

7. The method of power consumption optimization of a memory chip according to claim 6, wherein, The S4 specifically includes: S401: constructing the total power consumption model and the communication cost model according to the performance parameters; S402: constructing the temperature prediction model according to the physical parameters.

8. The method of power consumption optimization of a memory chip according to claim 7, wherein, The S402 specifically includes: S4021: constructing a thermal dynamics model; S4022: discretizing the thermal dynamics model to construct the temperature prediction model.

9. The method of power consumption optimization of a memory chip according to claim 1, wherein, The optimization algorithm is specifically a chicken swarm optimization algorithm.

10. A power consumption optimization system for a memory chip, comprising: The method comprises: a processor and a memory; The memory stores programs or instructions executable on the processor, and the programs or instructions are executed by the processor to implement the steps of the power consumption optimization method of the storage chip according to any one of claims 1 to 9.

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