Power quality comprehensive treatment system based on apf and svg cooperative control

Abstract

The application provides a power quality comprehensive treatment system based on APF and SVG collaborative control, belongs to the intelligent power grid industry and the power quality comprehensive treatment technical field, and comprises the following steps: acquiring power grid current signals and voltage signals, detecting harmonic components and voltage deviations through a harmonic detection module; adopting a collaborative decision controller to determine a compensation strategy according to the harmonic components and the voltage deviations, and distributing compensation tasks of active power filter channels and static var generator channels; generating harmonic compensation currents through the active power filter channels to suppress high-frequency harmonics; generating reactive compensation currents through the static var generator channels to stabilize voltage fluctuations; and filtering the compensation currents through a filtering module and outputting to the power grid. The power quality comprehensive treatment system can effectively suppress power grid harmonics, stabilize voltage fluctuations, improve power quality, and is suitable for complex power grid environments.

Description

Technical Field

[0001] This invention relates to the fields of smart grid industry and power quality management technology, and in particular to a power quality management system based on the coordinated control of active power filter (APF) and static var generator (SVG). Background Technology

[0002] Harmonics and voltage fluctuations in power grids have long plagued power system operation, severely impacting power quality and the safety of electrical equipment. Traditional compensation methods often treat harmonic suppression and voltage stability as independent issues, employing separate solutions that struggle to address the coupled effects of harmonics and voltage fluctuations in complex power grid environments. How to coordinate harmonics and voltage fluctuations at the system level to achieve comprehensive, high-precision power quality management across the entire frequency band has become a pressing technical challenge. This involves multiple challenges: first, how to accurately acquire full-frequency harmonic data and voltage deviation information; second, how to establish a coupling model of harmonics and voltage fluctuations and formulate optimal compensation strategies; third, how to coordinate active power filters and reactive power compensation equipment to achieve rapid and accurate compensation control; and finally, how to ensure the reliable operation of compensation devices in harsh power grid environments. These interconnected issues constitute a complex systemic problem, requiring holistic consideration and innovative breakthroughs across multiple stages, including detection, decision-making, control, and implementation, to achieve coordinated compensation of power grid harmonics and voltage fluctuations and comprehensively improve power quality. Summary of the Invention

[0003] This invention provides a comprehensive power quality management system based on APF and SVG coordinated control, mainly comprising:

[0004] The system acquires grid current and voltage signals, detects harmonic components and voltage deviations using a harmonic detection module, and employs a collaborative decision controller to determine compensation strategies based on harmonic components and voltage deviations, allocating compensation tasks to the active power filter channel and the static var generator channel. Harmonic compensation current is generated through the active power filter channel to suppress high-frequency harmonics, and reactive power compensation current is generated through the static var generator channel to stabilize voltage fluctuations. The compensation current is then filtered by a filtering module and output to the grid.

[0005] Furthermore, the process involves acquiring grid current and voltage signals, and detecting harmonic components and voltage deviations using a harmonic detection module. This includes: acquiring grid current signals using a wideband current transformer and obtaining full-band harmonic data using high-frequency sampling technology; acquiring grid voltage signals using a voltage sensor and detecting voltage deviation data; performing anti-aliasing filtering on the current and voltage signals using a preprocessing module to generate filtered signals; and synchronously sampling the filtered signals using an analog-to-digital converter to obtain harmonic components and voltage deviations.

[0006] Furthermore, a collaborative decision controller is employed to determine the compensation strategy based on the harmonic components and voltage deviation, including: obtaining the total harmonic distortion (THD) of the harmonic components and the deviation amplitude of the voltage deviation; determining whether the deviation amplitude exceeds a preset voltage deviation threshold; if it does, prioritizing the allocation of the static var generator (SVM) channel for voltage stabilization compensation; determining whether the THD exceeds a preset harmonic threshold; if it does, allocating the active power filter (APF) channel for harmonic compensation; and when neither the deviation amplitude nor the THD exceeds the preset threshold, using a preset ratio to allocate the APF channel and the SVM channel for preventative compensation.

[0007] Furthermore, generating harmonic compensation current through the active power filter channel includes: acquiring high-frequency harmonic data in the harmonic components; generating compensation current command based on the high-frequency harmonic data through a hysteresis comparator; controlling the inverter to generate high-frequency harmonic compensation current based on the compensation current command; and injecting the high-frequency harmonic compensation current into the power grid to cancel out high-frequency harmonics.

[0008] Furthermore, generating reactive power compensation current through the static var generator channel includes: acquiring voltage deviation and grid active power change data; calculating reactive power compensation demand based on a preset voltage fluctuation model, wherein the voltage fluctuation model determines the compensation amount based on the active power change and its integral; generating reactive power compensation current command through a quasi-proportional resonant controller; controlling the inverter to generate reactive power compensation current according to the reactive power compensation current command; and injecting the reactive power compensation current into the grid to stabilize the grid voltage.

[0009] Furthermore, the compensation current is filtered by a filtering module, including: acquiring the compensation current generated by the active power filter channel and the static var generator channel; calculating the grid impedance parameters through a real-time identification module; dynamically adjusting the filter parameters based on the grid impedance parameters; and filtering the compensation current to generate an output current that conforms to grid standards.

[0010] Furthermore, the device adopts a layered closed architecture, including: a power layer, a control layer, a redundancy layer, and a heat dissipation layer;

[0011] The power layer uses insulated gate bipolar transistor modules to convert electrical energy and employs direct current circuit technology to optimize conduction performance; the control layer uses field-programmable gate arrays to achieve high-speed computing and employs optocoupler isolation and shielding design to enhance anti-interference capabilities; the redundancy layer uses parallel power units to achieve automatic fault switching; and the heat dissipation layer uses a temperature-controlled heat dissipation system to support a wide temperature operating environment.

[0012] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects:

[0013] This invention discloses a comprehensive power quality management system based on the coordinated control of Active Power Filter (APF) and Static Var Generator (SVG). This system enables coordinated compensation for grid harmonics and voltage fluctuations. It acquires full-band harmonic data through wideband current transformers and high-frequency sampling technology, detects voltage deviations using voltage sensors, and a collaborative decision controller determines the compensation strategy based on harmonic components and voltage deviations, allocating compensation tasks to the Active Power Filter (APF) and Static Var Generator (SVA). The APF generates high-frequency harmonic compensation current through a hysteresis comparator, while the SVA generates reactive power compensation current based on a voltage fluctuation model and a quasi-proportional resonant controller, achieving harmonic suppression and voltage stabilization. This invention employs a layered closed architecture, configuring a power layer and a control layer, and improves reliability through parallel redundancy and temperature-controlled heat dissipation. This comprehensive power quality management system effectively suppresses grid harmonics, stabilizes voltage fluctuations, and improves power quality, making it suitable for complex grid environments. Attached Figure Description

[0014] Figure 1 This is a flowchart illustrating the power quality comprehensive management system based on APF and SVG collaborative control in this invention. Detailed Implementation

[0015] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] Example 1

[0017] like Figure 1 The power quality comprehensive management system based on APF and SVG collaborative control described in this embodiment may specifically include:

[0018] S101 acquires the grid current signal and voltage signal, and detects the harmonic components and voltage deviation through the harmonic detection module.

[0019] Step S101 specifically includes the following steps S1011-S1014:

[0020] S1011 acquires grid current signals through a wideband current transformer and uses high-frequency sampling technology to obtain full-band harmonic data.

[0021] Specifically, a wideband CT sensor is used to acquire the grid current signal, and a nanocrystalline magnetic core material is used to achieve a frequency band response of 0.5-3kHz, maintaining a linearity error of less than 0.1% within a current range of 100A-5000A. The ROGOWSKI coil samples the current signal at a high speed of 50kHz to ensure the capture of the 3rd to 37th harmonic components generated by equipment such as crushers and juice extraction motors in the sugar production line.

[0022] S1012 collects grid voltage signals through a voltage sensor and detects voltage deviation data.

[0023] Specifically, the current signal undergoes anti-aliasing filtering, with the cutoff frequency set to 25kHz to remove high-frequency noise interference. A 16-bit ADC sampling circuit, combined with 8-channel synchronous sampling technology, employs an OSR=128 oversampling method to improve the detection accuracy of weak harmonic signals, with quantization time controlled within 1µs.

[0024] S1013 uses a preprocessing module to perform anti-aliasing filtering on the current signal and voltage signal to generate the filtered signal.

[0025] Specifically, the preprocessing module uses an FPGA preprocessing unit to perform preliminary processing on the sampled data, extracting the fundamental component and each harmonic component. An improved IP-IQ algorithm combined with a notch filter design reduces the traditional detection delay from 50ms to 10ms, enabling real-time calculation of the total harmonic distortion (THDI) value.

[0026] S1014 synchronously samples the filtered signal through an analog-to-digital converter to obtain harmonic components and voltage deviation.

[0027] Specifically, the analog-to-digital converter synchronously acquires the 10kV bus voltage signal and detects the voltage deviation ΔU caused by fluctuations in bagasse fuel supply to the self-owned power plant. The voltage deviation is calculated using per-unit values, and a voltage fluctuation warning is triggered when |ΔU| exceeds 0.05 per-unit values.

[0028] S102 employs a collaborative decision controller to determine the compensation strategy based on harmonic components and voltage deviation, and allocates compensation tasks to the active power filter channel and the static var generator channel.

[0029] Step S102 specifically includes the following steps S1021-S1024:

[0030] S1021, obtain the total harmonic distortion rate of the harmonic components and the deviation amplitude of the voltage deviation.

[0031] Specifically, the collaborative decision controller executes a division-of-labor compensation strategy based on the harmonic spectrum analysis results. The Active Power Filter (APF) channel is specifically responsible for compensating for high-frequency harmonics of the 13th to 50th orders, generating compensation current using a hysteresis comparator with a response time controlled within 50µs. The Static Var Generator (SVG) channel undertakes the tasks of compensating for low-frequency harmonics of the 2nd to 13th orders and dynamic reactive power regulation, employing a quasi-PR controller to achieve a bandwidth coverage of 5-500Hz.

[0032] In one embodiment, when the 25th and 37th harmonic peaks are detected by the crusher inverter, the collaborative decision controller immediately allocates these high-frequency harmonics to the APF channel for processing. Based on the detected harmonic current amplitude of 300A, the APF channel generates a reverse compensation current through the Infineon IGBT module to quickly suppress the high-frequency harmonics. Simultaneously, the 5th, 7th, and 11th harmonics generated during the start-up and shutdown of the juicing motor are allocated to the SVG channel, which performs comprehensive processing in conjunction with reactive power compensation requirements.

[0033] S1022, determine whether the deviation amplitude exceeds the preset voltage deviation threshold. If it does, prioritize the allocation of the static var generator channel for voltage stabilization compensation.

[0034] A voltage fluctuation model is established, with the transfer function ΔU = 0.15·ΔP + 0.02·∫ΔPDT. When the change in active power ΔP of the self-owned power plant exceeds a preset threshold, the SVG channel calculates the required reactive power compensation based on this model. The coefficient 0.15 in the model reflects the direct impact of active power changes on voltage, while the integral term 0.02·∫ΔPDT considers the cumulative effect of power changes.

[0035] Specifically, when the output of a bagasse generator fluctuates due to unstable fuel supply, the active power change ΔP can reach ±200kW. Based on the voltage fluctuation model, a dynamic reactive power compensation of ±300KVAR is required from the SVG channel. After receiving the compensation command, the SVG channel completes reactive power output adjustment within 100ms, controlling the voltage fluctuation rate within ±2%.

[0036] S1023, determine whether the total harmonic distortion rate exceeds the preset harmonic threshold. If it does, allocate an active power filter channel for harmonic compensation.

[0037] Specifically, the priority control logic is executed. When the voltage deviation |ΔU| is greater than 0.05 per unit, the collaborative decision controller prioritizes the SVG channel for voltage stabilization control. When THDI exceeds 8%, the APF channel is activated for harmonic compensation. Under normal operating conditions, APF and SVG perform preventative compensation in a 3:1 ratio, with the APF channel handling 75% of the harmonic mitigation and the SVG channel handling 25% of the low-frequency harmonics and all reactive power compensation.

[0038] S1024 When the deviation amplitude and total harmonic distortion rate do not exceed the preset threshold, the active power filter channel and the static var generator channel are allocated in a preset ratio for preventive compensation.

[0039] Specifically, a recursive least squares method is used to identify the grid impedance parameters in real time, and the inductance and capacitance values ​​of the LCL filter are dynamically adjusted. When the grid impedance changes, the filter parameters automatically track and adjust to avoid system resonant point drift. The grid impedance identification period is set to 10 seconds to ensure that the filter parameters remain matched with the grid conditions.

[0040] In one possible implementation, during the heating process of the crystallizer, the grid impedance changes from 0.8Ω to 1.2Ω. After detecting the impedance change using the recursive least squares method, the inductance value of the LCL filter is automatically adjusted from 2.5mH ​​to 3.1mH and the capacitance value is adjusted from 150μF to 120μF to keep the filter resonant frequency stable at 1.8kHz, thus avoiding resonance with the main harmonic frequencies in the power grid.

[0041] Furthermore, a modular thermal redundancy control mechanism is established to support N+1 parallel operation of power units. When an IGBT power module fails due to over-temperature or over-current, the fault detection circuit identifies the fault state within 1µs and automatically switches to a redundant module to continue operation. After the faulty module is isolated, the remaining modules are reassigned compensation tasks to ensure that the overall compensation capability of the device is not affected.

[0042] It should be noted that in the sugar mill application case, the unit is equipped with six 300A APF power modules and four 400KVAR SVG power modules. When one APF module fails, the remaining five modules automatically take over the original compensation task, increasing the compensation current of a single module from 300A to 360A, while still meeting the harmonic control requirements of the crusher's frequency converter. The SVG modules also have an automatic fault switching function to ensure a stable voltage supply to critical equipment such as crystallizers and honey separators.

[0043] Preferably, the collaborative decision controller uses a KINTEX-7 FPGA for high-speed computation, is equipped with an optocoupler isolation circuit to provide electrical isolation of over 2500V, and features a double-layer metal shielding design to achieve an EMC level of III or higher. The controller has a built-in temperature monitoring function; when the ambient temperature exceeds 45℃, forced air cooling is activated, and the cooling fan stops when the temperature drops to 35℃, adapting to the harsh environment of the sugar factory with its high temperature and humidity.

[0044] S103 generates harmonic compensation current through the active power filter channel to suppress high-frequency harmonics.

[0045] S103 specifically includes the following steps S1031-S1034:

[0046] S1031, acquire high-frequency harmonic data in the harmonic components.

[0047] Specifically, a hysteresis comparator is used to track and control the detected 3rd to 50th harmonic components in real time. The hysteresis comparator sets upper and lower thresholds; when the harmonic current deviation exceeds the preset hysteresis bandwidth, it immediately triggers a switching state change. The hysteresis bandwidth is set to 0.5% of the fundamental current to ensure the tracking accuracy of the harmonic compensation current. When the difference between the detected harmonic current and the reference current exceeds the upper hysteresis limit, the control signal outputs a high level, driving the IGBT to turn on; when the difference is below the lower hysteresis limit, it outputs a low level, turning off the IGBT.

[0048] S1032 generates compensation current commands based on high-frequency harmonic data through a hysteresis comparator.

[0049] Specifically, the Infineon FF1400R17IP4 IGBT module enables rapid generation of harmonic compensation current. The IGBT module operates at a 1700V withstand voltage rating and reduces conduction losses by 30% through DCB ceramic substrate technology. An integrated temperature sensor monitors junction temperature changes in real time; when the junction temperature exceeds 125°C, it automatically derating to ensure device safety. The short-circuit protection circuit has a response time of less than 1 microsecond, identifying short-circuit faults by detecting changes in the collector-emitter voltage and immediately shutting down the IGBT to prevent device damage.

[0050] S1033 controls the inverter to generate high-frequency harmonic compensation current according to the compensation current command.

[0051] Specifically, a three-phase bridge inverter circuit converts the DC bus voltage into harmonic compensation current. The DC bus voltage is stabilized at 800V, maintained through dual closed-loop control of the voltage outer loop and the current inner loop. The voltage outer loop uses a PI controller with a proportional gain of 0.8 and an integral time constant of 50 milliseconds; the current inner loop uses a quasi-proportional resonant controller, with resonant points set at characteristic harmonic frequencies such as the 3rd, 5th, and 7th harmonics to achieve precise compensation for specific harmonic orders.

[0052] S1034 injects high-frequency harmonic compensation current into the power grid to cancel high-frequency harmonics.

[0053] Specifically, space vector pulse width modulation (SVM) technology is used to generate the IGBT drive signal. The carrier frequency is set to 20kHz, and the PWM signal is generated by comparing the triangular carrier wave with the modulating wave. The dead time is set to 2 microseconds to prevent shoot-through between the upper and lower bridge arms. The modulation index is controlled within 0.9 to avoid harmonic distortion caused by overmodulation. The drive circuit uses optocoupler isolation with an isolation voltage of 2500V to effectively suppress electromagnetic interference from the power circuit to the control circuit.

[0054] In one embodiment, for the 25th and 37th characteristic harmonics generated by the frequency converter of the sugar mill crusher, the APF channel calculates the effective value of the harmonic current to be approximately 300A by detecting the fundamental current of 1667A and the total harmonic distortion rate of 18%. The hysteresis comparator is set to a hysteresis bandwidth of 8.3A. When the deviation of the 25th harmonic current exceeds this threshold, the IGBT switching state is immediately adjusted. The IGBT module operates at a switching frequency of 20kHz and generates a compensation current with the same amplitude but opposite phase to the 25th harmonic through space vector modulation, achieving harmonic cancellation.

[0055] S104 generates reactive power compensation current through the static var generator channel to stabilize voltage fluctuations.

[0056] Step S104 includes the following steps S1041-S1045:

[0057] S1041, acquire voltage deviation and power grid active power change data.

[0058] Specifically, a quasi-proportional resonant controller is used to track the reactive current reference value. The transfer function of the quasi-PR controller is Gc(s) = Kp + 2Krs / (s) 2 +ωc 2 The controller is defined as follows: Kp is the proportional gain, Kr is the resonant frequency, and ωc is the resonant frequency. Setting the proportional gain Kp to 1.2 provides wideband control capability; setting the resonant frequency Kr to 800 provides high gain at 50Hz, enabling zero-steady-state-error tracking of the fundamental reactive current. The controller bandwidth covers a frequency range of 5-500Hz, allowing it to track rapidly changing reactive power demands.

[0059] S1042, calculates reactive power compensation requirements based on a preset voltage fluctuation model, wherein the voltage fluctuation model determines the compensation amount based on the change in active power and its integral.

[0060] Specifically, reactive power compensation is calculated based on a voltage fluctuation model. The voltage fluctuation model is: ΔU = 0.15·ΔP + 0.02·∫ΔPDT. By detecting the change in active power ΔP and its integral term, the voltage fluctuation trend is predicted. When an increase of 100kW in active power is detected, the voltage will rise by 15V according to the model calculation, and the SVG channel immediately outputs inductive reactive power for compensation. The integral term coefficient of 0.02 ensures the cumulative compensation effect for continuous power changes and avoids long-term voltage deviation.

[0061] S1043 generates reactive power compensation current commands through a quasi-proportional resonant controller.

[0062] Specifically, reactive power compensation strategies are optimized through real-time identification of grid impedance. The recursive least squares method is used to identify the equivalent grid impedance, with a forgetting factor set to 0.98 to balance tracking speed and noise immunity. When it is identified that an increase in grid impedance enhances the impact of the same reactive power change on voltage, the compensation coefficient is automatically adjusted to improve compensation accuracy. The impedance identification results are used to dynamically adjust LCL filter parameters and optimize system damping characteristics.

[0063] S1044 controls the inverter to generate reactive power compensation current according to the reactive power compensation current command, and injects the reactive power compensation current into the grid to stabilize the grid voltage.

[0064] Specifically, it achieves ±300kVar dynamic reactive power compensation output. The SVG channel adopts a three-level topology and reduces device voltage stress through midpoint clamping technology. The output reactor inductance is 0.8mH, limiting the switching ripple current amplitude to within 5%. The reactive power regulation range is -300kVar to +300kVar, with a response time controlled within 20 milliseconds. When the grid requires capacitive reactive power, the SVG outputs leading current; when inductive reactive power is required, it outputs lagging current, achieving four-quadrant reactive power regulation.

[0065] In one embodiment, when the sugar mill's juice extraction generator starts, it generates a 300kVar reactive power surge. The SVG channel detects an 8V drop in bus voltage using a voltage fluctuation model. The quasi-PR controller immediately calculates the reactive power compensation reference value and outputs 300kVar capacitive reactive power through a three-level inverter. The output reactor limits the switching ripple current to within 15A, which is then injected into the grid after LCL filtering. The entire compensation process is completed within 15 milliseconds, effectively suppressing voltage fluctuations and ensuring the normal operation of other production equipment.

[0066] It should be noted that the APF and SVG channels are powered by independent DC buses to avoid mutual interference. The APF DC bus voltage is 800V, mainly responsible for harmonic compensation; the SVG DC bus voltage is 1200V, specifically for reactive power compensation. The two channels achieve coordinated control through fiber optic communication, with the response time difference controlled within 5 microseconds to ensure the synchronization of compensation actions.

[0067] S105 filters the compensation current through a filter module and outputs it to the power grid.

[0068] Step S105 includes the following steps S1051-S1054:

[0069] S1051, obtain the compensation current generated by the active power filter channel and the static var generator channel.

[0070] Specifically, the recursive least squares method is used to identify the grid impedance in real time. By collecting grid voltage and current signals, the impedance value is calculated. The recursive least squares method is an iterative algorithm that uses historical data and current measurements to gradually update the model parameters. For example, the initial impedance model is set as Z(k) = R + jωL, where R is resistance, L is inductance, and ω is angular frequency. The values ​​of R and L are updated by minimizing the sum of squared errors to ensure that the identification accuracy is within 0.5%.

[0071] S1052 calculates the grid impedance parameters through a real-time identification module.

[0072] Specifically, the parameters of the LCL filter are dynamically adjusted based on the identified grid impedance. For example, the values ​​of inductors L1 and L2 and capacitor C are adjusted to ensure that the filter's resonant frequency avoids the grid harmonic frequency band and avoids resonance risks. The LCL filter is a three-element filter circuit consisting of two inductors and one capacitor, used to suppress high-frequency switching ripple. The adjustment process is achieved by solving for the poles of the filter's transfer function to ensure that the system gain is below -3dB.

[0073] S1053 dynamically adjusts filter parameters based on grid impedance parameters.

[0074] Specifically, the LCL filter after the compensation current input adjustment is filtered to eliminate high-frequency noise before being output to the power grid.

[0075] For example, in the case of a frequency converter load in a sugar production line crusher, when the compensation current contains 25th and 37th harmonic components, the grid impedance is first identified as 5Ω + j10Ω in step S1051. Then, in step S502, L1=1mH, L2=0.5mH, and C=10μF are adjusted to make the filter cutoff frequency above 2kHz, ensuring that the output current THDI drops below 4%. This effectively suppresses harmonic injection into the grid, improves equipment stability and production efficiency, and reduces motor temperature rise by 60%.

[0076] In one possible implementation, for the reactive power compensation scenario of the juicing motor load, the filtering process in step S105 also incorporates a voltage fluctuation model. When ΔU exceeds 0.05 pu, the compensation current input filter of the SVG channel is adjusted first. After filtering, the output stable voltage fluctuation is within ±2%, which is beneficial to maintaining the temperature deviation of the crystallizer within ±3℃ and improving the quality of sucrose.

[0077] Specifically, compared with fixed parameter filtering, this dynamic filtering method can adapt to changes in the power grid caused by fluctuations in fuel supply, with measured annual electricity savings of 1.2 million kWh and a 40% reduction in maintenance costs.

[0078] S1054 filters the compensation current to generate an output current that conforms to the power grid standard.

[0079] Example 2

[0080] Furthermore, the power quality comprehensive management system adopts a layered closed architecture, including: power layer, control layer, redundancy layer and heat dissipation layer;

[0081] The power layer uses insulated gate bipolar transistor modules to convert electrical energy and employs direct current circuit technology to optimize conduction performance; the control layer uses field-programmable gate arrays to achieve high-speed operation and employs optocoupler isolation and shielding design to enhance anti-interference capabilities; the redundancy layer uses parallel power units to achieve automatic fault switching; and the heat dissipation layer uses a temperature-controlled heat dissipation system to support a wide temperature operating environment.

[0082] Specifically, the power layer utilizes insulated-gate bipolar transistor (IGBT) modules for power conversion, employing direct current circuit technology to optimize conduction performance. The Infineon FF1400R17IP4 IGBT module is selected as the core power conversion device. This module has a rated voltage of 1700V and a rated current of 1400A, capable of withstanding the current surges generated during the start-up and shutdown of high-power equipment in sugar production lines. The IGBT module integrates gate drive and protection circuits, achieving rapid switching action through voltage control. The switching frequency can reach 20kHz, meeting the frequency requirements for 3rd-50th harmonic compensation. Direct current circuit technology is used to optimize the packaging of the IGBT module, directly soldering the power chip onto a ceramic substrate with high thermal conductivity and low thermal resistance. Direct current circuit technology reduces conduction losses by 30% by minimizing intermediate conductive layers, while simultaneously improving heat dissipation efficiency. The ceramic substrate is 0.63mm thick with a thermal conductivity of 24W / mK, ensuring that the power module's temperature remains below 85℃ under high load operation. A temperature sensor is integrated inside the insulated-gate bipolar transistor (IGBT) module to monitor the junction temperature changes of the chip in real time. When the junction temperature exceeds 125°C, the temperature protection circuit automatically reduces the switching frequency or suspends output to prevent overheating damage. The short-circuit protection circuit uses a desaturation detection method to detect changes in the collector-emitter voltage. When a short-circuit fault is detected, the protection circuit turns off the IGBT within 1 microsecond, providing a much faster response time than traditional fuse protection.

[0083] Specifically, the control layer utilizes a field-programmable gate array (FPGA) for high-speed computation, employing optocoupler isolation and shielding to enhance anti-interference capabilities. The Xilinx KINTEX-7 FPGA is selected as the control core; this device is manufactured using a 28nm process and integrates 468K logic units and 1540 digital signal processing units. Through its parallel processing architecture, the FPGA can simultaneously handle multiple harmonic detection and compensation control algorithms, achieving a computation speed more than five times faster than traditional digital signal processors. The logic units are reconfigurable, supporting hardware acceleration of improved IP-IQ algorithms. Optocoupler isolation circuits are configured around the FPGA, using high-speed HCPL-3120 optocouplers with an isolation voltage of 2500V and a response time of less than 100ns. These optocoupler isolation circuits completely isolate the control signals from the power circuits, blocking common-mode interference propagation paths. When electromagnetic interference generated during the start-up and shutdown of high-power equipment in the sugar factory production line propagates through the power lines, the optocoupler isolation circuits effectively block interference signals from entering the control circuit, ensuring the accurate execution of the control algorithm. A double-layer metal shielding design is employed to provide electromagnetic shielding protection for the control circuit. The inner shielding layer uses a 0.5mm thick aluminum alloy plate, while the outer shielding layer uses a 0.3mm thick galvanized steel plate. This double-layer shielding structure achieves an electromagnetic interference shielding effectiveness of over 80dB in the 20MHz-1GHz frequency band. Absorbing material is filled between the inner and outer shielding layers to further attenuate high-frequency interference signals. Conductive rubber sealing strips on the shielding shell ensure shielding continuity at the joints, achieving an overall electromagnetic compatibility level of Class III. Hardware acceleration of an improved IP-IQ algorithm is implemented within a field-programmable gate array (FPGA), using dedicated multipliers and accumulators to perform instantaneous power calculations. The algorithm converts three-phase current signals into two-phase quadrature components, separating active and reactive current components, reducing the detection delay from 50ms in traditional software algorithms to 10ms. The hardware accelerator employs a pipelined architecture, processing one set of sampled data per clock cycle, meeting the real-time processing requirements of a 50kHz sampling frequency.

[0084] Specifically, the redundancy layer achieves automatic fault switching through parallel power units. An N+1 modular redundancy design is adopted, decomposing the device's power capacity into multiple independent power unit modules, each with a rated capacity of 100kVA. When the total device capacity is 500kVA, six power units are configured, with five operating normally and one serving as a hot backup. The power units are connected via parallel buses, each with independent control and protection circuits, and communicate and coordinate with each other via a CAN bus. Each power unit integrates a fault detection circuit to monitor the operating status, output current waveform, and temperature parameters of the insulated-gate bipolar transistor (IGBT) in real time. The fault detection circuit employs multi-criteria logic; when abnormal conditions such as overcurrent, overtemperature, or output waveform distortion are detected, the power unit is determined to be faulty. The fault detection algorithm compares the deviation between the actual output current and the commanded current; when the deviation exceeds 10% and lasts for more than 100ms, a fault alarm is triggered. The automatic fault switching controller receives the status information of each power unit. When a fault is detected in a unit, it isolates the faulty unit from the parallel system within 50ms and simultaneously activates the backup unit. The switching process employs a soft-start method, with the standby unit's output current gradually increasing from zero to its rated value, avoiding disruption to the power grid caused by the switching shock. After the faulty unit is isolated, the remaining normal units automatically adjust their output power to ensure that the overall compensation effect of the device is not affected. A current-sharing control strategy is used among the power units to ensure uniform distribution of load current during parallel operation. The current-sharing controller detects the output current of each unit, calculates the average current value, and adjusts the output commands of each unit to make their output currents more consistent. The current-sharing accuracy is controlled within 5%, avoiding situations where some units are overloaded while others are lightly loaded due to uneven load distribution, thus improving the overall operating efficiency and reliability of the device.

[0085] Specifically, the heat dissipation layer's temperature-controlled cooling system supports a wide operating temperature range. The protective casing is made of 316L stainless steel, achieving an IP54 protection rating, providing dust and splash resistance. Internally, a forced-air cooling system automatically activates the cooling fans when the ambient temperature reaches 45℃ and shuts down when the temperature drops to 35℃. This cooling system, combined with heat pipe temperature equalization technology, supports operation within a wide temperature range of -25℃ to +60℃, meeting the harsh environmental requirements of high temperature and humidity in sugar factories.

[0086] In one embodiment, the selection of the insulated-gate bipolar transistor (IGBT) module needs to consider the load characteristics of the sugar production line. For example, the start-up of the crusher inverter generates a surge of 5 times the rated current, lasting approximately 2 seconds; therefore, the power module must have sufficient overload capacity. The FF1400R17IP4 module has an overload capacity of up to 2 times, and by connecting two modules in parallel, it can withstand a 4 times overload, meeting the crusher's start-up requirements. The application of direct current circuit technology makes temperature rise control more effective during overload operation, avoiding power derating due to excessive temperature.

[0087] In one embodiment, the configuration of the optocoupler isolation circuit needs to be optimized for the specific electromagnetic environment of a sugar factory. The power of the juice extraction motors in a sugar factory is typically above 1000kW, and the electromagnetic interference spectrum generated during start-up and shutdown ranges from tens of kHz to several MHz. The high-speed response characteristics of the HCPL-3120 optocoupler enable accurate transmission of control signals, while its 2500V isolation voltage is sufficient to block common-mode interference. In the double-layer metal shielding design, the inner aluminum alloy plate mainly shields against low-frequency magnetic field interference, while the outer galvanized steel plate mainly shields against high-frequency electric field interference; the two layers work together to achieve full-band shielding protection.

[0088] In one embodiment, the capacity configuration of the N+1 redundancy design needs to be determined based on the harmonic characteristics of the sugar mill load. The sugar production line has a high content of harmonics from the 3rd to the 37th order, with the 5th and 7th harmonics accounting for more than 60% of the total harmonics. Each 100kVA power unit can compensate for approximately 150A of harmonic current. When five units operate in parallel, the total harmonic compensation capacity reaches 750A, reducing the total harmonic distortion rate of the current from 15% to below 4%. The presence of backup units ensures that even in the event of a unit failure, the device can maintain more than 80% of its compensation capacity, guaranteeing the continuity of sugar mill production.

[0089] It is important to note that the response time of automatic fault switching is crucial for the stable operation of the sugar production line. Crystallizers in sugar mills are extremely sensitive to voltage fluctuations; fluctuations exceeding 3% can affect crystallization quality. A 50ms switching time can control voltage fluctuations within 2%, preventing impact on the production process. The use of a soft-start method further reduces voltage surges during switching, and the output current of the standby unit increases at a rate of 2A per millisecond, ensuring a smooth transition during switching.

[0090] Specifically, the hardware implementation of the improved IP-IQ algorithm significantly enhances harmonic detection accuracy. Traditional software algorithms, limited by processor speed, typically have sampling frequencies not exceeding 10kHz, making accurate detection of higher harmonics difficult. The parallel processing capability of field-programmable gate arrays (FPGAs) allows the sampling frequency to be increased to 50kHz, enabling accurate detection of all harmonic components up to the 50th order. The use of hardware multipliers avoids rounding errors inherent in software floating-point operations, improving harmonic detection accuracy to 0.2% and providing a reliable data foundation for precise compensation.

[0091] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A comprehensive power quality management system based on APF and SVG coordinated control, characterized in that, include: Acquire grid current and voltage signals, and detect harmonic components and voltage deviation through a harmonic detection module; A collaborative decision controller is used to determine the compensation strategy based on the harmonic components and the voltage deviation, and to allocate the compensation tasks to the active power filter channel and the static var generator channel. Harmonic compensation current is generated through the active power filter channel to suppress high-frequency harmonics; The static var generator channel generates reactive power compensation current to stabilize voltage fluctuations. The compensation current is filtered by a filtering module and then output to the power grid. The method of employing a collaborative decision controller to determine a compensation strategy based on the harmonic components and the voltage deviation includes: Obtain the total harmonic distortion rate of the harmonic components and the deviation magnitude of the voltage deviation; Determine whether the deviation amplitude exceeds a preset voltage deviation threshold. If it does, prioritize allocating the static var generator channel for voltage stabilization compensation. Determine whether the total harmonic distortion rate exceeds a preset harmonic threshold. If it does, allocate the active power filter channel for harmonic compensation. When the deviation amplitude and the total harmonic distortion rate do not exceed the preset threshold, the active power filter channel and the static var generator channel are allocated in a preset ratio for preventive compensation. The SVG channel undertakes the low-frequency harmonic and all reactive power compensation tasks in a preset ratio. The generation of harmonic compensation current through the active power filter channel includes: Obtain high-frequency harmonic data from the harmonic components; A compensation current command is generated based on the high-frequency harmonic data using a hysteresis comparator. The inverter is controlled to generate a high-frequency harmonic compensation current according to the compensation current command. The high-frequency harmonic compensation current is injected into the power grid to cancel out high-frequency harmonics; The generation of reactive power compensation current through the static var generator channel includes: Obtain the voltage deviation and the change in active power of the power grid; The reactive power compensation requirement is calculated based on a preset voltage fluctuation model, wherein the voltage fluctuation model determines the compensation amount based on the change in active power and its integral. The reactive power compensation current command is generated by a quasi-proportional resonant controller. The inverter is controlled to generate reactive power compensation current according to the reactive power compensation current command. The reactive power compensation current is injected into the power grid to stabilize the grid voltage.

2. The power quality comprehensive management system as described in claim 1, characterized in that, The process of acquiring the power grid current and voltage signals, and detecting harmonic components and voltage deviations through a harmonic detection module, includes: The power grid current signal is collected by a wideband current transformer, and full-band harmonic data is obtained by high-frequency sampling technology. Voltage deviation data is detected by acquiring grid voltage signals through voltage sensors. A preprocessing module is used to perform anti-aliasing filtering on the current signal and the voltage signal to generate a filtered signal. The filtered signal is synchronously sampled by an analog-to-digital converter to obtain the harmonic components and the voltage deviation.

3. The power quality comprehensive management system as described in claim 1, characterized in that, The filtering process of the compensation current by the filtering module includes: Obtain the compensation current generated by the active power filter channel and the static var generator channel; The power grid impedance parameters are calculated using a real-time identification module. The filter parameters are dynamically adjusted based on the aforementioned grid impedance parameters; The compensation current is filtered by a filter to generate an output current that conforms to the power grid standard.

4. The power quality comprehensive management system as described in claim 1, characterized in that, The system uses a layered closed architecture, including: a power layer, a control layer, a redundancy layer, and a heat dissipation layer; The power layer achieves power conversion through insulated gate bipolar transistor modules and optimizes conduction performance using direct current circuit technology. The control layer achieves high-speed computation through a field-programmable gate array and employs optical isolation and shielding design to enhance anti-interference capabilities. The redundancy layer achieves automatic fault switching through parallel power units; The heat dissipation layer supports a wide operating temperature range through a temperature-controlled heat dissipation system.

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