FPGA-based double-layer redundant power supply interleaving management system

Abstract

The invention discloses a double-layer redundant power supply interleaving management system based on an FPGA (Field Programmable Gate Array). The system comprises a power supply management chip group, an FPGA power supply controller, FPGA core logic, a power supply redundancy design and a power supply switcher. Through a cooperative monitoring mechanism of multiple paths of independent power supply units, the power supply reliability of the system is remarkably improved. According to the architecture, the FPGA is used for analyzing the state of a power supply in real time, pre-judging potential faults and triggering rapid switching; multiple redundancy protection and an efficient power supply multiplexing technology are combined, so that continuous and stable operation of industrial network equipment in a severe environment is ensured. According to the method, the downtime risk caused by power supply fluctuation in an industrial control scene is effectively solved, and the power supply requirements of high-real-time and high-reliability industrial equipment are met.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of industrial equipment, in particular to a double-layer redundant power supply interlaced management system of FPGA. Through the cooperative control of multiple independent power supply units, the reliability of system power supply is significantly improved, and the continuous and stable operation of industrial network equipment in harsh environment is ensured. BACKGROUND

[0002] In the field of industrial control, the key equipment such as network switch has extremely strict requirements on the continuity of power supply. The traditional power management scheme has the following limitations: Fault response lag: the monitoring system based on MCU adopts polling mechanism, and the fault monitoring delay time is long, which cannot meet the tolerance requirements of industrial scenes; Low efficiency of redundant switching: the action time of mechanical relay or switching circuit composed of mechanical relay is long, and the device restart or data loss is easily caused during switching; Lack of prediction ability: the existing scheme can only trigger protection after voltage anomaly, and cannot predict the trend of power failure, so it is difficult to prevent sudden downtime.

[0003] Although there are some redundant power supply designs at present, they are still limited by switching speed and other bottlenecks, and it is difficult to support the requirement of high availability in network switch and other scenes. Therefore, a power management architecture with prediction ability and multiple protection is urgently needed. SUMMARY

[0004] The purpose of the present application is to provide a double-layer redundant power supply interlaced management system based on FPGA, which realizes high reliability power supply of industrial equipment through hierarchical monitoring and decision mechanism. The core of the system is to build a multi-level power supply unit array, each power supply unit is independently controlled by a dedicated power management chip, and forms a high-speed data channel with the central FPGA.

[0005] The specific technical scheme to achieve the purpose of the present application is: A double-layer redundant power supply interlaced management system based on FPGA, comprising a power management chip group module, an FPGA power control module, a bank power monitoring bus module, a power switch module and an FPGA core logic module; The power management chip group module is connected with the bank power monitoring bus module and the power switch module, and is used for voltage regulation and current distribution to ensure normal system power supply; The FPGA power control module is connected with the bank power monitoring bus module, the power switch module and the FPGA core logic module, is used for receiving the power of the power switch module, providing the electrical parameters of the currently working power supply to the FPGA core logic through the I / O interface, realizing data interaction, and realizing bidirectional data communication with the power management chip group module through the bank power monitoring bus module. The bank power monitoring bus module is connected to the power management chip group module and the FPGA power control module to realize the collaboration between power chips and the communication between various modules. The power switch module is connected to the power management chip group and the FPGA power control module, and is used to perform power supply path switching based on power status feedback. The FPGA core logic module is connected to the power switch module and is used to integrate the data monitored by the power switch module to realize voltage and power detection, early warning, and power supply path switching control; wherein: The power management chip group module includes a bank1 power management chip group, a bank2 power management chip group and a bank3 power management chip group, and each power management chip group contains two MAX16062ETG chips. The power switch module includes a bank1 power switch, a bank2 power switch and a bank3 power switch; The FPGA power control module includes FPGA power control for bank2, FPGA power control for bank3, and FPGA power control for bank1. The bank power monitoring bus module includes a bank1 power monitoring bus, a bank2 power monitoring bus, and a bank3 power monitoring bus; The power management chipset of bank1 is connected to the power monitoring bus of bank1 and the power switch of bank1. The power management chipset of bank2 is connected to the power monitoring bus of bank2 and the power switch of bank2. The power management chipset of bank3 is connected to the power monitoring bus of bank3 and the power switch of bank3. These chipset respectively realize the interaction and collaborative control of power supply status detection data between chips in the group, and provide basic power supply and local power status monitoring for the corresponding bank. The FPGA power control for bank2 is connected to the power switch for bank2, the power monitoring bus for bank1, and the FPGA core logic. The FPGA power control for bank3 is connected to the power switch for bank3, the power monitoring bus for bank2, and the FPGA core logic. The FPGA power control for bank1 is connected to the power switch for bank1, the power monitoring bus for bank3, and the FPGA core logic. It receives power from its own bank, collects voltage, current, and power parameters from adjacent banks in real time, and transmits the data to the FPGA core logic module.

[0006] Further, the bank1 power switch, bank2 power switch and bank3 power switch are internally integrated with the same characteristics of the internal pull-up open-drain output circuit of the MAX16062ETG chip, the internal pull-up current is 30 µA, supports 5.5V external voltage driving output, and can execute the same group redundant power management chip power supply switching and cross-bank emergency power supply switching according to the instructions of the FPGA core logic module.

[0007] Further, the bank1 power switch, bank2 power switch and bank3 power switch support fixed 140ms reset timeout, capacitor adjustment reset timeout and manual reset operation, and are provided with margin enable and tolerance selection input, and the tolerance setting pin selects 5% or 10% input threshold.

[0008] Further, the FPGA core logic module is integrated with a watchdog timer matched with the MAX16062ETG chip, the timeout period is 1.6s, and the watchdog timer is triggered after timeout to trigger the / RESET output, which is used for monitoring the system running state, and the watchdog timer is disabled when the WDI is floating.

[0009] Further, the power management chip group module is connected with the FPGA power control module and the FPGA core logic module through the bank power monitoring bus module, and realizes bidirectional communication through the bus; the power management chip group module reports power supply parameters and chip state information to the FPGA power control module, and the FPGA core logic module issues output adjustment and fault emergency control instructions to the power management chip group module, and the communication protocol is adapted to the data transmission requirements of the MAX16062ETG chip.

[0010] The beneficial results of the application are as follows: 1. The cross-bank interlaced power management chip set design can eliminate the risk of single point failure. When a bank power is abnormal, the same group of redundant chips and the adjacent bank power can take over to ensure the system to run continuously.

[0011] 2. The high-precision monitoring capability of the MAX16062ETG chip, combined with the FPGA core logic module, realizes the "early warning + rapid switching" of voltage and power abnormalities, and reduces the fault influence to the minimum.

[0012] 3. The internal pull-up open-drain output of the power management chip set reduces external components; the intelligent switching of the power switch replaces manual intervention, reduces design and operation and maintenance costs, and improves fault handling efficiency BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1The schematic diagram of the present application; Figure 2 The schematic diagram of the power supply chip set of the present application. DETAILED DESCRIPTION

[0014] The present application is described in detail below in combination with the drawings and examples.

[0015] The present embodiment details the specific implementation of the above-mentioned FPGA-based double-layer redundant power supply interleaving management system, and presents the process of achieving high-reliability power supply by the hardware connection and data interaction process of each module.

[0016] Referring to Figure 1 The FPGA-based double-layer redundant power supply interleaving management system of the present application comprises a power management chip group module 1, an FPGA power control module 2, a power control bank bus module 3, a power switch module 4, and an FPGA core logic module 5.

[0017] The power management chip group module 1 is connected with the bank power monitoring bus module 3 and the power switch module 4, and is used for precise voltage regulation and reasonable current distribution to ensure normal power supply of the system.

[0018] The FPGA power control module 2 is connected with the bank power monitoring bus module 3, the power switch module 4, and the FPGA core logic 5, and is used for receiving the power supply of the power switch module 4, providing the electrical parameters of the currently working power supply to the FPGA core logic 5 through an I / O interface to realize data interaction, and realizing bidirectional data communication with the power management chip group module 1 through the bank power monitoring bus module 3.

[0019] The bank power monitoring bus module 3 is connected with the power management chip group module 1 and the FPGA power control module 2, and is used for realizing the cooperation of the power chips in the group and the communication between adjacent banks.

[0020] The power switch module 4 is connected with the power management chip group module 1 and the FPGA power control module 2, and is used for executing power supply path switching according to the power state feedback.

[0021] The FPGA core logic module 5 is connected with the power switch module 4, and is used for integrating the monitoring data of each bank to realize voltage and power detection, early warning, and power supply path switching control.

[0022] The power management chip group module 1 is composed of a bank1 power management chip group 6, a bank2 power management chip group 7, and a bank3 power management chip group 8, and each group contains at least 2 power management chips.

[0023] The bank1 power management chip set 6, the bank2 power management chip set 7 and the bank3 power management chip set 8 are connected to the bank1 power monitoring bus 15, the bank2 power monitoring bus 16 and the bank3 power monitoring bus 17 of the corresponding bank power monitoring bus module 3 respectively. Meanwhile, the bank1 power switch 9, the bank2 power switch 10 and the bank3 power switch 11 of the power switch module 4 are connected, completing the output of electric energy and the uploading of state data.

[0024] The FPGA power control module 2 includes the bank2 FPGA power control 12, the bank3 FPGA power control 13 and the bank1 FPGA power control 14. Each sub-module is connected to the corresponding bank power switch at one end to obtain power supply, and is connected to the FPGA core logic 5 through an I / O interface at the other end to transmit power electrical parameters. Meanwhile, the corresponding bus of the bank power monitoring bus module 3 is connected to realize bidirectional communication with other bank power management chip sets.

[0025] The bank power monitoring bus module 3 is composed of the bank1 power monitoring bus 15, the bank2 power monitoring bus 16 and the bank3 power monitoring bus 17. Each bus is independently connected to the corresponding bank power management chip set and the cross-bank sub-module of the FPGA power control module 2, serving as a data interaction channel.

[0026] The power switch module 4 includes the bank1 power switch, the bank2 power switch and the bank3 power switch. Each switch is connected to the corresponding bank power management chip set at one end and is connected to the corresponding sub-module of the FPGA power control module 2 at the other end to receive the switching instruction of the FPGA core logic 5.

[0027] The FPGA core logic module 5 integrates an adaptive Kalman filter extended prediction algorithm, a fault prediction model and a power switching control logic. The FPGA core logic module 5 is connected to each sub-module of the FPGA power control module through a data interface to collect electrical parameters of each bank in real time.

[0028] When the double-layer redundant power supply interleaving management system of the application is connected to a network switch, taking bank 1 abnormal power supply as an example: the FPGA core logic 5 collects the bank 1 power supply parameter abnormality through the bank 1 FPGA power supply control 14, the bank 1 power management chip set 6 monitors the local power supply state in real time, synchronizes the abnormal data to the bank 2 FPGA power supply control 12 through the bank 1 power supply monitoring bus 15, and at the same time, the bank 1 FPGA power supply control 14 transmits the real-time electrical parameters to the FPGA core logic module 5 through the I / O interface. The FPGA core logic module 5 calls the built-in adaptive Kalman filter extended prediction algorithm, directly outputs the prior estimate value of the next moment according to the input real-time electrical parameters, analyzes the bank 1 power supply abnormal trend by using the prediction step of Kalman filter, determines that it is an unstable power supply state, and generates a power switching instruction containing the target redundant power supply path and the switching execution object. The FPGA core logic module 5 sends the switching instruction to the bank 1 power switch 9; the bank 1 power switch 9 disconnects the abnormal power supply path with the bank 1 power management chip set 6 according to the instruction, and connects the redundant power supply path with the bank 2 power management chip set 7. The bank 2 power management chip set 7 synchronizes the state data of the redundant power supply to the bank 1 FPGA power supply control 14 through the bank 2 power supply monitoring bus 16; the bank 1 FPGA power supply control 14 returns the restored power supply parameters to the FPGA core logic 5, and confirms that the bank 1 power supply is restored to normal. At the same time, the bank 1 power management chip set 6 enters the fault self-checking and repairing process, and if the repair is successful, it can re-connect the power supply through the bank 1 power switch 9 to supplement the redundant level.

[0029] In the normal operation mode, taking bank2 power supply as an example: the bank2 power management chip set 7 synchronizes the local power supply state data to the bank2 FPGA power control 13 through the bank2 power supply monitoring bus 16; the bank2 FPGA power control 13 transmits the stable power supply parameters to the FPGA core logic module 5 through the I / O interface. The FPGA core logic 5 calls the built-in algorithm to analyze the voltage fluctuation, power margin and other parameters of the bank2 power supply, and confirms that it is in the safe operation interval. At the same time, the chips in the bank2 power management chip set 7 cooperate through the bank2 power supply monitoring bus 16 to real-time mutual transmission of state data. If a slight load abnormality occurs in a certain chip, other chips in the group automatically adjust the output power to compensate for the load difference and maintain the stability of the bank2 power supply. The bank3 power management chip set 8 and the bank1 power management chip set 6 synchronously execute the normal monitoring process, share the state data to the FPGA power control module 2 through the corresponding bank power supply monitoring bus, and build a global power supply monitoring network. The FPGA core logic 5 integrates the data of the three banks, periodically evaluates the system power redundancy, and if it finds that the power supply voltage of a certain bank is lower than the safety threshold, it triggers the redundancy compensation process in advance: through the power supply switch module 4, the idle power of other banks is allocated to ensure the overall power supply safety of the system.

[0030] Referring to Figure 2 The power management chip set shown in the embodiment is composed of two MAX16062ETG chips and a plurality of logic devices, and is built into two independent voltage monitoring and output links with logic control, for realizing voltage abnormality detection and logic output functions.

[0031] The first MAX16062ETG chip is connected with an enable signal EN (active at high level) and is provided with working power supply by VCC. The chip monitors the input voltage state in real time. When the voltage is in the normal range, the chip maintains stable working state, and out1 outputs normal monitoring level. If the voltage is abnormal, the chip triggers / RESET signal to flip. The / RESET signal is first inverted by an inverter, and then is connected with the out1 signal to a rear-end AND gate. The AND gate performs logic operation on the two signals: only when the chip has not triggered an abnormality (the / RESET after inversion meets the normal level logic, and the out1 output is valid), the AND gate outputs out3 to maintain the valid level; if the chip detects voltage abnormality, the / RESET signal flips, the logic level changes after inversion by the inverter, the logic operation result of the AND gate changes, and the out3 output state is updated, thereby transmitting the voltage abnormality monitoring result.

[0032] The second MAX16062ETG chip is also connected to the enable signal EN and the VCC power supply, and performs the same voltage monitoring logic as the first chip. When the chip is working normally, out2 outputs a normal level, and / RESET maintains the initial state; when the voltage is abnormal, the / RESET signal flips. The / RESET signal is first inverted by an inverter, and then input to the backend AND gate together with out2. The AND gate performs logical judgment according to the input signals: only when the chip has not triggered an exception (the logic of / RESET after inversion is normal, and out2 outputs valid), out4 maintains a valid level; if the voltage triggers / RESET to flip, after the level is changed by the inverter, the AND gate outputs out4 to change the state, and completes the logical transfer of the abnormal state.

[0033] In the overall workflow, the MAX16062ETG chip uses its voltage monitoring characteristics to verify the input voltage in real time; the inverter and the AND gate form a logic control unit, which logically integrates the abnormal state of the chip ( / RESET signal) and the normal monitoring output (out1, out2), and outputs two control signals out3 and out4. This circuit uses the voltage monitoring function of a single chip to build a modular monitoring link with basic logic devices, which can flexibly adapt to voltage patrol and logic control requirements in multiple scenarios, and realize a complete functional closed loop from voltage anomaly detection to logic output.

Claims

1. An FPGA-based dual-redundant power interleaving management system, characterized in that, The power management chip group module (1), the FPGA power control module (2), the bank power monitoring bus module (3), the power switch module (4) and the FPGA core logic module (5) are connected with each other. The power management chip group module (1) is connected with the bank power monitoring bus module (3) and the power switch module (4), and is used for voltage regulation and current distribution to ensure normal power supply of the system. The FPGA power control module (2) is connected with the bank power monitoring bus module (3), the power switch module (4) and the FPGA core logic module (5), and is used for receiving power supply of the power switch module (4), providing electrical parameters of the currently working power supply to the FPGA core logic (5) through an I / O interface, realizing data interaction, and realizing bidirectional data communication with the power management chip group module (1) through the bank power monitoring bus module (3). The bank power monitoring bus module (3) is connected with the power management chip group module (1) and the FPGA power control module (2), and is used for realizing cooperation between power supply chips and communication between modules. The power switch module (4) is connected with the power management chip group (1) and the FPGA power control module (2), and is used for executing power supply path switching according to power state feedback. The FPGA core logic module (5) is connected with the power switch module (4), and is used for integrating monitored data of the power switch module (4) to realize voltage and power detection, early warning and power supply path switching control. The power management chip group module (1) comprises a bank1 power management chip group (6), a bank2 power management chip group (7) and a bank3 power management chip group (8), each power chip management group comprising two MAX16062ETG chips. The power switch module (4) comprises a bank1 power switch (9), a bank2 power switch (10) and a bank3 power switch (11). The FPGA power control module (2) comprises a bank2 FPGA power control (12), a bank3 FPGA power control (13) and a bank1 FPGA power control (14). The bank power monitoring bus module (3) comprises a bank1 power monitoring bus (15), a bank2 power monitoring bus (16) and a bank3 power monitoring bus (17). The bank1 power management chip set (6) is connected with the bank1 power monitoring bus (15) and the bank1 power switcher (9), the bank2 power management chip set (7) is connected with the bank2 power monitoring bus (16) and the bank2 power switcher (10), and the bank3 power management chip set (8) is connected with the bank3 power monitoring bus (17) and the bank3 power switcher (11), which respectively realize the power supply state detection data interaction and cooperative control between chips in the group, provide basic power supply and local power state monitoring for the corresponding bank; The bank2 FPGA power control (12) is connected with the bank2 power switcher (10), the bank1 power monitoring bus (15) and the FPGA core logic (5), the bank3 FPGA power control (13) is connected with the bank3 power switcher (11), the bank2 power monitoring bus (16) and the FPGA core logic (5), and the bank1 FPGA power control (14) is connected with the bank1 power switcher (9), the bank3 power monitoring bus (17) and the FPGA core logic (5), which receives the power supply of the bank, collects the voltage, current and power parameters of the adjacent bank in real time, and transmits the data to the FPGA core logic module (5).

2. The dual redundant power supply interleaving management system of claim 1, wherein, The bank1 power switcher (9), the bank2 power switcher (10) and the bank3 power switcher (11) are all integrated with the drain open output circuit with the same characteristics as the MAX16062ETG chip inside, the internal pull-up current is 30µA, the external voltage driving output is supported to be 5.5V, and the same group redundant power management chip power supply switching and cross-bank emergency power support switching can be performed according to the instructions of the FPGA core logic module (5).

3. The dual redundant power supply interleaving management system of claim 1, wherein, The bank1 power switcher (9), the bank2 power switcher (10) and the bank3 power switcher (11) support fixed 140ms reset timeout, capacitor adjustment reset timeout and manual reset operation, and are provided with margin enable and tolerance selection input, and the tolerance setting pin selects 5% or 10% input threshold.

4. The dual redundant power supply interleaving management system of claim 1, wherein, The FPGA core logic module (5) is integrated with the watchdog timer matched with the MAX16062ETG chip, the timeout period is 1.6s, the watchdog timer is triggered after timeout, and is used for monitoring the system running state, and the watchdog timer is disabled when the WDI is floating.

5. The dual redundant power supply interleaving management system of claim 1, wherein, The power management chip group module (1) is connected with the FPGA power control module (2) and the FPGA core logic module (5) through the bank power monitoring bus module (3), and realizes bidirectional communication through the bus; the power management chip group module (1) reports power supply parameters and chip state information to the FPGA power control module (2), and the FPGA core logic module (5) issues output adjustment and fault emergency control instructions to the power management chip group module (1), and the communication protocol adapts to the data transmission requirements of the MAX16062ETG chip.

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