Satellite-borne firmware reinforcing method and system based on industrial-grade device

Abstract

The invention relates to a satellite-borne firmware reinforcement method and system based on industrial-grade devices, all devices are selected from industrial-grade devices, targeted reinforcement design is carried out on hardware by using a specific satellite-borne irradiation reinforcement scheme, and under the conditions of smaller size, smaller weight and smaller power consumption, the satellite-borne firmware reinforcement method and system based on the industrial-grade devices can be used for reinforcing the satellite-borne firmware. The characteristics of high communication rate, high signal-to-noise ratio, strong anti-interference capability and the like are achieved, the purpose of reinforcing satellite-borne firmware by an industrial-grade device is achieved, and adverse effects caused by single event upset and the like in a space environment are effectively coped with.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of satellite-borne circuit hardening design, and relates to a satellite-borne firmware hardening method and system based on industrial-grade devices. BACKGROUND

[0002] In recent years, the information communication technology field is in a key period of overall transformation. Ground mobile communication is marching towards the 5G era with characteristics of high speed, low delay and large-scale access. The current technology has become mature. At the same time, emerging satellite Internet space information technology represented by low-orbit broadband constellation system has become an important development direction with its global, all-way and ubiquitous broadband data access capability. In this background, CPU goes to space is inevitable, and the adverse effects of space environment on the normal work of CPU are technical challenges that must be faced. Traditional satellite communication adopts high-level aerospace devices to improve the reliability in orbit, which is high in cost and long in development cycle. How to effectively deal with the adverse effects of single event upset in space environment with industrial-grade devices has become one of the technical problems to be solved. SUMMARY

[0003] In view of the problems in the above-mentioned traditional technology, the application provides a latch-based satellite-borne firmware hardening method based on industrial-grade devices and a satellite communication system, which can effectively deal with the adverse effects of single event upset in space environment with industrial-grade devices.

[0004] In order to achieve the above-mentioned purpose, the embodiments of the application adopt the following technical solutions: On the one hand, a satellite-borne firmware hardening method based on industrial-grade devices is provided, which includes the following steps: At least 3 backups of the firmware of the monitoring FPGA are stored in the NAND FLASH; the firmware backup of the monitoring FPGA in the NAND FLASH is used to update the firmware of the internal FLASH of the monitoring FPGA; At least 3 copies of the firmware of the 5G SOC are saved in the NVME of the CPU; the saved firmware of the 5G SOC in the NVME is used to update the firmware of the 5G SOC; The program files of the interface FPGA are stored in three different hardware positions of the NAND FLASH, and the firmware of the interface FPGA is loaded through Selectmap at each power-on; the three different hardware positions are configured with serial triple modular redundancy to ensure the correctness of the program file data of each hardware position; The firmware of the CPU is checked and judged during the power-on starting process of the CPU, and the CPU is started from the main QSPI FLASH when the firmware of the CPU at the three positions is correct; the firmware of the CPU includes the firmware of the CPU stored in the NAND FLASH, the firmware of the CPU stored in the main QSPI FLASH at the monitoring FPGA end, and the firmware of the CPU stored in the backup QSPI FLASH. The running state of the CPU is monitored in real time by the monitoring FPGA during the running process of the CPU.

[0005] In one embodiment, the above-mentioned spaceborne firmware reinforcement method based on industrial-grade devices further includes the steps of: During the running process of the CPU, the monitoring FPGA detects that the CPU starts abnormally and cannot periodically report the state, and then triggers the firmware backup recovery mechanism; The firmware backup recovery mechanism is: The monitoring FPGA reads the firmware of the CPU in the NAND FLASH, the main QSPI FLASH and the backup QSPI FLASH to perform check and judgment, selects the correct firmware of the CPU therefrom, and performs confirmation after rewriting the firmware of the CPU in the error memory. The main QSPI FLASH is configured to start and the CPU is reset to start.

[0006] In one embodiment, the process of updating the firmware stored in the internal FLASH of the monitoring FPGA includes: If it is checked that the firmware of the monitoring FPGA has a check error, then the firmware of the monitoring FPGA is updated by performing two-out-of-three voting on the corresponding firmware backup of the monitoring FPGA from the NAND FLASH to vote out the correct firmware of the monitoring FPGA.

[0007] In one embodiment, the above-mentioned spaceborne firmware reinforcement method based on industrial-grade devices further includes the steps of: If the 5G SOC detects a firmware check error, the 5G SOC sends a firmware update request to the CPU; The CPU selects two of the three firmware of the 5G SOC saved in the NVME and judges the correctness of the firmware, and then sends the correct firmware of the 5G SOC to the 5G SOC through the PCIE interface for firmware update.

[0008] On the other hand, a satellite communication system is also provided, which includes the spaceborne firmware reinforced by the spaceborne firmware reinforcement method based on industrial-grade devices according to any one of the above; the spaceborne firmware includes the firmware of the monitoring FPGA, the firmware of the CPU, the firmware of the 5G SOC, and the firmware of the interface FPGA.

[0009] The one of the above technical solutions has the following advantages and beneficial effects: The above-mentioned spaceborne firmware hardening method and system based on industrial-grade devices use industrial-grade devices for device selection, and the hardware is subjected to targeted strengthening design by using a specific spaceborne irradiation hardening scheme, so that the characteristics of high communication rate, high signal-to-noise ratio and strong anti-interference ability are achieved in the case of smaller volume, smaller weight and smaller power consumption, the purpose of realizing spaceborne firmware hardening by using industrial-grade devices is achieved, and the adverse effects caused by single event upsets in the space environment are effectively coped with. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0011] Figure 1 The flowchart of the spaceborne firmware hardening method based on industrial-grade devices in one embodiment is shown in the figure. Figure 2 The spaceborne firmware hardening scheme block diagram in one embodiment is shown in the figure. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical solutions and advantages of the present application more clear, the present application will be further described in detail in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by those skilled in the art of the present application. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments and are not intended to limit the present application.

[0013] It should be noted that the reference to "embodiments" in this document means that the specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase is shown at various places in the specification does not necessarily refer to the same embodiment, nor is it independent or alternative to other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments.

[0014] The embodiments of the present application will be described in detail below in combination with the drawings in the embodiments of the present application.

[0015] In one embodiment, as Figure 1As shown, a satellite-based firmware hardening method based on industrial-grade devices is provided, which can include the following processing steps S12-S20: S12, at least 3 backups of the firmware of the monitoring FPGA are stored in the NAND FLASH; the firmware backup of the monitoring FPGA in the NAND FLASH is used for firmware update of the firmware stored in the internal FLASH of the monitoring FPGA; S14, at least 3 copies of the firmware of the 5G SOC are saved in the NVME of the CPU; the firmware of the 5G SOC saved in the NVME is used for firmware update of the 5G SOC; S16, the program file of the interface FPGA is stored in three different hardware positions of the NAND FLASH, and the firmware of the interface FPGA is loaded through Selectmap at each power-on; the three different hardware positions ensure the correctness of the program file data in each hardware position through configured serial triple modular redundancy; S18, the firmware of the CPU is verified and judged during the power-on starting process of the CPU, and the CPU is started from the main QSPI FLASH when the firmware of the CPU in the three positions is correct; the firmware of the CPU in the three positions includes the firmware of the CPU stored in the NAND FLASH, the firmware of the CPU stored in the main QSPI FLASH of the monitoring FPGA, and the firmware of the CPU stored in the backup QSPI FLASH; S20, the running state of the CPU is monitored in real time by the monitoring FPGA during the running process of the CPU.

[0016] It can be understood that the satellite-based firmware hardening scheme in the embodiment includes CPU, monitoring FPGA (Field - Programmable Gate Array, Field - Programmable Gate Array), clock module, power module, 5G SOC, interface FPGA and high-performance NAND FLASH in the satellite communication system. Among them, NAND FLASH is a kind of FLASH Memory, which belongs to non-volatile storage technology, that is, even if the device is powered off, the data stored will not be lost. The name of NAND FLASH comes from its circuit structure, the relationship between bit line and word line is similar to "NAND" logic gate, it is composed of floating - gate MOSFETs to form storage unit, these storage units are arranged in matrix form, data is stored in the form of electrons in the floating gate of the storage unit, different data states are represented by controlling the number of electrons on the floating gate.

[0017] NOR FLASH is a type of FLASH Memory, which belongs to non-volatile memory, that is, the stored data will not be lost even if the device is powered off. NOR FLASH is composed of a large number of storage units, each of which is essentially a metal oxide semiconductor field effect transistor (MOSFET), which stores data by controlling the electrons on the floating gate of the transistor. The storage units are arranged in an array and accessed by addressing through word lines and bit lines. When reading NOR FLASH, the word line applies the appropriate voltage to select the corresponding storage unit, and the current or voltage state of the bit line is detected to determine whether the stored data is "0" or "1".

[0018] Firmware refers to program code or configuration data stored in non-volatile storage units (such as FLASH memory) or external configuration chips, which defines the logical functions and behaviors of corresponding chips or circuit modules. Firmware is essentially a series of configuration information, which exists in the form of binary data. By loading different firmware, corresponding chips or circuit modules can implement various functions such as digital signal processing, image processing, or communication protocol processing.

[0019] The firmware of the interface FPGA is stored in the hardware design of the NAND FLASH that monitors the FPGA. The program file is stored in three different hardware locations of the NAND FLASH. The probability of an abnormality occurring simultaneously and in the same location in the three different hardware locations is extremely low. The firmware of the interface FPGA is loaded through Selectmap (a configuration method for FPGAs, mainly used to load configuration data through a parallel interface) each time the power is turned on. In software design, a serial triple module is provided at each hardware location of the NAND FLASH to ensure the correctness of the program file data at each hardware location. Through the above two triple module redundancy data processing, the probability of data abnormality is close to 0.

[0020] Among them, serial triple module is a technical means to improve system reliability and data correctness, and its full name is serial triple module redundancy (Triple Modular Redundancy, TMR). Its core idea is to tolerate errors through hardware or software redundancy. In critical hardware locations or program execution links, three identical modules (which can be hardware circuit modules or software program modules) are set up to process the same set of data or instructions simultaneously. After processing, a voter is used to vote on the output results of the three modules, and the output result of at least two modules that are the same is selected as the final output. In this way, even if one of the modules fails and outputs an incorrect result, it will not affect the final output because the outputs of the other two normal modules will occupy the majority, thereby ensuring the correctness of the output data.

[0021] The above-mentioned spaceborne firmware hardening method based on industrial-grade devices uses specific spaceborne irradiation hardening schemes to perform targeted hardening design on the hardware, and achieves the characteristics of high communication rate, high signal-to-noise ratio, and strong anti-interference ability in the case of smaller volume, smaller weight, and smaller power consumption, so as to achieve the purpose of realizing spaceborne firmware hardening with industrial-grade devices, and effectively cope with the adverse effects of single event upset in space environment.

[0022] In one embodiment, further, the process of updating the firmware of the internal FLASH storage of the monitoring FPGA can include: If it is found that the firmware of the monitoring FPGA has a check error, the firmware of the internal FLASH storage of the monitoring FPGA is updated by voting for the correct firmware of the monitoring FPGA through two out of three from the firmware backup of the monitoring FPGA in the NAND FLASH.

[0023] It can be understood that the firmware hardening method of the monitoring FPGA is that at least three backups of the firmware of the monitoring FPGA are stored in the NAND FLASH, and at the same time, a task is configured to periodically check and verify the firmware stored in the internal FLASH of the monitoring FPGA. If it is found that the firmware has a check error, the firmware of the internal FLASH storage of the monitoring FPGA is updated by voting for the correct firmware of the monitoring FPGA through two out of three from the firmware backup in the NAND FLASH.

[0024] By storing at least three (the number of backups can be selected flexibly according to the actual resource amount; as long as the required hardening effect can be ensured) firmware backups of the monitoring FPGA in the NAND FLASH, the correct firmware of the monitoring FPGA can be voted out in a system working process supporting at least three-mode redundancy to update the firmware stored in the internal FLASH of the monitoring FPGA, so that the firmware is correct, and the traditional space-grade devices do not need to be used for hardening to achieve the hardening goal of this part.

[0025] In one embodiment, further, the above-mentioned spaceborne firmware hardening method based on industrial-grade devices further includes the following steps: During the running of the CPU, the monitoring FPGA detects that the CPU startup is abnormal and cannot periodically report the state, and then triggers the firmware backup recovery mechanism. The firmware backup recovery mechanism is: The monitoring FPGA reads the firmware of the CPU in the NAND FLASH, the main QSPI FLASH, and the backup QSPI FLASH to perform check judgment and selects the correct firmware of the CPU therefrom, and then confirms the firmware of the CPU in the error storage after being written. The main QSPI FLASH is configured to start and the CPU is reset to reset and start.

[0026] It can be understood that the firmware reinforcement mode of the CPU includes a firmware reinforcement processing mode in a power-on starting process and a firmware reinforcement processing mode in a running process.

[0027] In the power-on starting process, the firmware of the CPU includes the firmware of the CPU stored in the NAND FLASH, the firmware of the CPU stored in the main QSPI FLASH at the monitoring FPGA end, and the firmware of the CPU stored in the internal backup QSPI FLASH. The firmware of the CPU is verified and judged each time the power is turned on, including mutual comparison of the three firmwares, and the firmware of the CPU itself. If the three firmwares are normal, the main QSPI FLASH is directly started, otherwise, the firmware backup recovery mechanism is triggered. QSPI is the abbreviation of Quad SPI, which represents a 6-wire SPI interface.

[0028] In the running process, the monitoring FPGA monitors the running state of the CPU in real time. If it is judged that the CPU starts abnormally and cannot periodically report the state, the firmware backup recovery mechanism is triggered. The firmware backup recovery mechanism is that the monitoring FPGA reads the firmware in the NAND FLASH, the main QSPI FLASH, and the backup QSPI FLASH to verify and judge, including mutual comparison of the three firmwares, and the firmware of the CPU itself. The correct firmware of the CPU is selected from the NAND FLASH, the main QSPI FLASH, and the backup QSPI FLASH, the firmware in the error storage is written, and after the writing is completed, it is confirmed, and then the main QSPI FLASH is configured to start and the CPU is reset to reset and start.

[0029] The main SPI FLASH and the backup SPI FLASH are two SPI interface flash chips in the "main backup redundancy" design scheme in the embedded system to improve the storage reliability. Its core function is to guarantee the safety of critical data (such as firmware and configuration information) and the stability of the system through double backup.

[0030] Through the above-mentioned firmware reinforcement mode design of the CPU, automatic firmware verification and recovery can be performed throughout the working process of the CPU in space, so that the firmware is always correct, and traditional space-grade devices do not need to be used for reinforcement to achieve the reinforcement goal of this part.

[0031] In one embodiment, the above-mentioned spaceborne firmware reinforcement method based on industrial-grade devices can further include the following steps: If the 5G SOC detects a firmware check error, a firmware update request is sent to the CPU; The CPU selects two of the three firmware of the 5G SOC saved in the NVME and judges the correctness of the firmware, and then sends the correct firmware of the 5G SOC to the 5G SOC through the PCIE interface for firmware update.

[0032] It can be understood that the firmware of the 5G SOC (i.e. an intelligent core component integrating the functions of 5G baseband, processor, and graphics processor) is saved in the NVME (i.e. Non-Volatile Memory Express) of the CPU and at least three copies are saved. If the 5G SOC detects a firmware check error, a firmware update request is sent to the CPU. The CPU selects two of the three firmware of the 5G SOC saved in the NVME and judges the correctness of the firmware, and then sends the correct firmware of the 5G SOC to the 5G SOC through the PCIE interface for firmware update, so that the firmware is correct, and traditional space-grade devices are not required to achieve the reinforcement goal of this part.

[0033] In one embodiment, a satellite communication system is also provided, which includes the on-board firmware reinforced based on the on-board firmware reinforcement method based on industrial-grade devices according to any of the above. The on-board firmware includes the firmware of the monitoring FPGA, the firmware of the CPU, the firmware of the 5G SOC, and the firmware of the interface FPGA.

[0034] The satellite communication system described above effectively improves the single event upset resistance of the on-board firmware in the system by applying the on-board firmware reinforcement method based on industrial-grade devices, thereby improving the reliability of the system in a high-energy particle irradiation environment.

[0035] The technical features of the above embodiments can be combined in any way. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present disclosure.

[0036] The above embodiments only express several embodiments of the present application, which are described in detail and specifically, but should not be considered as a limitation on the scope of protection. It should be noted that for those skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the scope of protection of the present application.

Claims

1. A spaceborne firmware hardening method based on industrial grade devices, characterized in that, The method comprises the steps of: At least three backups of the firmware of the monitoring FPGA are stored in the NAND FLASH; the firmware backup of the monitoring FPGA in the NAND FLASH is used to update the firmware of the internal FLASH of the monitoring FPGA; At least three copies of the firmware of the 5G SOC are saved in the NVME of the CPU; The firmware of the 5G SOC saved in the NVME is used to update the firmware of the 5G SOC; The program files of the interface FPGA are stored in three different hardware positions of the NAND FLASH, and the firmware of the interface FPGA is loaded through Selectmap at each power-on; During the power-on starting process of the CPU, the firmware of the CPU is checked and judged, and the CPU is started from the main QSPI FLASH when the firmware of the CPU in the three positions is correct; the firmware of the CPU in the three positions includes the firmware of the CPU stored in the NAND FLASH, the firmware of the CPU stored in the main QSPI FLASH of the monitoring FPGA, and the firmware of the CPU stored in the backup QSPI FLASH; During the running process of the CPU, the running state of the CPU is monitored in real time by the monitoring FPGA.

2. The industrial grade device based space-borne firmware hardening method of claim 1, wherein, The method further comprises the steps of: During the running process of the CPU, the monitoring FPGA detects that the CPU starts abnormally and cannot periodically report the state, and then triggers the firmware backup recovery mechanism; The firmware backup recovery mechanism comprises the steps of: The monitoring FPGA reads the firmware of the CPU in the NAND FLASH, the main QSPI FLASH and the backup QSPI FLASH, checks and judges, selects the correct firmware of the CPU therefrom, writes the firmware of the CPU in the error storage, and confirms; The main QSPI FLASH is configured to start and the CPU is reset.

3. The industrial grade device based on-board firmware hardening method according to claim 1 or 2, characterized in that, The process of updating the firmware of the internal FLASH of the monitoring FPGA comprises the steps of: If it is checked that the firmware of the monitoring FPGA has a check error, then two of the firmware of the monitoring FPGA are selected from the firmware backup of the monitoring FPGA in the NAND FLASH, the correct firmware of the monitoring FPGA is voted, and the firmware of the internal FLASH of the monitoring FPGA is updated.

4. The industrial grade device based on-board firmware hardening method according to claim 1 or 2, c h a r a c t e r i z e d b y, The method further comprises the steps of: If the 5G SOC detects a firmware check error, the 5G SOC sends a firmware update request to the CPU; The CPU selects two copies of the firmware of the 5G SOC from the three copies of the firmware of the 5G SOC saved in the NVME, judges the correctness of the firmware, and then sends the correct firmware of the 5G SOC to the 5G SOC through the PCIE interface to update the firmware.

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