General hash function class randomness extraction method and device

Abstract

The invention provides a general hash function class randomness extraction method and device, which can be applied to the technical fields of quantum key distribution, cryptography, information security and hardware acceleration. The method comprises the following steps: performing data buffering processing on an original random data stream to obtain an original random number sequence which has a first fixed length and is used for a universal hash function class; performing data slicing processing on the original random number sequence to obtain a plurality of random number subsequences with the same data length; performing finite field multiplication on the plurality of random number subsequences to obtain a plurality of finite field multiplication results; performing bitwise exclusive-or operation on the plurality of finite field multiplication operation results to obtain a plurality of bitwise exclusive-or operation results; and performing data splicing processing on the plurality of bitwise XOR operation results to obtain a target random number sequence with a second fixed length. The method provided by the invention overcomes the limitation of the prior art in the aspects of calculation efficiency and random seed length.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of quantum key distribution, cryptography, information security and hardware acceleration, in particular to a general hash function family randomness extraction method and device. BACKGROUND

[0002] In a secure communication system, a key step is privacy amplification. The purpose of privacy amplification is to extract a short but highly secret new random sequence from a partially leaked random source to an eavesdropper by applying a public random hash function. The efficiency and security of the process depend largely on the hash function used.

[0003] In the prior art, some special matrix structures with constant diagonal characteristics are usually used for matrix multiplication or universal hash function family (Universal Hash Function Family, or Universal Hash Function Class) to realize privacy amplification. However, these methods often sacrifice computational efficiency while pursuing the minimization of random seed length. For example, although some theoretical hash functions can achieve extremely short seed length, their hardware or software implementation complexity is high, which is difficult to meet the needs of high-throughput real-time communication systems. SUMMARY

[0004] In view of the above problems, the present application provides a general hash function family randomness extraction method and device for at least solving one of the above technical problems.

[0005] According to a first aspect of the present application, a general hash function family randomness extraction method is provided, comprising: performing data buffering processing on an original random data stream to obtain an original random number sequence with a first fixed length and used for a general hash function family; performing data slicing processing on the original random number sequence to obtain a plurality of random number sub-sequences with the same data length; performing finite field multiplication operation on the plurality of random number sub-sequences to obtain a plurality of finite field multiplication operation results; performing bitwise XOR operation on the plurality of finite field multiplication operation results to obtain a plurality of bitwise XOR operation results; and performing data splicing processing on the plurality of bitwise XOR operation results to obtain a target random number sequence with a second fixed length.

[0006] According to an embodiment of the present application, the above data buffering processing on the original random data stream to obtain the original random number sequence with the first fixed length and used for the general hash function family comprises: verifying the random data stream with random length in each clock cycle by using an original random number valid signal to obtain a valid random data stream; accumulating the valid random data streams in a plurality of clock cycles to obtain the original random data stream; and performing data buffering processing on the original random data stream to obtain the original random number sequence with the first fixed length and used for the general hash function family.

[0007] According to the embodiment of the present application, the above-mentioned performing finite field multiplication operation on the plurality of random number subsequences to obtain a plurality of finite field multiplication operation results comprises: in the process of performing the first finite field multiplication operation, multiplying the first power of the random seed sequence with the first random number subsequence to obtain the first finite field multiplication operation result, wherein, represents the number of the plurality of random number subsequences; in the process of performing the n-th finite field multiplication operation, multiplying the n-th power of the random seed sequence with the (n-1)-th finite field multiplication operation result to obtain the n-th finite field multiplication operation result, wherein, is a positive integer and n . is a positive integer and n . .

[0008] According to the embodiment of the present application, the above-mentioned in the process of performing the n-th finite field multiplication operation, multiplying the n-th power of the random seed sequence with the (n-1)-th finite field multiplication operation result to obtain the n-th finite field multiplication operation result comprises: multiplying the n-th power of the random seed sequence with the (n-1)-th finite field multiplication operation result to obtain an n-th intermediate polynomial multiplication result; performing modulo polynomial simplification on the n-th intermediate polynomial multiplication result according to a preset irreducible polynomial to obtain the n-th finite field multiplication operation result, wherein the highest power of the preset irreducible polynomial is the same as the data length of the random number subsequence.

[0009] According to the embodiment of the present application, the above-mentioned performing bitwise XOR operation on the plurality of finite field multiplication operation results in parallel to obtain a plurality of bitwise XOR operation results comprises: performing bitwise XOR operation on the first finite field multiplication operation result and the first random number subsequence in parallel to obtain the first bitwise XOR operation result, wherein, is a positive integer and n . .

[0010] According to the embodiment of the present application, the above-mentioned original random data stream is a digital sequence generated by detecting and quantifying a quantum physical entropy source.

[0011] ​​​​​​​​​​​​​According to an embodiment of the present application, the original random data stream is a digital sequence obtained by quantum communication parties through a quantum channel after negotiation.

[0012] According to a second aspect of the present application, a general hash function class randomness extraction device is provided, comprising: a data buffering module for performing data buffering processing on an original random data stream to obtain a first fixed-length original random number sequence for a general hash function class; a data slicing module for performing data slicing processing on the original random number sequence to obtain a plurality of random number subsequences with the same data length; a finite field multiplication module for performing finite field multiplication operation on the plurality of random number subsequences to obtain a plurality of finite field multiplication operation results; a bitwise XOR operation module for performing bitwise XOR operation on the plurality of finite field multiplication operation results to obtain a plurality of bitwise XOR operation results; and a data splicing module for performing data splicing processing on the plurality of bitwise XOR operation results to obtain a target random number sequence with a second fixed length.

[0013] According to an embodiment of the present application, the number of finite field multiplication modules is less than the number of random subsequences; each finite field multiplication module comprises a polynomial multiplication unit, an irreducible polynomial storage unit and a modulo polynomialization simple element; and all finite field multiplication modules are connected in a cascading manner.

[0014] According to an embodiment of the present application, the data buffering module, the data slicing module, the finite field multiplication module, the bitwise XOR operation module and the data splicing module are connected through a pipeline architecture.

[0015] The general hash function class randomness extraction method provided by the present application slices an original random data stream into a plurality of random number subsequences with the same length, and performs finite field multiplication operation and bitwise XOR operation on the plurality of random number subsequences in parallel to obtain a target random number sequence with a fixed length, thereby overcoming the limitations of the prior art in terms of calculation efficiency and random seed length, realizing high parallelism and low delay, and significantly reducing the required random seed length, and having a wide application prospect in the fields of quantum key distribution, password security, information security and hardware acceleration. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application taken with reference to the accompanying drawings, in which:

[0017] Figure 1 A scenario diagram of application of the general hash function class randomness extraction method according to an embodiment of the present application is schematically shown;

[0018] Figure 2A flow chart of a general hash function family randomness extraction method according to an embodiment of the present application is schematically shown;

[0019] Figure 3 A structural block diagram of a general hash function family randomness extraction apparatus according to an embodiment of the present application is schematically shown;

[0020] Figure 4 A structural schematic diagram of a finite field multiplication module is schematically shown;

[0021] Figure 5 A block diagram of an electronic device adapted to implement a general hash function family randomness extraction method according to an embodiment of the present application is schematically shown. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It is to be understood, however, that these descriptions are merely exemplary and are intended to interpret the scope of the present application. In the following detailed description of the embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that the embodiments of the present application can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring aspects of the present application.

[0023] The terms used herein are merely used to describe specific embodiments, and are not intended to limit the present application. The terms "include" and "have" and the like used herein indicate the presence of the described features, steps, operations, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

[0024] All terms used herein, including technical and scientific terms, have the same meanings as those generally understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having meanings consistent with the context of the present description, and should not be interpreted in an idealized or overly formal manner.

[0025] In the case of using expressions similar to "at least one of A, B, and C, etc.", it is generally to be interpreted as including one or more of the same as the meaning generally understood by one of ordinary skill in the art (for example, "a system having at least one of A, B, and C" should include a system having A alone, a system having B alone, a system having C alone, a system having A and B together, a system having A and C together, a system having B and C together, and / or a system having A, B, and C together, etc.).

[0026] Privacy amplification and randomness extraction are the core technologies of quantum key distribution (QKD) and secure communication systems, and the core goal is to extract a short random sequence with high security from a random source that may be partially leaked. Among them, Toeplitz matrix multiplication uses the linear algebraic properties of Toeplitz matrix to compress the random source through matrix-vector multiplication. However, Toeplitz matrix multiplication has the disadvantage that the balance between seed length optimization and computational efficiency is difficult to achieve, and in addition, Toeplitz matrix multiplication also has the problem of poor real-time performance, which is difficult to meet the throughput demand of high-speed quantum key distribution systems. In the process of using a family of hash functions to map the input random sequence to a shorter random sequence, there are problems of sacrificing computational efficiency and being difficult to scale up deployment on hardware, therefore, there is an urgent need for a privacy amplification hash function that can both maintain efficient implementation and significantly reduce the length of the random seed.

[0027] In order to at least solve one of the problems of the prior art, the present application provides a general hash function class randomness extraction method and device for efficiently performing randomness extraction of a general hash function class (i.e. a family of general hash functions), overcoming the limitations of prior art solutions, achieving high parallelism and low latency, while significantly reducing the demand for random seed length.

[0028] Figure 1 An application scenario diagram of the general hash function class randomness extraction method according to an embodiment of the present application is schematically shown.

[0029] As shown in Figure 1 The application scenario 100 according to this embodiment can include quantum key distribution, cryptographic security, information security, hardware acceleration, or other scenarios that require high-speed data randomness extraction and privacy amplification, etc. The network 104 is used to provide a communication link medium between the first terminal device 101, the second terminal device 102, the third terminal device 103 and the server 105. The network 104 can include various connection types, such as wired, wireless communication links, or optical fiber cables, etc.

[0030] Users can use the first terminal device 101, the second terminal device 102, the third terminal device 103 to interact with the server 105 through the network 104 to receive or send messages, etc. Various communication client applications can be installed on the first terminal device 101, the second terminal device 102, the third terminal device 103, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social platform software, etc. (only as an example).

[0031] The first terminal device 101, the second terminal device 102, and the third terminal device 103 can be various electronic devices with a display screen and supporting web browsing, including but not limited to a smart phone, a tablet computer, a laptop computer, a desktop computer, and the like.

[0032] The server 105 can be a server providing various services, for example, a background management server supporting a website browsed by a user using the first terminal device 101, the second terminal device 102, and the third terminal device 103 (only as an example). The background management server can perform analysis and the like on received user requests and the like, and feed back a processing result (for example, a web page, information, or data, or the like, obtained or generated according to a user request) to a terminal device.

[0033] It should be noted that the general hash function class randomness extraction method provided by the embodiment of the present application can be generally executed by the server 105. Correspondingly, the general hash function class randomness extraction device provided by the embodiment of the present application can be generally arranged in the server 105. The general hash function class randomness extraction method provided by the embodiment of the present application can also be executed by a server or a server cluster different from the server 105 and capable of communicating with the first terminal device 101, the second terminal device 102, the third terminal device 103, and / or the server 105. Correspondingly, the general hash function class randomness extraction device provided by the embodiment of the present application can also be arranged in a server or a server cluster different from the server 105 and capable of communicating with the first terminal device 101, the second terminal device 102, the third terminal device 103, and / or the server 105.

[0034] It should be understood that the number of terminal devices, networks, and servers in the system 100 is only illustrative. According to the implementation needs, there can be any number of terminal devices, networks, and servers. Figure 1

[0035] The following will be described based on the scenario described in the foregoing. Figure 1 The general hash function class randomness extraction method of the disclosed embodiment will be described in detail. Figures 2-4

[0036] Figure 2 An illustrative flowchart of the general hash function class randomness extraction method according to the embodiment of the present application is shown.

[0037] As shown in Figure 2 , the general hash function class randomness extraction method includes operations S210 to S250.

[0038] In operation S210, the original random data stream is subjected to data buffering processing to obtain an original random number sequence with a first fixed length and for a general hash function class. ​​

[0039] The operation S210 aggregates the continuous input random data stream (such as the bit stream output by the quantum random number generator, i.e. the original random data stream is obtained from the continuous input of multiple random data streams) into a data block (i.e. the original random data stream) with a fixed length (for example, the length of the data block is equal to the required input bit number).

[0040] According to an embodiment of the present application, the original random data stream is a digital sequence generated by detecting and quantifying a quantum physical entropy source; or the original random data stream is a digital sequence obtained by quantum communication parties through quantum channel negotiation in the field of quantum key distribution.

[0041] In operation S220, the original random number sequence is subjected to data slicing processing to obtain multiple random number sub-sequences with the same data length.

[0042] The operation S220 divides the original random number sequence into equal-length sub-sequences to ensure consistency in operation.

[0043] The original random sequence after data buffering is subjected to data slicing, which is equally divided into random number sub-sequences with a length of , wherein represents the number of random number sub-sequences, represents the first fixed length, represents the second fixed length.

[0044] In operation S230, the multiple random number sub-sequences are subjected to finite field multiplication operation to obtain multiple finite field multiplication operation results.

[0045] In operation S240, the multiple finite field multiplication operation results are subjected to bitwise XOR operation to obtain multiple bitwise XOR operation results.

[0046] The bitwise XOR operation result is one of the sub-sequences of the final random number sequence.

[0047] The bitwise XOR operation is performed on the finite field multiplication operation result and the random number sub-sequence through parallel architecture or pipeline to obtain multiple bitwise XOR operation results.

[0048] In operation S250, the multiple bitwise XOR operation results are subjected to data splicing processing to obtain a target random number sequence with the second fixed length.

[0049] The bitwise XOR operation result is one of the sub-sequences of the final random number sequence. and are unequal positive integers. ​

[0050] The general hash function class random sequence extraction method provided by the application cuts an original random data stream into multiple random number subsequences with the same length, and performs finite field multiplication operation and bitwise XOR operation on the multiple random number subsequences in parallel to obtain a target random number sequence with a fixed length, thereby overcoming the limitations of the prior art in calculation efficiency and random seed length, realizing high parallelism and low delay, and being capable of significantly reducing the required random seed length and having a wide application prospect in the fields of quantum key distribution, password security, information security and hardware acceleration.

[0051] The application aims to provide a mapping of , and a hardware architecture for implementing the mapping, wherein represents a random seed sequence, represents the i-th random number subsequence.

[0052] According to the embodiment of the application, the data buffering processing of the original random data stream to obtain the original random number sequence for the general hash function class and with the first fixed length comprises: verifying the random data stream with a random length in each clock cycle by using an original random number valid signal to obtain a valid random data stream; accumulating the valid random data streams in multiple clock cycles to obtain an original random data stream; and performing data buffering processing on the original random data stream to obtain the original random number sequence for the general hash function class and with the first fixed length.

[0053] The clock cycle verification and accumulation mechanism of the above embodiment effectively eliminates the timing correlation in the physical entropy source; meanwhile, the sampling window can be dynamically adjusted to adapt to physical entropy sources with different qualities. In hardware acceleration, the output fixed length sequence can be directly used as the seed of a related algorithm or used to initialize the key generation module of a post-quantum cryptographic algorithm.

[0054] The original random data stream with n bits (i.e., the original random data stream and the original random number sequence have the same length) is divided into s-bit subsequences, i.e. .

[0055] According to the embodiment of the application, the finite field multiplication operation on the multiple random number subsequences to obtain multiple finite field multiplication results comprises: in the process of the first finite field multiplication operation, multiplying the first power of the random seed sequence with the i-th random number subsequence to obtain the first finite field multiplication result, wherein represents the number of the multiple random number subsequences; and in the process of the i-th finite field multiplication operation, multiplying the i-th power of the random seed sequence with the i-th random number subsequence to obtain the i-th finite field multiplication result. ​​​​During the finite field multiplication operation, the random seed sequence is... The power and the first Multiplying the results of the finite field multiplication operation of the first operation yields the result of the second operation. The results of multiplication operations in finite fields, where are positive integers and .

[0056] According to an embodiment of the present invention, the above-described process of performing the first... During the finite field multiplication operation, the random seed sequence is... The power and the first Multiplying the results of the finite field multiplication operation of the first operation yields the result of the second operation. The result of a finite field multiplication operation includes: the result of a random seed sequence. The power and the first Perform polynomial multiplication on the result of the finite field multiplication operation to obtain the th . The result of multiplying the intermediate polynomials; based on the pre-defined irreducible polynomial, the result of multiplying the intermediate polynomials; Multiplying the intermediate polynomials together, we perform modular polynomial simplification to obtain the th... The result of a finite field multiplication operation, wherein the highest power of the pre-defined irreducible polynomial is the same as the data length of the random number subsequence.

[0057] The above embodiments, through a collaborative design of power iteration and polynomial modular arithmetic, achieve a breakthrough in computational efficiency while maintaining high randomness, making them particularly suitable for real-time key processing scenarios in quantum key distribution systems; through the random seed sequence... The exponentiation is multiplied by the progressively increasing historical results, resulting in an exponentially increasing algebraic complexity, which can effectively resist algebraic attacks; the second... The operation reuses the first This reduces redundant calculations. In terms of hardware acceleration, the polynomial modular arithmetic employs shift-XOR optimization, significantly reducing resource consumption.

[0058] According to an embodiment of the present invention, the above-described method of performing a bitwise XOR operation on the results of multiple finite field multiplications in parallel to obtain multiple bitwise XOR operation results includes: [The following is a partial translation of the original text, which is incomplete and requires further context.] The result of the first finite field multiplication operation is the same as the first... Perform bitwise XOR operations on the nth random number subsequence in parallel to obtain the nth random number subsequence. The result of a bitwise XOR operation, where... are positive integers and .

[0059] Perform a bitwise XOR (addition) operation between the result of the finite field multiplication and the corresponding random number subsequence, i.e., calculate... , ,…, wherein represents a bitwise XOR operator.

[0060] Based on the above general hash function class randomness extraction method, the application further provides a general hash function class randomness extraction device. The device will be described in detail below. Figure 3

[0061] Figure 3 A structural block diagram of the general hash function class randomness extraction device according to an embodiment of the application is schematically shown.

[0062] As Figure 3 shown, the general hash function class randomness extraction device 300 of this embodiment includes a data buffering module 310, a data slicing module 320, a finite field multiplication module 330, a bitwise XOR operation module 340, and a data splicing module 350.

[0063] The data buffering module 310 is configured to perform data buffering processing on the original random data stream to obtain a first fixed-length original random number sequence for the general hash function class. In an embodiment, the data buffering module 310 can be configured to perform the operation S210 described above, and thus no further description is given here.

[0064] The data slicing module 320 is configured to perform data slicing processing on the original random number sequence to obtain a plurality of random number subsequences with the same data length. In an embodiment, the data slicing module 320 can be configured to perform the operation S220 described above, and thus no further description is given here.

[0065] The finite field multiplication module 330 is configured to perform finite field multiplication operation on the plurality of random number subsequences to obtain a plurality of finite field multiplication operation results. In an embodiment, the finite field multiplication module 330 can be configured to perform the operation S230 described above, and thus no further description is given here.

[0066] The bitwise XOR operation module 340 is configured to perform bitwise XOR operation on the plurality of finite field multiplication operation results to obtain a plurality of bitwise XOR operation results. In an embodiment, the bitwise XOR operation module 340 can be configured to perform the operation S240 described above, and thus no further description is given here.

[0067] The data splicing module 350 is configured to perform data splicing processing on the plurality of bitwise XOR operation results to obtain a target random number sequence with a second fixed length. In an embodiment, the data splicing module 350 can be configured to perform the operation S250 described above, and thus no further description is given here.

[0068] ​The randomness extraction device based on the general hash function provided by this invention overcomes the limitations of existing technologies in terms of computational efficiency and random seed length. This invention maps the core algorithm of the general hash function to... Figure 3 The parallel hardware architecture shown implements efficient parallel multiplication and XOR operations over finite fields through dedicated hardware computing units. The device includes a data buffer module 310, a data slicing module 320, several parallel finite field multiplication modules 330, several parallel bitwise XOR operation modules 340, and a data concatenation module 350, achieving high parallelism and low latency, and significantly reducing the required random seed length. The hardware implementation method and system disclosed in this invention can be applied to data processing in fields such as quantum key distribution (QKD), secure communication, and quantum random number generation.

[0069] The data buffer module 310 is configured to receive the original random data stream and aggregate it into a fixed-length buffer. The original random number sequence.

[0070] The data slicing module 320 is configured to slice the data into slices. The original 1-bit random number sequence is divided into L s-bit random number subsequences and distributed to... A parallel finite field multiplication module 330.

[0071] Among them, several ( The finite field multiplication modules 330 are configured to be set up in parallel, each of which is configured to receive a corresponding data block (where the first finite field multiplication module receives a random number subsequence, and the other finite field multiplication modules receive the operation result of the previous finite field multiplication module) and an input based on a random seed sequence, and perform finite field multiplication operations.

[0072] Each finite field multiplication module 330 is configured to multiply in a finite field. The multiplication operation is performed by multiplying the input polynomials and then dividing by a preset value. This is achieved by modulo taking an irreducible polynomial.

[0073] Several finite field multiplication modules 330 are implemented in a cascaded manner, wherein the first finite field multiplication module 330 receives the last random number subsequence (the... The finite field multiplication module 330 receives the output of the previous finite field multiplication module 330 and the random seed sequence as input, thereby generating the multiple intermediate results in sequence.

[0074] Among them, several ( one) bit-wise XOR operation module 340, each of which is configured to perform bit-wise XOR operation between the operation result of the corresponding one finite field multiplication module and the corresponding one random number sub-sequence; the first bit-wise XOR operation module 340 (wherein from 1 to is configured to receive the first random number sub-sequence and the result of the first finite field multiplication module 330 as input, and output the bit-wise XOR value of the two.

[0075] The data splicing module 350 is configured to splice the outputs of all the XOR operation modules to form a final random number sequence (i.e. target random number sequence) of bits and output, i.e. the data splicing module 350 splices the bit-wise XOR results of bit-wise XOR operation modules 340 in sequence to form a final random number sequence (i.e. target random number sequence) of bits in length.

[0076] The data buffering module 310 outputs a data preparation signal after completing the aggregation of one bit original random data stream, to trigger the downstream data slicing module 320, finite field multiplication module 330 and bit-wise XOR operation module 340 to start processing.

[0077] According to the embodiments of the present application, the number of the above-mentioned finite field multiplication modules is less than the number of random sub-sequences; each finite field multiplication module includes a polynomial multiplication unit, an irreducible polynomial storage unit and a modulo polynomialization simple unit; all the finite field multiplication modules are connected in a cascading manner.

[0078] The finite field multiplication module 330 is used for efficient parallel multiplication operation on the finite field GF( ), and is a special hardware module of the general hash function class randomness extraction device 300.

[0079] Figure 4 The structure of the finite field multiplication module is schematically shown.

[0080] As Figure 4 ​As shown, the finite field multiplication module 330 includes a polynomial multiplication unit 331, an irreducible polynomial storage unit 332, and a modular polynomial simplification unit 333. The polynomial multiplication unit 331 includes two input data, i.e., the first finite field multiplication module 330 receives the last random number subsequence and the random seed sequence as input, and the subsequent finite field multiplication module 330 receives the finite field multiplication operation result of the previous finite field multiplication module 330 and the random seed sequence as input, and generates the multiplication result on the finite field in a single clock cycle through the two steps of polynomial multiplication and modular polynomial simplification, i.e., the irreducible polynomial storage unit 332 and the modular polynomial simplification unit 333 implement the modular polynomial simplification.

[0081] According to the embodiments of the present application, the data buffering module, the data slicing module, the finite field multiplication module, the bitwise XOR operation module, and the data concatenation module are connected through the pipeline architecture.

[0082] The data buffering module, the data slicing module, the finite field multiplication module, the bitwise XOR operation module, and the data concatenation module are connected through the pipeline architecture, and high throughput of data processing can be achieved.

[0083] According to the embodiments of the present application, any of the data buffering module 310, the data slicing module 320, the finite field multiplication module 330, the bitwise XOR operation module 340, and the data concatenation module 350 can be combined in one module for implementation, or any of the modules can be split into multiple modules. Alternatively, at least part of the functions of one or more of the modules can be combined with at least part of the functions of other modules, and implemented in one module. According to the embodiments of the present application, at least one of the data buffering module 310, the data slicing module 320, the finite field multiplication module 330, the bitwise XOR operation module 340, and the data concatenation module 350 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on board, a system on package, an application specific integrated circuit (ASIC), or any other reasonable manner of integrating or packaging a circuit, etc. hardware or firmware, or implemented in any one of software, hardware, and firmware or in a proper combination of any of them. Alternatively, at least one of the data buffering module 310, the data slicing module 320, the finite field multiplication module 330, the bitwise XOR operation module 340, and the data concatenation module 350 can be at least partially implemented as a computer program module which can perform corresponding functions when the computer program module is run.

[0084] Figure 5A block diagram of an electronic device suitable for implementing a general hash function class randomness extraction method according to an embodiment of the present application is shown schematically.

[0085] As shown in Figure 5 The electronic device 500 according to an embodiment of the present application includes a processor 501 that can perform various appropriate actions and processes in accordance with a program stored in a read only memory (ROM) 502 or a program loaded into a random access memory (RAM) 503 from a storage section 508. The processor 501 can include, for example, a general purpose microprocessor (e.g., a CPU), an instruction set processor, and / or a related chipset, and / or a special purpose microprocessor (e.g., an application specific integrated circuit (ASIC)), and / or the like. The processor 501 can also include an on-board memory for cache use. The processor 501 can include a single processing unit or multiple processing units to perform the various actions of the method processes according to embodiments of the present application.

[0086] In the RAM 503, various programs and data required for the operation of the electronic device 500 are stored. The processor 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. The processor 501 performs various operations of the method processes according to embodiments of the present application by executing the programs in the ROM 502 and / or the RAM 503. Note that the programs can also be stored in one or more memories other than the ROM 502 and the RAM 503. The processor 501 can also perform various operations of the method processes according to embodiments of the present application by executing the programs stored in the one or more memories.

[0087] According to an embodiment of the present application, the electronic device 500 can also include an input / output (I / O) interface 505 that is also connected to the bus 504. The electronic device 500 can also include one or more of the following components connected to the input / output (I / O) interface 505: an input section 506 including a keyboard, a mouse, etc.; an output section 507 including a display such as a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, a modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to the input / output (I / O) interface 505 as necessary. A removable recording medium 511 such as a magnetic disk, a magneto-optical disk, a semiconductor memory, etc. is attached to the drive 510 as necessary so that a computer program read therefrom is installed into the storage section 508 as necessary.

[0088] The application further provides a computer readable storage medium, which can be included in the device / apparatus / system described in the above embodiments, or can exist independently without being assembled into the device / apparatus / system. The computer readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the application.

[0089] According to the embodiments of the application, the computer readable storage medium can be a non-volatile computer readable storage medium, which can include, but is not limited to, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any appropriate combination thereof. In the present application, the computer readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device. For example, according to the embodiments of the application, the computer readable storage medium can include one or more memories of the ROM 502 and / or the RAM 503 described above and / or one or more memories other than the ROM 502 and the RAM 503.

[0090] The flowcharts and block diagrams in the drawings illustrate the possible architectures, functionality, and operations of systems, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flowcharts or block diagrams can represent a module, a segment, or a portion of code that comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks noted in succession can in fact be executed substantially concurrently or in the reverse order, depending on the functionality involved. It will also be noted that each block in the block diagrams or flowcharts, and combinations of blocks in the block diagrams or flowcharts, can be implemented by special-purpose hardware-based systems that perform the specified functions or operations, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0091] Those skilled in the art can understand that the features described in various embodiments of the application can be combined and / or integrated in various combinations, even if such combinations are not explicitly described in the application. In particular, the features described in various embodiments of the application can be combined and / or integrated in various combinations without departing from the spirit and teachings of the application. All such combinations fall within the scope of the application.

[0092] The embodiments of the application have been described. However, these embodiments are merely for illustration and are not intended to limit the scope of the application. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Various alternatives and modifications to the embodiments described herein will be apparent to those skilled in the art in view of the foregoing without departing from the scope of the application.

Claims

1. A method of extracting randomness from a universal hash function class, characterized by, The method comprises: data buffering processing on an original random data stream to obtain an original random number sequence with a first fixed length and for a general hash function class; data slicing processing on the original random number sequence to obtain a plurality of random number subsequences with the same data length; finite field multiplication operation on the plurality of random number subsequences to obtain a plurality of finite field multiplication operation results; bitwise XOR operation on the plurality of finite field multiplication operation results to obtain a plurality of bitwise XOR operation results; data splicing processing on the plurality of bitwise XOR operation results to obtain a target random number sequence with a second fixed length.

2. The method of claim 1, wherein, The data buffering processing on the original random data stream to obtain an original random number sequence with a first fixed length and for a general hash function class comprises: checking a random data stream with a random length in each clock cycle by using an original random number effective signal to obtain an effective random data stream; accumulating a plurality of effective random data streams in the clock cycle to obtain the original random data stream; data buffering processing on the original random data stream to obtain an original random number sequence with the first fixed length and for the general hash function class.

3. The method of claim 1, wherein, The finite field multiplication operation on the plurality of random number subsequences to obtain a plurality of finite field multiplication operation results comprises: In the first finite field multiplication operation, the first power of the random seed sequence is multiplied by the first random sub-sequence to obtain the first finite field multiplication operation result, wherein, represents the number of the random sub-sequences. represents the number of the random sub-sequences. During the first During the finite field multiplication operation, the random seed sequence is... The power and the first Multiplying the results of the finite field multiplication operation of the first operation yields the result of the second operation. The results of multiplication operations in finite fields, where are positive integers and .

4. The method of claim 3, wherein, During the first During the finite field multiplication operation, the random seed sequence is... The power and the first Multiplying the results of the finite field multiplication operation of the first operation yields the result of the second operation. The results of a finite field multiplication operation include: The polynomial multiplication operation is performed on the random seed sequence power and the finite field multiplication operation result of the first power to obtain the intermediate polynomial multiplication result of the first power. Based on the pre-defined irreducible polynomial, the first... Multiplying the intermediate polynomials together, we perform modular polynomial simplification to obtain the th... The result of a finite field multiplication operation, wherein the highest power of the preset irreducible polynomial is the same as the data length of the random number subsequence.

5. The method of claim 3, wherein, parallel bitwise XOR operation on the plurality of finite field multiplication operation results to obtain a plurality of bitwise XOR operation results comprises: The first The result of the first finite field multiplication operation is the same as the first... Perform bitwise XOR operations on the nth random number subsequence in parallel to obtain the nth random number subsequence. The result of a bitwise XOR operation, where... are positive integers and .

6. The method according to any one of claims 1 to 5, characterized in that, The original random data stream is a digital sequence generated by detecting and quantifying a quantum physical entropy source.

7. The method according to any one of claims 1 to 5, characterized in that, The original random data stream is a digital sequence obtained by quantum communication parties through a quantum channel negotiation in the field of quantum key distribution.

8. A general hash function-based randomness extraction device, characterized in that, The device comprises: a data buffering module configured to perform data buffering processing on an original random data stream to obtain an original random number sequence with a first fixed length and for a general hash function class; a data slicing module configured to perform data slicing processing on the original random number sequence to obtain a plurality of random number subsequences with the same data length; a finite field multiplication module configured to perform finite field multiplication operation on the plurality of random number subsequences to obtain a plurality of finite field multiplication operation results; a bitwise XOR operation module configured to perform bitwise XOR operation on the plurality of finite field multiplication operation results to obtain a plurality of bitwise XOR operation results; a data splicing module configured to perform data splicing processing on the plurality of bitwise XOR operation results to obtain a target random number sequence with a second fixed length.

9. The apparatus of claim 8, wherein, The number of the finite field multiplication modules is less than the number of the random subsequences; each of the finite field multiplication modules comprises a polynomial multiplication unit, an irreducible polynomial storage unit and a modular polynomial simple element; all the finite field multiplication modules are connected in a cascading manner.

10. The apparatus of claim 8, wherein, The data buffering module, the data slicing module, the finite field multiplication module, the bitwise XOR operation module and the data splicing module are connected through a pipeline architecture.

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