A dual-mode multiplicative congruential transformation system and method based on an FPGA platform

Abstract

The application discloses a dual-mode multiplier number theory transformation system and method based on an FPGA platform, relates to the field of post-quantum cryptography, and comprises a control module, eight butterfly execution units and 24 storage units, wherein each butterfly execution unit is equipped with three storage units and is connected with the control unit, and has two modular multiplication modules which are selectable for common modulus and special modulus. A host computer generates relevant data and sends the data to the 24 storage units of the FPGA, different modular multiplication modules are selected according to different requirements, and each butterfly execution module reads data and executes data conversion calculation. The application has the advantages of flexibility, high efficiency and reusability, can improve the efficiency of NTT execution, and further improve the efficiency of post-quantum cryptography execution, can be used in various encryption schemes which need to execute NTT, can also be used in identity authentication, key management and other cryptographic products, and effectively resists the threat brought by quantum computing.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of post-quantum cryptography, and more particularly to a dual-mode polynomial transform system and method based on an FPGA platform. BACKGROUND

[0002] With the continuous evolution of quantum computing technology, traditional public key encryption technologies such as RSA and elliptic curve encryption are facing the risk of being cracked by quantum computers, and their security cannot be guaranteed. Therefore, it is urgent to develop a new encryption system that can resist quantum computing attacks. Post-quantum cryptography (PQC), also known as quantum-resistant cryptography (QRC), involves polynomial multiplication in its core computing process, among which polynomial multiplication based on number theoretic transform (NTT) is the most widely used. NTT is an abbreviation for "Number Theoretic Transforms", which translates to "number theoretic transform" in Chinese. It is a mathematical transform technology based on number theory, mainly used for efficient convolution operation on integer sequences in modular domain. Similar to the classic fast Fourier transform (FFT), NTT also uses the concept of primitive roots, but its unique feature is to use the power of n-th primitive roots of modulus p as the primitive root, and perform the transform in the finite field (mod p). This feature allows NTT to avoid the accumulation of floating-point operation errors when dealing with large integer multiplication and polynomial multiplication, ensuring the accuracy of the operation results. SUMMARY

[0003] The present application provides a dual-mode polynomial transform system and method based on an FPGA platform, which can improve the efficiency of polynomial transform execution and thus improve the efficiency of post-quantum cryptography execution.

[0004] To achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0005] In a first aspect, the present application provides a dual-mode polynomial transform system based on an FPGA platform, comprising: a host computer, a control unit arranged on an FPGA platform, and a plurality of butterfly execution units, each butterfly execution unit being communicatively connected to a plurality of storage units, and each butterfly execution unit being communicatively connected to the host computer and the control unit; the butterfly execution unit comprises a modulo adder, a modulo subtractor and a modulo multiplier connected to each other, the modulo multiplier comprises a normal modulo multiplier and a special modulo multiplier, wherein the normal modulo multiplier and the special modulo multiplier are selected according to the properties of the modulo multiplication operation in the polynomial transform process.

[0006] The dual-mode multiplier number transformation system based on the FPGA platform as described above is further connected with three storage units in communication with each of the butterfly execution units, two of which are used for reading and writing data for performing the number transformation process, and one of which is used for storing a rotation factor for performing the number transformation process.

[0007] The dual-mode multiplier number transformation system based on the FPGA platform as described above is further characterized in that the execution period of the modulus multiplication operation of the general modulus multiplication unit for performing the number transformation process is determined according to the bit width of data, the execution period of the modulus multiplication operation of the special modulus multiplication unit for performing the number transformation process is 1, the execution period of the modulus addition operation of the modulus addition unit for performing the number transformation process is 1, and the execution period of the modulus subtraction operation of the modulus subtraction unit for performing the number transformation process is 1.

[0008] The dual-mode multiplier number transformation system based on the FPGA platform as described above is further characterized in that the host computer is connected in communication with the butterfly execution units through an address line reading signal DATA, and the control unit is connected in communication with the butterfly execution units through a start signal start and a stop signal stop, a write control signal w_r and a read control signal r_r, a modulus multiplication unit selection signal sle, and a rotation factor reading signal tw_w, and the output of the butterfly execution units is connected to a register EVEN and a register ODD through two address lines, respectively.

[0009] In a second aspect, the present application provides a dual-mode multiplier number transformation method, which is suitable for the dual-mode multiplier number transformation system based on the FPGA platform as described above, and includes the following steps:

[0010] Performing an initialization operation on each unit of the FPGA platform, and generating data according to a preset encryption scheme by using the host computer and transmitting the generated data to the storage unit according to a preset storage scheme;

[0011] The butterfly execution unit waits for the relevant control signals of the reading control unit.

[0012] The control unit controls the butterfly execution unit to perform the number transformation through signals, wherein the control unit controls the butterfly execution unit to start performing the number transformation process through a start signal start, controls the butterfly execution unit to read data for performing the number transformation process from the storage unit through a read control signal r_r, controls the butterfly execution unit to read a pre-arranged rotation factor from the storage unit through a rotation factor reading signal tw_w, selects a modulus multiplication unit through a modulus multiplication unit selection signal sle during the number transformation process, and controls the butterfly execution unit to write data generated during the number transformation process to the storage unit through a write control signal w_r.

[0013] If the preset execution number is reached, the number theory transformation is stopped, otherwise, the previous step is continued. When the number theory transformation is stopped, the control unit controls the butterfly execution unit to stop the number theory transformation process through the stop signal stop, and the result data is connected to the register EVEN and the register ODD through two address lines.

[0014] The double-mode multiplication number theory transformation method as described above, further, when the butterfly execution unit reads the data for executing the number theory transformation process from the storage unit through the read control signal r_r, and when the butterfly execution unit writes the data generated in the number theory transformation process into the storage unit through the write control signal w_r, the address of the data reading and writing is controlled through the address parameter signal add_res, and the address of the data reading and writing is generated by the address generation program contained in the control unit.

[0015] The double-mode multiplication number theory transformation method as described above, further, the initialization operation is performed on each unit of the FPGA platform, wherein each unit includes: a number counter, a control unit, a plurality of butterfly execution units and a plurality of storage units.

[0016] The double-mode multiplication number theory transformation method as described above, further, the data generated in the number theory transformation process includes: data generated by the host computer according to a preset encryption scheme, intermediate data generated in the number theory transformation process, and result data generated in the number theory transformation process.

[0017] The double-mode multiplication number theory transformation method as described above, further, the preset execution number is achieved through the number counter.

[0018] The double-mode multiplication number theory transformation method as described above, further, when the modulus multiplier is selected in the number theory transformation process through the modulus multiplier selection signal sle, if the modulus is a Mersenne prime number, a special modulus multiplier is used, otherwise, a general modulus multiplier is used.

[0019] Compared with the prior art, the present application has the beneficial effects that the present application is suitable for any post-quantum encryption scheme that needs to perform NTT. The flexibility is reflected in the ability to update the storage unit data in real time to adapt to different scenarios, and the efficiency is derived from the optional modular multiplier, which can achieve different execution performance. The two modular multipliers complement each other and can be configured according to different data bit width requirements to realize multiplexing, thereby expanding the application scenarios. In addition, the dual modular number theoretic transform system of the present application has 8 parallel computing butterfly execution units, which can significantly reduce the overall execution time. Each execution unit can configure storage units with different functions according to the requirements, realizing the controllability of storage resources. This design not only improves the efficiency of NTT execution, but also correspondingly improves the efficiency of post-quantum cryptography execution, and is suitable for various encryption schemes that need to perform NTT, as well as identity authentication, key management and other cryptographic products, effectively resisting the potential threat of quantum computing. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0021] Fig. 1 The overall framework schematic diagram of the dual modular number theoretic transform system based on the FPGA platform provided by the present application is shown in the figure.

[0022] Fig. 2 The butterfly execution unit structure schematic diagram of the dual modular number theoretic transform system based on the FPGA platform provided by the present application is shown in the figure. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0024] Embodiment:

[0025] It should be noted that the terms "include" and "have" and any variations thereof in the embodiments of the present application are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to the process, method, product or device.

[0026] In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly specified and limited. In addition, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0027] Referring to Figs. 1-2 The embodiment of the present application provides a dual-mode multiplier number theory transformation system based on an FPGA platform, which comprises a host computer, a control unit and a plurality of butterfly execution units arranged on the FPGA platform, each butterfly execution unit is in communication connection with a plurality of storage units, and each butterfly execution unit is in communication connection with the host computer and the control unit respectively; the butterfly execution unit comprises a modulo adder, a modulo subtractor and a modulo multiplier connected with each other, the modulo multiplier comprises a general modulo multiplier and a special modulo multiplier, wherein the general modulo multiplier and the special modulo multiplier are selected according to the properties of the modulo multiplication operation of the execution of the number theory transformation process.

[0028] Therefore, different execution performances are achieved by selecting different modulo multiplication modules, and flexible and configurable multiplexing is achieved by updating the data of the storage units.

[0029] In some embodiments, each butterfly execution unit is in communication connection with three storage units, wherein two storage units are used for reading and writing data of the execution of the number theory transformation process, and one storage unit is used for storing a rotation factor of the execution of the number theory transformation process.

[0030] In some embodiments, the execution period of the modulo multiplication operation of the number theory transformation process performed by the general modulo multiplier is determined according to the bit width of the data, the execution period of the modulo multiplication operation of the number theory transformation process performed by the special modulo multiplier is 1, the execution period of the modulo addition operation of the number theory transformation process performed by the modulo adder is 1 respectively, and the execution period of the modulo subtraction operation of the number theory transformation process performed by the modulo subtractor is 1.

[0031] In some embodiments, the host computer is in communication connection with the butterfly execution unit through an address line reading signal DATA; the control unit is in communication connection with the butterfly execution unit through a start signal start and a stop signal stop, a write control signal w_r and a read control signal r_r, a modulo multiplier selection signal sle, an address parameter signal add_res and a rotation factor reading signal tw_w; the output of the butterfly execution unit is connected to a register EVEN and a register ODD through two address lines respectively.

[0032] In another embodiment, the embodiment of the present application also provides a double-mode multiplicative number transformation method, which is suitable for a double-mode multiplicative number transformation system based on an FPGA platform, and includes the following steps:

[0033] Step 1: performing an initialization operation on each unit of the FPGA platform; meanwhile, generating data according to a preset encryption scheme by using an upper computer, and transmitting the generated data into a storage unit according to a preset storage scheme.

[0034] In actual operation, the initialization operation is performed on each unit of the FPGA platform, wherein each unit includes a frequency counter, a control unit, a plurality of butterfly execution units and a plurality of storage units.

[0035] In the specific execution process, the generated data is transmitted into the storage unit according to the preset storage scheme, which means that two storage units are used to read and write data in the execution of the number transformation process, and one storage unit is used to store the rotation factor in the execution of the number transformation process. The coefficients DATA enter the storage unit in batches, and the rotation factor tw_w is generated and sorted in the upper computer first, so as to avoid the time and hardware resources consumed in the FPGA for generating and sorting. Exemplarily, 8-point NTT (x0-x7) is executed in three stages, the first stage needs rotation factors the second stage needs and the third stage needs The first stage is (x0, x4), (x1, x5), (x2, x6), (x3, x7) to perform butterfly operation to obtain results (y0-y7), the second stage is (y0, y2), (y1, y3), (y4, y6), (y5, y7) to perform butterfly operation to obtain results (z0-z7), and the third stage is (z0, z1), (z2, z3), (z4, z5), (z6, z7). According to the example, x0, x1, x2, x3 are put into one of the storage units, and the other four are put into another storage unit, the upper computer generates and puts them into the third storage unit in order.

[0036] The data generated according to the preset encryption scheme refers to that the upper computer is responsible for generating data meeting the requirement of a specific encryption scheme. According to different encryption schemes, different encryption schemes have different data requirements, which usually involve setting a modulus q and a data quantity N, and then generating N data points in the (0, q-1) interval through random sampling or other specified sampling methods. The application adopts a random sampling technology (the user can customize other sampling methods), and sets the modulus q and the data quantity N, wherein q must be a prime number, and N should be a power of 2. For example, q is set to 520193 and N is set to 1024, then 1024 data points in the (0, 520192) interval are generated, and these data points are transmitted to the storage unit of the FPGA according to the predetermined requirement.

[0037] And the NTT is a derivative of the fast Fourier transform FFT, and the execution process of the FFT is not different from that of the NTT except for the data form, so the overall calculation execution times can be determined by the data quantity N of the NTT and the number of butterfly units. The number of stages of the NTT is obtained by taking the logarithm of N, then N / 2 times of butterfly calculation are required for each stage, and the butterfly execution unit is 8, so the overall times can be determined. According to the above description, N is set to 16, log216 is 4, the number of stages is 4, 16 / 2 times of butterfly operation are performed for each stage, a total of 32 times of butterfly operation. Since there are 8 butterfly execution units that can perform parallel calculation, the NTT in the FPGA needs to be performed a total of 32 / 8 times, i.e. 4 times.

[0038] Step 2: The butterfly execution unit waits for the relevant control signals of the reading control unit.

[0039] Step 3: The control unit controls the butterfly execution unit to perform the number theory transformation through signals, wherein the butterfly execution unit starts to perform the number theory transformation process through a start signal start, reads the data for performing the number theory transformation process from the storage unit through a reading control signal r_r, reads the pre-arranged rotation factor from the storage unit through a rotation factor reading signal tw_w, selects the modulus multiplier through a modulus multiplier selection signal sle during the number theory transformation process, and writes the data generated in the number theory transformation process into the storage unit through a writing control signal w_r.

[0040] In actual operation, the data generated in the number theory transformation process includes the data generated by the upper computer according to the preset encryption scheme, the intermediate data generated in the number theory transformation process, and the result data generated in the number theory transformation process.

[0041] During the actual execution process, when the butterfly execution unit is controlled by the read control signal r_r to read data from the storage unit to perform the number theory transformation process, and when the butterfly execution unit is controlled by the write control signal w_r to write data generated during the number theory transformation process to the storage unit, the address parameter signal add_res controls the address for data reading and writing. The address for data reading and writing is generated by the address generation program contained in the control unit.

[0042] In practice, when selecting the modular multiplier using the modular multiplier selection signal sle during number theory transformations, a special modular multiplier is used if the modulus is a Mersenne prime; otherwise, a regular modular multiplier is used. For example, regular modular multiplication requires determining the number of iterations based on the modulus width K and the amount of data N converted from the NTT, obtaining the parameter W = log₂2N. Using K and W, the number of iterations required for word-level Montgomery modular multiplication can be determined. Using word-level Montgomery modular multiplication is superior to using classic Montgomery modular multiplication. Classical Montgomery modular multiplication processes data directly, resulting in the use of more hardware resources such as multipliers with longer bit widths. Word-level Montgomery modular multiplication avoids this problem by using a "loop" step to "segment" the data. Furthermore, special modular multiplication methods are suitable for q=2. i ±2 j The generalized Mersenne modulus in ±1 form has a dedicated modular reduction operation procedure, requiring fewer multiplier resources and simple shift operations. The two modular multiplication methods differ from designs that use only one modular multiplication algorithm, providing options to suit different performance and scenario requirements. Users can switch between different modular multipliers by modifying the sle signal, improving flexibility.

[0043] Step 4: If the preset number of executions is reached, the number theory transformation will stop; otherwise, the previous step will continue. When the number theory transformation stops, the control unit controls the butterfly execution unit to stop the number theory transformation process through the stop signal and connects the result data to the EVEN register and the ODD register through two address lines respectively.

[0044] In practice, reaching the predetermined number of executions is achieved using a count counter.

[0045] During execution, the final data is output to the EVEN and ODD registers. The result of the modular multiplication operation is output to the ODD register, while other result data is output to the EVEN register. By setting the buffer time of EVEN, it is possible to wait for ODD to finish receiving the result of the modular multiplication operation in the butterfly execution unit, and then both registers output all results synchronously.

[0046] As an example, the dual-mode multiplier transformation method can also include the following processes: ①: first, initialize each unit of the FPGA. The host computer generates data that meets the requirements of the encryption scheme. Since different encryption schemes have different requirements for data, N data is usually generated in the range of (0, q-1) through random sampling or other methods after the modulus value q and the data amount N are determined. The present application uses random sampling (of course, other sampling methods can also be set), determines the q value and the data amount N, requires q to be a prime number, and N to be a power of 2. For example, set q = 520193 and N = 1024, generate 1024 data in the range of (0, 520192), and transmit them to the storage unit of the FPGA as required; ②: each butterfly execution unit is configured to connect three storage units, two of which are used to store coefficients and data, and the other is used to store the rotation factor tw_w, and waits for related control signals to be read; ③: the control unit is responsible for the control of the overall process, uses the start signal to start executing NTT, uses r_r and w_r to control the reading and writing of data, uses sle to select the modular multiplier, and uses add_res to control the address of data reading and writing; ④: the control unit starts executing NTT, first sets the start signal high and the r_r signal high, and the butterfly execution unit starts reading data from the storage unit, wherein the data address is generated by the address generation program contained in the control unit, and the rotation factor is generated and sorted in the host computer in priority, and can be read in order; ⑤: after the coefficients and the rotation factor are read, the butterfly calculation is performed according to the GS butterfly. The coefficients are first subjected to modulo addition and subtraction, which consumes one period respectively; ⑥: the modular multiplication is realized through the modular multiplier, which selects different modular multipliers according to the different high and low of the sle signal caused by different moduli, i.e. the ordinary modular multiplier and the special modular multiplier; if the modulus is a Mersenne prime, the special modular multiplier is used, which only needs simple shift and addition and subtraction calculation, otherwise the word-level Montgomery modular multiplication is used to execute LOOP times of Montgomery modular multiplication; in actual operation, the ordinary modular multiplication needs to determine the number of cycles according to the modulus bit width K and the data amount N of NTT conversion, obtain the parameter W = log22N, and determine the number of cycles of word-level Montgomery modular multiplication using K and W And the special modular multiplication is for the generalized Mersenne prime modulus in the form of q = 2 i ±2 j ±1; ⑦: the calculation result is set high through w_r, and then written back to the corresponding position of the storage unit according to the parameters generated by the address generation program; ⑧: stop when the preset execution number is reached, otherwise continue to execute steps ③-⑧; ⑨: when the preset execution number is reached, the control signal stop is set high and the start is set low, the result data is read, and the execution number counter count is reset.

[0047] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples without contradiction.

[0048] The above embodiments are only for the purpose of illustrating the technical concepts and characteristics of the present application, and the purpose is to enable those of ordinary skill in the art to understand the content of the present application and to implement it, and cannot limit the protection scope of the present application. Any equivalent changes or modifications made in accordance with the essence of the present application should be covered within the protection scope of the present application.

Claims

1. A dual-mode multiplier-theoretic transform system based on an FPGA platform, characterized in that, include: The system comprises a host computer, a control unit mounted on an FPGA platform, and multiple butterfly execution units. Each butterfly execution unit is communicatively connected to several storage units, and each butterfly execution unit is communicatively connected to both the host computer and the control unit. The control unit controls the butterfly execution units to perform number theory transformations via signals. Specifically, a start signal (start) controls the butterfly execution units to begin the number theory transformation process; a read control signal (r_r) controls the butterfly execution units to read data from the storage units for the number theory transformation process; and a rotation factor read signal (tw_w) controls the butterfly execution units to read pre-arranged rotation factors from the storage units. In the process of number-theoretical transformation, the modular multiplier is selected via the modular multiplier selection signal sle, and the butterfly execution unit is controlled by the write control signal w_r to write the data generated during the number-theoretical transformation into the storage unit. The butterfly execution unit includes modular adders, modular subtractors, and modular multipliers connected to each other. The modular multipliers include ordinary modular multipliers and special modular multipliers. The ordinary modular multipliers and the special modular multipliers are selected according to the nature of the modular multiplication operation in the number-theoretical transformation process. The modular multiplication operation is implemented by the modular multipliers, and the modular multipliers select different modular multipliers based on the different levels of the sle signal caused by different moduli. When the modulus is a Mersenne prime, a special modular multiplier is used to perform shift and addition / subtraction calculations; otherwise, word-level Montgomery modular multiplication is used, performing LOOP Montgomery modular multiplications.

2. The dual-mode multiplier-theoretic transform system based on an FPGA platform according to claim 1, characterized in that, Each of the butterfly execution units is communicatively connected to three storage units, two of which are used to read and write data for performing the number-theoretical transformation process, and one storage unit is used to store the rotation factor for performing the number-theoretical transformation process.

3. The dual-mode multiplier-theoretic transform system based on an FPGA platform according to claim 1, characterized in that, The execution cycle of the modular multiplication operation in the number theory transformation process of the ordinary modular multiplier is determined according to the bit width of the data. The execution cycle of the modular multiplication operation in the number theory transformation process of the special modular multiplier is 1. The execution cycle of the modular addition operation in the number theory transformation process of the modular adder is 1. The execution cycle of the modular subtraction operation in the number theory transformation process of the modular subtraction is 1.

4. The dual-mode multiplier-theoretic transform system based on an FPGA platform according to claim 1, characterized in that, The host computer and the butterfly execution unit are connected via address lines to read the DATA signal and communicate; the control unit and the butterfly execution unit are connected via start and stop signals, write control signal w_r and read control signal r_r, modular multiplier selection signal sle, address parameter signal add_res, and tw_w read signal; the output of the butterfly execution unit is connected to register EVEN and register ODD via two address lines respectively.

5. A dual-mode multiplier-theory transform method, applicable to the dual-mode multiplier-theory transform system based on an FPGA platform as described in claim 1, characterized in that, Including the following steps: Initialization operations are performed on each unit of the FPGA platform; at the same time, data is generated by the host computer according to the preset encryption scheme, and the generated data is transmitted to the storage unit according to the preset storage scheme. The butterfly actuator waits to read relevant control signals from the control unit; If the preset number of executions is reached, the number transformation will stop; otherwise, the previous step will continue. When the number transformation stops, the control unit controls the butterfly execution unit to stop the number transformation process through the stop signal and connects the result data to the EVEN register and the ODD register through two address lines respectively.

6. The dual-modulus multiplier-theory transform method according to claim 5, characterized in that, When the butterfly execution unit is controlled by the read control signal r_r to read data from the storage unit to perform the number theory transformation process, and when the butterfly execution unit is controlled by the write control signal w_r to write data generated during the number theory transformation process to the storage unit, the address for data reading and writing is controlled by the address parameter signal add_res. The address for data reading and writing is generated by the address generation program contained in the control unit.

7. The dual-modulus multiplier-theory transform method according to claim 5, characterized in that, The initialization operation is performed on each unit of the FPGA platform, wherein each unit includes: a count counter, a control unit, multiple butterfly execution units, and several storage units.

8. The dual-modulus multiplier-theory transform method according to claim 5, characterized in that, The data generated during the number theory transformation process includes: data generated by the host computer according to a preset encryption scheme, intermediate data generated during the number theory transformation process, and result data generated during the number theory transformation process.

9. The dual-modulus multiplier-theory transformation method according to claim 5, characterized in that, The preset number of executions is achieved through a counter.

10. The dual-modulus multiplier-theory transform method according to claim 5, characterized in that, When selecting the modular multiplier using the modular multiplier selection signal sle during the number theory transformation process, a special modular multiplier is used if the modulus is a Mersenne prime; otherwise, a regular modular multiplier is used.

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