Waveform file conversion method and apparatus for chip testing, and computer readable storage medium

Abstract

The present application relates to a waveform file conversion method and apparatus for chip testing, and a computer readable storage medium. The method comprises: performing content analysis on a waveform file to be converted, to acquire period information, pin information, and state information of pins in each period of said waveform file; generating a PAT-format digital signal waveform file; and on the basis of a mapping relationship between pins and ATE channels, converting the PAT-format digital signal waveform file into a binary vector file for ATE testing. A waveform file in any format is converted into a PAT-format digital signal waveform file which uses periods as rows and pins as columns, so that each row vector not only contains current time information but also contains a logical state of each pin; in addition, to facilitate understanding, the PAT-format digital signal waveform file is further converted into a binary vector for ATE testing, so that efficient processing of waveform files in a plurality of different formats can be realized, thereby improving the universality of conversion.

Description

Waveform file conversion method, device and computer readable storage medium for chip testing

[0001] Related applications

[0002] The present application claims priority to the Chinese patent application No. 202411092337X, filed on August 9, 2024, entitled "Waveform file conversion method, device and computer readable storage medium for chip testing", the contents of which are hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of format conversion, and in particular, to a waveform file conversion method, device and computer readable storage medium for chip testing. BACKGROUND

[0004] In the field of semiconductor device manufacturing and electronic testing, waveform vector files are an important data format used to describe the timing operation of digital signal driving, response and control devices of the chip under test. These files usually contain a series of time points and corresponding pin digital signal states, which are crucial for the normal operation of the device and semiconductor testing. However, these waveform vector files usually have a complex format, which is not easy to understand, and it is more difficult to directly apply them to the production field by the test device.

[0005] In the conventional technology, these complex waveform vector files are mainly converted into other forms that are easier to understand and process by specific conversion tools. For example, some tools can convert these files into text format for human reading. In addition, some tools can convert these files into binary encoding form for computer processing.

[0006] However, although the conversion tools solve the problem of reading and processing waveform vector files to some extent, the existing conversion tools can only process a single type of file format. SUMMARY

[0007] According to various embodiments of the present application, a waveform file conversion method, device and computer readable storage medium for chip testing are provided.

[0008] In a first aspect, the present application provides a waveform file conversion method for chip testing, comprising:

[0009] performing content analysis on a waveform file to be converted to obtain cycle information, pin information and state information of each pin in each cycle of the waveform file to be converted; the waveform file to be converted is a chip simulation file in the process of circuit design and testing;

[0010] According to the cycle information, pin information and state information of each pin in each cycle, a digital signal waveform file in PAT format is generated, which records the state information of each pin in each cycle in rows of cycles and columns of pins.

[0011] Based on the mapping relationship between each pin and the channel of the automatic test equipment, the digital signal waveform file in PAT format is converted into a binary vector file for testing by the automatic test equipment.

[0012] In one embodiment, the method further comprises: sampling the state information of each pin in each cycle according to the cycle information; and performing vector reorganization on the state information of each pin in each cycle according to the timing growth to generate the digital signal waveform file in PAT format.

[0013] In one embodiment, the method further comprises: performing vector reorganization on the state information of each pin in each cycle according to the timing growth to generate the digital signal waveform file in PAT format.

[0014] In one embodiment, after the vector reorganization of the state information of each pin in each cycle, the method further comprises: identifying a continuous repeating cycle of the vector to determine a repeating vector; and performing vector compression on the repeating vector based on the corresponding continuous repeating cycle, and generating the digital signal waveform file in PAT format according to the compressed vector.

[0015] In one embodiment, the method further comprises: obtaining timing information of the waveform file to be converted and timing information of the compressed vector; verifying and adjusting the timing information of the compressed vector according to the comparison result of the timing information; and generating the digital signal waveform file in PAT format according to the verified and adjusted vector.

[0016] In one embodiment, the verification is implemented based on at least one of unit testing, code review and performance analysis; and the adjustment comprises adjusting the execution frequency or time interval of a loop.

[0017] In one embodiment, the method for converting the digital signal waveform file in the PAT format into a binary vector file for testing by the automated test equipment based on the mapping relationship between the pins and the channels of the automated test equipment comprises: determining the mapping relationship between the pins and the channels of the automated test equipment based on the circuit design and the test plan; obtaining channel information corresponding to each board card in the automated test equipment, and determining target pins corresponding to the channel information of the board card according to the mapping relationship; extracting state information of each cycle of the target pins from the digital signal waveform file in the PAT format by column; and generating a binary vector file for testing by the automated test equipment for the board card based on the extracted state information of each cycle of the target pins.

[0018] In one embodiment, before the extracting state information of each cycle of the target pins from the digital signal waveform file in the PAT format by column, the method further comprises: checking the digital signal waveform file in the PAT format by row based on a preset regular expression to determine whether the state information of each pin is valid; and in the case where it is determined that the state information of each pin is valid, performing semantic analysis on the state information of each pin by using a structured syntax tree to obtain a corresponding syntax tree.

[0019] In one embodiment, the method further comprises: inserting a label in the binary vector file according to the syntax tree.

[0020] In one embodiment, the content analysis on the to-be-converted waveform file to obtain the cycle information, pin information, and state information of each pin in each cycle of the to-be-converted waveform file comprises: identifying a file format of the to-be-converted waveform file, and determining a file specification corresponding to the file format; and performing content analysis on the to-be-converted waveform file according to the file specification to obtain the cycle information, pin information, and state information of each pin in each cycle of the to-be-converted waveform file.

[0021] In a second aspect, the application further provides a waveform file conversion device for chip testing, comprising:

[0022] The analysis module is configured to perform content analysis on a to-be-converted waveform file to obtain cycle information, pin information, and state information of each pin in each cycle of the to-be-converted waveform file; and the to-be-converted waveform file is a chip simulation file in a circuit design and test process.

[0023] The first format conversion module is configured to generate a digital signal waveform file in the PAT format according to the cycle information, pin information, and state information of each pin in each cycle, and the digital signal waveform file in the PAT format records the state information of each pin in each cycle by column and by row.

[0024] The second format conversion module is configured to convert the digital signal waveform file in the PAT format into a binary vector file for testing by the automated test equipment based on the mapping relationship between the pins and the channels of the automated test equipment.

[0025] In one embodiment, the first format conversion module is specifically configured to: sample the state information of each pin in each cycle according to the cycle information; and perform vector recombination on the state information of each pin in each cycle according to the timing growth, to generate the digital signal waveform file in the PAT format.

[0026] In a third aspect, the present application provides a computer device, including a memory and a processor, the memory stores a computer program, and the processor implements the steps of the method in the first aspect when executing the computer program.

[0027] In a fourth aspect, the present application provides a computer readable storage medium, which stores a computer program, and the computer program implements the steps of the method in the first aspect when executed by a processor.

[0028] In a fifth aspect, the present application provides a computer program product, which includes a computer program, and the computer program implements the steps of the method in the first aspect when executed by a processor.

[0029] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the application will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of the disclosed drawings.

[0031] FIG. 1 is a flowchart of a waveform file conversion method for chip testing in one embodiment;

[0032] FIG. 2 is a flowchart of a content analysis step in one embodiment;

[0033] FIG. 3 is a flowchart of a PAT format file generation step in one embodiment;

[0034] FIG. 4 is a flowchart of a binary conversion step in one embodiment;

[0035] Fig. 5 is a structural block diagram of a waveform file conversion device for chip testing in an embodiment;

[0036] Fig. 6 is an internal structural diagram of a computer device in an embodiment. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0038] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0039] In an embodiment, the present application provides a waveform file conversion method for chip testing. The present embodiment is exemplified by the method applied to a computer device. As shown in Fig. 1, the method comprises the following steps:

[0040] In step 102, the content of the waveform file to be converted is parsed to obtain the period information, pin information and state information of each pin in each period of the waveform file to be converted.

[0041] The to-be-converted waveform file is a chip simulation file in a circuit design and test process. In the field of semiconductor device manufacturing and electronic testing, when designing a circuit, a chip designer usually describes various behaviors and functions of the circuit operation by using a hardware description language (such as Verilog or VHDL (Very-High-Speed Integrated Circuit Hardware Description Language)) and performs simulation by using a simulation tool (such as ModelSim or Cadence) after the design is completed. During the simulation process, the tool generates a waveform file, that is, a chip simulation file, to record the changes of signals in the circuit. Based on different simulation tools, the formats of the generated chip simulation files are different. Usually, the formats of the chip simulation files include VCD (Value Change Dump, language based on event form), EVCD (Extended Value Change Dump), WGL (Waveform Language), STIL (Standard Test Interface Language), and the like. These files play an important role in circuit design and testing, helping designers verify and debug their designs to ensure the correctness and reliability of the circuit design.

[0042] However, the formats of these chip simulation files are usually complex and difficult to understand, and it is more difficult for them to be directly applied to the production field by a test device. Usually, a conversion tool needs to be used for format conversion. However, the existing conversion tools can usually only process a single type of file format and cannot process files in multiple different formats. In addition, the existing conversion tools may have low efficiency when processing a large amount of data, and cannot preserve all information in the original file, resulting in differences between the converted file and the original file.

[0043] Based on this, in the embodiment, a computer device is used to parse the content of a chip simulation file, that is, a to-be-converted waveform file, to obtain period information, pin information, and state information of each pin in each period of the to-be-converted waveform file, and then the to-be-converted waveform file is converted by using subsequent steps, so that the chip simulation files in different formats can be converted.

[0044] Since the chip simulation file describes various behaviors and functions of the circuit operation, it usually includes a series of time points and corresponding pin digital signal states. Therefore, by content parsing of the chip simulation file on the computer device, the period information, pin information and state information of each pin in each period of the chip simulation file, i.e. the waveform file to be converted, can be obtained. Specifically, the state information can be the digital signal state of the corresponding pin, which can be represented by different logic symbols, such as driving low level 0, driving high level 1, driving high impedance Z, capturing logic low signal L, capturing logic high signal H, capturing logic valid signal V, capturing digital K, etc.

[0045] In step 104, a digital signal waveform file in PAT format is generated according to the period information, pin information and state information of each pin in each period.

[0046] Among them, PAT (Pulse Analysis Technology) format is a file format for describing digital signal waveform, which is mainly used in electronic test equipment and integrated circuit (IC) test. The PAT file usually contains the timing information and level change of digital signal, which is used to simulate and test circuit design to verify its performance.

[0047] In this embodiment, the digital signal waveform file in PAT format records the state information of each pin in each period in the form of period as row and pin as column. Specifically, the computer device obtains the period information, pin information and state information of each pin in each period of the waveform file to be converted by content parsing of various formats of the waveform file to be converted, and converts it into a digital signal waveform file in PAT format with period as row and pin as column, so that each row vector contains not only the current time information, but also the logic state of each pin, which is more intuitive and convenient for understanding, problem tracking and debugging.

[0048] In step 106, the digital signal waveform file in PAT format is converted into a binary vector file for ATE test based on the mapping relationship between each pin and ATE channel.

[0049] The ATE (Automatic Test Equipment) is a device for automatically testing the performance and functions of a chip in the field of chip testing, and is the last process in the production and manufacturing of integrated circuits to ensure the quality of the production and manufacturing of integrated circuits. Specifically, the ATE applies a required excitation signal to the pins of a chip through its channels and monitors the output pins of the chip to verify whether the output signal of the chip is as expected. For example, the ATE can apply an excitation signal to the input pipe of the chip while monitoring the output pin of the chip to see whether the output signal of the chip is the expected value. Therefore, the channels of the ATE need to correspond to the pins of the chip one by one to ensure that the test signal can be correctly applied to the chip. Each channel can be independently controlled to perform direct current parameter testing, alternating current parameter testing, and function testing.

[0050] Specifically, based on the circuit design corresponding to the chip simulation file and the test plan of the ATE, the mapping relationship between each pin in the circuit design and the channel of the ATE can be determined. Then, based on the mapping relationship, the computer device can convert the digital signal waveform file in the PAT format into a binary vector file for ATE testing. The binary vector file is logic 1 and logic 0 data for testing or operation applied to the pins of the device in each clock cycle.

[0051] In the above waveform file conversion method for chip testing, the computer device obtains the period information, pin information, and state information of each pin in each period of the waveform file to be converted by content analysis on the waveform file to be converted, and generates a digital signal waveform file in the PAT format according to the period information, pin information, and state information of each pin in each period. Based on the mapping relationship between each pin and the channel of the ATE, the digital signal waveform file in the PAT format is converted into a binary vector file for ATE testing. By converting waveform files in various formats into a digital signal waveform file in the PAT format with periods as rows and pins as columns, each row of vectors contains both the current time information and the logic state of each pin, and then the digital signal waveform file in the PAT format is converted into a binary vector file for ATE testing, which can effectively process waveform files in various formats and improve the versatility of the conversion.

[0052] In an exemplary embodiment, as shown in FIG. 2, in step 102, the content of the waveform file to be converted is analyzed to obtain the period information, pin information, and state information of each pin in each period of the waveform file to be converted, which can specifically include:

[0053] In step 202, the file format of the waveform file to be converted is identified, and the file specification corresponding to the file format is determined.

[0054] The file format refers to the storage method of data in the file, including the organization structure, encoding method, etc. of the data. The file format determines the type and extension of the file. The file format is usually identified by the header information (also known as magic number or signature) of the file. These information can help the operating system and application program to determine how to open and process the file. The file specification refers to the rules and standards for creating and managing files. These rules may include file naming rules, file size limits, file organization structure, metadata requirements, etc. The file specification ensures the consistency, accessibility and maintainability of the file. The file specification may be established by the organization itself, or it may follow industry standards or international standards.

[0055] Specifically, the computer device identifies the file format of the waveform file to be converted, so as to determine the file specification corresponding to the file format, and then processes through subsequent steps to extract the required information.

[0056] In step 204, the content of the waveform file to be converted is parsed according to the file specification to obtain the period information, pin information and state information of each pin in each period of the waveform file to be converted.

[0057] The content parsing refers to the process of analyzing the content of the waveform file to be converted to extract useful information. In this embodiment, the computer device can parse the content of the waveform file to be converted according to the file specification of the waveform file to be converted to obtain the period information, pin information and state information of each pin in each period of the waveform file to be converted.

[0058] Specifically, the file reading function can be used to open the waveform file to be converted and read the file content, ignore the blank lines and comments, and identify the instruction type of each line according to the file format specification. According to the instruction type, the definition and waveform data of the signal are parsed. The parsed data is stored in a suitable data structure, such as a dictionary or a class. For all formats, the waveform data needs to be synchronized according to the timestamp.

[0059] For example, taking the file format of the waveform file to be converted as VCD format as an example, the waveform file in VCD format is usually used to record the change of digital signal. It is composed of a series of instructions starting with $. When parsing the file in this format, by reading the file content, ignoring all lines not starting with $, according to the instruction, the definition of the signal is parsed to obtain the time value (time point of period, edge jump, etc.) and the subsequent signal value to obtain the waveform data. And according to the time value, the period information is extracted, and according to the definition of the signal, the pin information is determined to determine the state information of each pin in each period.

[0060] Taking a file format of the waveform file to be converted as an example, the waveform text in the WGL format is usually used for simulation and testing. It can contain complex descriptions such as periodic waveforms, random waveforms, etc. When parsing the file in this format, the file is read, the syntax of the waveform description is identified, and the parameters of the periodic waveform such as frequency, amplitude, phase, etc. are parsed. For complex waveforms, mathematical expressions or functions may need to be parsed. To obtain the period information, pin information, and state information of each pin in each period of the waveform file to be converted.

[0061] In an exemplary embodiment, as shown in FIG. 3, in step 104, according to the period information, the pin information, and the state information of each pin in each period, a digital signal waveform file in the PAT format is generated, which can specifically include:

[0062] Step 302: sampling the state information of each pin in each period according to the period information.

[0063] Specifically, the computer device can sample the state information of each pin once in each period according to the period information to obtain the input and output state of each pin in each period.

[0064] Step 304: vector reorganization of the state information of each pin in each period according to the timing growth to generate a digital signal waveform file in the PAT format.

[0065] Specifically, according to the timing growth, the state information of each pin in each period is vector reorganized in a period as a row and a pin as a column to generate a digital signal waveform file in the PAT format.

[0066] For example, taking the pin information including Pin1, Pin2, and Pin3 as an example, these pins are pins used in a semiconductor ATE device. Assuming that each period is 1 ms, the waveform vector can be reorganized one period per row from top to bottom in time sequence. For example, in the first period, the state of Pin1 can be driving low level 0, the state of Pin2 can be driving high level 1, and the state of Pin3 can be driving high impedance state Z. After reorganizing the first period, the second period is reorganized by line, that is, each row is incremented by one clock period until the state information of each pin in all periods is reorganized to obtain the converted digital signal waveform file in the PAT format. Each row vector after conversion contains not only the current time information but also the logic state of each pin, and is more intuitive, convenient to understand, problem tracking and debugging. And this structured design can improve the efficiency of the computer device processing, avoiding the problem of low efficiency when processing a large amount of data.

[0067] In an example embodiment, after the state information of each pin in each cycle is vector-recombined in step 304, the method can further include: identifying a continuous repeating cycle of the vector, determining a repeating vector; performing vector compression on the repeating vector based on the corresponding continuous repeating cycle, and generating a digital signal waveform file in PAT format according to the compressed vector.

[0068] The continuous repeating cycle refers to a continuous repeating cycle of the vector, that is, a repeating vector with a continuous cycle. The vector can be the state information of each pin in a cycle after recombination, that is, a row of vector in the digital signal waveform file in PAT format. The vector compression can be implemented by RPT (Repeat) / LOOP (Loop Control) instructions. Specifically, in this embodiment, the computer device identifies a continuous repeating cycle of the vector, determines a repeating vector, performs vector compression on the repeating vector based on the corresponding continuous repeating cycle, and generates a digital signal waveform file in PAT format according to the compressed vector. For example, if a row of vector repeats for 3 cycles, the three rows of vector can be compressed into one row, and "3" is filled in RPT to compress the repeating vector, so that the file format is more concise, and the storage space of the digital signal waveform file in PAT format can be saved.

[0069] In an example embodiment, as shown in FIG. 4, in step 106, the digital signal waveform file in PAT format is converted into a binary vector file for ATE testing based on the mapping relationship between the pins and the ATE channels, which can specifically include:

[0070] Step 402: Determine the mapping relationship between the pins and the ATE channels based on the circuit design and the test plan.

[0071] Since the circuit design describes various behaviors and functions of the circuit operation, and the test plan is the required excitation signal applied to the chip pins corresponding to the circuit by the ATE channels, and the output pins of the chip are monitored to verify whether the output signal meets the expected plan. Therefore, the computer device can determine the mapping relationship between the pins of the chip and the channels of the ATE based on the circuit design corresponding to the chip simulation file and the test plan of the ATE.

[0072] Step 404: Obtain the channel information of each board card in the ATE, and determine the target pin corresponding to the channel information of the board card according to the mapping relationship.

[0073] The ATE usually includes multiple boards, each of which can be independently used for testing, and each of which has a corresponding channel. Therefore, for each board, an encoding table of the corresponding channel can be established. The encoding table can record all channel information of the corresponding board. Since each channel has a mapping relationship with a chip pin in the circuit design, based on the mapping relationship and the channel information of each board in the ATE, the computer device can determine the target pin corresponding to the channel information of each board. The target pin is the pin corresponding to the channel of each board.

[0074] Specifically, the computer device can divide the channels based on the boards, thereby obtaining the encoding table of the channel corresponding to each board, and determine the pin corresponding to each channel in the encoding table of each board based on the mapping relationship between the channel and the pin, that is, obtain the target pin of each board.

[0075] Step 406: extracting, from the digital signal waveform file in PAT format, the state information of each period of the target pin by column.

[0076] Since the digital signal waveform file in PAT format records the state information of each pin in each period by column, in the embodiment, the computer device can extract the state information of each period of the target pin from the digital signal waveform file in PAT format by column, that is, extract the state information of each period of the target pin corresponding to each board.

[0077] Step 408: generating a binary vector file for ATE testing of the board based on the extracted state information of each period of the target pin.

[0078] Specifically, the computer device can generate a binary vector file for ATE testing of the board based on the extracted state information of each period of the target pin corresponding to each board, that is, generate a binary vector file for ATE testing of each board. Therefore, the digital signal waveform file in PAT format is converted into a binary vector file for ATE testing.

[0079] In an exemplary embodiment, before the state information of each period of the target pin is extracted from the digital signal waveform file in PAT format by column in step 406, the above method can further include: based on a preset regular expression, verifying each row of the digital signal waveform file in PAT format to determine whether the state information of each pin is valid, thereby verifying the validity of the digital signal waveform file in PAT format. In the case where the state information of each pin is valid, the state information of each pin is semantically analyzed by using a structured syntax tree, so as to understand the meaning of each row of vector and obtain the corresponding syntax tree, thereby organizing and managing the waveform vector.

[0080] In an exemplary embodiment, the above-mentioned waveform file conversion method for chip testing is further described, which can specifically include the following steps:

[0081] Step one: read the waveform file to be converted in.vcd / .evcd / .wgl format, parse the text content according to the specification of each file.

[0082] Step two: extract time information from the waveform file, including cycle information, edge transition time point, etc.

[0083] Step three: according to the timing growth, sample the input and output state of multiple pins once in each cycle, and recombine the vector data.

[0084] That is, one line corresponds to one clock cycle, each line increments one clock cycle, and each line vector contains multiple pins, indicating the digital signal state of multiple pins in the current clock cycle. The valid digital signal state includes input driving and output capturing in two directions, which adopts different logic consistent representation, for example, driving low 0, driving high 1, driving high impedance Z, capturing logic low signal L, capturing logic high signal H, capturing logic valid signal V, and capturing digital K. This way makes each line vector contain both current time information and logic state of each pin. And these encoding methods are more suitable for binary encoding of semiconductor ATE equipment, which can improve the operation efficiency and accuracy of the equipment.

[0085] Step four: compress the continuous repeating vector, and adjust and check the timing through RPT / LOOP instructions.

[0086] Among them, the RPT (Repeat) instruction is used to repeat the execution of a code block until a certain condition is met, usually needs to specify the number of repetitions or conditions. The LOOP instruction is usually used to create a loop, which will continue to execute a piece of code until a specific exit condition is encountered. In this embodiment, after the vector is compressed, the timing information of the compressed vector can be checked and adjusted based on the timing information of the waveform file to be converted before compression and the timing information of the compressed vector. Specifically, the timing information of the compressed vector can be compared based on the timing information of the waveform file to be converted before compression to obtain a comparison result, and the timing information of the compressed vector is checked and adjusted according to the comparison result, and a digital signal waveform file in PAT format is generated according to the vector after checking and adjusting.

[0087] In some cases, it can be necessary to adjust the execution frequency or time interval of the loop to match specific timing requirements. Verification usually involves ensuring that the loop is executed as expected, avoiding infinite loops, checking the logic within the loop for correctness, avoiding logic errors, and meeting performance requirements. Verification can be implemented based on unit testing, code review, performance analysis, etc.

[0088] Step five: output the adjusted vector by row to create a.pat format waveform vector file. In this file, first list the pin list, such as Pin1, Pin2, Pin3, etc., which are the pins used in the semiconductor ATE device. Then, in time sequence, from top to bottom, one period of waveform vector per row, so that the state of each pin in each period can be clearly seen, making the file more intuitive, easy to understand, problem tracking and debugging. For example, you can set each period to 1ms, then in the first period, the state of Pin1 may be driven to low level 0, the state of Pin2 may be driven to high level 1, and the state of Pin3 may be driven to high impedance Z.

[0089] Step six: prepare for compilation, get the channel distribution of each pin of the multi-chip according to the circuit diagram or test program, so as to obtain the pin and channel mapping relationship of each chip and ATE.

[0090] Step seven: establish a coding table for each test card corresponding to all channels, determine the mapping table of test card channels and chip pins according to the pin and channel mapping relationship of the chip determined in step six.

[0091] Step eight: parse the vector by row using regular expressions. In this step, regular expressions can be used to parse each row of vector to understand the meaning of each row of vector. For example, if the regular expression is set as "^[0-9a-fA-Fa-fZ]", then it can be identified whether each bit in the vector is a valid signal state.

[0092] Step nine: understand the above waveform vector using techniques such as structured syntax tree, keyword index, etc. In this step, techniques similar to structured syntax tree can be used to organize and manage the above waveform vector. At the same time, keyword index technology can also be used to quickly find and locate the required waveform vector.

[0093] Step ten: Real-time analysis and table encoding. In this step, the.pat file is parsed line by line, analyzed in real time, and encoded by looking up the table. This means that at any time, any row vector in the.pat file can be parsed and analyzed. In addition, special "tags" can be added at the start of different encoding segments. In this step, the corresponding tags can also be generated based on the above-mentioned syntax tree, and the tags can be added at the start of the corresponding encoding segment to clearly understand the meaning and length of the encoding segment.

[0094] Step eleven: Write the binary sequence into the.tsi / .rtf file in order from top to bottom according to the tag sequence, where the.tsi stores continuous binary vectors, and the.rtf stores the start and end positions of the tags for ATE testing.

[0095] The above embodiment simplifies the file format by converting various different formats of files into PAT format, which describes the pin signal state in time periods, and can process various different formats of files, with strong adaptability and flexibility. In the PAT file, each row vector contains the signal state of multiple pins in the current period, and multiple period vectors are filled in the.pat format waveform vector file by rows, making the file format more concise and easy to understand and process. The.pat file is divided into two parts, the first part is the pin list, which describes which pin names are used in the current file, and the second part is the waveform vector in time sequence from top to bottom, one period per row. This structured design can improve the efficiency of computer processing and avoid the problem of low efficiency when processing a large amount of data. When compiling the.pat file, the vector is parsed line by line by regular expression, and technologies such as structured syntax tree and keyword index are used to realize real-time analysis and table encoding of the.pat file. This method can ensure that all information in the original file is preserved during the conversion process, avoiding differences between the converted file and the original file.

[0096] It should be understood that although the steps in the flowcharts involved in the embodiments described above are shown in sequence according to the arrows, the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the embodiments described above can include multiple steps or multiple stages, which are not necessarily executed at the same time but can be executed at different times, and the execution order of the steps or stages is not necessarily sequential but can be alternately or alternately executed with at least part of other steps or steps or stages in other steps.

[0097] Based on the same inventive concept, the embodiments of the present application also provide a conversion device for implementing the above-mentioned waveform file conversion method for chip testing. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more waveform file conversion device embodiments for chip testing provided below can refer to the limitations of the waveform file conversion method for chip testing described above, which will not be repeated here.

[0098] In an exemplary embodiment, as shown in FIG. 5, a waveform file conversion device for chip testing is provided, comprising: an analysis module 502, a first format conversion module 504 and a second format conversion module 506, wherein:

[0099] The analysis module 502 is configured to analyze the content of the waveform file to be converted, obtain the period information, pin information and state information of each pin in each period of the waveform file to be converted, and the waveform file to be converted is a chip simulation file in a circuit design and test process.

[0100] The first format conversion module 504 is configured to generate a digital signal waveform file in PAT format according to the period information, pin information and state information of each pin in each period, and the digital signal waveform file in PAT format records the state information of each pin in each period in rows and columns.

[0101] The second format conversion module 506 is configured to convert the digital signal waveform file in PAT format into a binary vector file for ATE testing based on the mapping relationship between the pins and the ATE channels.

[0102] In an exemplary embodiment, the first format conversion module is specifically configured to sample the state information of each pin in each period according to the period information, and perform vector recombination on the state information of each pin in each period according to the timing growth to generate a digital signal waveform file in PAT format.

[0103] In an example embodiment, the first format conversion module is further configured to: identify a continuous repeating period of the vector, determine a repeating vector; perform vector compression based on the corresponding continuous repeating period for the repeating vector, and generate the digital signal waveform file in the PAT format according to the compressed vector.

[0104] In an example embodiment, the device further comprises a verification module configured to: obtain timing information of the waveform file to be converted and timing information of the compressed vector; perform verification and adjustment on the timing information of the compressed vector according to a comparison result of the timing information; and generate the digital signal waveform file in the PAT format according to the vector after verification and adjustment.

[0105] In an example embodiment, the second format conversion module is specifically configured to: determine a mapping relationship between each pin and an ATE channel based on the circuit design and a test plan; obtain channel information corresponding to each board card in the ATE, determine a target pin corresponding to the channel information of the board card according to the mapping relationship; extract state information of each period of the target pin from the digital signal waveform file in the PAT format; and generate a binary vector file for ATE test of the board card based on the extracted state information of each period of the target pin.

[0106] In an example embodiment, the second format conversion module is further configured to: perform line-by-line verification on the digital signal waveform file in the PAT format based on a preset regular expression, to determine whether the state information of each pin is valid; and in a case where it is determined that the state information of each pin is valid, perform semantic analysis on the state information of each pin using a structured syntax tree, to obtain a corresponding syntax tree.

[0107] In an example embodiment, the device further comprises a label insertion module configured to insert a label into the binary vector file according to the syntax tree.

[0108] In an example embodiment, the parsing module is specifically configured to: identify a file format of the waveform file to be converted, determine a file specification corresponding to the file format; perform content parsing on the waveform file to be converted according to the file specification, and obtain period information, pin information, and state information of each pin in each period of the waveform file to be converted.

[0109] The modules in the above-described waveform file conversion device for chip testing can be implemented wholly or partially by software, hardware, or a combination thereof. The modules can be embedded in or independent of a processor in a computer device in hardware form, or stored in a memory in the computer device in software form, so as to be called and executed by a processor to perform operations corresponding to the modules.

[0110] As used in this application, the terms "component," "module," and "system" are intended to refer to a computer-related entity, either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and / or thread of execution and a component can be localized, partially or wholly, in one computer or distributed

[0111] In an exemplary embodiment, a computer device can be provided, which can be a terminal, and an internal structure diagram of the computer device can be as shown in FIG. 6. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner, and the wireless manner can be achieved through WIFI, mobile cellular network, near field communication (NFC), or other technologies. The computer program is executed by the processor to implement a waveform file conversion method for chip testing. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball, or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0112] Those skilled in the art can understand that the structure shown in FIG. 6 is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. A specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0113] In an example embodiment, a computer device is provided, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the steps in the above method embodiments when executing the computer program.

[0114] In an example embodiment, a computer readable storage medium is provided, storing a computer program, and the computer program implementing the steps in the above method embodiments when executed by a processor.

[0115] In an example embodiment, a computer program product is provided, comprising a computer program, and the computer program implementing the steps in the above method embodiments when executed by a processor.

[0116] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant regulations.

[0117] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0118] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above-mentioned embodiments are not described, however, as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present application.

[0119] The above-described embodiments are merely illustrative of several embodiments of the present application, which are described in more detail and in a specific manner, but should not be construed as limiting the scope of the patent application. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A waveform file conversion method for chip testing, characterized by, The method comprises: content analysis is performed on a to-be-converted waveform file to obtain period information, pin information, and state information of each pin in each period of the to-be-converted waveform file; the to-be-converted waveform file is a chip simulation file in a circuit design and test process; a PAT format digital signal waveform file is generated according to the period information, the pin information, and the state information of each pin in each period; the PAT format digital signal waveform file records the state information of each pin in each period in the form of rows of periods and columns of pins; the PAT format digital signal waveform file is converted into a binary vector file for testing of an automated test equipment based on a mapping relationship between the pins and channels of the automated test equipment.

2. The method of claim 1, wherein, The method of generating the PAT format digital signal waveform file according to the period information, the pin information, and the state information of each pin in each period comprises: the state information of each pin in each period is sampled according to the period information; the state information of each pin in each period is vector-reorganized according to a timing increase to generate the PAT format digital signal waveform file.

3. The method of claim 2, wherein, The method of generating the PAT format digital signal waveform file according to the timing increase and vector-reorganizing the state information of each pin in each period comprises: the state information of each pin in each period is vector-reorganized according to the timing increase in the form of rows of periods and columns of pins to generate the PAT format digital signal waveform file.

4. The method of claim 2, wherein, After the vector-reorganization of the state information of each pin in each period, the method further comprises: a repeated vector is determined by identifying a continuously repeated period of the vector; the repeated vector is compressed based on the corresponding continuously repeated period, and the PAT format digital signal waveform file is generated according to the compressed vector.

5. The method of claim 4, wherein, The method further comprises: timing information of the to-be-converted waveform file and timing information of the compressed vector are obtained; the timing information of the compressed vector is checked and adjusted according to a comparison result of the timing information; the PAT format digital signal waveform file is generated according to the checked and adjusted vector.

6. The method of claim 5, wherein, The checking is implemented based on at least one of unit testing, code review, and performance analysis; the adjustment comprises adjusting an execution frequency or a time interval of a loop.

7. The method of claim 1, wherein, The method of converting the PAT format digital signal waveform file into a binary vector file for testing of an automated test equipment based on a mapping relationship between the pins and channels of the automated test equipment comprises: the mapping relationship between the pins and channels of the automated test equipment is determined based on the circuit design and a test plan; channel information corresponding to each board card in the automated test equipment is obtained, and target pins corresponding to the channel information of the board card are determined according to the mapping relationship; state information of each period of the target pins is extracted from the PAT format digital signal waveform file column by column; a binary vector file for testing of the board card for the automated test equipment is generated based on the extracted state information of each period of the target pins.

8. The method of claim 7, wherein, Before the extracting the state information of each cycle of the target pin from the PAT format digital signal waveform file by column, the method further comprises: Based on a preset regular expression, the PAT format digital signal waveform file is checked by row to determine whether the state information of each pin is valid; In the case of determining that the state information of each pin is valid, the state information of each pin is semantically analyzed by using a structured syntax tree to obtain a corresponding syntax tree.

9. The method of claim 8, wherein, The method further comprises: According to the syntax tree, a label is inserted in the binary vector file.

10. The method according to any one of claims 1 to 9, characterized in that, The content analysis of the to-be-converted waveform file to obtain the cycle information, pin information and state information of each pin in each cycle of the to-be-converted waveform file comprises: Identifying the file format of the to-be-converted waveform file to determine the file specification corresponding to the file format; According to the file specification, the content of the to-be-converted waveform file is analyzed to obtain the cycle information, pin information and state information of each pin in each cycle of the to-be-converted waveform file.

11. A waveform file conversion apparatus for chip testing, characterized by, The device comprises: The parsing module is configured to analyze the content of the to-be-converted waveform file to obtain the cycle information, pin information and state information of each pin in each cycle of the to-be-converted waveform file; the to-be-converted waveform file is a chip simulation file in a circuit design and test process; The first format conversion module is configured to generate a PAT format digital signal waveform file according to the cycle information, pin information and state information of each pin in each cycle; the PAT format digital signal waveform file records the state information of each pin in each cycle by row and by column; The second format conversion module is configured to convert the PAT format digital signal waveform file into a binary vector file for testing by an automated test equipment based on a mapping relationship between each pin and a channel of the automated test equipment.

12. The apparatus of claim 11, wherein, The first format conversion module is specifically configured to sample the state information of each pin in each cycle according to the cycle information; and perform vector reorganization on the state information of each pin in each cycle according to time sequence growth to generate the PAT format digital signal waveform file.

13. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that, The processor executes the computer program to implement the steps of the method in any one of claims 1 to 10.

14. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 10.

15. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 10. The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 10.

Images