Display panel and display device

Abstract

The invention provides a display panel and a display device, the display panel is provided with a chip binding area, and the display panel comprises an output terminal group, a multiplexer, a test terminal group and an input terminal group which are sequentially arranged in the chip binding area; the display panel further comprises an organic layer arranged in the chip binding area, the organic layer comprises a first boundary and a second boundary, the first boundary is located between the multiplexer and the output terminal set, the distance between the first boundary and the output terminal set is a, and a is larger than or equal to 30 microns; the second boundary is located between the test terminal set and the input terminal set, the distance between the second boundary and the input terminal set is b, and b is larger than or equal to 30 microns. According to the display panel and the display device, the problem of film stripping of the chip binding area can be solved, and therefore the problem that chip output signals are abnormal due to film stripping is solved; the display quality of the display panel and the display device is improved.

Description

[0001] This application is a divisional application of application No. 202310538406.4, titled "Display panel and display device", filed on May 12, 2023. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] Compared with liquid crystal display, organic light-emitting diode (OLED) display panel has the advantages of lightness, good display effect, high resolution, wide color gamut, low power consumption, and flexible display, etc., so that it has rapidly developed in recent years and has become the preferred display panel type for mobile terminals.

[0004] With the development of OLED display technology, users' requirements for the performance of display panels are gradually increasing. Usually, double 85 experiments / HAST experiments (also known as RA experiments) are used to test the limits of OLED display panels in harsh environments of high temperature and high humidity. The common defect of OLED display panels in double 85 experiments / HAST experiments is the peeling problem of the film layer in the chip on panel (COP) area. The peeling of the film layer in the COP area will cause abnormal output signals of the chip, resulting in vertical bright lines on the OLED display panel and affecting the display quality of the display panel. This problem needs to be solved urgently. SUMMARY

[0005] The present application provides a display panel and a display device, which can effectively solve the problems of display abnormalities and reduced display quality of existing OLED display panels.

[0006] In one aspect, the present application provides a display panel, which has a chip bonding area. The display panel includes an output terminal group, a multiplexer, a test terminal group and an input terminal group arranged in the chip bonding area in sequence. The display panel further includes an organic layer arranged in the chip bonding area. The organic layer includes a first boundary and a second boundary. The first boundary is located between the multiplexer and the output terminal group. The distance between the first boundary and the output terminal group is a, and a≥30μm. The second boundary is located between the test terminal group and the input terminal group. The distance between the second boundary and the input terminal group is b, and b≥30μm.

[0007] Optionally, no electrostatic protection circuit is arranged between the output terminal group and the input terminal group.

[0008] Optionally, the organic layer located between the first boundary and the second boundary is continuously arranged.

[0009] Optionally, the organic layer located between the first boundary and the second boundary is discontinuously arranged, wherein the display panel further comprises a dummy terminal group arranged at the chip bonding area, the dummy terminal group is located between the multiplexer and the test terminal group, the organic layer comprises a third boundary and a fourth boundary, wherein the third boundary is located between the multiplexer and the dummy terminal group, the distance between the third boundary and the dummy terminal group is c, wherein c > m / 6, m is the distance between the third boundary and the first boundary; the fourth boundary is located between the test terminal group and the dummy terminal group, the distance between the fourth boundary and the dummy terminal group is d, wherein d > n / 6, n is the distance between the fourth boundary and the second boundary.

[0010] Optionally, the dummy terminal group comprises a plurality of dummy terminals, and the plurality of dummy terminals form a plurality of dummy terminal rows, wherein c = d ≥ 50 μm.

[0011] Optionally, the organic layer is not arranged between any two adjacent dummy terminal rows.

[0012] Optionally, the dummy terminal group comprises a plurality of dummy terminals, and the plurality of dummy terminals form a dummy terminal row, wherein c = d ≥ 80 μm.

[0013] Optionally, a = b = c = d.

[0014] Optionally, the organic layer is integrally formed.

[0015] In another aspect, the present application provides a display device, comprising: a housing and the display panel according to any one of the above aspects, wherein the housing has a receiving space, and the display panel is arranged in the receiving space.

[0016] The application provides a display panel and a display device, the display panel has a chip binding area, and the display panel comprises an output terminal group, a multiplexer, a test terminal group and an input terminal group arranged in sequence in the chip binding area; the display panel further comprises an organic layer arranged in the chip binding area, and the organic layer comprises a first boundary and a second boundary, wherein the first boundary is located between the multiplexer and the output terminal group, the distance between the first boundary and the output terminal group is a, and a is greater than or equal to 30 microns; the second boundary is located between the test terminal group and the input terminal group, the distance between the second boundary and the input terminal group is b, and b is greater than or equal to 30 microns, the display panel and the display device provided by the application can improve the film layer peeling problem of the chip binding area, thereby improving the chip output signal abnormality problem caused by the film layer peeling, and improving the display quality. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0018] Figure 1 A plan view of a display area and a chip binding area of the display panel provided by the first embodiment of the application;

[0019] Figure 2 A plan view of an electrical element and an organic layer in the chip binding area provided by the first embodiment of the application;

[0020] Figure 3 A film layer structure schematic view of the display panel provided by the first embodiment of the application;

[0021] Figure 4 A simulation data graph of a strain difference between the organic layer and the interlayer dielectric layer in a pressure and thermal expansion state provided by the first embodiment of the application;

[0022] Figure 5 A plan view of an electrical element and an organic layer in the chip binding area provided by the second embodiment of the application;

[0023] Figure 6 A film layer structure schematic view of the display panel provided by the second embodiment of the application;

[0024] Figure 7 A plan view of an electrical element and an organic layer in the chip binding area provided by the third embodiment of the application;

[0025] Figure 8A schematic diagram of a film layer structure of a display panel is provided for Embodiment Three of the present application.

[0026] Explanation of reference signs:

[0027] Display panel 01; display area 10; chip bonding area 20; output terminal group 21; multiplexer 22; test terminal group 23; input terminal group 24; dummy terminal group 25; dummy terminal 251; substrate 100; first conductive layer 110; interlayer dielectric layer 120; second conductive layer 130; organic layer 140; first boundary 141; second boundary 142; third boundary 143; fourth boundary 144; third conductive layer 150; passivation layer 160; fourth conductive layer 170 DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the outline of the device.

[0029] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplicity, the components and arrangements of the various examples are described in the following detailed description. These are, of course, merely examples and are not intended to limit the application from that described. Furthermore, the application can be implemented in a variety of environments and applications, and, thus, is not limited to the specific examples described herein. Additionally, the present application contemplates that the components and / or the features of the particular examples can be combined with each other and / or separated from each other into further combinations. Moreover, the disclosure provides a number of particular examples relating to specific processes and materials. However, one skilled in the art will recognize that the application is not limited to these particular examples and that changes and modifications can be practiced in various applications. Each of the following examples is made for illustration of the present application. The order of description of the examples below is not meant to imply a preferred order of implementation or a sequence of embodiments.

[0030] Figure 1 A schematic diagram of a display area and a chip bonding area of a display panel is provided for Embodiment One of the present application. Refer to Figure 1As shown, the embodiment one of the present application provides a display panel 01, the display panel 01 has a display area 10 and a chip binding area 20, wherein the display area 10 includes a plurality of data lines and a plurality of scan lines, the orthogonal projection of the data line and the scan line on the display area 10 is cross arranged; the chip binding area 20 or the binding area is provided with a plurality of electrical elements, such as binding terminals, test terminals, multiplexers and the like, the number of the same type of electrical elements can be multiple, and multiple electrical elements of the same type can form an electrical element group. Among them, the binding terminal is electrically connected with the chip, the data line and / or the scan line of the display panel 01 through the binding process, and the type of the binding terminal can be an input terminal electrically connected with the chip, an output terminal electrically connected with the data line and / or the scan line, the input terminal and the output terminal belong to different types of electrical elements; the test terminal is used to be electrically connected with the test circuit during the process of the display panel 01, so as to detect the display performance of the display panel 01; the multiplexer is used to realize the multiplexing function, so as to simplify the circuit structure of the display panel 01.

[0031] Figure 2 The planar schematic diagram of the electrical elements in the chip binding area provided by the embodiment one of the present application and the organic layer; Figure 3 The film layer structure schematic diagram of the display panel provided by the embodiment one of the present application. Combined with Figures 1-3 As shown, in some embodiments of the present application, the display panel 01 has a chip binding area 20, the display panel 01 includes an output terminal group 21, a multiplexer 22, a test terminal group 23 and an input terminal group 24 arranged in the chip binding area 20 in sequence, and the display panel 01 further includes an organic layer 140 arranged in the chip binding area 20, the organic layer 140 includes a first boundary 141 and a second boundary 142, wherein the first boundary 141 is located between the multiplexer 22 and the output terminal group 21, the distance between the first boundary 141 and the output terminal group 21 is a, a≥30μm; the second boundary 142 is located between the test terminal group 23 and the input terminal group 24, the distance between the second boundary 142 and the input terminal group 24 is b, b≥30μm.

[0032] In the related art, when the binding process is performed, the binding terminal and / or other terminals need to be pressed. Because the terminal generally has a certain thickness, when pressed, the terminal will deform, the deformation will pull the film layer near the terminal, and then cause the peeling phenomenon or the peeling trend between the film layers. Because the test environment of double 85 test / HAST test is a high temperature and high humidity environment, it will further aggravate the peeling degree between the film layers, cause the abnormal output signal of the chip, and make the OLED display panel produce vertical bright lines, which affects the display quality of the display panel 01.

[0033] The researchers of the present application find through a large number of experiments that the organic layer 140 is the key film layer that is most prone to peeling problems among the multiple film layers. In the display panel 01 provided by the present application, the distance between the first boundary 141 and the output terminal group 21 is not less than 30 μm, so that the distance between the first boundary 141 and the output terminals in the output terminal group 21 is kept above the minimum safety distance, and thus the peeling problem caused by the output terminals in the output terminal group 21 being pressed to deform and pull the first boundary 141 during the binding process of the output terminal group 21 can be improved, and the probability of abnormal chip output signal is reduced, and the display quality of the display panel 01 is improved. At the same time, the distance between the second boundary 142 and the input terminal group 24 is not less than 30 μm, so that the distance between the second boundary 142 and the input terminals in the input terminal group 24 is kept above the minimum safety distance, and thus the peeling problem caused by the input terminals in the input terminal group 24 being pressed to deform and pull the second boundary 142 during the binding process of the input terminal group 24 can be improved, and the probability of abnormal chip output signal is reduced, and the display quality of the display panel 01 is improved.

[0034] Exemplarily, the arrangement direction of the output terminal group 21, the multiplexer 22, the test terminal group 23 and the input terminal group 24 is a first direction, the first direction is parallel to the data line, wherein the output terminal group 21 includes a plurality of output terminals, the plurality of output terminals are arranged in sequence along a second direction; the test terminal group 23 includes a plurality of test terminals, the test terminals are arranged in sequence along the second direction; the input terminal group 24 includes a plurality of input terminals, the plurality of input terminals are arranged in sequence along the second direction, and the first direction and the second direction are cross arranged in the orthographic projection of the chip binding area 20.

[0035] In some embodiments of the present application, no electrostatic protection circuit is arranged between the output terminal group 21 and the input terminal group 24.

[0036] In the related art, the chip binding area 20 often also has an electrostatic protection circuit, and the layout area of the electrostatic protection circuit is large, which compresses the distance between the terminals and the organic layer 140. In the display panel 01 provided by the present application, no electrostatic protection circuit is arranged between the output terminal group 21 and the input terminal group 24, so that the layout area of other electrical elements between the output terminal group 21 and the input terminal group 24 is increased, and the layout design freedom is greatly improved, so that the distance between the first boundary 141 and the output terminal group 21 is not less than 30 μm, and the distance between the second boundary 142 and the input terminal group 24 is not less than 30 μm.

[0037] In some embodiments of the present application, the organic layer 140 located between the first boundary 141 and the second boundary 142 is continuously arranged.

[0038] In the display panel provided by the present application, the organic layer 140 located between the first boundary 141 and the second boundary 142 is continuously arranged, which can enhance the integrity and stability of the organic layer 140.

[0039] In some embodiments of the present application, a=b.

[0040] In the display panel 01 provided by the present application, a=b, that is, the distance between the first boundary 141 and the output terminal group 21 is equal to the distance between the second boundary 142 and the input terminal group 24, so as to improve the film layer design consistency of the display panel 01, which is conducive to the improvement of production efficiency, thereby achieving the effect of reducing the production cost of the display panel 01.

[0041] In some embodiments of the present application, the display panel 01 comprises, in the chip bonding area 20, a substrate 100, a first conductive layer 110, an interlayer dielectric layer 120, a second conductive layer 130, an organic layer 140, a third conductive layer 150, a passivation layer 160 and a fourth conductive layer 170 arranged in sequence.

[0042] Optionally, the substrate 100 can be a flexible substrate or a rigid substrate, and the material of the substrate 100 is not limited in the present application, which can be an organic material or an inorganic material; for example, the first conductive layer 110 is arranged in the same layer as the gate layer of the display area 10, and the gate layer comprises a gate; for example, the second conductive layer 130 is arranged in the same layer as the first source-drain layer of the display area 10, and the first source-drain layer comprises a first source and a first drain; for example, the third conductive layer 150 is arranged in the same layer as the second source-drain layer of the display area 10, and the second source-drain layer comprises a second source and a second drain.

[0043] In some embodiments of the present application, the organic layer 140 covers the multiplexer 22 to protect the components in the multiplexer 22; and the organic layer 140 does not cover the test terminal, so as to facilitate the staff to test the display panel 01 through the test terminal during the preparation process of the display panel 01.

[0044] In some embodiments of the present application, the organic layer 140 is integrally formed.

[0045] In the related art, the organic layer 140 of the chip bonding area 20 is a double-film layer structure, and the double-film layer structure increases the thickness of the organic layer 140 and the complexity of the structure, increases the peeling risk of the organic layer 140 in the bonding process and the upper limit of expansion in the high-temperature and high-humidity environment created by the double 85 test / HAST test. In the display panel 01 provided in the present application, the organic layer 140 is integrally formed, so that the organic layer 140 is a single-film layer structure, thereby reducing the strain difference between the organic layer 140 and other film layers in the bonding process and the double 85 test / HAST test process.

[0046] Figure 4 The simulation data graph of the strain difference between the organic layer and the interlayer dielectric layer in the state of pressure and thermal expansion is provided for the chip bonding area of the embodiment one of the present application. Figure 4 It can be seen that in the state of pressure in the bonding process, the strain difference between the organic layer 140 and the interlayer dielectric layer 120 in the display panel 01 with the double organic layer 140 is as high as 6.872E-04, while the strain difference between the organic layer 140 and the interlayer dielectric layer 120 in the display panel 01 with the single organic layer 140 is only 4.771E-04, and the strain difference is greatly reduced. In the state of thermal expansion in the double 85 test / HAST test, the strain difference between the organic layer 140 and the interlayer dielectric layer 120 in the display panel 01 with the double organic layer 140 is as high as 7.149E-04, while the strain difference between the organic layer 140 and the interlayer dielectric layer 120 in the display panel 01 with the single organic layer 140 is only 3.408E-04, and the strain difference is greatly reduced.

[0047] In some embodiments of the present application, the thickness of the organic layer 140 is less than or equal to 4 μm.

[0048] Specifically, in the related art, the thickness of each sub-film layer in the organic layer 140 of the chip bonding area 20 is more than 2 μm, and therefore the thickness of the organic layer 140 with the double-film layer structure is more than 4 μm. By reducing the thickness of the organic layer 140, the present application can further reduce the strain difference between the organic layer 140 and other film layers in the bonding process and the double 85 test / HAST test process.

[0049] On the other hand, the present application also provides a display device, which comprises a housing and the display panel 01 according to any one of the above embodiments, wherein the housing has a receiving space, and the display panel 01 is arranged in the receiving space.

[0050] Embodiment two

[0051] Figure 5 The plan view of the electrical element and the organic layer in the chip bonding area is provided for the embodiment two of the present application. Figure 6FIG. 2 shows a schematic diagram of a film layer structure of a display panel according to an embodiment of the present application. Figure 1 、 Figure 5 and Figure 6 According to the second embodiment of the present application, a display panel 01 and a display device are provided. The display panel 01 has a chip bonding area 20. The display panel 01 includes, in sequence, an output terminal group 21, a multiplexer 22, a test terminal group 23, and an input terminal group 24 in the chip bonding area 20. The display panel 01 further includes an organic layer 140 disposed in the chip bonding area 20. The organic layer 140 includes a first boundary 141 and a second boundary 142. The first boundary 141 is located between the multiplexer 22 and the output terminal group 21. The distance between the first boundary 141 and the output terminal group 21 is a, and a ≥ 30 μm. The second boundary 142 is located between the test terminal group 23 and the input terminal group 24. The distance between the second boundary 142 and the input terminal group 24 is b, and b ≥ 30 μm. The display device includes a housing and the display panel 01. The housing has a receiving space, and the display panel 01 is disposed in the receiving space.

[0052] It should be noted that the structure of the display panel 01 and the display device according to the second embodiment of the present application is similar to that of the display panel 01 and the display device according to the first embodiment of the present application. The same parts will not be described again.

[0053] The difference is that, in some embodiments of the present application, the organic layer 140 disposed between the first boundary 141 and the second boundary 142 is discontinuous. The display panel 01 further includes a dummy terminal group 25 disposed in the chip bonding area 20. The dummy terminal group 25 is located between the multiplexer 22 and the test terminal group 23. The organic layer 140 includes a third boundary 143 and a fourth boundary 144. The third boundary 143 is located between the multiplexer 22 and the dummy terminal group 25. The distance between the third boundary 143 and the dummy terminal group 25 is c. c > m / 6, and m is the distance between the third boundary 143 and the first boundary 141. The fourth boundary 144 is located between the test terminal group 23 and the dummy terminal group 25. The distance between the fourth boundary 144 and the dummy terminal group 25 is d. d > n / 6, and n is the distance between the fourth boundary 144 and the second boundary 142.

[0054] In the related art, the dummy terminal group 25 plays a role of auxiliary support during the binding process. The researchers found that, since the dummy terminal group 25 is located between the multiplexer 22 and the test terminal group 23, it is easier to pull the organic layer 140 near the dummy terminal group 25 during the binding compression, thereby causing the peeling problem of the organic layer 140 at the third boundary 143 and the fourth boundary 144.

[0055] The present application is specially designed according to the special position of the dummy terminal group 25, so that the distance between the third boundary 143 and the dummy terminal group 25 is not less than one sixth of the distance between the third boundary 143 and the first boundary 141, and the distance between the fourth boundary 144 and the dummy terminal group 25 is not less than one sixth of the distance between the fourth boundary 144 and the second boundary 142. The distance between the third boundary 143, the fourth boundary 144 and the dummy terminal 251 in the dummy terminal group 25 is kept above the safe distance, so that the peeling problem caused by the dummy terminal 251 in the dummy terminal group 25 being pressed and deformed to pull the third boundary 143 and the fourth boundary 144 during the binding process of the output terminal group 21 and the input terminal group 24 can be improved, thereby reducing the probability of abnormal chip output signal and improving the display quality of the display panel 01.

[0056] In some embodiments of the present application, the dummy terminal group 25 includes a plurality of dummy terminals 251, and the plurality of dummy terminals 251 form a plurality of dummy terminal rows, wherein c=d≥50μm, and m / 6 and n / 6 are both less than 50μm.

[0057] In the display panel 01 provided by the present application, the plurality of dummy terminals 251 form a plurality of dummy terminal rows, and the dummy terminal row closest to the output terminal group 21 can play a role of auxiliary support during the binding process of the output terminal; and the dummy terminal row closest to the input terminal group 24 can play a role of auxiliary support during the binding process of the input terminal.

[0058] In the display panel 01 provided by the present application, since c=d≥50μm, the distance between the third boundary and the dummy terminal group and the distance between the fourth boundary and the test terminal group are both d, which are much larger than the safe distance 30μm in Embodiment I, thereby improving the peeling problem caused by the dummy terminal group being pressed more and deformed more, and improving the stability of the display panel.

[0059] And, since c=d, that is, the distance between the third boundary 143 and the output terminal group 21 is equal to the distance between the fourth boundary 144 and the input terminal group 24, the film layer design consistency of the display panel 01 can be improved, which is beneficial to the improvement of production efficiency, thereby achieving the effect of reducing the production cost of the display panel 01.

[0060] In some embodiments of the present application, the organic layer 140 is not arranged between any two adjacent dummy terminal rows.

[0061] In the display panel 01 provided by the present application, since the organic layer 140 is not arranged between any two adjacent dummy terminal rows, the probability of film layer peeling when the area between the two adjacent dummy terminal rows is pressed and expands due to heat is greatly reduced.

[0062] Further, a=b=c=d.

[0063] In the display panel 01 provided by the present application, a=b=c=d, that is, the distance between the first boundary 141 and the output terminal group 21, the distance between the second boundary 142 and the input terminal group 24, the distance between the third boundary 143 and the dummy terminal group 25, and the distance between the fourth boundary 144 and the test terminal group 23 are all equal, thereby improving the film layer design consistency of the display panel 01, which is beneficial to the improvement of production efficiency, thereby achieving the effect of reducing the production cost of the display panel 01.

[0064] Embodiment three

[0065] Figure 7 The plan view of the electrical elements and the organic layer in the chip binding area provided by the third embodiment of the present application is shown in the figure; Figure 8 The film layer structure diagram of the display panel provided by the third embodiment of the present application is shown in the figure. Combined with the above description of the chip binding area, Figure 1 、 Figure 7 and Figure 8As shown, the embodiment three of the present application provides a display panel 01 and a display device, the display panel 01 has a chip binding area 20, the display panel 01 includes an output terminal group 21, a multiplexer 22, a test terminal group 23 and an input terminal group 24 arranged in the chip binding area 20 in turn, the display panel 01 further includes an organic layer 140 arranged in the chip binding area 20, the organic layer 140 includes a first boundary 141 and a second boundary 142, wherein the first boundary 141 is located between the multiplexer 22 and the output terminal group 21, the distance between the first boundary 141 and the output terminal group 21 is a, a≥30μm; the second boundary 142 is located between the test terminal group 23 and the input terminal group 24, the distance between the second boundary 142 and the input terminal group 24 is b, b≥30μm, the display device includes a shell and the display panel 01, wherein the shell has a containing space, and the display panel 01 is arranged in the containing space.

[0066] It should be noted that the structure of the display panel 01 and the display device provided by the embodiment three of the present application is similar to the structure of the display panel 01 and the display device provided by the embodiment two of the present application, and the same parts will not be described here.

[0067] The difference is that in some embodiments of the present application, the dummy terminal group 25 includes a plurality of dummy terminals 251, and the plurality of dummy terminals 251 form a dummy terminal row, wherein c=d≥80μm.

[0068] In the display panel 01 provided by the present application, because the plurality of dummy terminals 251 form a dummy terminal row, during the binding process of the output terminal and the input terminal, the dummy terminal row needs to be pressed to play a supporting role, and by further increasing the distance between the third boundary 143 and the dummy terminal group 25 and further increasing the distance between the fourth boundary 144 and the dummy terminal group 25, the problem of increased film layer peeling risk caused by the increased deformation amount of the dummy terminal row under pressure can be improved.

[0069] And because the plurality of dummy terminals 251 form a dummy terminal row, the layout area of the dummy terminal group 25 can be reduced, thereby further increasing the distance between the third boundary 143 and the dummy terminal group 25 and further increasing the distance between the fourth boundary 144 and the dummy terminal group 25, thereby further reducing the peeling problem caused by the dummy terminals 251 in the dummy terminal group 25 being pressed and deformed to pull the first boundary 141, and further reducing the probability of abnormal chip output signal and improving the display quality of the display panel 01.

[0070] In addition, since c=d, that is, the distance between the third boundary 143 and the output terminal group 21 is equal to the distance between the fourth boundary 144 and the input terminal group 24, the film layer design consistency of the display panel 01 can be improved, the production efficiency is improved, and the production cost of the display panel 01 is reduced.

[0071] Further, a=b=c=d.

[0072] In the display panel 01 provided by the application, a=b=c=d, that is, the distance between the first boundary 141 and the output terminal group 21, the distance between the second boundary 142 and the input terminal group 24, the distance between the third boundary 143 and the dummy terminal group 25, and the distance between the fourth boundary 144 and the test terminal group 23 are all equal, so that the film layer design consistency of the display panel 01 can be improved, the production efficiency is improved, and the production cost of the display panel 01 is reduced.

[0073] In summary, the application provides a display panel and a display device, the display panel has a chip binding area, and the display panel includes an output terminal group, a multiplexer, a test terminal group, and an input terminal group arranged in the chip binding area in sequence; the display panel further includes an organic layer arranged in the chip binding area, and the organic layer includes a first boundary and a second boundary, wherein the first boundary is located between the multiplexer and the output terminal group, the distance between the first boundary and the output terminal group is a, and a≥30μm; the second boundary is located between the test terminal group and the input terminal group, and the distance between the second boundary and the input terminal group is b, and b≥30μm. The display panel and the display device provided by the application can improve the film layer peeling problem of the chip binding area, thereby improving the chip output signal abnormality problem caused by film layer peeling, and improving the display quality.

[0074] The above describes a display panel and a display device provided by the application in detail, and the principles and implementation modes of the application are described by applying specific examples. The above description of the embodiments is only used to help understand the method of the application and its core idea; at the same time, for those skilled in the art, according to the idea of the application, the specific implementation mode and application range will be changed, and the above description of the application should not be understood as a limitation.

Claims

1. A display panel, characterized by, The display panel has a chip bonding area, and the display panel comprises: an output terminal group located in the chip bonding area; an input terminal group located in the chip bonding area; and an organic layer located in the chip bonding area and comprising a first boundary and a second boundary, the first boundary and the second boundary being located between the output terminal group and the input terminal group; the first boundary is adjacent to the output terminal group, and the distance between the first boundary and the output terminal group is a; the second boundary is adjacent to and spaced apart from the input terminal group, and the distance between the second boundary and the input terminal group is b; wherein a≥30μm, and / or b≥30μm.

2. The display panel of claim 1, wherein, No electrostatic protection circuit is arranged between the output terminal group and the input terminal group.

3. The display panel of claim 1, wherein, The organic layer continuously arranged between the first boundary and the second boundary.

4. The display panel of claim 1, wherein, The organic layer further comprises a third boundary and a fourth boundary, the third boundary and the fourth boundary being located between the first boundary and the second boundary; the third boundary is adjacent to the first boundary, and the distance between the third boundary and the first boundary is m; the fourth boundary is adjacent to the second boundary, and the distance between the fourth boundary and the second boundary is n; The display panel further comprises a dummy terminal group located in the chip bonding area and between the third boundary and the fourth boundary; the distance between the third boundary and the dummy terminal group is c, and the distance between the fourth boundary and the dummy terminal group is d; wherein c>m / 6, and / or d>n / 6.

5. The display panel of claim 4, wherein, The organic layer is continuously arranged between the first boundary and the third boundary, and continuously arranged between the second boundary and the fourth boundary.

6. The display panel of claim 4, wherein, The organic layer is disconnected by a breakage between the third boundary and the fourth boundary.

7. The display panel of claim 4, wherein, c≥50μm, and d≥50μm.

8. The display panel of claim 4, wherein, c and d satisfy the relationship c=d.

9. The display panel of claim 4, wherein, The dummy terminal group comprises one or more dummy terminal rows, and one dummy terminal row comprises a plurality of dummy terminals.

10. The display panel of claim 9, wherein, The dummy terminal group comprises a plurality of dummy terminal rows, and no organic layer is arranged between any two adjacent dummy terminal rows.

11. The display panel of claim 1, wherein, a and b satisfy the relationship a=b.

12. The display panel of any one of claims 1 to 11, wherein, Further comprising: a multiplexer located in the chip bonding area; the organic layer covers the multiplexer; and a test terminal group located in the chip bonding area and between the multiplexer and the input terminal group, and comprising test terminals, part of the test terminals being located in the organic layer. The organic layer is a single film layer structure.

13. The display panel of any one of claims 1 to 11, wherein, The thickness of the organic layer is less than or equal to 4μm.

14. The display panel of any one of claims 1 to 11, wherein, The display device comprises the display panel of any one of claims 1 to 14.

15. A display device comprising: ​

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