Debugging system

Abstract

The invention provides a debugging system. The debugging system comprises debugging equipment; a coaxial cable; a debugged device; the debugging equipment is used for sending control data to the debugged equipment through the coaxial cable and receiving feedback data of the debugged equipment, the control data comprises a read / write block instruction, a block address instruction and a read / write start instruction, and the read / write block instruction represents information of the data size of a target data set to be read / written; the block address instruction represents initial address information of the target data set in the debugged equipment, the read / write start instruction is an instruction for indicating the debugged equipment to perform read / write operation, and the target data set comprises multiple pieces of target data; and the debugged equipment is used for performing read / write operation according to the read / write block instruction, the block address instruction and the read / write start instruction, and sending feedback data to the debugged equipment. According to the invention, the problems of long debugging time and weak anti-interference capability caused by slow data transmission in the debugging process in the prior art are solved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and more specifically, to a debugging system. Background Technology

[0002] The operation of a modern car engine is controlled by the car's computer (ECU, or Electronic Control Unit). The ECU controls the engine's intake air volume, fuel injection volume, ignition timing, etc., thereby determining the engine's operating efficiency, power, torque, and other performance characteristics. The ECU is essentially an electronic control unit, composed of input processing circuitry, a microcontroller (SoC, or System on Chip) chip, output processing circuitry, system communication circuitry, and a power supply. After installation, the automotive ECU requires vehicle-wide debugging. The debugging equipment primarily targets the MCU / SoC chip and data storage chip within the ECU. Currently, the MCU / SoC chips in automotive ECUs often use the multi-wire JTAG (Joint Test Action Group) protocol or the two-wire SWD (Serial Wire Debug) protocol for debugging. Existing debugging systems suffer from weak anti-interference capabilities.

[0003] In existing debugging systems, when reading / writing to the memory in an ECU, if there are multiple data items to be read / written, the debugger needs to send the read / write command and address information corresponding to each data item in sequence. Only then will the ECU feed back the corresponding data to the debugger in sequence according to the read / write command and address information. When there is too much data to read / write, the debugging time is long and the data transmission is slow. Summary of the Invention

[0004] The main objective of this application is to provide a debugging system that at least solves the problem of slow data transmission leading to long debugging times in the prior art.

[0005] To achieve the above objectives, according to one aspect of this application, a debugging system is provided, comprising: a debugging device; a coaxial cable including a metal cladding layer and a center conductor, the metal cladding layer surrounding the center conductor and grounded, a first end of the center conductor being electrically connected to the debugging device; a device under debugging, a second end of the center conductor being electrically connected to the device under debugging; the debugging device being configured to transmit control data to the device under debugging via the coaxial cable, the control data including a read / write block instruction, a block address instruction, and a read / write start instruction, the read / write block instruction representing information about the size of a target data group to be read / written, the block address instruction representing information about the starting address of the target data group in the device under debugging, the read / write start instruction being an instruction instructing the device under debugging to perform a read / write operation, the target data group including multiple target data; the device under debugging being configured to perform the read / write operation according to the read / write block instruction, the block address instruction, and the read / write start instruction, and to send feedback data corresponding to the target data group to the debugging device.

[0006] Optionally, the device under test is further configured to read / write the target data group starting from the target block corresponding to the starting address information according to the read / write block instruction, the block address instruction and the read / write start instruction, wherein the target data group occupies multiple blocks including the target block.

[0007] Optionally, the debugging system further includes a pull-up circuit, wherein the second end of the center conductor is electrically connected to the device under debugging through the pull-up circuit.

[0008] Optionally, the debugging device is further configured to determine one of a plurality of communication formats recognizable by the device under debugging as the target communication format, and configure the communication format of the control data as the target communication format; the device under debugging is further configured to send the feedback data after configuring the communication format of the feedback data as the target communication format.

[0009] Optionally, the debugging device is further configured to configure the data bit width of the control data; the device under debugging is further configured to configure the data bit width of the feedback data.

[0010] Optionally, the debugging device includes: a first interrupt detection module, which is used to determine whether a transmission error has occurred in the communication with the device under debugging, and to issue a first interrupt command if the transmission error occurs; and a first interrupt request module, which is connected to both the first interrupt detection module and the device under debugging, and is used to interrupt the transmission of the control data upon receiving the first interrupt command. The device under debugging includes: a second interrupt detection module, which is used to determine whether a transmission error has occurred in the communication with the debugging device, and to issue a second interrupt command if the transmission error occurs; and a second interrupt request module, which is connected to both the second interrupt detection module and the debugging device, and is used to interrupt the transmission of the feedback data upon receiving the second interrupt command.

[0011] Optionally, the first interruption detection module is further configured to determine that a transmission error has occurred in communication with the device under test when the first transmission duration is greater than a first threshold duration, wherein the first transmission duration is the duration for transmitting the control data and the first threshold duration is a preset duration for normal transmission of the control data; the second interruption detection module is further configured to determine that a transmission error has occurred in communication with the device under test when the second transmission duration is greater than a second threshold duration, wherein the second transmission duration is the duration for transmitting the feedback data and the second threshold duration is a preset duration for normal transmission of the feedback data.

[0012] Optionally, the debugging device is further configured to send a timing instruction to the device under debugging, the timing instruction being an instruction representing the read / write operation performed according to a timing read / write interval duration; the device under debugging is further configured to store the timing read / write interval duration upon receiving the timing instruction, and to perform the read / write operation according to the timing read / write interval duration upon receiving the read / write start instruction.

[0013] Optionally, the target communication format includes phase offset keying format and NRZ (Non-Return-to-Zerocode) UART (Universal Asynchronous Receiver / Transmitter) format.

[0014] Optionally, the data bit width includes one of 8 bits, 16 bits, 32 bits, and 64 bits.

[0015] According to the technical solution of this application, the debugging system includes debugging equipment, a coaxial cable, and a device under debugging. The coaxial cable includes a metal cladding layer and a central conductor surrounded by the metal cladding layer. The metal cladding layer is grounded. A first end of the central conductor is electrically connected to the debugging equipment, and a second end of the central conductor is electrically connected to the device under debugging. The debugging equipment is used to send control data, including read / write block instructions, block address instructions, and read / write start instructions, to the device under debugging via the coaxial cable. The read / write block instructions represent the data size information of a target data group containing multiple target data to be read / written. The block address instructions represent the starting address information of the target data group in the device under debugging. The read / write start instructions are instructions to the device under debugging to perform read / write operations. The device under debugging is used to perform read / write operations according to the read / write block instructions, block address instructions, and read / write start instructions, and send feedback data corresponding to the target data group to the debugging equipment. Compared to existing debugging systems where multiple data need to be read / written, requiring the debugger to sequentially send read / write commands and address information for each data item before the ECU can feed back the corresponding data, resulting in longer debugging times and slower data transmission when there is a large amount of data to be read / written, this application addresses the problem that when the target data group to be read / written includes multiple target data items, the debugging device only needs to send a read / write block command, a block address command, and a read / write start command to the device under debugging once. The block address command represents the starting address information of the target data group in the device under debugging, which can complete the reading / writing of multiple target data items in the target data group at once and send the corresponding feedback data to the debugging device. This eliminates the need to send multiple read / write commands and address information, ensuring shorter debugging time, faster data transmission, and higher debugging efficiency. In addition, this application uses coaxial cable for signal transmission, ensuring faster data transmission speed, and the grounding of the metal envelope layer ensures strong anti-interference capability of the debugging system. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A schematic diagram of the structure of a debugging system provided in an embodiment of this application is shown;

[0018] Figure 2 A schematic diagram of a debugging system provided according to an embodiment of this application is shown when the device being debugged is an MCU in an automotive ECU;

[0019] Figure 3An embodiment of this application is shown, which provides a method for... Figure 2 A schematic diagram of the storage block transfer function in the corresponding debugging system;

[0020] Figure 4 An embodiment of this application is shown, which provides a method for... Figure 3 A schematic diagram of the timed transmission function of the storage block in the corresponding debugging system;

[0021] Figure 5 An embodiment of this application is shown, which provides a method for... Figure 2 A more detailed structural diagram of the corresponding debugging system;

[0022] Figure 6 An embodiment of this application is shown, which provides a method for... Figure 2 A schematic diagram of the debugging system structure when the device being debugged is an external storage device;

[0023] Figure 7 A waveform diagram of data transmission with a target communication format of phase offset keying is shown according to an embodiment of this application;

[0024] Figure 8 A waveform diagram of data transmission in NRZ UART format, according to an embodiment of this application, is shown.

[0025] The above figures include the following reference numerals:

[0026] 10. Debugging equipment; 11. Coaxial cable; 12. Metal cladding layer; 13. Center wire; 14. Device under test; 15. Single-bus on-chip debugging unit; 16. Memory read / write unit; 17. Pull-up circuit; 18. First diode; 19. First resistor; 20. First power supply; 21. Second power supply; 22. Second resistor; 23. Output port; 24. Input port; 25. Third power supply; 26. Second diode; 27. Third diode; 28. Transistor; 29. ​​Input interface; 30. Bus unit; 31. Register unit; 32. CPU unit 33. Third resistor; 34. Receiver subunit; 35. Transmitter subunit; 36. Register subunit; 37. Control subunit; 38. Filtering module; 39. Second interrupt detection module; 40. Data set module; 41. Sampling module; 42. SP conversion module; 43. Second interrupt request module; 44. Transmitting module; 45. Selection module; 46. Memory read / write control module; 47. Bus control module; 48. Register read / write control module; 49. Transmit / receive control module; 50. Arbitration selection unit; 51. External MCU / SOC unit. Detailed Implementation

[0027] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] As described in the background section, the slow data transmission during the debugging process of the prior art results in a long debugging time. To solve the above problems, the embodiments of this application provide a debugging system.

[0031] In a typical embodiment of this application, a debugging system is provided, such as... Figure 1 As shown, it includes:

[0032] Debugging equipment 10;

[0033] The coaxial cable 11 includes a metal cladding layer 12 and a center conductor 13. The metal cladding layer 12 surrounds the center conductor 13. The metal cladding layer 12 is grounded. The first end of the center conductor 13 is electrically connected to the debugging equipment 10.

[0034] The second end of the center wire 13 of the device under test 14 is electrically connected to the device under test 10.

[0035] Specifically, the device under debugging includes at least one of an MCU, a SoC, and a standalone memory, without any specific limitation in this application. The standalone memory includes, but is not limited to, MRAM (Magnetoresistive Random-Access Memory), FRAM (Ferroelectric Random Access Memory), RRAM (Resistive Random Access Memory), FLASH ROM (Flash Read-Only Memory), and SRAM (Static Random Access Memory).

[0036] The aforementioned debugging device 10 is used to send control data to the device under debugging 14 via the aforementioned coaxial cable 11. The aforementioned control data includes read / write block instructions, block address instructions, and read / write start instructions. The aforementioned read / write block instructions represent the data size information of the target data group to be read / written. The aforementioned block address instructions represent the starting address information of the target data group in the device under debugging 14. The aforementioned read / write start instructions are instructions to the device under debugging 14 to perform read / write operations. The aforementioned target data group includes multiple target data.

[0037] The device under test 14 is used to perform the read / write operation according to the read / write block instruction, the block address instruction and the read / write start instruction, and send the feedback data corresponding to the target data group to the debugging device 10.

[0038] The aforementioned debugging system includes debugging equipment, a coaxial cable, and a device under debugging. The coaxial cable includes a metal sheath and a central conductor surrounded by the metal sheath. The metal sheath is grounded. One end of the central conductor is electrically connected to the debugging equipment, and the other end is electrically connected to the device under debugging. The debugging equipment transmits control data, including read / write block instructions, block address instructions, and read / write start instructions, to the device under debugging via the coaxial cable. The read / write block instructions represent the size of a target data group containing multiple target data items to be read / written. The block address instructions represent the starting address of the target data group within the device under debugging. The read / write start instructions instruct the device under debugging to perform read / write operations. The device under debugging performs read / write operations according to the read / write block instructions, block address instructions, and read / write start instructions, and sends feedback data corresponding to the target data group to the debugging equipment. Compared to existing debugging systems where multiple data need to be read / written, requiring the debugger to sequentially send read / write commands and address information for each data item before the ECU can feed back the corresponding data, resulting in longer debugging times and slower data transmission when there is a large amount of data to be read / written, this application addresses the problem that when the target data group to be read / written includes multiple target data items, the debugging device only needs to send a read / write block command, a block address command, and a read / write start command to the device under debugging once. The block address command represents the starting address information of the target data group in the device under debugging, which can complete the reading / writing of multiple target data items in the target data group at once and send the corresponding feedback data to the debugging device. This eliminates the need to send multiple read / write commands and address information, ensuring shorter debugging time, faster data transmission, and higher debugging efficiency. In addition, this application uses coaxial cable for signal transmission, ensuring faster data transmission speed, and the grounding of the metal envelope layer ensures strong anti-interference capability of the debugging system.

[0039] In addition, the debugging device described in this application is connected to the device being debugged via a single coaxial cable, which requires only one chip pin. Compared with JTAG (5 lines) and SWD (2 lines), it consumes fewer hardware resources and reduces hardware costs. Specifically, the data transmission speed of this application can reach 32Mbps.

[0040] Figure 2 This is a schematic diagram of the debugging system when the device being debugged is the MCU in an automotive ECU.

[0041] Specifically, such as Figure 2As shown, the device under test 14 includes a single-bus on-chip debugging unit 15 and a memory read / write unit 16. The first end of the single-bus on-chip debugging unit 15 is connected to the second end of the center wire 13, and the second end of the single-bus on-chip debugging unit 15 is connected to the memory read / write unit 16. The debugging device 10 sends the control data to the single-bus on-chip debugging unit 15, and the single-bus on-chip debugging unit 15 controls the memory read / write unit 16 to perform read / write operations.

[0042] In one optional embodiment, the device under debugging is further configured to read / write the target data group starting from the target block corresponding to the starting address information according to the read / write block instruction, the block address instruction, and the read / write start instruction. The target data group occupies multiple blocks including the target block. In this embodiment, the debugging device starts reading / writing the target data group from the target block corresponding to the starting address information, and the target data group occupies multiple blocks including the target block. That is, after reading / writing part of the target data group according to the starting address information, the debugging device then sequentially reads / writes the remaining part of the target data group from other blocks after the target block until the entire target data group is read / written. This further ensures a shorter debugging time and a faster data transmission process, thereby further ensuring higher debugging efficiency.

[0043] Specifically, the aforementioned memory read / write unit includes multiple of the aforementioned blocks.

[0044] In other embodiments, such as Figure 2 As shown, the above-mentioned debugging system also includes a pull-up circuit 17, through which the second end of the center wire 13 is electrically connected to the device under debugging 14. In this embodiment, the second end of the center wire is electrically connected to the device under debugging through the pull-up circuit. When there is no external input signal, the pull-up circuit will keep the input terminal in a high-level state, preventing the input terminal from drifting to an undefined state, thereby ensuring good stability and reliability of the debugging system.

[0045] Specifically, if it is a write operation, the debugging device continues to output control data, and the device under debugging receives the corresponding control data; if it is a read operation, when the debugging device finishes sending the control data, it transfers the control of the coaxial cable from the debugging device to the device under debugging, keeps the coaxial cable in an up state, waits for the device under debugging to send feedback data, and receives the corresponding feedback data.

[0046] Specifically, such as Figure 2As shown, the pull-up circuit 17 includes a first diode 18, a first resistor 19, and a first power supply 20. The anode of the first diode 18 is connected to the second end of the center wire 13, and the cathode of the first diode 18 is connected to the first power supply 20. The anode of the first diode 18 is also connected to the first end of the first resistor 19, and the cathode of the first diode 18 is also connected to the second end of the first resistor 19. In this embodiment, the first power supply is 5V.

[0047] Specifically, such as Figure 2 As shown, the aforementioned debugging device 10 includes a second power supply 21, a second resistor 22, an output port 23, and an input port 24. The first end of the output port 23 is connected to the second power supply 21, the second end of the output port 23 is grounded, the third end of the output port 23 is connected to the first end of the second resistor 22, the second end of the second resistor 22 is connected to the input port 24, and the input port 24 is also connected to the first end of the center wire 13. In this embodiment, the second resistor is 50Ω.

[0048] Specifically, such as Figure 2 As shown, the device under test 14 further includes a third power supply 25, a second diode 26, a third diode 27, a transistor 28, an input interface 29, a bus unit 30, a register unit 31, and a CPU unit 32. The anode of the second diode 26 is connected to the second terminal of the first resistor 19, and the cathode of the second diode 26 is connected to the third power supply 25. The anode of the second diode 26 is also connected to the cathode of the third diode 27. The anode of the third diode 27 is grounded, and the cathode of the third diode 27 is also connected to the first terminal of the transistor 28. The second terminal of the transistor 28 is grounded, and the first terminal of the transistor 28 is also connected to the first terminal of the input interface 29. The second terminal of the input interface 29 is connected to the first terminal of the single-bus on-chip debugging unit 15. The second terminal of the single-bus on-chip debugging unit 15 is connected to the first terminal of the bus unit 30. The second terminal of the bus unit 30 is connected to the memory read / write unit 16, the register unit 31, and the CPU unit 32, respectively. The aforementioned bus unit is used to select one of the aforementioned memory read / write unit, the aforementioned register unit, and the aforementioned CPU unit to establish a control connection with the aforementioned single-bus on-chip debug unit. In this embodiment, the aforementioned third power supply is 5V.

[0049] Specifically, such as Figure 2 As shown, the second end of the aforementioned center conductor 13 is connected to the aforementioned pull-up circuit 17 via a third resistor 33. In this embodiment, the aforementioned third resistor is 50Ω.

[0050] Figure 3 To and Figure 2 A schematic diagram of the storage block transfer function in the corresponding debugging system. For example... Figure 3 As shown, the debugging device sends read / write block instructions, block address instructions, and read / write start instructions to the single-bus on-chip debugging unit in the device under debugging. The single-bus on-chip debugging unit controls the memory read / write unit to start reading / writing the target data group from the target block corresponding to the start address information. The memory read / write unit sends the feedback data corresponding to the target data group to the single-bus on-chip debugging unit, and the single-bus on-chip debugging unit sends the feedback data to the debugging device. The target data group occupies multiple blocks including the target block. The read / write block instructions include read / write block initial instructions and data size information, the block address instructions include block address initial instructions and start address information, and the read / write start instructions include read / write start initial instructions and data information.

[0051] In one exemplary embodiment of this application, the debugging device is further configured to determine one of a plurality of communication formats recognizable by the device under test as the target communication format, and configure the communication format of the control data as the target communication format; the device under test is further configured to send the feedback data after configuring the communication format of the feedback data as the target communication format. In this embodiment, the debugging device is further configured to determine one of a plurality of communication formats recognizable by the device under test as the target communication format, and configure the communication format of the control data as the target communication format; the device under test is further configured to send the feedback data after configuring the communication format of the feedback data as the target communication format, ensuring that the device under test can better identify the communication format of the control data, and that the debugging device can configure the communication format of the control data according to actual needs, ensuring that the communication format of the data transmission is relatively compatible.

[0052] According to a specific embodiment of this application, the debugging device is further configured to configure the data bit width of the control data; the device under debugging is further configured to configure the data bit width of the feedback data. In this embodiment, the debugging device is further configured to configure the data bit width of the control data, and the device under debugging is further configured to configure the data bit width of the feedback data. By configuring a data bit width that meets actual needs, the data transmission process is further ensured to be relatively fast.

[0053] Specifically, the default 32-bit data width is usually configured as an 8-bit, 16-bit, or 64-bit data width.

[0054] According to another specific embodiment of this application, the debugging device includes: a first interrupt detection module, which is used to determine whether a transmission error has occurred in the communication with the device under debugging, and to issue a first interrupt command if the transmission error occurs; and a first interrupt request module, which is connected to the first interrupt detection module and the device under debugging, and is used to interrupt the transmission of the control data upon receiving the first interrupt command. The device under debugging includes: a second interrupt detection module, which is used to determine whether a transmission error has occurred in the communication with the debugging device, and to issue a second interrupt command if the transmission error occurs; and a second interrupt request module, which is connected to the second interrupt detection module and the debugging device, and is used to interrupt the transmission of the feedback data upon receiving the second interrupt command. In this embodiment, the first interrupt detection module and the first interrupt request module can interrupt the transmission of control data when a transmission error occurs during the transmission of control data, thus preventing the debugged device from receiving erroneous signals. The second interrupt detection module and the second interrupt request module can interrupt the transmission of feedback data when a transmission error occurs during the transmission of feedback data, thus preventing the debugged device from receiving erroneous signals. This ensures a high accuracy rate of data transmission in the debugging system and further ensures the reliability of the debugging system.

[0055] In other embodiments, the first interruption detection module is further configured to determine that a transmission error has occurred in communication with the device under test when the first transmission duration exceeds a first threshold duration. The first transmission duration is the duration for transmitting the control data, and the first threshold duration is a preset duration for normal transmission of the control data. The second interruption detection module is further configured to determine that a transmission error has occurred in communication with the debugging device when the second transmission duration exceeds a second threshold duration. The second transmission duration is the duration for transmitting the feedback data, and the second threshold duration is a preset duration for normal transmission of the feedback data. In this embodiment, the first interruption detection module is further configured to determine that a transmission error has occurred in communication with the device under test when the first transmission duration exceeds the first threshold duration, and the second interruption detection module is further configured to determine that a transmission error has occurred in communication with the debugging device when the second transmission duration exceeds the second threshold duration. This ensures that the detection of transmission errors is relatively accurate, thereby further ensuring a high accuracy rate of data transmission in the debugging system and further ensuring the reliability of the debugging system.

[0056] In practical applications, those skilled in the art can set the first threshold duration and the second threshold duration based on experience, or obtain them through multiple experiments. This application does not impose any specific restrictions on this.

[0057] According to another specific embodiment of this application, the debugging device is further configured to send a timing instruction to the device under debugging, wherein the timing instruction is an instruction representing the read / write operation performed according to a timing read / write interval; the device under debugging is further configured to store the timing read / write interval upon receiving the timing instruction, and perform the read / write operation according to the timing read / write interval upon receiving the read / write start instruction. In this embodiment, the debugging device is further configured to send a timing instruction to the device under debugging, and the device under debugging is further configured to store the timing read / write interval upon receiving the timing instruction, and perform the read / write operation according to the timing read / write interval upon receiving the read / write start instruction. By performing the read / write operation according to the timing read / write interval, the status of the device under debugging can be monitored periodically, and only one read / write start instruction needs to be sent to the device under debugging, eliminating the need to repeatedly send read / write start instructions to the device under debugging at regular intervals, further ensuring a shorter debugging process and thus further ensuring higher debugging efficiency.

[0058] In practical applications, those skilled in the art can set the above read / write interval based on experience, or obtain it through multiple experiments. This application does not impose any specific restrictions on this.

[0059] Figure 4 To and Figure 3 A schematic diagram of the timed transmission function of the storage block in the corresponding debugging system. (For example...) Figure 4 As shown, the debugging device transmits read / write block instructions, block address instructions, and read / write start instructions to the single-bus on-chip debugging unit in the device under debugging. The single-bus on-chip debugging unit controls the memory read / write unit to read / write the target data group from the target block corresponding to the start address information according to the timed read / write interval. The memory read / write unit sends the feedback data corresponding to the target data group to the single-bus on-chip debugging unit, and the single-bus on-chip debugging unit sends the feedback data to the debugging device. The target data group occupies multiple blocks including the target block. The read / write block instructions include the initial read / write block instructions and data size information, the block address instructions include the initial block address instructions and start address information, and the read / write start instructions include the initial read / write start instructions and data information.

[0060] Figure 5 To and Figure 2 A more detailed structural diagram of the corresponding debugging system. For example... Figure 5As shown, the single-bus on-chip debugging unit 15 includes a receiving subunit 34, a transmitting subunit 35, a register subunit 36, and a control subunit 37. The receiving subunit 34 is used to receive control data sent by the debugging device (not shown in the figure). The receiving subunit 34 is connected to the register subunit 36 ​​and the control subunit 37 respectively. The register subunit 36 ​​is also connected to the bus unit 30, the control subunit 37, and the transmitting subunit 35 respectively. The control subunit 37 is also connected to the bus unit 30 and the transmitting subunit 35 respectively. The transmitting subunit 35 is used to send feedback data to the debugging device. The receiving subunit 34 includes a filtering module 38, a second interrupt detection module 39, a data set module 40, a sampling module 41, and an SP conversion module 42. The output of the filtering module 38 is connected to the input of the second interrupt detection module 39 and the data set module 40 respectively. The output of the data set module 40 is connected to the input of the sampling module 41 and the SP conversion module 42 respectively. The output of the sampling module 41 is connected to the input of the SP conversion module 42. The filtering module 38 is used to filter the received control data signals. The system performs filtering. The dataset module 40 aggregates the filtered control data, the sampling module 41 samples the aggregated control data, and the SP transformation module 42 performs SP transformation on the sampled control data. The transmitting subunit 35 includes a second interrupt request module 43, a transmitting module 44, and a selection module 45. The selection module 45 selects one of the second interrupt request module 43 and the transmitting module 44 (i.e., selects whether to transmit interrupt feedback data or transmit normal feedback data). The selection module 45 is connected to the transmitting module 44 and the second interrupt request module 43, respectively. The control subunit 37 includes a memory read / write control module 46, a bus control module 47, a register read / write control module 48, and a transmit / receive control module 49. The memory read / write control module 46 controls the memory read / write unit (not shown in the figure) to perform read / write operations. The transmit / receive control module 49 controls the transmit / receive operations of the transmitting subunit 35 and the receiving subunit 34. The bus control module 47 controls the bus unit 30, and the register read / write control module 48 controls the read and write operations of the register subunit 36.

[0061] Specifically, the receiving subunit and the transmitting subunit cannot operate simultaneously. When the single-bus on-chip debug unit is located inside the SoC, the receiving subunit is enabled by default, meaning the SoC is used as a slave device. The receiving subunit samples the electrical signals corresponding to the received control data and converts them into digital signals. Based on these digital signals, it controls the configuration of the register subunit and the control subunit. When a read operation from the debug device is received, the control subunit and the register subunit read data from the SoC's internal bus unit according to the command and control the transmitting subunit to output the data via electrical signals. When a write operation from the debug device is received, the control subunit and the register subunit read data from the receiving subunit according to the command and control the relevant internal modules through the SoC's bus unit. This process completes the on-chip debug operation.

[0062] Figure 6 To and Figure 2 A schematic diagram of the debugging system structure when the device being debugged is an external storage device. For example... Figure 6 As shown, the device under test 14 includes a third power supply 25, a second diode 26, a third diode 27, a transistor 28, an input interface 29, a single-bus on-chip debugging unit 15, an arbitration selection unit 50, and a memory read / write unit 16. The second end of the single-bus on-chip debugging unit 15 is connected to the memory read / write unit 16 through the arbitration selection unit 50. The external MCU / SOC unit 51 is connected to the memory read / write unit 16 through the arbitration selection unit 50. The arbitration selection unit 50 is used to select the connection between the memory read / write unit 16 and one of the single-bus on-chip debugging unit 15 and the external MCU / SOC unit 51.

[0063] Specifically, the two ends of the coaxial cable are connected to the debugging equipment and the external memory through pull-up circuits. The single-bus on-chip debugging unit is connected to the memory read / write unit through the arbitration selection unit. When the arbitration selection unit prioritizes connecting the memory read / write unit to the single-bus on-chip debugging unit, the debugging equipment can debug the memory read / write unit through the coaxial cable.

[0064] More specifically, in some embodiments, the target communication format includes phase-shift keying (PSK) format and NRZ UART format. In this embodiment, the target communication format includes both PSK and NRZ UART format, further ensuring the correctness and reliability of data transmission.

[0065] Figure 7 This is a waveform diagram for data transmission in phase-shift keying (PSK) format. (Example:) Figure 7 As shown, Start Bit indicates the start of data transmission, Stop Bit indicates the end of data transmission, Parity Bit is used to verify whether the data transmission is correct, Data[] represents data bits, and 1Frame represents one frame transmission.

[0066] Figure 8 This is a waveform diagram illustrating data transmission in NRZ UART format. Figure 8 As shown, Start Bit indicates the start of data transmission, Stop Bit indicates the end of data transmission, and 1 Frame indicates one frame transmission.

[0067] Of course, in addition to phase shift keying format and NRZ UART format, the above-mentioned target communication formats may also include, but are not limited to, frequency keying format, amplitude keying format and pulse modulation format. This application does not impose specific limitations on these.

[0068] In other embodiments, the data bit width includes one of 8 bits, 16 bits, 32 bits, and 64 bits. In this embodiment, by setting an appropriate data bit width, a faster data transmission speed is further ensured, thereby further ensuring higher debugging efficiency.

[0069] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0070] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0071] The debugging system of this application includes debugging equipment, a coaxial cable, and a device under debugging. The coaxial cable includes a metal cladding layer and a central conductor surrounded by the metal cladding layer. The metal cladding layer is grounded. A first end of the central conductor is electrically connected to the debugging equipment, and a second end of the central conductor is electrically connected to the device under debugging. The debugging equipment is used to send control data, including read / write block instructions, block address instructions, and read / write start instructions, to the device under debugging via the coaxial cable. The read / write block instructions represent the data size information of a target data group containing multiple target data to be read / written. The block address instructions represent the starting address information of the target data group in the device under debugging. The read / write start instructions are instructions to the device under debugging to perform read / write operations. The device under debugging is used to perform read / write operations according to the read / write block instructions, block address instructions, and read / write start instructions, and send feedback data corresponding to the target data group to the debugging equipment. Compared to existing debugging systems where multiple data need to be read / written, requiring the debugger to sequentially send read / write commands and address information for each data item before the ECU can feed back the corresponding data, resulting in longer debugging times and slower data transmission when there is a large amount of data to be read / written, this application addresses the problem that when the target data group to be read / written includes multiple target data items, the debugging device only needs to send a read / write block command, a block address command, and a read / write start command to the device under debugging once. The block address command represents the starting address information of the target data group in the device under debugging, which can complete the reading / writing of multiple target data items in the target data group at once and send the corresponding feedback data to the debugging device. This eliminates the need to send multiple read / write commands and address information, ensuring shorter debugging time, faster data transmission, and higher debugging efficiency. In addition, this application uses coaxial cable for signal transmission, ensuring faster data transmission speed, and the grounding of the metal envelope layer ensures strong anti-interference capability of the debugging system.

[0072] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A debugging system, characterized in that, include: Debugging equipment; A coaxial cable includes a metal cladding layer and a center conductor, the metal cladding layer surrounding the center conductor, the metal cladding layer being grounded, and a first end of the center conductor being electrically connected to the debugging equipment; The device under test, wherein the second end of the center conductor is electrically connected to the device under test; The debugging device is used to send control data to the device under debugging via the coaxial cable. The control data includes read / write block instructions, block address instructions, and read / write start instructions. The read / write block instructions represent the data size information of the target data group to be read / written. The block address instructions represent the starting address information of the target data group in the device under debugging. The read / write start instructions are instructions to the device under debugging to perform read / write operations. The target data group includes multiple target data. The device under test is used to perform the read / write operation according to the read / write block instruction, the block address instruction and the read / write start instruction, and send the feedback data corresponding to the target data group to the debugging device.

2. The debugging system according to claim 1, characterized in that, The device under test is further configured to read / write the target data group starting from the target block corresponding to the starting address information according to the read / write block instruction, the block address instruction and the read / write start instruction, wherein the target data group occupies multiple blocks including the target block.

3. The debugging system according to claim 1, characterized in that, The debugging system also includes: A pull-up circuit is provided, through which the second end of the center conductor is electrically connected to the device under test.

4. The debugging system according to claim 1, characterized in that, The debugging device is also used to determine one of a plurality of communication formats recognizable by the device under debugging as the target communication format, and to configure the communication format of the control data as the target communication format; The device under test is also used to configure the communication format of the feedback data to the target communication format before sending it out.

5. The debugging system according to claim 1, characterized in that, The debugging equipment is also used to configure the data bit width of the control data; The device being debugged is also used to configure the data bit width of the feedback data.

6. The debugging system according to claim 1, characterized in that, The debugging equipment includes: The first interrupt detection module is used to determine whether a transmission error has occurred in the communication with the device under test, and to issue a first interrupt command if the transmission error occurs. The first interrupt request module is connected to both the first interrupt detection module and the device under test. The first interrupt request module is used to interrupt the transmission of control data upon receiving the first interrupt command. The device being debugged includes: The second interrupt detection module is used to determine whether a transmission error has occurred in the communication with the debugging device, and to issue a second interrupt command if a transmission error occurs. The second interrupt request module is connected to both the second interrupt detection module and the debugging device. The second interrupt request module is used to interrupt the transmission of the feedback data upon receiving the second interrupt command.

7. The debugging system according to claim 6, characterized in that, The first interruption detection module is further configured to determine that a transmission error has occurred in communication with the device under test when the first transmission duration is greater than the first threshold duration, wherein the first transmission duration is the duration for transmitting the control data, and the first threshold duration is a preset duration for normal transmission of the control data; The second interruption detection module is further configured to determine that a transmission error has occurred in communication with the debugging device when the second transmission duration is greater than the second threshold duration, wherein the second transmission duration is the duration for transmitting the feedback data, and the second threshold duration is a preset duration for normal transmission of the feedback data.

8. The debugging system according to claim 1, characterized in that, The debugging device is also used to send a timing instruction to the device being debugged, the timing instruction being an instruction that indicates the read / write operation to be performed according to the timing read / write interval duration; The device under test is also configured to store the timing read / write interval duration when receiving the timing instruction, and to perform the read / write operation according to the timing read / write interval duration when receiving the read / write start instruction.

9. The debugging system according to claim 4, characterized in that, The target communication formats include phase-off keying format and NRZ UART format.

10. The debugging system according to claim 5, characterized in that, The data bit width includes one of 8 bits, 16 bits, 32 bits, and 64 bits.

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