Data transmission method, device and equipment based on PCIe speed reduction bridge and storage medium

Abstract

The invention relates to a data transmission method, device and equipment based on a PCIe speed reduction bridge and a storage medium, and is applied to the field of PCIe circuit verification, and the method comprises the steps: initializing a speed reduction bridge module, enabling a first PCIe link and a second PCIe link to enter a normal operation state, and entering an activated state; the control verification platform end generates to-be-transmitted data and transmits the to-be-transmitted data to the simulation terminal module; controlling the simulation terminal module to carry out data analysis on the to-be-transmitted data, and generating a data link layer packet and a transaction layer data packet; the simulation terminal module is controlled to perform data verification on the data link layer packet and the transaction layer data packet, and valid data passing verification is stored in a preset data storage module; and the effective data stored in the data storage module is transmitted to the full-speed terminal module and is transmitted to an upper computer end. The method has the technical effects that the data transmission problem of rate mismatching between the two ends of the PCIe link is solved, and the cost of on-board verification is reduced.

Description

Technical Field

[0001] This application relates to the field of PCIe circuit verification technology, and in particular to a data transmission method, apparatus, device and storage medium based on a PCIe speed-down bridge. Background Technology

[0002] PCI (Peripheral Component Interconnect) bus is a parallel, synchronous, high-speed computer local bus standard. With the increasing demands for graphics processing and high-speed storage, the traditional parallel PCI bus has gradually become a bottleneck in terms of bandwidth, scalability, and signal integrity. Therefore, as a high-speed serial computer expansion bus standard, PCIe has replaced the earlier PCI parallel bus standard and has broad development prospects in the computer and communication fields. However, the continuous updates and iterations of the PCIe protocol, with its ever-increasing transmission rates, have led to increasing difficulties in the development and verification of the PCIe protocol, especially for Gen5 and higher speeds. PCIe Gen5, also known as the fifth generation of PCIe, boasts a transmission rate of up to 32GT / s (GigaTransfers per second).

[0003] Currently, for 32GT / s PCIe, the design of some large chips involves a large and complex amount of code, which runs slowly in software simulation environments and cannot simulate the actual working speed of PCIe Gen5. This results in a mismatch between the speed of the PIPE interface (Physical Interface for PCI Express) on the prototype verification platform and the physical layer speed. Consequently, the PCIe Root Complex (RC) and PCIe Endpoint (EP) cannot be directly connected for on-board verification. Summary of the Invention

[0004] To help solve the problem that large chip designs run slowly in software simulation environments and cannot simulate the actual operating speed of PCIe Gen5, resulting in a mismatch between the PIPE interface speed and the physical layer speed of the prototype verification platform, and the inability to directly connect the PCIe root complex and PCIe endpoint devices, this application provides a data transmission method, apparatus, device and storage medium based on a PCIe speed-down bridge.

[0005] Firstly, this application provides a data transmission method based on a PCIe speed-reducing bridge, employing the following technical solution: The method is applied to a data transmission system based on a PCIe speed-reducing bridge, the system comprising a verification platform, a host computer, and a speed-reducing bridge module, the speed-reducing bridge module comprising a full-speed terminal module and a simulation terminal module, the simulation terminal module being connected to the verification platform via a first PCIe link, and the full-speed terminal module being connected to the host computer via a second PCIe link; the method includes: The speed reduction bridge module is initialized to enable the first PCIe link and the second PCIe link to enter normal operation and activation state. The verification platform is controlled to generate data to be transmitted and then transmit the data to the simulation terminal module. The simulation terminal module is controlled to parse the data to be transmitted and generate data link layer packets and transaction layer data packets. The simulation terminal module is controlled to perform data verification on the data link layer packet and the transaction layer data packet respectively, and the valid data corresponding to the verified data link layer packet and transaction layer data packet is stored in the preset data storage module; The valid data stored in the data storage module is transmitted to the full-speed terminal module, and then transmitted to the host computer through the preset PCIe physical layer module.

[0006] In one specific implementation, the simulation terminal module includes a first flow control module, and the full-speed terminal module includes a second flow control module; initializing the speed-reducing bridge module to bring the first PCIe link and the second PCIe link into normal operation and activation states includes: The simulation terminal module and the full-speed terminal module are controlled to perform link training on the first PCIe link and the second PCIe link respectively, so that the first PCIe link and the second PCIe link enter the normal operation state. The system controls the interaction between the first flow control module and the second flow control module, and determines whether the buffer capacity of the host computer is greater than a preset value based on the information exchanged. If the buffer capacity of the host computer is greater than a preset value, the first PCIe link and the second PCIe link are controlled to enter the active state.

[0007] In one specific implementation scheme, after the verification platform generates the data to be transmitted and transmits the data to the simulation terminal module, the scheme further includes: The simulation terminal module is controlled to descramble the data to be transmitted and generate descrambled transmission data; The process of controlling the simulation terminal module to parse the data to be transmitted includes: The simulation terminal module is controlled to parse the descrambled transmission data.

[0008] In one specific implementation, the transaction layer data packet includes a transaction layer data body, transaction layer CRC data, and a sequence code, and the data link layer packet includes link layer CRC data; The step of controlling the simulation terminal module to perform data verification on the data link layer packets and the transaction layer packets respectively, and storing the valid data corresponding to the verified data link layer packets and transaction layer packets into a preset data storage module includes: The simulation terminal module is controlled to verify the transaction layer CRC data and the sequence code, and retain the transaction layer data body corresponding to the transaction layer data packet that passes the verification; The simulation terminal module is controlled to verify the CRC data of the link layer and retain the credit data of the updated flow control storage unit corresponding to the data link layer packet that passes the verification. The transaction layer data body and the updated flow control storage unit credit data are set as valid data, and the valid data is stored in a preset data storage module; The updated flow control storage unit credit data is generated by the simulation terminal module based on the verified and retained data link layer packets.

[0009] In one specific implementation, the transaction layer data body corresponding to the retained transaction layer data packet that has passed verification includes: If the transaction layer CRC data and the sequence code are verified correctly, the simulation terminal module is controlled to give a positive response, generate a positive response value, and retain the transaction layer data body corresponding to the transaction layer data packet that has passed the verification. If the transaction layer CRC data and the sequence code are incorrect, the simulation terminal module is controlled to issue a negative response and generate a negative response value. The positive response value or the negative response value is fed back to the verification platform.

[0010] In one specific implementation scheme, the verification platform includes a first PIPE serial-to-parallel conversion module, and the data transmission system of the PCIe speed-down bridge includes a second PIPE serial-to-parallel conversion module. The step of transmitting the data to be transmitted to the simulation terminal module includes: The data to be transmitted is transmitted to the first PIPE serial-to-parallel conversion module, and first converted data is generated; The first converted data is transmitted to the second PIPE serial-to-parallel conversion module, and the second converted data is generated. The second conversion data is transmitted to the simulation terminal module; The process of controlling the simulation terminal module to parse the data to be transmitted includes: The simulation terminal module is controlled to parse the second conversion data.

[0011] In one specific implementation, the step of transmitting the valid data stored in the data storage module to the full-speed terminal module, and then transmitting it to the host computer via a preset PCIe physical layer module, includes: The valid data in the data storage module is transmitted to the full-speed terminal module, and reassembled according to the data format requirements of the host computer to generate reassembled data; The recombined data is scrambled according to a preset scrambling method, and recombined scrambled data is generated; The recombined scrambling data is transmitted to the host computer via a preset PCIe physical layer module.

[0012] Secondly, this application provides a data transmission device based on a PCIe speed-reducing bridge, employing the following technical solution: the device is applied to a data transmission system based on a PCIe speed-reducing bridge, the system including a verification platform, a host computer, and a speed-reducing bridge module, the speed-reducing bridge module including a full-speed terminal module and a simulation terminal module, the simulation terminal module and the verification platform include a first PCIe link, the full-speed terminal module and the host computer include a second PCIe link; the device includes: The system initialization module is used to initialize the speed reduction bridge module so that the first PCIe link and the second PCIe link enter the normal operation state and the activation state. The data generation module is used to control the verification platform to generate data to be transmitted and to transmit the data to the simulation terminal module. The data parsing module is used to control the simulation terminal module to parse the data to be transmitted and generate data link layer packets and transaction layer data packets; The data storage module is used to control the simulation terminal module to perform data verification on the data link layer packets and the transaction layer data packets respectively, and to store the valid data corresponding to the verified data link layer packets and transaction layer data packets into the preset data storage module; The data transmission module is used to transmit the valid data stored in the data storage module to the full-speed terminal module, and then transmit it to the host computer through the preset PCIe physical layer module.

[0013] Thirdly, this application provides a computer device that adopts the following technical solution: it includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed as any of the above-mentioned data transmission methods based on the PCIe speed-reduction bridge.

[0014] Fourthly, this application provides a computer-readable storage medium that employs the following technical solution: storing a computer program capable of being loaded by a processor and executing any of the above-mentioned data transmission methods based on a PCIe speed-reduction bridge.

[0015] In summary, this application has the following beneficial technical effects: By designing a speed-reducing bridge—that is, by combining full-speed terminal modules and emulation terminal modules—efficient and accurate data transmission can be achieved between the verification platform and the commercial PC even with speed mismatches. This allows for direct connection between the PCIe Root Complex (PCIe RC) and the PCIe Endpoint Device (PCIe EP) via the speed-reducing bridge, enabling onboard verification. Furthermore, the speed-reducing bridge design avoids the need for expensive third-party verification systems, thereby reducing verification costs. Attached Figure Description

[0016] Figure 1 This is a flowchart of the data transmission method based on the PCIe speed-reduction bridge in the embodiments of this application; Figure 2 This is a framework diagram of the data transmission system based on the PCIe speed-reduction bridge in the embodiments of this application; Figure 3 This is a schematic diagram of a data transmission device based on a PCIe speed-reduction bridge in an embodiment of this application; Figure 4 This is a schematic diagram used to illustrate a computer device in the embodiments of this application.

[0017] Reference numerals: 301, System initialization module; 302, Data generation module; 303, Data parsing module; 304, Data storage module; 305, Data transmission module. Detailed Implementation

[0018] The following combination Figures 1-4 This application will be described in further detail.

[0019] This application discloses a data transmission method based on a PCIe speed-reducing bridge. This data transmission method can solve the problem of rate mismatch at both ends of a PCIe link. At the same time, it avoids the use of expensive third-party verification systems and can reduce verification costs.

[0020] PCI (Peripheral Component Interconnect) bus is a parallel, synchronous, high-speed computer local bus standard. With the increasing demands for graphics processing and high-speed storage, the traditional parallel PCI bus has gradually become a bottleneck in terms of bandwidth, scalability, and signal integrity. Therefore, as a high-speed serial computer expansion bus standard, PCIe has replaced the earlier PCI parallel bus standard and has broad development prospects in the computer and communication fields. However, the continuous updates and iterations of the PCIe protocol, with its ever-increasing transmission rates, have led to increasing difficulties in the development and verification of the PCIe protocol, especially for Gen5 and higher speeds. PCIe Gen5, also known as the fifth generation of PCIe, boasts a transmission rate of up to 32GT / s (GigaTransfers per second).

[0021] Currently, for 32GT / s PCIe designs targeting large chips, the code is extensive and complex, resulting in slow operation in software simulation environments. This fails to simulate the actual operating speed of PCIe Gen5, leading to a mismatch between the PIPE (Physical Interface for PCI Express) speed and the physical layer speed on the prototype verification platform. Consequently, the PCIe Root Complex (RC) and PCIe Endpoint (EP) cannot be directly connected for on-board verification. While independent third-party on-board verification systems exist, they are typically expensive, increasing verification costs. Therefore, to address the speed mismatch issue at both ends of the link and reduce verification costs, this application provides a data transmission method based on a PCIe speed-reduction bridge.

[0022] Reference Figure 1 The method includes the following steps: S10, initialize the speed reduction bridge module to enable the first PCIe link and the second PCIe link to enter normal operation and activation state.

[0023] Specifically, the data transmission method based on PCIe speed-reduction bridges is applied to data transmission systems based on PCIe speed-reduction bridges. The system includes a verification platform, a host computer, and a speed-reduction bridge logic platform. The verification platform typically includes a DUT (Device Under Test), while the host computer can be a commercial PC, a PCIe Endpoint Device (PCIe EP), etc.; the PCIe EP can be a graphics card, network card, etc. The speed-reduction bridge logic platform mainly includes the speed-reduction bridge module, which contains a full-speed terminal module, a simulating terminal module, and a data storage module. The full-speed terminal module connects to the host computer, such as a commercial PC, via a PCIe link, which represents the actual PCIe speed. There is also a PCIe link between the simulating terminal module and the verification platform; however, the speed of this PCIe link is not the actual PCIe speed, but rather a simulated speed, which is generally much lower than the actual PCIe speed.

[0024] Normal data transmission typically requires the PCIe link and the speed reduction bridge module to be in a normal working state before data transmission can occur. Therefore, the speed reduction bridge module needs to be initialized before data transmission to ensure the PCIe link is in a working state. Specifically, the simulation terminal module includes a first flow control module and a first link training module, while the full-speed terminal module includes a second flow control module and a second link training module.

[0025] First, the control simulation terminal module and the full-speed terminal module perform link training on the first PCIe link and the second PCIe link respectively, so that the first PCIe link and the second PCIe link enter the normal operation state. Specifically, the link training module in the simulation terminal module and the link training module in the full-speed terminal module can train the corresponding first PCIe link and the second PCIe link respectively, so that the two PCIe links enter the normal operation state, that is, the two PCIe links LTSSM (link training state) both enter the L0 state (L0 state is also the normal operation state).

[0026] Subsequently, the first and second flow control modules interact, and based on the information exchanged, determine whether the buffer capacity of the host computer exceeds a preset value. Both the full-speed terminal module and the simulation terminal module of the speed-reducing bridge module are equipped with flow control modules. These modules ensure reliable data transmission between the sender and receiver through a credit mechanism, preventing receive buffer overflow. During initialization, the initial synchronization of credit values ​​is completed through InitFC1 (receiver transmits credit capacity) and InitFC2 (sender confirms) DLLP packets, establishing the foundation for data transmission. If the buffer capacity of the host computer (i.e., the data receiver) exceeds the preset value, it can be understood that the receiver's buffer capacity can receive the data, and the PCIe links on both sides enter an active state, allowing subsequent data transmission.

[0027] S20, the control verification platform generates the data to be transmitted and transmits the data to the simulation terminal module.

[0028] Specifically, after both PCIe links have entered normal operating state (L0 state) and are activated, the normal data transmission process can begin. During data transmission, the control verification platform (such as the DUT) first generates data to be transmitted and transmits it to the simulation terminal module in the speed reduction bridge logic platform. After processing the data accordingly, it is then transmitted to the host computer.

[0029] S30 controls the simulation terminal module to parse the data to be transmitted and generate data link layer packets and transaction layer data packets.

[0030] Specifically, the raw generated data is a comprehensive dataset containing multiple functions and data types. The built-in parsing module processes this raw data, dividing it into different parts for separate processing. This ensures the main data component is efficiently and accurately transmitted to the receiving end. After parsing, Data Link Layer (DLLP) packets and Transaction Layer (TLP) packets are generated. TLP packets, generated by the transaction layer, carry the actual data—the subject of the data to be transmitted. DLLP packets, generated by the data link layer, are primarily used for data link management, including flow control.

[0031] S40, the control simulation terminal module performs data verification on the data link layer packets and transaction layer packets respectively, and stores the valid data corresponding to the verified data link layer packets and transaction layer packets into the preset data storage module.

[0032] Specifically, the parsed transaction layer data packets and data link layer packets undergo data verification to ensure that the data has been transmitted and received in the simulation terminal module. The verification also checks for mistransmissions, omissions, or other data transmission problems during transmission, ensuring both efficient and accurate data transmission. The valid data from the verified DLLP and TLP packets is then stored in a pre-defined data storage module.

[0033] S50 transmits valid data stored in the data storage module to the full-speed terminal module, and then transmits it to the host computer through the preset PCIe physical layer module.

[0034] Specifically, the data to be transmitted is processed inside the simulation terminal module and then stored in the data storage module. The data storage module then transmits the data to be transmitted to the full-speed terminal module for processing. Finally, it is transmitted to the host computer, such as a commercial PC, through the PCIe physical layer module, thus completing the data transmission process.

[0035] The specific process can be as follows: First, the valid data from the data storage module is transmitted to the full-speed terminal module. The built-in packet assembly module in the full-speed terminal module then reassembles the data according to the data format requirements of the host computer, generating reassembled data. Next, the reassembled data is scrambled according to a preset scrambling method, generating reassembled scrambled data. Considering that the communication link may be idle for extended periods when the system is not transmitting data, leading to instability and susceptibility to interference, scrambling allows for interference-based data transmission even when the system is not transmitting data. This reduces the possibility of interference to the entire link. Furthermore, scrambling improves the data's anti-interference capability, reduces the probability of sudden errors, enhances overall fault tolerance, and improves channel adaptability and transmission robustness. Finally, the reassembled scrambled data is transmitted to the host computer through a preset PCIe physical layer module. The PCIe physical layer module, also known as the PCIe PHY module, is the physical layer integrated circuit in the PCIe interface. It converts received PCIE physical layer data into PIPE interface data and converts PIPE interface data to be transmitted into serial data.

[0036] It's important to note that data transmission via the PCIe link is bidirectional. After data is generated at the DUT and transmitted to the commercial PC via a speed-reducing bridge, the commercial PC will also return corresponding data, enabling data exchange. Similarly, the host computer can generate new data and transmit it to the DUT using the same data transmission method. For example, after the commercial PC generates data, it transmits it to the full-speed terminal module via the PCIe PHY module. The full-speed terminal module processes and verifies the data, storing the verified data in the data storage module. Then, the data from the data storage module is transmitted to the emulation terminal module. The built-in packet assembly module of the emulation terminal module reassembles the received data according to the DUT's data format requirements, scrambles it, and sends it back to the DUT. The DUT then receives the data and sends it back to the commercial PC, completing the data exchange.

[0037] In this application, the design of a speed-reducing bridge—that is, a design using both full-speed and emulation terminal modules—enables efficient and accurate data transmission between the verification platform and the commercial PC even with speed mismatches. This allows for direct connection between the PCIe Root Complex (PCIe RC) and the PCIe Endpoint Device (PCIe EP) via the speed-reducing bridge, enabling onboard verification. Furthermore, the speed-reducing bridge design avoids the need for expensive third-party verification systems, thereby reducing verification costs.

[0038] In one embodiment, considering that scrambled data can affect the accuracy of the data, after generating the data to be transmitted on the control verification platform and transmitting the data to be transmitted to the simulation terminal module, the following steps can also be performed: The control simulation terminal module descrambles the data to be transmitted and generates descrambled transmission data. The control simulation terminal module performs data parsing on the descrambled transmission data.

[0039] In this application, considering that no data is transmitted on the data link (i.e., no-data transmission) would reduce the stability of the entire communication link and affect the accuracy of data transmission, the data is usually scrambled before transmission. This reduces the possibility of interference to the entire link and improves channel adaptability and transmission robustness. Therefore, before performing verification and other processing on the data during transmission, it is necessary to descramble the data to avoid the influence of pre-added interference data on the accuracy of the actual transmitted data.

[0040] In one embodiment, the transaction layer data packet includes the transaction layer data body, transaction layer CRC data, and sequence code; the data link layer packet includes update flow control storage unit credit data and link layer CRC data. The control simulation terminal module performs data verification on the data link layer packet and the transaction layer data packet, and stores the valid data corresponding to the verified data link layer packet and transaction layer data packet into a preset data storage module. This can be specifically executed as follows: First, the control simulation terminal module verifies the transaction layer CRC data and sequence code, and retains the transaction layer data body corresponding to the transaction layer data packets that pass the verification. Specifically, the simulation terminal module has an internal TLP verification module (TLP Error Check module). The TLP Error Check module verifies the TLP sequence code (Seq_Num) and the CRC checksum of the TLP packet. If the transaction layer CRC data and sequence code verification is correct, the control simulation terminal module issues a positive response, generates a positive response value, and retains the transaction layer data body corresponding to the verified transaction layer data packets. The data body is the data after removing the packet header, packet trailer, and CRC checksum. If the transaction layer CRC data and sequence code verification is incorrect, the control simulation terminal module issues a negative response, generates a negative response value, and feeds back the positive or negative response value to the verification platform.

[0041] Sequence code verification checks whether the data transmission order is correct and whether the data is transmitted according to the preset order. If the data transmission is correct, an ACK response is given; if a data transmission is missed, the verification module will give a NAK response. CRC (Cyclic Redundancy Check) is an algorithm that generates a short, fixed-length checksum based on network data packets or computer files. It is mainly used to detect or verify errors that may occur during data transmission or storage. If the CRC data after data transmission matches the CRC data calculated before data transmission, the data is fine, and an ACK response is generated. If the two CRC data are inconsistent, a problem may have occurred during data transmission, and a NAK response is given, and the problematic data is discarded.

[0042] The response mechanism, also known as ACK / NAK response, generates an ACK response (positive response) when data verification passes and a NAK response (negative response) when data verification fails. The simulation terminal module has an internal ACK / NAK response module that generates a corresponding response data packet based on the ACK or NAK response value and transmits it to the DUT. Considering that data processing and transmission take time, a prolonged lack of data reception might mistakenly lead the system to interpret it as a data transmission error or a failure to receive data, triggering a warning. The response mechanism provides a flag to the data sender, indicating that data transmission has occurred, thus preventing system errors and improving data transmission efficiency.

[0043] Next, the control simulation terminal module verifies the CRC data of the link layer and retains the updated flow control storage unit credit data corresponding to the data link layer packets that pass the verification. The CRC data verification of DLLP packets is the same as that of TLP packets. If the CRC data verification fails, the corresponding DLLP packet is discarded; if the CRC verification passes, the DLLP packet data is transmitted to the flow control module built into the simulation terminal module. The flow control module generates updated flow control storage unit credit data (UpdateFC) based on the retained DLLP packets. Finally, the transaction layer data body and the updated flow control storage unit credit data are set as valid data, and the valid data is stored in the preset data storage module.

[0044] In this application, a checksum and acknowledgment mechanism is used to verify the accuracy of data transmission during the data transmission process by checking the data sequence code and CRC checksum, ensuring accurate data transmission. Furthermore, the acknowledgment mechanism transmits either an ACK or NAK acknowledgment to the data sender to inform them of the data transmission status, preventing system errors caused by prolonged system unresponsiveness.

[0045] In one embodiment, the verification platform includes a first PIPE serial-to-parallel conversion module, and the data transmission system of the PCIe speed-down bridge includes a second PIPE serial-to-parallel conversion module; the method of transmitting the data to be transmitted to the simulation terminal module can be specifically executed as follows: First, the data to be transmitted is transmitted to the first PIPE serial-to-parallel conversion module, generating first converted data. Then, the first converted data is transmitted to the second PIPE serial-to-parallel conversion module, generating second converted data. Finally, the second converted data is transmitted to the simulation terminal module. Controlling the simulation terminal module to parse the data to be transmitted includes: controlling the simulation terminal module to parse the second converted data.

[0046] The PIPE serial-to-parallel conversion module in this application is designed to address the challenges of achieving consistent latency and complex wiring associated with the large number of parallel PIPE data lines. The parallel transmitting end of the PIPE serial-to-parallel conversion module on the speed-reduction bridge logic platform is connected to the PIPE data transmitting end of the speed-reduction bridge module; the parallel receiving end of the PIPE serial-to-parallel conversion module on the speed-reduction bridge logic platform is connected to the PIPE data receiving end of the speed-reduction bridge module; the serial transmitting end of the PIPE serial-to-parallel conversion module on the speed-reduction bridge logic platform is connected to the serial receiving end of the PIPE serial-to-parallel conversion module on the verification platform; and the serial receiving end of the PIPE serial-to-parallel conversion module on the speed-reduction bridge logic platform is connected to the serial transmitting end of the PIPE serial-to-parallel conversion module on the verification platform.

[0047] Reference Figure 2 This is a complete system framework diagram of the data transmission based on the PCIe speed-reduction bridge in this application. The system consists of three main parts: the verification platform, the speed-reduction bridge logic platform, and the commercial PC / endpoint device (Endpoint) end. The verification platform mainly includes the DUT and the first PIPE serial-to-parallel conversion module. The parallel transmitting end of the PIPE serial-to-parallel conversion module on the verification platform receives the PIPE data from the DUT under test, and the parallel receiving end of the PIPE serial-to-parallel conversion module on the verification platform receives the PIPE data from the DUT under test. The serial transmitting end of the PIPE serial-to-parallel conversion module on the verification platform is connected to the serial receiving end of the PIPE serial-to-parallel conversion module on the speed-reduction bridge logic platform, and the serial receiving end of the PIPE serial-to-parallel conversion module on the verification platform is connected to the serial transmitting end of the PIPE serial-to-parallel conversion module on the speed-reduction bridge logic platform. The DUT is a PCIe module to be verified. The DUT can operate in PCIe Ep (Endpoint) or PCIe RC (Root Complex). The DUT supports any combination of Gen1-Gen5 (rates 2.5GT / s-32GT / s) and 1 Lane-16 Lane.

[0048] The speed reduction bridge logic platform mainly includes a speed reduction bridge module, a second PIPE serial-to-parallel conversion module, a mode configuration module, a PCIe PHY module, and PCIe hardware devices. The PCIe hardware devices are primarily responsible for the PCIe physical interface between the commercial PC / Endpoint device and the PCIe PHY module. The PCIe PHY module converts received PCIe physical layer data into PIPE interface data and converts PIPE interface data to be sent into serial data. The mode configuration module is mainly used to configure relevant parameters of the speed reduction bridge. When the DUT is Ep, the speed reduction bridge is configured to operate in Ep mode; when the DUT is RC, the operating mode is configured to RC. It also configures the PCIe mode, operating speed, and number of PCIe lanes in the SimSpeed ​​section of the speed reduction bridge. The PIPE serial-to-parallel conversion module has the same function as the PIPE serial-to-parallel conversion module in the verification platform. Its purpose is to solve the problem of the large number of parallel data lines in PIPE data transmission, making it difficult to achieve consistent latency and complex wiring.

[0049] The speed reduction bridge module includes a Simspeed terminal module, a Fullspeed terminal module, and a data storage module. The data storage module is primarily used to store the data to be transmitted. The Simspeed and Fullspeed terminal modules have identical internal structures, each containing a link training module, a descrambling module, a scrambling module, a data parsing module, a TLP verification module, a DLLP verification module, an ACK / NAK response module, a flow control module, and a packet assembly module. Before data transmission begins, the link training modules on both the Fullspeed and Simspeed ends train their respective PCIe links, bringing them into normal operation (L0 state). Then, the flow control modules on both sides exchange information, sending and receiving InitFC packets to determine the buffer capacity of the data receiver. If the buffer capacity is sufficient to receive data, the state transitions, activating the PCIe links on both sides and enabling normal data transmission.

[0050] After initialization and state transition are completed, the PCIe link can transmit data normally. The data sending end, which can be either the DUT or a commercial PC, generates the data to be transmitted. If the data sending end is the DUT, the data to be transmitted is transmitted to the simulation terminal module through two PIPE serial-to-parallel conversion modules. If the data sending end is a commercial PC, the data to be transmitted is transmitted to the full-speed terminal module through PCIe hardware and the PCIe PHY module. Next, the data to be transmitted is first descrambled, and then transmitted to the data parsing module for parsing, resulting in TLP packets (Transaction Layer Packets) and DLLP packets (Data Link Layer Packets). The TLP verification module verifies the sequence code and CRC data of the TLP packets, and generates corresponding ACK and NAK responses, feeding back the ACK or NAK response value to the data sender. The data body of the verified TLP packets, with the header, trailer, and CRC check data removed, is stored in the data storage module. The DLLP verification module verifies the CRC data of the DLLP packets. If the data verification passes, the data is transmitted to the flow control module, which updates and generates Update Flow Control Storage Unit Credit Data (UpdateFC), and also stores the UpdateFC in the data storage module. If the verification fails, the corresponding DLLP packet is discarded.

[0051] Next, the data in the data storage module is transferred to the side corresponding to the data receiving end. For example, if the data sending end is the DUT (Data Under Test) end, the data is processed on the Simspeed side, and the data in the storage module is transferred to the Fullspeed side. If the data sending end is a commercial PC end, the data is processed on the Fullspeed side, and the data in the storage module is transferred to the Simspeed side. The built-in packet reassembly module reassembles the data according to the requirements of the data receiving end, then scrambles it before transmitting it to the data receiving end. After receiving a piece of data, the data receiving end simultaneously sends a piece of data back to the data sending end, thus enabling data exchange.

[0052] Commercial PC / PCIe Endpoint devices are used for data transmission together with the DUT to be verified. When the DUT to be verified is an Endpoint, the commercial PC transmits data with the DUT through a speed-reducing bridge module. The commercial PC only needs to support PCIe that meets the Gen1x1 Lane requirement. When the DUT to be verified is a Root Complex, the PCIe Endpoint device transmits data with the DUT through a speed-reducing bridge module. The PCIe Ep device can be a graphics card, network card, etc., and the PCIe Endpoint device only needs to support PCIe that meets the Gen1x1 Lane requirement.

[0053] Figure 1This is a flowchart illustrating a data transmission method based on a PCIe speed-down bridge in one embodiment. It should be understood that, although... Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows; unless explicitly stated otherwise, there is no strict order requirement for the execution of these steps, and they can be executed in other orders; and Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0054] Based on the above method, this application also discloses a data transmission device based on a PCIe speed-down bridge.

[0055] Reference Figure 3 The device includes the following modules: The system initialization module 301 is used to initialize the speed reduction bridge module so that the first PCIe link and the second PCIe link can enter the normal operation state and the activation state. The data generation module 302 is used to control the verification platform to generate data to be transmitted and transmit the data to the simulation terminal module. The data parsing module 303 is used to control the simulation terminal module to parse the data to be transmitted and generate data link layer packets and transaction layer data packets; The data storage module 304 is used to control the simulation terminal module to perform data verification on the data link layer packets and transaction layer packets respectively, and to store the valid data corresponding to the verified data link layer packets and transaction layer packets into the preset data storage module. The data transmission module 305 is used to transmit the valid data stored in the data storage module to the full-speed terminal module, and then transmit it to the host computer through the preset PCIe physical layer module.

[0056] In one embodiment, the system initialization module 301 is specifically used to control the simulation terminal module and the full-speed terminal module to perform link training on the first PCIe link and the second PCIe link respectively, so that the first PCIe link and the second PCIe link enter the normal operation state; control the first flow control module to interact with the second flow control module, and determine whether the buffer capacity of the host computer is greater than a preset value based on the information of the interaction; if the buffer capacity of the host computer is greater than the preset value, then control the first PCIe link and the second PCIe link to enter the activation state.

[0057] In one embodiment, the data generation module 302 is further configured to control the simulation terminal module to descramble the data to be transmitted and generate descrambled transmission data; controlling the simulation terminal module to parse the data to be transmitted includes controlling the simulation terminal module to parse the descrambled transmission data.

[0058] In one embodiment, the data storage module 304 is specifically used to control the simulation terminal module to verify the transaction layer CRC data and sequence code, and retain the transaction layer data body corresponding to the verified transaction layer data packet; control the simulation terminal module to verify the link layer CRC data, and retain the updated flow control storage unit credit data corresponding to the verified data link layer packet; set the transaction layer data body and the updated flow control storage unit credit data as valid data, and store the valid data in a preset data storage module; wherein, the updated flow control storage unit credit data is generated by the simulation terminal module based on the verified and retained data link layer packet.

[0059] In one embodiment, the data storage module 304 is specifically used to control the simulation terminal module to give a positive response, generate a positive response value, and retain the transaction layer data body corresponding to the transaction layer data packet that has passed the verification if the transaction layer CRC data and sequence code verification are correct; if the transaction layer CRC data and sequence code verification are incorrect, control the simulation terminal module to give a negative response and generate a negative response value; and feed back the positive response value or negative response value to the verification platform.

[0060] In one embodiment, the data generation module 302 is specifically used to transmit the data to be transmitted to the first PIPE serial-to-parallel conversion module and generate first converted data; transmit the first converted data to the second PIPE serial-to-parallel conversion module and generate second converted data; transmit the second converted data to the simulation terminal module; and control the simulation terminal module to parse the data to be transmitted, including controlling the simulation terminal module to parse the second converted data.

[0061] In one embodiment, the data transmission module 305 is specifically used to transmit valid data from the data storage module to the full-speed terminal module, and to reassemble the data according to the data format requirements of the host computer, and generate reassembled data; to scramble the reassembled data according to a preset scrambling method, and generate reassembled scrambled data; and to transmit the reassembled scrambled data to the host computer through a preset PCIe physical layer module.

[0062] The data transmission device based on the PCIe speed reduction bridge provided in this application embodiment can be applied to the data transmission method based on the PCIe speed reduction bridge provided in the above embodiment. For relevant details, please refer to the above method embodiment. The implementation principle and technical effect are similar, and will not be repeated here.

[0063] It should be noted that the data transmission device based on a PCIe speed-reducing bridge provided in this embodiment is only illustrated by the above-described division of functional modules / units. In practical applications, the functions described above can be assigned to different functional modules / units as needed, that is, the internal structure of the data transmission device based on a PCIe speed-reducing bridge can be divided into different functional modules / units to complete all or part of the functions described above. Furthermore, the implementation method of the data transmission method based on a PCIe speed-reducing bridge provided in the above method embodiments and the implementation method of the data transmission device based on a PCIe speed-reducing bridge provided in this embodiment belong to the same concept. For details of the specific implementation process of the data transmission device based on a PCIe speed-reducing bridge provided in this embodiment, please refer to the above method embodiments, which will not be repeated here.

[0064] This application also discloses a computer device.

[0065] Specifically, such as Figure 4 As shown, the computer device can be a desktop computer, laptop computer, handheld computer, or cloud server, etc. The computer device may include, but is not limited to, a processor and memory. The processor and memory can be connected via a bus or other means. The processor can be a Central Processing Unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, graphics processing units (GPUs), embedded neural network processing units (NPUs) or other dedicated deep learning coprocessors, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips.

[0066] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the methods in the above embodiments of this application. The processor executes various functional applications and data processing by running the non-transitory software programs, instructions, and modules stored in the memory, thereby implementing the methods in the above embodiments. The memory may include a program storage area and a data storage area, wherein the program storage area may store the operating system and at least one application program required for a function; the data storage area may store data created by the processor, etc. Furthermore, the memory may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0067] This application also discloses a computer-readable storage medium.

[0068] Specifically, the computer-readable storage medium is used to store a computer program, which, when executed by a processor, implements the methods described in the above-described method embodiments. Those skilled in the art will understand that implementing all or part of the processes in the methods described in the above-described embodiments of this application can be accomplished by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments described above. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory.

[0069] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

Claims

1. A data transmission method based on a PCIe speed-reduction bridge, characterized in that: The method is applied to a data transmission system based on a PCIe speed-reduction bridge. The system includes a verification platform, a host computer, and a speed-reduction bridge module. The speed-reduction bridge module includes a full-speed terminal module and a simulation terminal module. A first PCIe link connects the simulation terminal module to the verification platform, and a second PCIe link connects the full-speed terminal module to the host computer. The method includes: The speed reduction bridge module is initialized to enable the first PCIe link and the second PCIe link to enter normal operation and activation state. The verification platform is controlled to generate data to be transmitted and then transmit the data to the simulation terminal module. The simulation terminal module is controlled to parse the data to be transmitted and generate data link layer packets and transaction layer data packets. The simulation terminal module is controlled to perform data verification on the data link layer packet and the transaction layer data packet respectively, and the valid data corresponding to the verified data link layer packet and transaction layer data packet is stored in the preset data storage module; The valid data stored in the data storage module is transmitted to the full-speed terminal module, and then transmitted to the host computer through the preset PCIe physical layer module.

2. The data transmission method based on a PCIe speed-reduction bridge according to claim 1, characterized in that: The simulation terminal module includes a first flow control module, and the full-speed terminal module includes a second flow control module; The initialization of the speed reduction bridge module to enable the first PCIe link and the second PCIe link to enter normal operation and activation states includes: The simulation terminal module and the full-speed terminal module are controlled to perform link training on the first PCIe link and the second PCIe link respectively, so that the first PCIe link and the second PCIe link enter the normal operation state. The system controls the interaction between the first flow control module and the second flow control module, and determines whether the buffer capacity of the host computer is greater than a preset value based on the information exchanged. If the buffer capacity of the host computer is greater than a preset value, the first PCIe link and the second PCIe link are controlled to enter the active state.

3. The data transmission method based on a PCIe speed-reduction bridge according to claim 1, characterized in that: After the verification platform generates the data to be transmitted and transmits the data to the simulation terminal module, the method further includes: The simulation terminal module is controlled to descramble the data to be transmitted and generate descrambled transmission data; The process of controlling the simulation terminal module to parse the data to be transmitted includes: The simulation terminal module is controlled to parse the descrambled transmission data.

4. The data transmission method based on a PCIe speed-reduction bridge according to claim 1, characterized in that: The transaction layer data packet includes a transaction layer data body, transaction layer CRC data, and a sequence code; the data link layer packet includes link layer CRC data. The step of controlling the simulation terminal module to perform data verification on the data link layer packets and the transaction layer packets respectively, and storing the valid data corresponding to the verified data link layer packets and transaction layer packets into a preset data storage module includes: The simulation terminal module is controlled to verify the transaction layer CRC data and the sequence code, and retain the transaction layer data body corresponding to the transaction layer data packet that passes the verification; The simulation terminal module is controlled to verify the CRC data of the link layer and retain the credit data of the updated flow control storage unit corresponding to the data link layer packet that passes the verification. The transaction layer data body and the updated flow control storage unit credit data are set as valid data, and the valid data is stored in a preset data storage module; The updated flow control storage unit credit data is generated by the simulation terminal module based on the verified and retained data link layer packets.

5. The data transmission method based on a PCIe speed-reduction bridge according to claim 4, characterized in that: The transaction layer data body corresponding to the retained transaction layer data packet that passed the verification includes: If the transaction layer CRC data and the sequence code are verified correctly, the simulation terminal module is controlled to give a positive response, generate a positive response value, and retain the transaction layer data body corresponding to the transaction layer data packet that has passed the verification. If the transaction layer CRC data and the sequence code are incorrect, the simulation terminal module is controlled to issue a negative response and generate a negative response value. The positive response value or the negative response value is fed back to the verification platform.

6. The data transmission method based on a PCIe speed-reduction bridge according to claim 1, characterized in that: The verification platform includes a first PIPE serial-to-parallel conversion module, and the data transmission system of the PCIe speed-down bridge includes a second PIPE serial-to-parallel conversion module. The step of transmitting the data to be transmitted to the simulation terminal module includes: The data to be transmitted is transmitted to the first PIPE serial-to-parallel conversion module, and first converted data is generated; The first converted data is transmitted to the second PIPE serial-to-parallel conversion module, and the second converted data is generated. The second conversion data is transmitted to the simulation terminal module; The process of controlling the simulation terminal module to parse the data to be transmitted includes: The simulation terminal module is controlled to parse the second conversion data.

7. The data transmission method based on a PCIe speed-reduction bridge according to claim 1, characterized in that: The step of transmitting the valid data stored in the data storage module to the full-speed terminal module, and then transmitting it to the host computer through the preset PCIe physical layer module includes: The valid data in the data storage module is transmitted to the full-speed terminal module, and reassembled according to the data format requirements of the host computer to generate reassembled data; The recombined data is scrambled according to a preset scrambling method, and recombined scrambled data is generated; The recombined scrambling data is transmitted to the host computer via a preset PCIe physical layer module.

8. A data transmission device based on a PCIe speed-reduction bridge, characterized in that: The device is applied to a data transmission system based on a PCIe speed-reduction bridge. The system includes a verification platform, a host computer, and a speed-reduction bridge module. The speed-reduction bridge module includes a full-speed terminal module and a simulation terminal module. A first PCIe link is included between the simulation terminal module and the verification platform, and a second PCIe link is included between the full-speed terminal module and the host computer. The device includes: The system initialization module (301) is used to initialize the speed reduction bridge module so that the first PCIe link and the second PCIe link enter the normal operation state and the activation state. The data generation module (302) is used to control the verification platform to generate data to be transmitted and transmit the data to be transmitted to the simulation terminal module; The data parsing module (303) is used to control the simulation terminal module to parse the data to be transmitted and generate data link layer packets and transaction layer data packets; The data storage module (304) is used to control the simulation terminal module to perform data verification on the data link layer packet and the transaction layer data packet respectively, and to store the valid data corresponding to the verified data link layer packet and transaction layer data packet into the preset data storage module; The data transmission module (305) is used to transmit the valid data stored in the data storage module to the full-speed terminal module, and then transmit it to the host computer through the preset PCIe physical layer module.

9. A computer device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer program is stored that can be loaded by a processor and executed as described in any one of claims 1 to 7.

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