Computing device, information processing method based on computing device, medium and equipment

Abstract

The invention discloses a computing device, an information processing method based on the computing device, a medium and equipment. The apparatus comprises: a memory; the first calculation circuit is used for performing multiple first calculations; storing the sub-result data to a memory; in response to sub-result data which is newly added in the memory and meets a first preset synchronization condition, generating first synchronization information; the second calculation circuit is used for responding to the first synchronization information, determining sub-result data required by newly adding a second calculation in the memory, and performing the second calculation on the sub-result data; generating second synchronization information in response to the condition that the sub-result data meeting a second preset synchronization condition in the memory and the second calculation conform to the target relationship; the first calculation circuit is further used for determining releasable storage space information based on the second synchronization information; determining free storage space information; it is determined whether to abort the first calculation. On the premise of achieving the same calculation effect as serial calculation, the calculation time is shortened, and the overall calculation efficiency is improved.

Description

Technical Field

[0001] This disclosure relates to information processing technology, and in particular to a computing device, a method for information processing based on the computing device, a medium, and an apparatus. Background Technology

[0002] In fields such as neural networks and image processing, many scenarios require sequential computation, where the next computation can only begin after the previous one is completed. This leads to excessively long overall computation time and low overall computational efficiency. How to shorten the overall computation time and improve overall computational efficiency while achieving the same computational effect as sequential computation is a technical problem worthy of attention for those skilled in the art. Summary of the Invention

[0003] To address the aforementioned technical problems, this disclosure provides a computing device, an information processing method based on the computing device, a medium, and an apparatus.

[0004] According to one aspect of the present disclosure, a computing device is provided, including: a memory, a first computing circuit, and a second computing circuit;

[0005] The first computing circuit is used to perform multiple first calculations sequentially on the data to be calculated; in response to generating sub-result data of a first calculation, it stores the sub-result data of the first calculation in the memory; in response to adding sub-result data that meets the first preset synchronization condition to the memory, it generates first synchronization information.

[0006] The second calculation circuit is configured to, in response to the first synchronization information, determine the sub-result data required for adding a second calculation in the memory, and perform a second calculation on the sub-result data required for the second calculation; and generate second synchronization information in response to the sub-result data in the memory that meets the second preset synchronization condition and conforms to the target relationship with the second calculation; wherein, any sub-result data conforming to the target relationship with the second calculation means that: any sub-result data has been used for the second calculation for the last time; or, any sub-result data belongs to data outside the calculation scope of the second calculation;

[0007] The first computing circuit is further configured to determine, based on the second synchronization information, the releasable storage space information of the memory; determine the free storage space information of the memory; and, based on the releasable storage space information and the free storage space information, determine whether to terminate the first computing.

[0008] According to another aspect of the present disclosure, an information processing method based on a computing device is provided, the computing device comprising: a memory, a first computing circuit, and a second computing circuit, the method comprising:

[0009] The first computing circuit performs multiple first calculations on the data to be calculated in sequence.

[0010] In response to the first computing circuit generating a sub-result data of a first calculation, the first computing circuit stores the sub-result data of the first calculation in the memory;

[0011] In response to the addition of sub-result data that meets the first preset synchronization condition in the memory, the first calculation circuit generates first synchronization information.

[0012] In response to determining, based on the first synchronization information, that sub-result data required for adding a second calculation to the memory is added, a second calculation is performed on the sub-result data required for the second calculation through the second calculation circuit;

[0013] In response to the sub-result data in the memory that satisfies the second preset synchronization condition and conforms to the target relationship with the second calculation, the second calculation circuit generates second synchronization information; wherein, any sub-result data conforming to the target relationship with the second calculation means that: any sub-result data has been used for the second calculation for the last time; or, any sub-result data belongs to data outside the calculation scope of the second calculation;

[0014] Based on the second synchronization information, the releasable storage space information of the memory is determined by the first calculation circuit;

[0015] The free storage space information of the memory is determined by the first computing circuit;

[0016] Based on the releasable storage space information and the free storage space information, the first computing circuit determines whether to suspend the first calculation.

[0017] According to another aspect of the present disclosure, a computer-readable storage medium is provided, the storage medium storing a computer program that is executed by a processor to perform the above-described information processing method based on a computing device.

[0018] According to another aspect of the present disclosure, an electronic device is provided, the electronic device comprising:

[0019] processor;

[0020] Memory used to store the processor's executable instructions;

[0021] The processor is configured to read the executable instructions from the memory and execute the instructions to implement the aforementioned information processing method based on a computing device.

[0022] According to another aspect of the present disclosure, a computer program product is provided that, when instructions in the computer program product are executed by a processor, performs the above-described information processing method based on a computing device.

[0023] Based on the computing device, information processing method, medium, device, and program product provided in the above embodiments of this disclosure, the computing task corresponding to the first computing can be decomposed into multiple first sub-tasks, and the computing task corresponding to the second computing can be decomposed into multiple second sub-tasks. The first computing circuit performs a first computing operation on the data to be computed, which is equivalent to completing a first sub-task. The first computing circuit can store the sub-result data corresponding to this first sub-task in the memory. Furthermore, in response to the addition of sub-result data that meets the first preset synchronization condition in the memory, the first computing circuit can generate first synchronization information and send it to the second computing circuit. Based on the first synchronization information, the second computing circuit can determine whether new sub-result data required for a second computing operation has been added to the memory, i.e., whether new sub-result data required for executing a second sub-task has been added to the memory. If new sub-result data required for executing a second sub-task has been added to the memory, a second computing operation can be performed on that sub-result data, which is equivalent to completing a second sub-task. Clearly, the second computing circuit does not need to wait for all first sub-computations to be completed before starting to execute the second sub-task. There can be a certain degree of parallelism between the first and second sub-tasks, which helps to shorten the overall computing time and improve the overall computing efficiency. Furthermore, the second computing circuit can generate second synchronization information and send it to the first computing circuit in response to the sub-result data in the memory that meets the second preset synchronization condition and the second calculation conforms to the target relationship. This provides a valid reference for determining the free storage space information of the memory. Combined with the free storage space information of the memory, the first computing circuit can determine whether there is sufficient space in the memory to store the sub-result data to be generated. Based on this, the first computing circuit can adaptively determine whether to suspend the first calculation. It should be noted that if there is insufficient space in the memory for data storage, but the first computing circuit stores new sub-result data in the memory, it is very likely that existing sub-result data in the memory that has not been used by the second computing circuit will be overwritten. This will lead to calculation errors in the second computing circuit. In the embodiments of this disclosure, since the first computing circuit can adaptively determine whether to suspend the first calculation, it can avoid overwriting existing sub-result data in the memory that has not been used by the second computing circuit, thereby avoiding calculation errors in the second computing circuit. This is beneficial to ensuring the correct calculation of the second computing circuit. Therefore, even if the task is decomposed, the same calculation effect as the serial calculation in the related technology can be achieved. As can be seen, in the embodiments of this disclosure, by working together with the memory, the first computing circuit and the second computing circuit, the overall computing time can be shortened and the overall computing efficiency can be improved while achieving the same computing effect as serial computing, thereby better meeting actual needs, such as meeting the needs of high real-time requirements by reducing computing latency. Attached Figure Description

[0024] Figure 1 This is one of the structural schematic diagrams of a computing device provided in some exemplary embodiments of this disclosure.

[0025] Figure 2-1 This is one of the schematic diagrams of the data to be calculated in some exemplary embodiments of this disclosure.

[0026] Figure 2-2 This is a schematic diagram of the data to be calculated, the convolution kernel, the first calculation result data, and the second calculation result data in some exemplary embodiments of this disclosure.

[0027] Figure 2-3 This is a schematic diagram of the data to be calculated and the first calculation result data in some exemplary embodiments of this disclosure.

[0028] Figure 2-4 This is a second schematic diagram of the data to be calculated in some exemplary embodiments of this disclosure.

[0029] Figure 2-5 This is a schematic diagram of the first computation result data and the convolution kernel in some exemplary embodiments of this disclosure.

[0030] Figure 3-1 This is a second schematic diagram of the structure of a computing device provided in some exemplary embodiments of this disclosure.

[0031] Figure 3-2 This is the third of several exemplary embodiments of a computing device provided in this disclosure.

[0032] Figure 4 This is the fourth of several exemplary embodiments of a computing device provided in this disclosure.

[0033] Figure 5 This is the fifth of several exemplary embodiments of the computing device provided in this disclosure.

[0034] Figure 6 This is a schematic diagram illustrating how some exemplary embodiments of this disclosure achieve the same computational effect as serial computation.

[0035] Figure 7 This is one of the flowcharts illustrating an information processing method based on a computing device provided in some exemplary embodiments of this disclosure.

[0036] Figure 8 This is a second schematic flowchart of an information processing method based on a computing device provided by some exemplary embodiments of this disclosure.

[0037] Figure 9 This is the third flowchart illustrating an information processing method based on a computing device provided in some exemplary embodiments of this disclosure.

[0038] Figure 10This is the fourth flowchart illustrating an information processing method based on a computing device provided in some exemplary embodiments of this disclosure.

[0039] Figure 11 This is the fifth of several exemplary embodiments of the information processing method based on a computing device provided in this disclosure.

[0040] Figure 12 This is the sixth of several exemplary embodiments of the information processing method based on a computing device provided in this disclosure.

[0041] Figure 13 This is the seventh flowchart illustrating an information processing method based on a computing device provided in some exemplary embodiments of this disclosure.

[0042] Figure 14 This is a schematic diagram of the structure of an electronic device provided by some exemplary embodiments of this disclosure. Detailed Implementation

[0043] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0044] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0045] Application Overview

[0046] Serial computation refers to computations performed in a strict sequential order; a new computation can only begin after the previous one has been completed. For example, a neural network consists of sequentially arranged convolution and pooling operators. When running a neural network, convolution and pooling computations must be performed sequentially, and pooling computations can only begin after all convolution computations have been completed.

[0047] It should be noted that serial computation has an excessively long overall computation time and low overall efficiency, making it difficult to meet practical needs, such as those requiring high real-time performance. Therefore, how to shorten the overall computation time and improve the overall computation efficiency while achieving the same computational effect as serial computation is a technical problem worthy of attention for those skilled in the art.

[0048] Exemplary System

[0049] In the embodiments of this disclosure, for scenarios requiring serial computation, the computational task corresponding to the former type of computation can be decomposed into multiple first subtasks, and the computational task corresponding to the latter type of computation can be decomposed into multiple second subtasks. In response to obtaining sub-result data usable for a second subtask by executing several first subtasks, the second subtask can be executed immediately without waiting for all first subtasks to complete before starting the second subtask. This improves the parallelism of data computation. Therefore, the embodiments of this disclosure can shorten the overall computation time and improve the overall computational efficiency while achieving the same computational effect as serial computation, thereby better meeting practical needs, such as those with high real-time requirements.

[0050] Exemplary device

[0051] Embodiments of this disclosure provide a computing device. The computing device can be applied to a computing system in any device. This "any device" can be, for example, an autonomous mobile device such as a vehicle, robot, or drone, or an electronic device such as a mobile phone, tablet, or wearable device. The computing system can be, for example, a system-on-a-chip (SoC) or other form of task processing system.

[0052] like Figure 1 As shown, the computing device may include a memory 20, a first computing circuit 40, and a second computing circuit 60;

[0053] The first calculation circuit 40 is used to perform multiple first calculations sequentially on the data to be calculated; in response to generating sub-result data of a first calculation, it stores the sub-result data of a first calculation in the memory 20; in response to adding sub-result data that meets the first preset synchronization condition to the memory 20, it generates first synchronization information.

[0054] The second calculation circuit 60 is used to determine, in response to the first synchronization information, the sub-result data required for adding a second calculation in the memory 20, and to perform a second calculation on the sub-result data required for the second calculation; and to generate second synchronization information in response to the sub-result data in the memory 20 that meets the second preset synchronization conditions and conforms to the target relationship with the second calculation; wherein, any sub-result data conforming to the target relationship with the second calculation means that: the sub-result data has been used for the second calculation for the last time; or, the sub-result data belongs to data outside the calculation scope of the second calculation;

[0055] The first computing circuit 40 is also used to determine the free storage space information of the memory 20 based on the second synchronization information; determine the free storage space information of the memory 20; and determine whether to terminate the first computing based on the free storage space information and the free storage space information.

[0056] Optionally, memory 20 may be circuitry in a computing device used for storing data. Memory 20 may include, for example but not limited to, static random access memory (SRAM), dynamic random access memory (DRAM), double data rate synchronous dynamic random access memory (DDR), etc.

[0057] Optionally, the first computing circuit 40 may be a circuit in the computing device that supports the first computing, and the second computing circuit 60 may be a circuit in the computing device that supports the second computing. The second computing circuit 60 may be located downstream of the first computing circuit 40.

[0058] Suppose that the computing device is used in a computing system to support intelligent driving of vehicles. The realization of intelligent driving of vehicles relies on some neural networks for environmental perception. The neural network includes various operators, such as convolution operators, pooling operators, and rectified linear unit (ReLU) operators. In one optional example, the first computation can be a convolution computation and the second computation can be a pooling computation. In another optional example, the first computation can be a pooling computation and the second computation can be a convolution computation. In yet another optional example, the first computation can be a pooling computation and the second computation can be a rectified linear unit (ReLU) computation.

[0059] Assuming the computing system used by the computing device is used to support high-quality imaging of the mobile phone, and the high-quality imaging of the mobile phone requires image processing by an image signal processor (ISP), then in one optional example, the first calculation can be a bad pixel correction calculation, and the second calculation can be an automatic white balance calculation. In another optional example, the first calculation can be a de-mosaic calculation, and the second calculation can be a color correction calculation.

[0060] Optionally, the data to be calculated may be data to be input into the first computing circuit 40 for a first calculation. The data to be calculated may be tensor data, such as, but not limited to, image data, feature map data, etc. If the computing system in which the computing device is applied is used to support intelligent driving of a vehicle, the data to be calculated may be image data captured by a first camera installed on the vehicle, or feature map data obtained after performing a third calculation (which may be different from the first and second calculations) on the image data captured by the first camera. The third calculation may be, for example, a normalization calculation. If the computing system in which the computing device is applied is used to support high-quality imaging of a mobile phone, the data to be calculated may be image data captured by a second camera installed on the mobile phone, or image data obtained after performing a fourth calculation (which may be different from the first and second calculations) on the image data captured by the second camera. The fourth calculation may be, for example, a noise reduction calculation.

[0061] In an optional example, such as Figure 2-1 As shown, the data to be calculated has a size of 1 in the batch processing dimension, and a size of 4 in the width, height, and channel dimensions. In another optional example, such as... Figure 2-2 As shown, the data to be calculated has a size of 1 in both the batch and channel dimensions, and a size of 4 in both the width and height dimensions. In another optional example, such as... Figure 2-3 As shown, the data to be calculated has a size of 1 in both the batch and channel dimensions, and a size of 5 in both the width and height dimensions. In another optional example, such as Figure 2-4 As shown, the size of the data to be calculated in the batch processing dimension is 4. Figure 2-4 ①, ②, ③, and ④ in the diagram each correspond to a batch, and the data to be calculated has a size of 16 in the width, height, and channel dimensions.

[0062] It should be noted that the calculations in the embodiments of this disclosure can be interpreted broadly, and their types are not limited to convolution, pooling, ReLU, normalization, bad pixel correction, automatic white balance, de-mosaic, color correction, noise reduction, etc. For example, they can also be data loading, data write-back, data reassembly, etc., which will not be listed here.

[0063] In the embodiments of this disclosure, the first calculation circuit 40 can sequentially perform multiple first calculations on the data to be calculated. Specifically, the first calculation circuit 40 can first perform a first calculation on the data to be calculated to obtain sub-result data of the first calculation; then perform a second calculation on the data to be calculated to obtain sub-result data of the second calculation; then perform a third calculation on the data to be calculated to obtain sub-result data of the third calculation; and so on, until the last calculation is performed on the data to be calculated to obtain sub-result data of the last calculation. The complete calculation result data obtained by the first calculation circuit 40 through the first calculations may include sub-result data of each first calculation.

[0064] In an optional example, such as Figure 2-2 As shown, the data to be calculated includes 16 elements in a 4x4 matrix. The first calculation is a convolution calculation. The convolution kernel used in the convolution calculation includes 9 elements in a 3x3 matrix, and the stride used in the convolution calculation is 1. Therefore, the 3x3 elements in the top left corner of the data to be calculated are multiplied at corresponding positions by the 3x3 elements in the convolution kernel, and all products are summed to obtain P11. P11 can be used as the sub-result data of the first term, the first calculation. The 3x3 elements in the top right corner of the data to be calculated are multiplied at corresponding positions by the 3x3 elements in the convolution kernel, and the sum of all products is then obtained. Summing all products yields P12, which can be used as a sub-result of the first calculation in the second term. Multiplying the 3x3 elements in the bottom left corner of the data to be calculated by the corresponding elements of the 3x3 elements in the convolution kernel, and summing all products, yields P21, which can be used as a sub-result of the first calculation in the third term. Multiplying the 3x3 elements in the bottom right corner of the data to be calculated by the corresponding elements of the 3x3 elements in the convolution kernel, and summing all products, yields P22, which can be used as a sub-result of the first calculation in the fourth term. Thus, P11, P12, P21, and P22 satisfy the following:

[0065] P11=X11*W11+X12*W12+X13*W13+X21*W21+X22*W22+X23*W23+X31*W31+X32*W32+X33*W33;

[0066] P12=X12*W11+X13*W12+X14*W13+X22*W21+X23*W22+X24*W23+X32*W31+X33*W32+X34*W33;

[0067] P21=X21*W11+X22*W12+X23*W13+X31*W21+X32*W22+X33*W23+X41*W31+X42*W32+X43*W33;

[0068] P22=X22*W11+X23*W12+X24*W13+X32*W21+X33*W22+X34*W23+X42*W31+X43*W32+X44*W33.

[0069] For ease of description, the complete calculation result data obtained by the first calculation circuit 40 through the first calculation will be referred to as the first calculation result data. The first calculation result data may include P11, P12, P21, and P22; wherein, P11 may be located in the first row and first column of the first calculation result data; P12 may be located in the first row and second column of the first calculation result data; P21 may be located in the second row and first column of the first calculation result data; and P22 may be located in the second row and second column of the first calculation result data.

[0070] In another alternative example, such as Figure 2-3 As shown, the data to be calculated includes 25 elements in a 5x5 matrix. The first calculation is pooling, specifically average pooling. The pooling window size used for average pooling is 3x3, and the step size is 1. Therefore, nine first calculations are performed sequentially on the data. Assuming the nine sub-results corresponding to these nine first calculations are represented as B11, B12, B13, B21, B22, B23, B31, B32, and B33, then:

[0071] B11=(R11+R12+R13+R21+R22+R23+R31+R32+R33) / 9

[0072] B12=(R12+R13+R14+R22+R23+R24+R32+R33+R34) / 9

[0073] B13=(R13+R14+R15+R23+R24+R25+R33+R34+R35) / 9

[0074] B21=(R21+R22+R23+R31+R32+R33+R41+R42+R43) / 9

[0075] B22=(R22+R23+R24+R32+R33+R34+R42+R43+R44) / 9

[0076] B23=(R23+R24+R25+R33+R34+R35+R43+R44+R45) / 9

[0077] B31=(R31+R32+R33+R41+R42+R43+R51+R52+R53) / 9

[0078] B22=(R32+R33+R34+R42+R43+R44+R52+R53+R54) / 9

[0079] B23=(R33+R34+R35+R43+R44+R45+R53+R54+R55) / 9

[0080] The first calculation result data may include B11, B12, B13, B21, B22, B23, B31, B32, and B33; wherein, B11 may be located in the first row and first column of the first calculation result data; B12 may be located in the first row and second column of the first calculation result data; B13 may be located in the first row and third column of the first calculation result data; B21 may be located in the second row and first column of the first calculation result data; B22 may be located in the second row and second column of the first calculation result data; B23 may be located in the second row and third column of the first calculation result data; B31 may be located in the third row and first column of the first calculation result data; B32 may be located in the third row and second column of the first calculation result data; and B33 may be located in the third row and third column of the first calculation result data.

[0081] The first computing circuit 40 can be electrically connected to the memory 20, so that, in response to generating a sub-result data of a first calculation, the first computing circuit 40 can store the sub-result data of the first calculation in the memory 20. For example, the first computing circuit 40 can respond to generating... Figure 2-2 P11 in the middle, store P11 in memory 20; in response to generation Figure 2-2 P12 in the memory is stored in memory 20; in response to the generation Figure 2-2 P21 in the middle, store P21 in memory 20; in response to generation Figure 2-2 P22 in the memory is stored in the memory 20.

[0082] The first computing circuit 40 may be pre-configured with a first preset synchronization condition. The first preset synchronization condition may, for example, be a first preset data quantity. The first preset data quantity can be set according to actual conditions, and this disclosure does not limit it. Since the sub-result data in the memory 20 is stored by the first computing circuit 40, the first computing circuit 40 can determine the addition of sub-result data in the memory 20. Based on this, the first computing circuit 40 can determine whether new sub-result data satisfying the first preset synchronization condition has been added to the memory 20. If new sub-result data satisfying the first preset synchronization condition has been added to the memory 20, the first computing circuit 40 can generate first synchronization information. The first synchronization information may be information used to indicate that new sub-result data satisfying the first preset synchronization condition has been added to the memory 20. The first computing circuit 40 can be electrically connected to the second computing circuit 60, so that the first computing circuit 40 can send the first synchronization information to the second computing circuit 60.

[0083] The second computing circuit 60 can receive first synchronization information from the first computing circuit 40. Since the first synchronization information indicates that new sub-result data satisfying the first preset synchronization condition has been added to the memory 20, based on the first synchronization information, the second computing circuit 60 can infer the addition of sub-result data in the memory 20. Based on this, the second computing circuit 60 can determine whether new sub-result data required for a second calculation has been added to the memory 20. The sub-result data required for a second calculation may include only the sub-result data obtained by the first computing circuit 40 through a first calculation, or it may include more than one sub-result data obtained by the first computing circuit 40 through more than one first calculation, depending on the type of the second calculation. For example, if the second calculation is a ReLU calculation, the sub-result data required for a second calculation may only include the sub-result data obtained by the first computing circuit 40 through a first calculation; if the second calculation is a convolution calculation or a pooling calculation, the sub-result data required for a second calculation includes more than one sub-result data obtained by the first computing circuit 40 through more than one first calculation. If new sub-result data required for a second calculation is added to the memory 20, the second computing circuit 60 can perform a second calculation on the sub-result data required for the second calculation.

[0084] In an optional example, the first calculation result data is as follows: Figure 2-2As shown, the second calculation is of the ReLU type. The second calculation circuit 60 can obtain the second calculation result data through four ReLU calculations. Specifically, P11 can be the sub-result data required for the first ReLU calculation; P12 can be the sub-result data required for the second ReLU calculation; P21 can be the sub-result data required for the third ReLU calculation; and P22 can be the sub-result data required for the fourth ReLU calculation. Therefore, if P11 is added to the memory 20, the second calculation circuit 60 can perform the first ReLU calculation on P11 to obtain Q11; if P12 is added to the memory 20, the second calculation circuit 60 can perform the second ReLU calculation on P12 to obtain Q12; if P21 is added to the memory 20, the second calculation circuit 60 can perform the third ReLU calculation on P21 to obtain Q21; and if P22 is added to the memory 20, the second calculation circuit 60 can perform the fourth ReLU calculation on P22 to obtain Q22. The second calculation result data may include Q11, Q12, Q21, and Q22; wherein, Q11 may be located in the first row and first column of the second calculation result data; Q12 may be located in the first row and second column of the second calculation result data; Q21 may be located in the second row and first column of the second calculation result data; and Q22 may be located in the second row and second column of the second calculation result data.

[0085] The second calculation circuit 60 may be pre-configured with a second preset synchronization condition. The second preset synchronization condition may, for example, be a second preset data amount. The second preset data amount can be set according to actual conditions, and this disclosure does not limit it. The second preset data amount may be the same as or different from the first preset data amount mentioned above. The second calculation circuit 60 can determine whether there is sub-result data in the memory 20 that satisfies the second preset synchronization condition and conforms to the target relationship of the second calculation. Here, there are two cases where any sub-result data conforms to the target relationship of the second calculation, which will be described below.

[0086] First scenario:

[0087] This sub-result data has been used in the second calculation for the last time. For example, in conjunction with the above text regarding... Figure 2-2For example, P11 is the sub-result data required for the first ReLU calculation, P12 is the sub-result data required for the second ReLU calculation, P21 is the sub-result data required for the third ReLU calculation, and P22 is the sub-result data required for the fourth ReLU calculation. Clearly, each of P11, P12, P21, and P22 participates in only one second calculation. Therefore, in response to the completion of the first ReLU calculation, it can be determined that P11 has been used for the last time in the second calculation; in response to the completion of the second ReLU calculation, it can be determined that P12 has been used for the last time in the second calculation; in response to the completion of the third ReLU calculation, it can be determined that P21 has been used for the last time in the second calculation; and in response to the completion of the fourth ReLU calculation, it can be determined that P22 has been used for the last time in the second calculation. As another example, if the second calculation is a convolution calculation, the convolution window needs to be slid during the convolution calculation process. The convolution window before and after the sliding may overlap, which may cause some sub-result data to participate in more than one second calculation. Therefore, it can only be determined that the sub-result data has been used for the last time in the second calculation after it has participated in all of these multiple second calculations.

[0088] The second scenario:

[0089] This sub-result data falls outside the scope of the second calculation. In other words, this sub-result data does not participate in the second calculation; that is, it is data that the second calculation does not require. For example, the first calculation result data is as follows: Figure 2-5 As shown, there are 20 sub-result data, including G11, G12, G13, ..., G44, G45. The second calculation is a convolution calculation, and the convolution kernel used in the convolution calculation is as follows: Figure 2-5 As shown, the width and height of the convolution kernel are both 2. Assuming the stride of the convolution calculation is 2 in both the width and height directions, the second calculation circuit 60 can obtain the second calculation result data through four convolution calculations. Among them, G11, G12, G21, and G22 can be the sub-result data required for the first convolution calculation; G13, G14, G23, and G24 can be the sub-result data required for the second convolution calculation; G31, G32, G41, and G42 can be the sub-result data required for the third convolution calculation; and G33, G34, G43, and G44 can be the sub-result data required for the fourth convolution calculation. Obviously, G15, G25, G35, and G45 are data not needed for the convolution calculation. Therefore, G15, G25, G35, and G45 belong to the calculation scope outside the second calculation.

[0090] If the sub-result data in memory 20 that meets the second preset synchronization condition conforms to the target relationship with the second calculation, the second calculation circuit 60 can generate second synchronization information. This second synchronization information can be used to indicate that the sub-result data in memory 20 that meets the second preset synchronization condition conforms to the target relationship with the second calculation. The second calculation circuit 60 can be electrically connected to the first calculation circuit 40, so that the second calculation circuit 60 can send the second synchronization information to the first calculation circuit 40.

[0091] The first computing circuit 40 can receive second synchronization information from the second computing circuit 60. Since the second synchronization information is used to indicate that the sub-result data in the memory 20 that meets the second preset synchronization condition conforms to the target relationship with the second calculation, this indicates that each sub-result data may have been used for the second calculation last time, or it may be data that the second calculation does not need. That is, each sub-result data may be sub-result data that the second computing circuit 60 has finished using, or it may be sub-result data that the second computing circuit 60 will not use. Even if the memory 20 no longer stores these sub-result data, it will not affect the normal operation of the second computing circuit 60. Therefore, the first computing circuit 40 can determine the releasable storage space information of the memory 20 based on the second synchronization information. The releasable storage space information of the memory 20 can at least characterize the releasable storage space capacity of the memory 20. The releasable storage space capacity can be understood as the size of the releasable storage space of the memory 20. The releasable storage space of the memory 20 can be understood as the space in the memory 20 where data is stored, but the deletion of the stored data will not have an adverse effect. The first computing circuit 40 can also determine the free storage space information of the memory 20; wherein, the free storage space information of the memory 20 can at least characterize the free storage space capacity of the memory 20, the free storage space capacity can be understood as the size of the free storage space of the memory 20, and the free storage space of the memory 20 can be understood as the space in the memory 20 that does not store data. Optionally, the freeable storage space information of the memory 20 can also characterize the freeable storage space address of the memory 20, and the free storage space information of the memory 20 can also indicate the free storage space address of the memory 20.

[0092] The first computing circuit 40 can determine whether there is sufficient space in the memory 20 to store the sub-result data to be generated, based on the information on releasable storage space and free storage space. If there is sufficient space in the memory 20 to store the sub-result data to be generated, the first computing circuit 40 can determine not to suspend the first calculation, but to continue the first calculation and store the newly generated sub-result data in the memory 20. If there is insufficient space in the memory 20 to store the sub-result data to be generated, the first computing circuit 40 can determine to suspend the first calculation. In this case, the first computing circuit 40 will not generate new sub-result data in a short period of time. When the second computing circuit 60 continues to perform the second calculation, causing the information on releasable storage space to change, and thus causing the memory 20 to change to have sufficient space to store the sub-result data to be generated, the first computing circuit 40 can resume the first calculation.

[0093] In the embodiments of this disclosure, the computational task corresponding to the first computation can be decomposed into multiple first sub-tasks, and the computational task corresponding to the second computation can be decomposed into multiple second sub-tasks. The first computational circuit 40 performs a first computation on the data to be computed, which is equivalent to completing a first sub-task. The first computational circuit 40 can store the sub-result data corresponding to this first sub-task in the memory 20. Furthermore, in response to the addition of sub-result data satisfying a first preset synchronization condition in the memory 20, the first computational circuit 40 can generate first synchronization information and send it to the second computational circuit 60. Based on the first synchronization information, the second computational circuit 60 can determine whether new sub-result data required for a second computation has been added to the memory 20, i.e., whether new sub-result data required for executing a second sub-task has been added to the memory 20. If new sub-result data required for executing a second sub-task has been added to the memory 20, a second computation can be performed on that sub-result data, which is equivalent to completing a second sub-task. Clearly, the second computational circuit 60 does not need to wait for all first sub-computations to be completed before starting to execute the second sub-task. There can be a certain degree of parallelism between the first and second sub-tasks, which helps to shorten the overall computation time and improve the overall computational efficiency. In addition, the second calculation circuit 60 can generate second synchronization information and send it to the first calculation circuit 40 in response to the sub-result data in the memory 20 that meets the second preset synchronization condition and the second calculation conforms to the target relationship. This provides an effective reference for determining the free storage space information of the memory 20. Combined with the free storage space information of the memory 20, the first calculation circuit 40 can determine whether there is sufficient space in the memory 20 to store the sub-result data to be generated. Based on this, the first calculation circuit 40 can adaptively determine whether to suspend the first calculation. It should be noted that if there is insufficient space in the memory 20 for data storage, but the first calculation circuit 40 stores new sub-result data in the memory 20, it is likely that existing sub-result data in the memory 20 that has not been used by the second calculation circuit 60 will be overwritten. This could lead to calculation errors in the second calculation circuit 60. In the embodiments of this disclosure, since the first calculation circuit 40 can adaptively determine whether to suspend the first calculation, it can avoid overwriting existing sub-result data in the memory 20 that has not been used by the second calculation circuit 60, thereby avoiding calculation errors in the second calculation circuit 60. This helps ensure the correct calculation of the second calculation circuit 60. Therefore, even with task decomposition, the same calculation effect as serial calculation in related technologies can be achieved. It can be seen that in the embodiments of this disclosure, through the collaborative work of the memory 20, the first calculation circuit 40, and the second calculation circuit 60, the overall calculation time can be shortened and the overall calculation efficiency improved while achieving the same calculation effect as serial calculation, thereby better meeting actual needs, such as meeting the requirements for high real-time performance by reducing calculation latency.

[0094] It should be emphasized that, since the task is decomposed in the embodiments of this disclosure, the memory 20 does not need to store the entire first calculation result data at the same time, but only stores several sub-result data. Therefore, it is beneficial to reduce the storage space occupied in the memory 20 and improve the utilization rate of the storage space in the memory 20.

[0095] In some alternative examples, the first computing circuit 40 is used to determine whether to abort the first computing based on free storage space information and free storage space information, and may include:

[0096] The first computing circuit 40 is used to determine the free storage capacity of the memory 20 based on the free storage space information; determine the free storage capacity of the memory 20 based on the free storage space information; determine the available storage capacity of the memory 20 based on the free storage capacity and the free storage capacity; and determine whether to suspend the first computing based on the available storage capacity.

[0097] As described above, the freeable storage space information of memory 20 can at least characterize the freeable storage space capacity of memory 20, and the free storage space information of memory 20 can at least characterize the free storage space capacity of memory 20. Therefore, based on the freeable storage space information and the free storage space information, the first calculation circuit 40 can efficiently and reliably determine the freeable storage space capacity and the free storage space capacity of memory 20. The first calculation circuit 40 can determine the available storage space capacity of memory 20 based on the freeable storage space capacity and the free storage space capacity. For example, the first calculation circuit 40 can sum the freeable storage space capacity and the free storage space capacity, and the sum can be used as the available storage space capacity of memory 20. Alternatively, a storage space capacity that is less than the sum but substantially the same as the sum can be used as the available storage space capacity of memory 20. The first calculation circuit 40 can also compare the available storage space capacity of memory 20 with a preset storage space capacity; wherein, the preset storage space capacity can be a pre-set storage space capacity used to assess whether the available storage space of memory 20 is sufficient. If the available storage space capacity is greater than the preset storage space capacity, the first calculation circuit 40 can determine that there is sufficient space in the memory 20 to store the sub-result data to be generated, and the first calculation circuit 40 can determine not to terminate the first calculation. If the available storage space capacity is not greater than the preset storage space capacity, the first calculation circuit 40 can determine that there is insufficient space in the memory 20 to store the sub-result data to be generated, and the first calculation circuit 40 can determine to terminate the first calculation.

[0098] It should be noted that the free storage space capacity of memory 20 is the size of the free storage space of memory 20, and the freeable storage space capacity of memory 20 is the size of the freeable storage space of memory 20. Both the free storage space and the freeable storage space can be used to store the sub-result data to be generated. Therefore, by combining the free storage space capacity and the freeable storage space capacity, the available storage space capacity of memory 20 can be reasonably determined. Based on this, it is possible to efficiently, quickly and reasonably determine whether the first calculation needs to be terminated.

[0099] In some optional examples, such as Figure 3-1 As shown, the first computing circuit 40 may include a first computing sub-circuit 401 and a first synchronous transmission sub-circuit 403;

[0100] The first calculation circuit 40 is used to sequentially perform multiple first calculations on the data to be calculated; in response to generating sub-result data of a first calculation, it stores the sub-result data of a first calculation in the memory 20; in response to the addition of sub-result data that meets the first preset synchronization condition in the memory 20, it generates first synchronization information, which may include:

[0101] The first calculation sub-circuit 401 is used to perform multiple first calculations sequentially on the data to be calculated; in response to generating sub-result data of a first calculation, it stores the sub-result data of a first calculation in the memory 20; and determines the dimension information of the sub-result data of a first calculation.

[0102] The first synchronous transmission sub-circuit 403 is used to respond to the determination of newly added sub-result data in the memory 20 that meets the first preset synchronization condition based on dimension information and a first preset data granularity, and to generate first synchronization information.

[0103] Optionally, the first computing sub-circuit 401 may be a circuit in the first computing circuit 40 that supports the first calculation, and the first synchronous transmission sub-circuit 403 may be a sub-circuit in the first computing circuit 40 used to communicate with the first computing sub-circuit 401 and the second computing circuit 60 respectively. Specifically, the first synchronous transmission sub-circuit 403 may be electrically connected to the first computing sub-circuit 401 to receive information sent by the first computing sub-circuit 401; the first synchronous transmission sub-circuit 403 may also be electrically connected to the second computing circuit 60 to send information to the second computing circuit 60. In addition, the first computing sub-circuit 401 may be electrically connected to the memory 20, and the second computing circuit 60 may also be electrically connected to the memory 20.

[0104] Optionally, the first preset data granularity can be a pre-defined data granularity used to represent fine-grained data. In one optional example, the first preset data granularity can be N1 pixels, where N1 can be an integer greater than or equal to 1. In another optional example, the first preset data granularity can be N2 rows of pixels, where N2 can be an integer greater than or equal to 1. In yet another optional example, the first preset data granularity can be N3 columns of pixels, where N3 can be an integer greater than or equal to 1. In yet another optional example, the first preset data granularity can be a first preset data block size, which can include the dimensions corresponding to the width dimension, height dimension, and channel dimension, respectively.

[0105] In the embodiments of this disclosure, the first calculation sub-circuit 401 can sequentially perform multiple first calculations on the data to be calculated. Specifically, the first calculation sub-circuit 401 can first perform a first calculation on the data to be calculated to obtain sub-result data of the first calculation; then perform a second calculation on the data to be calculated to obtain sub-result data of the second calculation; then perform a third calculation on the data to be calculated to obtain sub-result data of the third calculation; and so on, until the last calculation is performed on the data to be calculated to obtain sub-result data of the last calculation. In response to generating sub-result data of a first calculation, the first calculation sub-circuit 401 can not only store the sub-result data of a first calculation in the memory 20, but also determine the dimension information of the sub-result data of a first calculation. The dimension information can be the index information of the sub-result data of a first calculation in the first calculation result data, used to characterize which rows, columns, channels, etc., of the sub-result data of a first calculation are located in the first calculation result data.

[0106] In an optional example, a sub-result data of the first calculation (e.g.) Figure 2-2 If P11 is located in the first row and first column of the first calculation result data, then the dimension information can be: h0, w0; where h0 corresponds to the first row and w0 corresponds to the first column.

[0107] In another optional example, a sub-result data of the first calculation (e.g.) Figure 2-2 If P22 is located in the second row and second column of the first calculation result data, then the dimension information can be: h1, w1; where h1 corresponds to the second row and w0 corresponds to the second column.

[0108] In another alternative example, if a sub-result data of a first calculation is located in the first row to the second row of the first calculation result data, in the first column to the eighth column of the first calculation result data, and in the first channel to the eighth channel of the first calculation result data, then the dimension information can be: h0-1, w0-7, c0-7; where h0-1 corresponds to the first row to the second row, w0-7 corresponds to the first column to the eighth column, and c0-7 corresponds to the first channel to the eighth channel.

[0109] In another optional example, if a sub-result data of the first calculation is located in the third and fourth rows, the first to eighth columns, and the first to eighth channels of the first calculation result data, then the dimension information can be: h2-3, w0-7, c0-7; where h2-3 corresponds to the third and fourth rows, w0-7 corresponds to the first to eighth columns, and c0-7 corresponds to the first to eighth channels. The first calculation sub-circuit 401 can send the dimension information to the first synchronous transmission sub-circuit 403.

[0110] The first synchronous transmission sub-circuit 403 can receive dimension information from the first calculation sub-circuit 401. The first synchronous transmission sub-circuit 403 can be pre-configured with a first preset data granularity. As described above, the dimension information can be the index information of the corresponding sub-result data in the first calculation result data. Therefore, based on the dimension information, the first synchronous transmission sub-circuit 403 can deduce which sub-result data from the first calculation result data has been added to the memory 20. Furthermore, the first preset synchronization condition can be associated with the first preset data granularity. For example, the first preset synchronization condition can be: having the first preset data granularity, or it can be: the data volume is a preset multiple of the first preset data granularity. Combining the dimension information and the first preset data granularity, the first synchronous transmission sub-circuit 403 can determine whether sub-result data satisfying the first preset synchronization condition has been added to the memory 20. If sub-result data satisfying the first preset synchronization condition has been added to the memory 20, the first synchronous transmission sub-circuit 403 can generate first synchronization information and send the first synchronization information to the second calculation circuit 60.

[0111] The second calculation circuit 60 can receive first synchronization information from the first synchronization transmission sub-circuit 403. In response to determining, based on the first synchronization information, that sub-result data required for adding a second calculation to the memory 20, the second calculation circuit 60 can perform a second calculation on the sub-result data required for the second calculation. By performing multiple second calculations, the second calculation circuit 60 can obtain the second calculation result data.

[0112] In the embodiments of this disclosure, the first computing sub-circuit 401 can not only store the sub-result data corresponding to the first subtask in the memory 20, but also determine the dimension information of the sub-result data and send it to the first synchronization transmission sub-circuit 403. Based on the received dimension information and combined with a pre-configured first preset data granularity, the first synchronization transmission sub-circuit 403 can perform relevant condition judgments (e.g., judging whether the first preset synchronization condition is met). If the condition is met, it can generate first synchronization information for the second computing circuit 60, so that the second computing circuit 60 can judge whether the sub-result data required for a second subtask is ready. If the judgment result is that the data is ready, the second computing circuit 60 can execute the second subtask. Thus, through the collaborative work of the first computing sub-circuit 401, the first synchronization transmission sub-circuit 403, the memory 20, and the second computing circuit 60, a certain degree of parallelism can be achieved between the first and second subtasks, thereby helping to shorten the overall computation time and improve the overall computational efficiency.

[0113] In some optional examples, the first synchronization transmission sub-circuit 403 is used to determine, in response to dimension information and a first preset data granularity, that newly added sub-result data satisfying the first preset synchronization condition has been added to the memory 20, and to generate first synchronization information, which may include:

[0114] The first synchronous transmission sub-circuit 403 is used to respond to the determination of sub-result data in the memory 20 based on dimension information, which includes a first target number of first preset data granularities, and to generate first synchronization information including the first target number.

[0115] The second calculation circuit 60 is configured to, in response to determining, based on the first synchronization information, sub-result data required for adding a second calculation to the memory 20, and to perform a second calculation on the sub-result data required for the second calculation, may include:

[0116] The second calculation circuit 60 is used to obtain a first target quantity from the first synchronization information; in response to determining the sub-result data required for adding a second calculation in the memory 20 based on the first target quantity and the first preset data granularity, a second calculation is performed on the sub-result data required for the second calculation.

[0117] Optionally, the first preset synchronization condition can be: the data volume is a multiple of the first target number of the first preset data granularity. The first target number can be a fixed number, such as 2, 3, 5, 6, 8, 9, or 10. Alternatively, the first target number can be a periodically changing number. For example, the first target number can change according to the pattern 10 / 9 / 8. In the first period, the first target number can be 10; in the second period, it can be 9; in the third period, it can be 8; in the fourth period, it can be 10; in the fifth period, it can be 9; in the sixth period, it can be 8, and so on. This will not be elaborated further here.

[0118] As described above, the dimension information can be the index information of the corresponding sub-result data in the first calculation result data. Based on the dimension information, the first synchronization transmission sub-circuit 403 can deduce which sub-result data from the first calculation result data has been added to the memory 20. This allows it to determine whether sub-result data including the first target number of data with the first preset data granularity has been added to the memory 20. If sub-result data including the first target number of data with the first preset data granularity has been added to the memory 20, it can be determined that sub-result data satisfying the first preset synchronization condition has been added. Then, the first synchronization transmission sub-circuit 403 can generate first synchronization information including the first target number and send the first synchronization information to the second calculation circuit 60. In an optional example, the first preset data granularity is 1 pixel, and the first target number is 9. If sub-result data including the color values ​​of 9 pixels has been added to the memory 20, the first synchronization transmission sub-circuit 403 can generate first synchronization information including the first target number of 9 and send the first synchronization information to the second calculation circuit 60.

[0119] The second calculation circuit 60 can receive first synchronization information from the first synchronization transmission sub-circuit 403, and can extract the first target quantity from the first synchronization information. The second calculation circuit 60 can be configured with a first preset data granularity. Combining the first target quantity and the first preset data granularity, the second calculation circuit 60 can determine the size of the area occupied by the added sub-result data in the memory 20 within the first calculation result data. Furthermore, when the first calculation sub-circuit 401 performs multiple first calculations, it performs the first calculations in a certain order. Figure 2-2For example, the first calculation sub-circuit 401 can sequentially obtain P11, P12, P21, and P22 through the first calculation. Combining the calculation order of the first calculation sub-circuit 401 and the size of the area occupied by the sub-result data added to the memory 20 in the first calculation result data, the second calculation circuit 60 can deduce which specific sub-result data has been added to the memory 20. Based on this, the second calculation circuit 60 can determine whether a sub-result data required for a second calculation has been added to the memory 20. If a sub-result data required for a second calculation has been added to the memory 20, the second calculation circuit 60 can perform a second calculation on the sub-result data required for a second calculation to complete a second subtask.

[0120] In the embodiments of this disclosure, since the first synchronization information includes the first target quantity, and combined with the first target quantity in the first synchronization information and the first preset data granularity configured in the second calculation circuit 60, the second calculation circuit 60 can efficiently and reliably infer the addition of sub-result data in the memory 20. Thus, it can accurately identify the situation where a new sub-result data required for a second calculation is added to the memory 20, and promptly execute a second sub-task in response to the situation, which is beneficial to shorten the overall calculation time and improve the overall calculation efficiency.

[0121] In some optional examples, such as Figure 3-2 As shown, the first computing circuit 40 may include a first computing sub-circuit 401 and a first synchronization receiving sub-circuit 405;

[0122] The first calculation circuit 40 is used to perform multiple first calculations sequentially on the data to be calculated, and may include:

[0123] The first calculation sub-circuit 401 is used to perform multiple first calculations sequentially on the data to be calculated.

[0124] The first computing circuit 40 is further configured to determine, based on the second synchronization information, the free storage space information of the memory 20; determine the free storage space information of the memory 20; and, based on the free storage space information and the free storage space information, determine whether to suspend the first computing, which may include:

[0125] The first synchronization receiving sub-circuit 405 is used to determine the freeable storage space information of the memory 20 based on the second synchronization information; determine the free storage space information of the memory 20; and determine whether to control the first calculation sub-circuit 401 to stop the first calculation based on the freeable storage space information and the free storage space information.

[0126] Optionally, the first calculation sub-circuit 401 may be a circuit in the first calculation circuit 40 that supports the first calculation, and the first synchronization receiving sub-circuit 405 may be a circuit in the first calculation circuit 40 used to communicate with the first calculation sub-circuit 401 and the second calculation circuit 60 respectively. Specifically, the first synchronization receiving sub-circuit 405 may be electrically connected to the second calculation circuit 60 to receive information sent by the second calculation circuit 60; the first synchronization receiving sub-circuit 405 may also be electrically connected to the first calculation sub-circuit 401 to control the first calculation sub-circuit 401. Furthermore, the first calculation sub-circuit 401 may be electrically connected to the memory 20, and the second calculation circuit 60 may also be electrically connected to the memory 20.

[0127] In embodiments of this disclosure, the first calculation sub-circuit 401 can sequentially perform multiple first calculations on the data to be calculated. In response to generating sub-result data for one first calculation, the first calculation sub-circuit 401 can not only store the sub-result data for one first calculation in the memory 20, but also determine the dimensional information of the sub-result data for one first calculation. Optionally, the first calculation circuit 401 may further include... Figure 3-1 The first synchronous transmission sub-circuit 403 shown can send dimension information to the first calculation sub-circuit 401. Combining the dimension information and the first preset data granularity, the first synchronous transmission sub-circuit 403 can determine whether new sub-result data satisfying the first preset synchronization condition has been added to the memory 20. If new sub-result data satisfying the first preset synchronization condition has been added to the memory 20, the first synchronous transmission sub-circuit 403 can generate first synchronization information and send the first synchronization information to the second calculation circuit 60.

[0128] The second calculation circuit 60 can, in response to the first synchronization information, determine the sub-result data required for adding a second calculation in the memory 20, and perform a second calculation on the sub-result data required for the second calculation. If the sub-result data in the memory 20 that meets the second preset synchronization condition conforms to the target relationship with the second calculation (i.e., each sub-result data in these sub-result data may be data that was last used in the second calculation, or may be data that is not needed by the second calculation), the second calculation circuit 60 can generate the second synchronization information and send the second synchronization information to the first synchronization receiving sub-circuit 405.

[0129] The first synchronization receiving sub-circuit 405 can receive second synchronization information from the second computing circuit 60, and based on the second synchronization information, determine the freeable storage space information of the memory 20. The first synchronization receiving sub-circuit 405 can also determine the free storage space information of the memory 20. The meanings of the freeable storage space information and the free storage space information are as described above and will not be repeated here. The first synchronization receiving sub-circuit 405 can combine the freeable storage space information and the free storage space information to determine the available storage space capacity of the memory 20. By comparing the available storage space capacity with the preset storage space capacity, it can be determined whether there is sufficient space in the memory 20 to store the sub-result data to be generated. If there is sufficient space in the memory 20 to store the sub-result data to be generated, the first synchronization receiving sub-circuit 405 can send a first control signal to the first computing sub-circuit 401 to control the first computing sub-circuit 401 to continue the first calculation. If there is insufficient space in memory 20 to store the sub-result data to be generated, the first synchronization receiving sub-circuit 405 can send a second control signal to the first calculation sub-circuit 401 to control the first calculation sub-circuit 401 to suspend the first calculation. Here, the first control signal can be, for example, a high-level signal, and the second control signal can be, for example, a low-level signal.

[0130] In the embodiments of this disclosure, the state of the first calculation sub-circuit 401 can be flexibly controlled by the first synchronization receiving sub-circuit 405. When there is sufficient space in the memory 20 to store the sub-result data to be generated, the first calculation sub-circuit 401 maintains the calculation state. When there is insufficient space in the memory 20 to store the sub-result data to be generated, the first calculation sub-circuit 401 exits the calculation state. This effectively avoids the sub-result data that is already in the memory 20 and has not been used by the second calculation circuit 60 from being overwritten, avoids calculation errors in the second calculation circuit 60, and helps to ensure the correct calculation of the second calculation circuit 60.

[0131] In some optional examples, such as Figure 4 As shown, the second computing circuit 60 may include a second computing sub-circuit 601, a second synchronous receiving sub-circuit 603, and a second synchronous transmitting sub-circuit 605;

[0132] The second calculation circuit 60 is configured to, in response to determining, based on the first synchronization information, the sub-result data required for adding a second calculation to the memory 20, and perform a second calculation on the sub-result data required for the second calculation; and to generate second synchronization information in response to the sub-result data in the memory 20 that meets the second preset synchronization condition and the second calculation conforming to the target relationship, which may include:

[0133] The second synchronization receiving sub-circuit 603 is used to respond to determining, based on the first synchronization information, that a new sub-result data required for a second calculation is added to the memory 20, and to control the second calculation sub-circuit 601 to perform a second calculation on the sub-result data required for a second calculation.

[0134] The second calculation sub-circuit 601 is used to generate calculation completion information corresponding to the target sub-result data in response to the fact that the target sub-result data in the sub-result data required for a second calculation has been used for the second calculation for the last time.

[0135] The second synchronization transmission sub-circuit 605 is used to determine, in response to the calculation completion information and the second preset data granularity, the sub-result data in the memory 20 that meets the second preset synchronization condition and the second calculation conforms to the target relationship, and generate the second synchronization information.

[0136] Optionally, the second computing sub-circuit 601 can be a circuit in the second computing circuit 60 that supports the second computing; the second synchronous receiving sub-circuit 603 can be a sub-circuit in the second computing circuit 60 used to communicate with the second computing sub-circuit 601 and the first computing circuit 40 respectively; and the second synchronous transmitting sub-circuit 605 can be a sub-circuit in the second computing circuit 60 used to communicate with the second computing sub-circuit 601 and the first computing circuit 40 respectively. Specifically, the second synchronous receiving sub-circuit 603 can be electrically connected to the first computing circuit 40 to receive information sent by the first computing circuit 40, and can also be electrically connected to the second computing sub-circuit 601 to control the second computing sub-circuit 601; the second synchronous transmitting sub-circuit 605 can be electrically connected to the second computing sub-circuit 601 to receive information sent by the second computing sub-circuit 601, and can also be electrically connected to the first computing circuit 40 to send information to the first computing circuit 40.

[0137] Optionally, the second preset data granularity can be a pre-defined data granularity used to characterize the finer granularity of the data. Specific examples of the second preset data granularity can be found in the description of the first preset data granularity above, and will not be repeated here. It should be noted that the second preset data granularity can be the same as or a different data granularity from the first preset data granularity mentioned above.

[0138] In the embodiments of this disclosure, the second synchronization receiving sub-circuit 603 can receive first synchronization information from the first calculation circuit 40, and based on the first synchronization information, determine whether a new sub-result data required for a second calculation has been added to the memory 20. If a new sub-result data required for a second calculation has been added to the memory 20, the second synchronization receiving sub-circuit 603 can send a third control signal to the second calculation sub-circuit 601 to control the second calculation sub-circuit 601 to perform a second calculation. If no new sub-result data required for a second calculation has been added to the memory 20, the second synchronization receiving sub-circuit 603 can send a fourth control signal to the second calculation sub-circuit 601 to control the second calculation sub-circuit 601 to temporarily suspend the second calculation. Here, the third control signal can be, for example, a high-level signal, and the fourth control signal can be, for example, a low-level signal.

[0139] The second computation sub-circuit 601 can generate computation completion information corresponding to the target sub-result data in response to the fact that the target sub-result data in the sub-result data required for a second computation has been used for the second computation for the last time. Here, the meaning of "the target sub-result data has been used for the second computation for the last time" is explained in the relevant examples above and will not be repeated here. The target sub-result data may be all the sub-result data in the sub-result data required for a second computation, or it may be a portion of the sub-result data in the sub-result data required for a second computation. The computation completion information corresponding to the target sub-result data can indicate that all the second computations requiring the target sub-result data have been completed; that is, the target sub-result data is the sub-result data that the second computation circuit 60 has finished using. Optionally, the computation completion information may include the dimension information of the target sub-result data. The second computation sub-circuit 601 can send the computation completion information to the second synchronous transmission sub-circuit 605.

[0140] The second synchronization transmission subcircuit 605 can receive computation completion information from the second calculation subcircuit 601. Since there is a correspondence between the computation completion information and the target sub-result data, based on this correspondence, the second synchronization transmission subcircuit 605 can infer which sub-result data in the memory 20 has been last used in the second calculation. Furthermore, the second synchronization transmission subcircuit 605 can be pre-configured with a second preset data granularity, and the second preset synchronization condition can be associated with the second preset data granularity. For example, the second preset synchronization condition can be: having the second preset data granularity, or it can be: the data volume is a preset multiple of the second preset data granularity. Combining the computation completion information and the second preset data granularity, the second synchronization transmission subcircuit 605 can determine whether there is sub-result data in the memory 20 that satisfies the second preset synchronization condition and conforms to the target relationship of the second calculation. If there is sub-result data in the memory 20 that satisfies the second preset synchronization condition and conforms to the target relationship of the second calculation, the second synchronization transmission subcircuit 605 can generate second synchronization information and send the second synchronization information to the first calculation circuit 40.

[0141] The first calculation circuit 40 can receive the second synchronization information from the second synchronization transmission sub-circuit 605, and based on the second synchronization information, determine the releasable storage space capacity of the memory 20. Combined with the free storage space capacity of the memory 20, the first calculation circuit 40 can determine whether to suspend the first calculation.

[0142] In the embodiments of this disclosure, the second synchronization receiving sub-circuit 603 can receive the first synchronization information, thereby reasonably determining the timing for controlling the second calculation sub-circuit 601 to perform various second calculations (i.e., the timing for executing each second sub-task). The second calculation sub-circuit 601 can also generate calculation completion information and transmit it to the second synchronization transmitting sub-circuit 605. In this way, combining the calculation completion information and the second preset data granularity, the second synchronization transmitting sub-circuit 605 can perform relevant condition judgments (e.g., judging whether there is sub-result data that meets the second preset synchronization conditions and conforms to the target relationship with the second calculation). If the judgment result is that there is, the second synchronization information can be generated for the first calculation circuit 40, so that the first calculation circuit 40 can judge whether it is necessary to suspend the first calculation (i.e., whether to suspend the execution of the first sub-task). Thus, through the coordinated operation of the second calculation sub-circuit 601, the second synchronous receiving sub-circuit 603, the second synchronous transmitting sub-circuit 605, the memory 20, and the first calculation circuit 40, a certain degree of parallelism can be achieved between the first subtask and the second subtask, which helps to shorten the overall calculation time and improve the overall calculation efficiency. At the same time, it can prevent the sub-result data that is already in the memory 20 and has not been used by the second calculation circuit 60 from being overwritten, thereby avoiding calculation errors in the second calculation circuit 60 and ensuring the correct calculation of the second calculation circuit 60.

[0143] In some optional examples, the second synchronization transmission sub-circuit 605 is used to determine, in response to computation completion information and a second preset data granularity, the sub-result data in the memory 20 that satisfies the second preset synchronization condition and the second computation conforms to the target relationship, and to generate second synchronization information, which may include:

[0144] The second synchronous transmission sub-circuit 605 is used to respond to the calculation completion information, determine the sub-result data in the memory 20, which includes the second target number of second preset data granularities, and the second calculation conforms to the target relationship, and generate second synchronization information including the second target number.

[0145] The first computing circuit 40 is also used to determine the freeable storage space information of the memory 20 based on the second synchronization information, which may include:

[0146] The first computing circuit 40 is used to obtain the second target quantity from the second synchronization information; and based on the second target quantity and the second preset data granularity, to determine the releasable storage space information of the memory 20.

[0147] Optionally, the second preset synchronization condition can be: the data volume is a multiple of the second target quantity of the second preset data granularity. The second target quantity can be a fixed quantity or a quantity that can change periodically. For details, please refer to the relevant introduction of the first target quantity above, which will not be repeated here.

[0148] In the embodiments of this disclosure, based on the calculation completion information from the second calculation sub-circuit 601, the second synchronization transmission sub-circuit 605 can infer which sub-result data in the memory 20 has been last used in the second calculation. This allows it to determine whether there is sub-result data in the memory 20 containing a second target number of second preset data granularities that matches the target relationship of the second calculation. In an optional example, the second preset data granularity is 1 pixel, and the second target number is 4. If sub-result data containing the color values ​​of 4 pixels has been last used in the second calculation in the memory 20 recently, the second synchronization transmission sub-circuit 605 can generate second synchronization information including the second target number of 4 pixels and send the second synchronization information to the first calculation circuit 40.

[0149] The first calculation circuit 40 can receive second synchronization information from the second synchronization transmission sub-circuit 605, and can extract the second target quantity from the second synchronization information. The first calculation circuit 40 can be pre-configured with a second preset data granularity. Based on the second target quantity and the second preset data granularity, the first calculation circuit 40 can determine the releasable storage space information of the memory 20. Taking the case where the second preset data granularity is 1 pixel and the second target quantity is 4 as an example, combining the second target quantity and the second preset data granularity, the first calculation circuit 40 can infer that sub-result data including the color values ​​of 4 pixels has been used for the second calculation for the last time in a recent period. Furthermore, similar to the description of the first calculation sub-circuit 401 above, the second calculation sub-circuit 601 also typically performs the second calculation in a certain order. Therefore, by referring to the calculation order of the second calculation sub-circuit 601, the first calculation circuit 40 can deduce which part of the sub-result data, including the color values ​​of the four pixels, is in the memory 20. The space occupied by this part of the sub-result data in the memory 20 can be considered as a releasable space, thereby determining the releasable storage space information of the memory 20.

[0150] In the embodiments of this disclosure, the second synchronization information includes a second target quantity. Combining the second target quantity in the second synchronization information with the second preset data granularity configured in the first computing circuit 40, the first computing circuit 40 can efficiently and reliably infer the releasable storage space information of the memory 20.

[0151] In some optional examples, such as Figure 5 As shown, the computing device may include a memory 20, a first computing circuit 40, and a second computing circuit 60. The first computing circuit 40 may include a first computing sub-circuit 401, a first synchronous transmission sub-circuit 403, and a first synchronous reception sub-circuit 405. The second computing circuit 60 may include a second computing sub-circuit 601, a second synchronous reception sub-circuit 603, and a second synchronous transmission sub-circuit 605. The first computing sub-circuit 401 may be electrically connected to the first synchronous transmission sub-circuit 403, the first synchronous reception sub-circuit 405, and the memory 20, respectively. The second computing sub-circuit 601 may be electrically connected to the second synchronous reception sub-circuit 603, the second synchronous transmission sub-circuit 605, and the memory 20, respectively. The second synchronous reception sub-circuit 603 may be electrically connected to the first synchronous transmission sub-circuit 403, and the first synchronous reception circuit 405 may be electrically connected to the second synchronous transmission circuit 605.

[0152] In specific implementation, the first calculation sub-circuit 401 can sequentially perform multiple first calculations on the data to be calculated; in response to generating a sub-result data of a first calculation, it stores the sub-result data of a first calculation in the memory 20; it determines the dimension information of the sub-result data of a first calculation and sends the dimension information to the first synchronous transmission sub-circuit 403.

[0153] The first synchronous transmission sub-circuit 403 can determine whether new sub-result data satisfying the first preset synchronization condition has been added to the memory 20 based on dimension information and the first preset data granularity. If new sub-result data satisfying the first preset synchronization condition has been added to the memory 20, the first synchronous transmission sub-circuit 403 can generate first synchronization information and send the first synchronization information to the second synchronous receiving sub-circuit 603.

[0154] The second synchronization receiving sub-circuit 603 can receive the first synchronization information and, based on the first synchronization information, determine whether a new sub-result data required for the second calculation has been added to the memory 20. If a new sub-result data required for the second calculation has been added to the memory 20, the second synchronization receiving sub-circuit 603 can control the second calculation sub-circuit 601 to perform a second calculation on the sub-result data required for the second calculation. In response to the fact that the target sub-result data in the sub-result data required for the second calculation has been used for the second calculation for the last time, the second calculation sub-circuit 601 can generate calculation completion information corresponding to the target sub-result data and send the calculation completion information to the second synchronization transmitting sub-circuit 605.

[0155] The second synchronous transmission sub-circuit 605 can receive calculation completion information and, based on the calculation completion information and the second preset data granularity, determine whether there is sub-result data in the memory 20 that meets the second preset synchronization condition and conforms to the target relationship of the second calculation. If there is sub-result data in the memory 20 that meets the second preset synchronization condition and conforms to the target relationship of the second calculation, the second synchronous transmission sub-circuit 605 can generate second synchronization information and send the second synchronization information to the first synchronous receiving sub-circuit 405.

[0156] The first synchronization receiving sub-circuit 405 can receive the second synchronization information and, based on the second synchronization information, determine the freeable storage space information of the memory 20. Combined with the free storage space information of the memory 20, the second synchronization receiving sub-circuit 603 can determine the available storage space capacity of the memory 20. Based on the available storage space capacity of the memory 20, the second synchronization receiving sub-circuit 603 can determine whether to control the first calculation sub-circuit 401 to suspend the first calculation.

[0157] Optionally, the number of first computing circuits 40 in the computing device can be configured according to actual conditions, the number of second computing circuits 60 in the computing device can also be configured according to actual conditions, and the first preset data granularity, the second preset data granularity, the first preset synchronization condition, and the second preset synchronization condition can also be configured according to actual conditions.

[0158] In some embodiments, certain types of second calculations may require multiple first calculation circuits 40 to provide input. For example, if the second calculation is a point-to-point elementwise calculation, and a second calculation performed by the second calculation circuit 60 requires the use of sub-result data generated by the two first calculation circuits 40 respectively, then the second calculation circuit 60 will only use the sub-result data stored in the memory 20 after both of the sub-result data generated by the two first calculation circuits 40 are stored in the memory 20.

[0159] In some embodiments, the first computing circuit 40 may need to provide input to multiple second computing circuits 60. In this case, for a certain sub-result data in the memory 20, the space where the sub-result data is located can only be released (i.e. used to store other sub-result data) after all multiple second computing circuits 60 no longer need to use the sub-result data.

[0160] In some optional examples, such as Figure 6 As shown, for scenarios requiring the sequential execution of three calculations (engine1, engine2, and engine3), the calculation task corresponding to engine1 can be decomposed into multiple first subtasks, the calculation task corresponding to engine2 into multiple second subtasks, and the calculation task corresponding to engine3 into multiple third subtasks. Once several first subtasks are executed (the inputs required for each first subtask can be represented as do and d1), the storage system will have additional sub-result data (represented as d2) needed to execute a second subtask, and so on, once several second subtasks are executed, the storage system will have additional sub-result data (represented as d3) needed to execute a third subtask, and so on, and so on. This allows for a certain degree of parallelism between different types of subtasks, which helps to shorten the overall computation time and improve overall computational efficiency. Here, the storage system may include at least one memory 20 as described above.

[0161] In summary, the embodiments of this disclosure can solve the data dependency problem by synchronizing information between computing circuits, enabling simultaneous computation by different computing circuits, thereby shortening the overall computation time, improving the overall computation efficiency, significantly reducing computation latency, saving storage space, and improving the utilization rate of storage space.

[0162] Exemplary methods

[0163] Embodiments of this disclosure also provide an information processing method based on a computing device. The computing device may include a memory, a first computing circuit, and a second computing circuit. Specific implementations of the computing device are described in the above-described device embodiments section and will not be repeated here. Figure 7 As shown, information processing methods based on computing devices may include:

[0164] Step 710: The first calculation circuit performs multiple first calculations on the data to be calculated in sequence.

[0165] Step 720: In response to the first computing circuit generating a sub-result data of a first calculation, the first computing circuit stores the sub-result data of the first calculation in the memory.

[0166] Step 730: In response to the addition of sub-result data that meets the first preset synchronization condition in the memory, the first synchronization information is generated by the first calculation circuit;

[0167] Step 740: In response to determining, based on the first synchronization information, the sub-result data required for adding a second calculation in the memory is added, and a second calculation is performed on the sub-result data required for the second calculation through the second calculation circuit;

[0168] Step 750: In response to the sub-result data in the memory that satisfies the second preset synchronization condition and conforms to the target relationship with the second calculation, the second calculation circuit generates second synchronization information; wherein, any sub-result data conforming to the target relationship with the second calculation means that: the sub-result data has been used for the second calculation for the last time; or, the sub-result data belongs to data outside the calculation scope of the second calculation.

[0169] Step 760: Based on the second synchronization information, determine the releasable storage space information of the memory through the first calculation circuit;

[0170] Step 770: Determine the free storage space information of the memory through the first calculation circuit;

[0171] Step 780: Based on the information on releasable storage space and free storage space, determine whether to terminate the first calculation through the first calculation circuit.

[0172] In some optional examples, such as Figure 8 As shown, step 780 includes:

[0173] Step 810: Determine the capacity of the freeable storage space of the memory based on the freeable storage space information;

[0174] Step 820: Determine the free storage space capacity of the memory based on the free storage space information;

[0175] Step 830: Determine the available storage space capacity of the memory based on the free storage space capacity and the free storage space capacity;

[0176] Step 840: Based on the available storage space capacity, determine whether to suspend the first calculation through the first computing circuit.

[0177] In some alternative examples, the first computing circuit includes a first computing sub-circuit and a first synchronous transmission sub-circuit;

[0178] like Figure 9 As shown, step 710 includes:

[0179] Step 910: The first calculation sub-circuit performs multiple first calculations on the data to be calculated in sequence;

[0180] Step 720 includes:

[0181] Step 920: In response to the first calculation sub-circuit generating a sub-result data of a first calculation, the first calculation sub-circuit stores the sub-result data of the first calculation in the memory;

[0182] Step 730 includes:

[0183] Step 930: In response to the first computing sub-circuit generating a sub-result data of a first calculation, the dimension information of the sub-result data of the first calculation is determined by the first computing sub-circuit.

[0184] Step 940: In response to determining the newly added sub-result data in the memory that meets the first preset synchronization condition based on dimensional information and the first preset data granularity, the first synchronization information is generated through the first synchronization transmission sub-circuit.

[0185] In some optional examples, such as Figure 10 As shown, step 940 includes:

[0186] Step 1010: In response to determining, based on dimension information, that the newly added sub-result data in the memory includes a first target number of first preset data granularities, first synchronization information including the first target number is generated through the first synchronization transmission sub-circuit.

[0187] Step 740 includes:

[0188] Step 1020: Obtain the first target quantity from the first synchronization information;

[0189] Step 1030: In response to determining the sub-result data required for adding a second calculation in the memory based on the first target quantity and the first preset data granularity, a second calculation is performed on the sub-result data required for the second calculation through the second calculation circuit.

[0190] In some alternative examples, the first computing circuit includes a first computing sub-circuit and a first synchronization receiving sub-circuit;

[0191] like Figure 11 As shown, step 710 includes:

[0192] Step 1110: The first calculation sub-circuit performs multiple first calculations on the data to be calculated in sequence;

[0193] Step 760 includes:

[0194] Step 1120: Based on the second synchronization information, determine the releasable storage space information of the memory through the first synchronization receiving sub-circuit;

[0195] Step 780 includes:

[0196] Step 1130: Determine the free storage space information of the memory through the first synchronous receiving sub-circuit;

[0197] Step 1140: Based on the information on releasable storage space and free storage space, determine whether to control the first calculation sub-circuit to suspend the first calculation through the first synchronization receiving sub-circuit.

[0198] In some alternative examples, the second computing circuit includes a second computing sub-circuit, a second synchronous receiving sub-circuit, and a second synchronous transmitting sub-circuit;

[0199] like Figure 12 As shown, step 740 includes:

[0200] Step 1210: In response to determining the sub-result data required for adding a second calculation in the memory based on the first synchronization information through the second synchronization receiving sub-circuit, the second calculation sub-circuit is controlled to perform a second calculation on the sub-result data required for the second calculation through the second synchronization receiving sub-circuit.

[0201] Step 750 includes:

[0202] Step 1220: In response to the fact that the target sub-result data in the sub-result data required for a second calculation has been used for the second calculation for the last time, calculation completion information corresponding to the target sub-result data is generated;

[0203] Step 1230: In response to the calculation completion information and the second preset data granularity, the second synchronous transmission sub-circuit determines the sub-result data in the memory that meets the second preset synchronization condition and the second calculation conforms to the target relationship, and generates the second synchronization information through the second synchronous transmission sub-circuit.

[0204] In some optional examples, such as Figure 13 As shown, step 1230 includes:

[0205] Step 1310: In response to the calculation completion information, the second synchronous transmission sub-circuit determines that the sub-result data in the memory, which includes the second target number of second preset data granularities, conforms to the target relationship with the second calculation, and generates second synchronization information including the second target number through the second synchronous transmission sub-circuit.

[0206] Step 760 includes:

[0207] Step 1320: Obtain the second target quantity from the second synchronization information;

[0208] Step 1330: Based on the second target quantity and the second preset data granularity, the releasable storage space information of the memory is determined by the first calculation circuit.

[0209] In the methods disclosed herein, the various optional embodiments, optional implementation methods and optional examples disclosed in the above exemplary device section can be flexibly selected and combined as needed to achieve the corresponding functions and effects, and this disclosure does not list them all.

[0210] The beneficial technical effects corresponding to the exemplary embodiments of this method can be found in the corresponding beneficial technical effects of the exemplary device section above, and will not be repeated here.

[0211] Exemplary electronic devices

[0212] Figure 14 The illustration shows a block diagram of an electronic device according to an embodiment of the present disclosure. The electronic device 1400 includes one or more processors 1410 and memory 1420.

[0213] The processor 1410 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 1400 to perform desired functions.

[0214] The memory 1420 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1410 may execute one or more computer program instructions to implement the methods of the various embodiments of this disclosure described above and / or other desired functions.

[0215] In one example, electronic device 1400 may further include input device 1430 and output device 1440, these components being interconnected via a bus system and / or other forms of connection mechanism (not shown). Input device 1430 may also include, for example, a keyboard, mouse, etc. Output device 1440 may output various information to the outside, and may include, for example, a display, speaker, printer, and communication network and its connected remote output devices, etc.

[0216] Of course, for the sake of simplicity, Figure 14 Only some of the components of the electronic device 1400 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 1400 may include any other suitable components depending on the specific application.

[0217] Exemplary computer program products and computer-readable storage media

[0218] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0219] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0220] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the methods according to various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0221] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0222] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. The specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the specific details described above.

[0223] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A computing device, comprising: Memory, first computing circuit, and second computing circuit; The first computing circuit is used to perform multiple first calculations sequentially on the data to be calculated; In response to generating a sub-result data of a first calculation, the sub-result data of the first calculation is stored in the memory; in response to adding sub-result data that meets a first preset synchronization condition to the memory, first synchronization information is generated. The second calculation circuit is configured to, in response to the first synchronization information, determine the sub-result data required for adding a second calculation in the memory, and perform a second calculation on the sub-result data required for the second calculation; and generate second synchronization information in response to the sub-result data in the memory that meets the second preset synchronization condition and conforms to the target relationship with the second calculation; wherein, any sub-result data conforming to the target relationship with the second calculation means that: any sub-result data has been used for the second calculation for the last time; or, any sub-result data belongs to data outside the calculation scope of the second calculation; The first computing circuit is further configured to determine, based on the second synchronization information, the releasable storage space information of the memory; determine the free storage space information of the memory; and, based on the releasable storage space information and the free storage space information, determine whether to terminate the first computing.

2. The apparatus according to claim 1, wherein, The first computing circuit is used to determine whether to suspend the first computing based on the releasable storage space information and the free storage space information, including: The first computing circuit is used to determine the free storage space capacity of the memory based on the free storage space information; to determine the free storage space capacity of the memory based on the free storage space information; to determine the available storage space capacity of the memory based on the free storage space capacity and the free storage space capacity; and to determine whether to suspend the first calculation based on the available storage space capacity.

3. The apparatus according to claim 1, wherein, The first computing circuit includes: a first computing sub-circuit and a first synchronous transmission sub-circuit; The first computing circuit is used to sequentially perform multiple first calculations on the data to be calculated; in response to generating sub-result data of a first calculation, it stores the sub-result data of the first calculation in the memory; in response to adding sub-result data that meets a first preset synchronization condition to the memory, it generates first synchronization information, including: The first calculation sub-circuit is used to sequentially perform multiple first calculations on the data to be calculated; in response to generating a sub-result data of a first calculation, the sub-result data of the first calculation is stored in the memory; and the dimension information of the sub-result data of the first calculation is determined. The first synchronization transmission sub-circuit is used to determine, based on the dimension information and the first preset data granularity, newly added sub-result data that meets the first preset synchronization condition in the memory, and generate first synchronization information.

4. The apparatus according to claim 3, wherein, The first synchronization transmission sub-circuit is used to respond to determining, based on the dimension information and the first preset data granularity, newly added sub-result data satisfying the first preset synchronization condition in the memory, and generating first synchronization information, including: The first synchronous transmission sub-circuit is used to respond to determining, based on the dimension information, that the memory has newly added sub-result data including a first target number of first preset data granularities, and to generate first synchronization information including the first target number; The second calculation circuit is configured to, in response to the first synchronization information, determine sub-result data required for adding a second calculation to the memory, and perform a second calculation on the sub-result data required for the second calculation, including: The second calculation circuit is used to obtain the first target quantity from the first synchronization information; in response to determining the sub-result data required for adding a second calculation in the memory based on the first target quantity and the first preset data granularity, a second calculation is performed on the sub-result data required for the second calculation.

5. The apparatus according to claim 1, wherein, The first computing circuit includes: a first computing sub-circuit and a first synchronization receiving sub-circuit; The first computing circuit is used to perform multiple first calculations sequentially on the data to be calculated, including: The first calculation sub-circuit is used to perform multiple first calculations sequentially on the data to be calculated; The first computing circuit is further configured to determine, based on the second synchronization information, the free storage space information of the memory; determine the free storage space information of the memory; and, based on the free storage space information and the free storage space information, determine whether to suspend the first calculation, including: The first synchronization receiving sub-circuit is used to determine the free storage space information of the memory based on the second synchronization information; determine the free storage space information of the memory; and determine whether to control the first calculation sub-circuit to suspend the first calculation based on the free storage space information and the free storage space information.

6. The apparatus according to claim 1, wherein, The second computing circuit includes: a second computing sub-circuit, a second synchronous receiving sub-circuit, and a second synchronous transmitting sub-circuit; The second calculation circuit is configured to, in response to the first synchronization information, determine the sub-result data required for adding a second calculation in the memory, and perform a second calculation on the sub-result data required for the second calculation; and, in response to the sub-result data in the memory that satisfies a second preset synchronization condition and the second calculation conforming to a target relationship, generate second synchronization information, including: The second synchronization receiving sub-circuit is used to respond to determining, based on the first synchronization information, that a new item of sub-result data required for the second calculation has been added to the memory, and to control the second calculation sub-circuit to perform a second calculation on the item of sub-result data required for the second calculation; The second calculation sub-circuit is used to generate calculation completion information corresponding to the target sub-result data in response to the fact that the target sub-result data in the sub-result data required for the second calculation has been used for the second calculation for the last time; The second synchronization transmission sub-circuit is used to determine, in response to the calculation completion information and the second preset data granularity, whether the sub-result data in the memory that satisfies the second preset synchronization condition conforms to the target relationship with the second calculation, and to generate the second synchronization information.

7. The apparatus according to claim 6, wherein, The second synchronization transmission sub-circuit is used to, in response to the calculation completion information and the second preset data granularity, determine that the sub-result data in the memory that satisfies the second preset synchronization condition conforms to the target relationship with the second calculation, and generate second synchronization information, including: The second synchronous transmission sub-circuit is used to respond to the calculation completion information, determine that the sub-result data in the memory, which includes a second target number of data with a second preset data granularity, conforms to the target relationship with the second calculation, and generate second synchronization information including the second target number; The first computing circuit is further configured to determine the freeable storage space information of the memory based on the second synchronization information, including: The first computing circuit is used to obtain the second target quantity from the second synchronization information; and to determine the releasable storage space information of the memory based on the second target quantity and the second preset data granularity.

8. An information processing method based on a computing device, the computing device comprising: The method includes a memory, a first computing circuit, and a second computing circuit, comprising: The first computing circuit performs multiple first calculations on the data to be calculated in sequence. In response to the first computing circuit generating a sub-result data of a first calculation, the first computing circuit stores the sub-result data of the first calculation in the memory; In response to the addition of sub-result data that meets the first preset synchronization condition in the memory, the first calculation circuit generates first synchronization information. In response to determining, based on the first synchronization information, that sub-result data required for adding a second calculation to the memory is added, a second calculation is performed on the sub-result data required for the second calculation through the second calculation circuit; In response to the sub-result data in the memory that satisfies the second preset synchronization condition and conforms to the target relationship with the second calculation, the second calculation circuit generates second synchronization information; wherein, any sub-result data conforming to the target relationship with the second calculation means that: any sub-result data has been used for the second calculation for the last time; or, any sub-result data belongs to data outside the calculation scope of the second calculation; Based on the second synchronization information, the releasable storage space information of the memory is determined by the first calculation circuit; The free storage space information of the memory is determined by the first computing circuit; Based on the releasable storage space information and the free storage space information, the first computing circuit determines whether to suspend the first calculation.

9. A computer-readable storage medium storing a computer program that is executed by a processor to perform the method of claim 8.

10. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the method of claim 8.

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