An artificial intelligence-assisted wiring method and apparatus
By employing an AI-assisted routing method, utilizing global design rule detection and solver optimization of routing paths, the problem of clearing design rule violations during the routing process is solved, achieving more efficient routing resource allocation and path optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI BANXIN TECH CO LTD
- Filing Date
- 2025-08-19
- Publication Date
- 2026-06-05
AI Technical Summary
Existing routing methods face challenges in clearing design rule violations, including congestion caused by relying on fixed network ordering, heuristic algorithms blocking other network paths, and inconsistent cost parameters.
An AI-assisted approach is used to detect global design rule violations by obtaining the initial routing path, generate multiple optional routing paths, and use a preset solver to resolve conflicts and connectivity constraints to determine the target routing path.
It effectively solves the problem of clearing design rule violations, improves the efficiency of the cabling process and the rationality of resource allocation, and avoids the dependence on specific network ordering and parameter tuning processes.
Smart Images
Figure CN120930587B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, specifically to an artificial intelligence-assisted wiring method. This application also relates to artificial intelligence-assisted wiring apparatus, electronic devices, and computer-readable storage media. Background Technology
[0002] Very Large Scale Integration (VLSI) is a technology that integrates millions of electronic components (transistors, capacitors, resistors, etc.) onto a single chip. VLSI physical design is the process of translating the logic design of a circuit into its actual geometric layout, enabling a factory to manufacture it on a semiconductor wafer. The VLSI physical design process is divided into several sub-steps, including placement, clock network design, timing optimization, and routing.
[0003] In the field of cabling, during the cabling process, all pins in each net must be connected by wires, and short circuits and open circuits between wires of different nets must be avoided. At the same time, multiple objectives need to be optimized while meeting many complex physical design rules. Optimization objectives include total wire length, number of vias, timing critical path length, etc.
[0004] Existing routing methods all suffer from the Design Rule Violation Cleanup Challenge, specifically as follows: Some routing methods rely on a fixed order of all networks to be routed and perform routing according to this fixed order. This method makes it easier for networks that are routed first to obtain critical routing resources, thus making it easier for networks that are routed later to become congested, leading to an unsolvable global routing problem. Some routing methods use heuristic algorithms (such as simulated annealing, genetic algorithms, etc.) during the routing process. This method may block the necessary paths of other networks while providing routing resources for one network. Some routing methods rely on the transformation parameter (cost parameter) from Design Rule Violation (DRV) to path cost. This parameter largely determines the effectiveness of the algorithm, and the applicable cost parameter may be inconsistent for different layout designs. Summary of the Invention
[0005] This invention provides an artificial intelligence-assisted wiring method, apparatus, electronic device, and computer-readable storage medium to solve the problem that existing wiring methods cannot effectively address the challenge of clearing design rule violations.
[0006] To solve or partially solve the above-mentioned technical problems, according to one aspect of the present invention, an artificial intelligence-assisted wiring method is provided, comprising:
[0007] Obtain the initial cabling path for each network to be cabled;
[0008] The initial routing path is subjected to global design rule violation detection, and based on the result of the global design rule violation detection, the initial routing path is transformed into multiple optional routing paths of the network to be routed, wherein any of the optional routing paths connects all pins of the network to be routed and avoids violation information;
[0009] For each of the optional routing paths, corresponding conflict constraints and connectivity constraints are generated, and the conflict constraints and connectivity constraints are solved using a preset solver. The optional routing path corresponding to the successfully solved result is determined as the target routing path for the network to be routed.
[0010] In one implementation, obtaining the initial cabling path corresponding to each network to be cabled includes:
[0011] In response to the network to be wired being divided into a partially connected state or an unwired state, an initial wiring path is generated for the network to be wired.
[0012] In one embodiment, obtaining the initial wiring path corresponding to each network to be wired includes: in response to the network to be wired being in a fully connected state, correcting the fully connected network to be wired to obtain the initial wiring path.
[0013] In one implementation, the method further includes: generating corresponding conflict constraints and connectivity constraints for the initial routing path in response to the initial routing path not containing violation information.
[0014] In one implementation, before generating conflict constraints and connectivity constraints for the optional routing paths, the method further includes filtering the optional routing paths.
[0015] In one implementation, the method further includes converting the conflict constraints and connectivity constraints into an input form corresponding to the objective solver.
[0016] In one implementation, the initial routing path is subjected to global design rule violation detection, and based on the result of the global design rule violation detection, the initial routing path is transformed into multiple optional routing paths for the network to be routed, including:
[0017] For each initial cabling path, a global DRC is detected, and the DRC violation identifier is associated with the corresponding initial cabling path; for each initial cabling path with a DRC violation identifier, multiple alternative cabling paths are generated.
[0018] In one implementation, after solving the conflict constraints and connectivity constraints using a preset solver, if the solution fails, the initial routing paths between all networks to be routed are detected.
[0019] According to another aspect of the present invention, an artificial intelligence-assisted wiring device is provided, the device comprising:
[0020] The initial wiring path acquisition unit is used to obtain the initial wiring path corresponding to each network to be wired.
[0021] An optional routing path acquisition unit is used to perform global design rule violation detection on the initial routing path, and transform the initial routing path into multiple optional routing paths of the network to be routed based on the result of the global design rule violation detection, wherein any of the optional routing paths connects all pins of the network to be routed and avoids violation information.
[0022] The target routing path determination unit is used to generate corresponding conflict constraints and connectivity constraints for each of the optional routing paths, and to solve the conflict constraints and connectivity constraints using a preset solver, and to determine the optional routing path corresponding to the successfully solved result as the target routing path of the network to be routed.
[0023] According to another aspect of the present invention, an electronic device is also provided, including a processor and a memory; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the above-described method.
[0024] According to another aspect of the present invention, a computer-readable storage medium is also provided, on which one or more computer instructions are stored, which are executed by a processor to implement the above-described method.
[0025] Compared with the prior art, the present invention has the following advantages:
[0026] The AI-assisted routing method provided by this invention includes: obtaining initial routing paths corresponding to each network to be routed; performing global design rule violation detection on the initial routing paths, and transforming the initial routing paths into multiple optional routing paths for the network to be routed based on the results of the global design rule violation detection, wherein any optional routing path connects all pins of the network to be routed and avoids violation information; generating corresponding conflict constraints and connectivity constraints for each optional routing path, and solving the conflict constraints and connectivity constraints using a preset solver, and determining the optional routing path corresponding to the successfully solved result as the target routing path for the network to be routed. By using this method, the routing problem can be transformed into a logic problem. Specifically, after obtaining the initial routing paths for the networks to be routed, at least one potential optional routing path can be generated for each network to be routed while avoiding all conflicts, and constraints representing a logic reasoning problem can be constructed based on this. The constraints can be solved using a solver through logical reasoning, and the target routing path for the network to be routed can be determined based on the successfully solved result. This routing method transforms the routing problem into a logical problem of the solver. By using the logical solution method, the problems in the routing are considered in a comprehensive manner. It does not rely on a specific network layout, avoids the parameter tuning process, effectively solves the problem of critical routing resource allocation, and makes the routing process more efficient. Attached Figure Description
[0027] Figure 1 This is a flowchart of the AI-assisted wiring method provided in the embodiments of this application;
[0028] Figure 2 This is a unit block diagram of the artificial intelligence-assisted wiring device provided in the embodiments of this application;
[0029] Figure 3 This is a schematic diagram of the logical structure of the electronic device provided in the embodiments of this application. Detailed Implementation
[0030] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.
[0031] To address the need to avoid design rule violations during cabling, this application provides an AI-assisted cabling method, a corresponding AI-assisted cabling device, an electronic device, and a computer-readable storage medium. The following embodiments provide a detailed description of the method, device, electronic device, and computer-readable storage medium.
[0032] The first embodiment of this application provides an artificial intelligence-assisted wiring method, the application subject of which can be a computing device application used to implement wiring. Figure 1 This is a flowchart of the AI-assisted wiring method provided in the first embodiment of this application, which is described below in conjunction with... Figure 1 The method provided in this embodiment will be described in detail. The embodiments described below are used to explain the principle of the method and are not intended to limit actual use.
[0033] like Figure 1 As shown, the AI-assisted wiring method provided in this embodiment includes the following steps:
[0034] S101, obtain the initial cabling path corresponding to each network to be cabled.
[0035] This step is used to obtain the initial routing path corresponding to each network to be routed. Specifically, this process can refer to: when the network to be routed is divided into a partially connected state or an unrouted state, generating an initial routing path for the network to be routed; when the network to be routed is in a fully connected state, modifying the fully connected network to be routed, for example, pruning and optimizing the routing tree of the network to be routed so that there are no cycles, multiple edges, useless points, and useless edges in the routing tree, so as to minimize the use of routing resources in the connected state, and determining the modified routing tree as the initial routing path.
[0036] In this embodiment, when the network to be routed is divided into a partially connected state or an unrouted state, the initial routing path can be generated for the network to be routed in the following way: First, a Rectilinear Steiner Minimal Tree (RSMT) is constructed for the network to be routed. For example, the RC aware tree algorithm is used to construct the RSMT for the network to be routed, so as to minimize the network bus length while ensuring that the path delay from source to sink does not violate timing rules (e.g., setup timing rules and hold timing rules); Second, path search is performed under the guidance of the RSMT (e.g., using Dijkstra's algorithm or A* algorithm for path search) to achieve network connectivity. The path search process needs to avoid the same network design rules, including limiting the minimum connected path length of a layer to avoid minimum area DRC, limiting the path in the same direction before turning during the pathfinding process to not be too short to avoid minimum step DRC, and selecting vias that conform to the rules for metal wires of different widths to avoid minimum cut DRC. DRC, or Geometric Design Rule Check, is a series of constraints and inspection rules established during the integrated circuit design process to ensure the feasibility of the manufacturing process and the reliability of the circuit, regarding the size, shape, spacing, overlap, and other aspects of geometric figures.
[0037] S102, perform global design rule violation detection on the initial wiring path, and transform the initial wiring path into multiple optional wiring paths for the network to be wired based on the results of the global design rule violation detection.
[0038] The above steps obtain the initial routing paths corresponding to each network to be routed. This step is used to perform global design rule violation detection on the initial routing paths, and based on the results of the global design rule violation detection, the initial routing paths are transformed into multiple optional routing paths for the network to be routed. Each optional routing path connects all pins of the network to be routed and avoids violation information.
[0039] In this embodiment, the aforementioned global design rule violation detection of the initial routing path, and the transformation of the initial routing path into multiple optional routing paths for the network to be routed based on the results of the global design rule violation detection, specifically refers to: detecting global DRC for each initial routing path and associating DRC violation identifiers with the corresponding initial routing path; generating multiple optional routing paths for each initial routing path with a DRC violation identifier. Common rules for DRC detection include the following:
[0040] Minimum linewidth rules are used to specify the minimum width of traces such as metal lines and polysilicon lines. For example, in a certain integrated circuit process, the minimum linewidth is 0.1μm. Therefore, the width of all lines in the design must not be less than this value. Otherwise, problems such as line breakage may occur during the manufacturing process.
[0041] Minimum spacing rules are used to define the minimum distance between patterns in the same or different layers. For example, the spacing between two adjacent metal lines must not be less than a specified value to prevent short circuits or signal crosstalk.
[0042] Minimum via size rules are used to specify the minimum diameter, ring width, and other dimensions of vias. In integrated circuits, vias are used to connect different metal layers. If the via size is too small, it may lead to problems such as unreliable connections or excessive resistance.
[0043] This embodiment uses a scan-line algorithm to detect global design rule violations. Specifically, the following algorithm is executed for each metal layer:
[0044] Calculate the maximum rectangle for each orthogonal metal polygon, that is, find the inscribed rectangle with the largest area among all orthogonal metal polygons. The coordinates of the four vertices of the maximum rectangle are represented as Xmin, Ymin, Xmax, and Ymax.
[0045] Perform a topological sort on each largest rectangle, sorting in ascending order according to the values of its corresponding coordinates (Xmin, Ymin, Xmax, Ymax).
[0046] Calculate the maximum violation spacing (max drc Spacing) corresponding to the current metal layer. The maximum violation spacing represents the maximum spacing that can generate DRC. That is, if the spacing exceeds this, DRC is impossible to generate.
[0047] Use an interval tree to maintain the valid region; only the largest rectangle within the valid region can generate a DRC.
[0048] Traverse all sorted largest rectangles and dynamically detect DRC based on this: Expand the interval corresponding to the current largest rectangle in the Y direction to the maximum violation spacing to obtain the coordinate interval that may generate DRC with the current largest rectangle. Based on this coordinate interval, search for a set of rectangles that may generate DRC with the current largest rectangle in the valid area, and determine the DRC with the current largest rectangle based on the following conditions: Check whether the x and y coordinate intervals of each largest rectangle in the rectangle set overlap with the current largest rectangle. If there is overlap in both x and y dimensions, the design rule is determined to be violated. Calculate the required spacing based on the surrounding environment of the two largest rectangles and the preset spacing design rule. If the Euler distance between the two largest rectangles is less than the spacing, the design rule is determined to be violated. Filter and delete the largest rectangles in the valid area that do not meet the preset conditions (e.g., the corresponding Xmax≤Xmin-maxdrcSpacing) using the dynamic range constraint parameter (Xmin-maxdrcSpacing) of the current largest rectangle, and add the current largest rectangle to the valid area.
[0049] The aforementioned transformation of the initial routing path into multiple optional routing paths for the network to be routed, based on the DRC violations identified by the global detection, means that for each network to be routed, a heuristic strategy is used to transform the initial routing path into multiple new optional routing paths based on the DRC violations identified by the global detection. The transformation process must ensure that the new optional routing paths connect all pins of the network to be routed and avoid DRC violations. Specifically, taking a routing tree as an example, for routing tree edges with DRC violations, different transformation methods can be applied to the routing tree according to the type of the edge. This process may result in disconnections in the routing tree; therefore, disconnected parts need to be repaired with new edges to reconnect the transformed optional routing paths.
[0050] In this embodiment, the above-mentioned transformation of the wiring tree can be implemented in the following way:
[0051] If the edge type is leg or jog, it is broken into multiple sub-edges based on the type of DRC (Device Rule Concerning). Only one of these sub-edges retains a DRC violation. Then, the edge and the sub-edge with the DRC violation are moved to adjacent tracks or to a position with the minimum spacing required for calculation (i.e., jump track), or the edge and the sub-edge with the DRC violation are moved to an adjacent metal layer (i.e., jump layer). If the edge is a via (i.e., the edge perpendicularly connects different metal layers), it is moved to an adjacent track grid point (i.e., jump via). If the routing tree violates the design rules or timing rules of the same network, it is filtered out, or the DRC violation is corrected through subsequent processing.
[0052] S103, generate corresponding conflict constraints and connectivity constraints for each optional routing path, and use a preset solver to solve the conflict constraints and connectivity constraints, and determine the optional routing path corresponding to the successfully solved result as the target routing path of the network to be routed.
[0053] After the above steps transform the initial routing path into multiple optional routing paths for the network to be routed based on the results of global design rule violation detection, this step is used to generate corresponding conflict constraints and connectivity constraints for each optional routing path, and use a preset solver to solve the conflict constraints and connectivity constraints. The optional routing path corresponding to the successfully solved result is determined as the target routing path for the network to be routed, and the initial routing path is replaced by the target routing path.
[0054] When constructing constraints, a wiring tree is considered a variable. For example, based on the constructed optional wiring paths, the solver can model the conflict constraints and connectivity constraints corresponding to solving logical reasoning problems in the following way:
[0055] In modeling, for conflict constraints, conflict constraints are generated for the alternative routing paths (i.e., diffnet drc) between different networks that have a DRC problem. For each diffnet drc, only one alternative routing path can be selected from the different networks associated with that drc (they cannot exist simultaneously). For connectivity constraints, constraints must ensure that each network has at least one alternative routing path that is selected.
[0056] In this step, when solving the constraints generated above using a solver, selectable solvers include satsolver (Boolean satisfiability solver), max-sat solver, csp solver, ILP solver (integer linear programming solver), etc. After solving the conflict constraints and connectivity constraints using the above-mentioned preset solvers, if the solution is unsuccessful, the initial routing paths between all networks to be routed are checked. Taking the sat solver as an example, the above constraints are first constructed into a CNF file corresponding to the sat solver. After the sat solver reads the CNF file and solves it, the output of the sat solver is obtained. If the result is satisfiable, the sat solver returns a set of solutions that satisfy the constraints; if the result is unsatisfiable, it means that the current constraint is unsatisfiable, and the iteration process needs to be entered to generate more potential alternative routing paths.
[0057] In another implementation, when the initial wiring path does not contain DRC violations, corresponding conflict constraints and connectivity constraints can be generated for the initial wiring path.
[0058] In this embodiment, before generating conflict constraints and connectivity constraints for the optional cabling paths, the optional cabling paths can be filtered to remove those that consume excessive cabling resources. Filtering methods may include: filtering optional cabling paths with same-net DRC violations; filtering optional cabling paths that have DRC violations with more than a predetermined number of other optional cabling paths; and filtering optional cabling paths with excessively high cabling resource consumption (optional cabling paths with excessive detours), etc.
[0059] In this embodiment, before using a preset solver to solve conflict constraints and connectivity constraints, it is necessary to convert the conflict constraints and connectivity constraints into an input form corresponding to the target solver.
[0060] By using the AI-assisted routing method provided in this embodiment, the routing problem can be transformed into a logic problem. Specifically, after obtaining the initial routing path for the network to be routed, at least one potential alternative routing path can be generated for each network to be routed, avoiding all conflicts. Constraints representing the logic reasoning problem are then constructed, and the constraints are solved by a solver using logical reasoning. Based on the successful solution, the target routing path for the network to be routed is determined. This AI-assisted routing method transforms the routing problem into a logic problem for the solver, comprehensively considering the issues in routing through logical solving. It does not rely on a specific network layout, avoids parameter tuning, effectively solves the problem of allocating critical routing resources, and makes the routing process more efficient.
[0061] The AI-assisted routing method provided in this embodiment does not rely on a specific network order, thus solving the dependency on network order in sequence-based AI-assisted routing methods. This AI-assisted routing method does not rely on a large number of cost hyperparameters, avoiding parameter tuning, and is universally applicable to all layout designs. Unlike existing greedy heuristic methods, the AI-assisted routing method provided in this embodiment effectively considers global conflicts, effectively solving the problem of unreasonable allocation of critical routing resources. Furthermore, compared to track gridpoint-based modeling, the AI-assisted routing method provided in this embodiment significantly reduces the number of variables and constraints during the solution process, making the solution process more efficient.
[0062] The above embodiments provide an artificial intelligence-assisted wiring method. Correspondingly, another embodiment of this application also provides an artificial intelligence-assisted wiring device. Since the device embodiment is basically similar to the method embodiment, it is described in a relatively simple way. For details of the relevant technical features, please refer to the corresponding description of the method embodiment provided above. The following description of the device embodiment is merely illustrative.
[0063] Please refer to Figure 2 Understanding this embodiment, Figure 2 This is a unit block diagram of the AI-assisted wiring device provided in this embodiment, such as... Figure 2 As shown, the AI-assisted wiring device provided in this embodiment includes:
[0064] Initial routing path acquisition unit 201 is used to obtain the initial routing path corresponding to each network to be routed;
[0065] The optional routing path acquisition unit 202 is used to perform global design rule violation detection on the initial routing path, and transform the initial routing path into multiple optional routing paths of the network to be routed based on the result of the global design rule violation detection. Each optional routing path connects all pins of the network to be routed and avoids violation information.
[0066] The target routing path determination unit 203 is used to generate corresponding conflict constraints and connectivity constraints for each optional routing path, and to solve the conflict constraints and connectivity constraints using a preset solver, and to determine the optional routing path corresponding to the successfully solved result as the target routing path of the network to be routed.
[0067] In one implementation, the initial cabling path is transformed into multiple optional cabling paths for the network to be cabled based on the result of global design rule violation detection, including: constructing optional cabling paths in the form of a directed acyclic graph according to the usage of cabling resources.
[0068] In one implementation, the initial cabling path is transformed into multiple optional cabling paths for the network to be cabled based on the result of global design rule violation detection, including: constructing optional cabling paths in the form of a cabling tree according to the usage of cabling resources.
[0069] In one implementation, obtaining the initial cabling path corresponding to each network to be cabled includes:
[0070] In response to the network to be wired being divided into a partially connected state or an unwired state, an initial wiring path is generated for the network to be wired.
[0071] In one embodiment, obtaining the initial wiring path corresponding to each network to be wired includes: in response to the network to be wired being in a fully connected state, correcting the fully connected network to be wired to obtain the initial wiring path.
[0072] In one implementation, the method further includes: generating corresponding conflict constraints and connectivity constraints for the initial routing path in response to the initial routing path not containing violation information.
[0073] In one implementation, before generating conflict constraints and connectivity constraints for the optional routing paths, the method further includes filtering the optional routing paths.
[0074] In one implementation, the method further includes converting the conflict constraints and connectivity constraints into an input form corresponding to the objective solver.
[0075] In one implementation, the initial routing path is subjected to global design rule violation detection, and based on the result of the global design rule violation detection, the initial routing path is transformed into multiple optional routing paths for the network to be routed, including:
[0076] For each initial cabling path, a global DRC is detected, and the DRC violation identifier is associated with the corresponding initial cabling path; for each initial cabling path with a DRC violation identifier, multiple alternative cabling paths are generated.
[0077] In one implementation, after solving the conflict constraints and connectivity constraints using a preset solver, if the solution fails, the initial routing paths between all networks to be routed are detected.
[0078] In the above embodiments, an AI-assisted wiring method and an AI-assisted wiring device are provided. Furthermore, another embodiment of this application provides an electronic device. Since the electronic device embodiment is basically similar to the method embodiment, it is described simply. For details of the relevant technical features, please refer to the corresponding descriptions of the above-provided method embodiments. The following description of the electronic device embodiment is merely illustrative. The electronic device embodiment is as follows:
[0079] Please refer to Figure 3 To understand this embodiment, Figure 3 This is a schematic diagram of the electronic device provided in this embodiment.
[0080] like Figure 3 As shown, the electronic device provided in this embodiment includes: a processor 301 and a memory 302;
[0081] The memory 302 is used to store computer instructions for data processing. When these computer instructions are read and executed by the processor 301, they perform the following operations:
[0082] Obtain the initial cabling path for each network to be cabled;
[0083] The initial routing path is subjected to global design rule violation detection, and based on the result of the global design rule violation detection, the initial routing path is transformed into multiple optional routing paths of the network to be routed, wherein any of the optional routing paths connects all pins of the network to be routed and avoids violation information;
[0084] For each of the optional routing paths, corresponding conflict constraints and connectivity constraints are generated, and the conflict constraints and connectivity constraints are solved using a preset solver. The optional routing path corresponding to the successfully solved result is determined as the target routing path for the network to be routed.
[0085] In one implementation, the initial cabling path is transformed into multiple optional cabling paths for the network to be cabled based on the result of global design rule violation detection, including: constructing optional cabling paths in the form of a directed acyclic graph according to the usage of cabling resources.
[0086] In one implementation, the initial cabling path is transformed into multiple optional cabling paths for the network to be cabled based on the result of global design rule violation detection, including: constructing optional cabling paths in the form of a cabling tree according to the usage of cabling resources.
[0087] In one implementation, obtaining the initial cabling path corresponding to each network to be cabled includes:
[0088] In response to the network to be wired being divided into a partially connected state or an unwired state, an initial wiring path is generated for the network to be wired.
[0089] In one embodiment, obtaining the initial wiring path corresponding to each network to be wired includes: in response to the network to be wired being in a fully connected state, correcting the fully connected network to be wired to obtain the initial wiring path.
[0090] In one implementation, the method further includes: generating corresponding conflict constraints and connectivity constraints for the initial routing path in response to the initial routing path not containing violation information.
[0091] In one implementation, before generating conflict constraints and connectivity constraints for the optional routing paths, the method further includes filtering the optional routing paths.
[0092] In one implementation, the method further includes converting the conflict constraints and connectivity constraints into an input form corresponding to the objective solver.
[0093] In one implementation, the initial routing path is subjected to global design rule violation detection, and based on the result of the global design rule violation detection, the initial routing path is transformed into multiple optional routing paths for the network to be routed, including:
[0094] For each initial cabling path, a global DRC is detected, and the DRC violation identifier is associated with the corresponding initial cabling path; for each initial cabling path with a DRC violation identifier, multiple alternative cabling paths are generated.
[0095] In one implementation, after solving the conflict constraints and connectivity constraints using a preset solver, if the solution fails, the initial routing paths between all networks to be routed are detected.
[0096] In the above embodiments, an AI-assisted wiring method, an AI-assisted wiring apparatus, and an electronic device are provided. Furthermore, another embodiment of this application provides a computer-readable storage medium for implementing the above-described AI-assisted wiring method. The computer-readable storage medium embodiments provided in this application are described relatively simply; relevant parts can be found in the corresponding descriptions of the above method embodiments.
[0097] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.
[0098] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.
[0099] 1. Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include non-transitory computer-readable media, such as modulated data signals and carrier waves.
[0100] 2. Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0101] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.
Claims
1. An artificial intelligence-assisted wiring method, characterized in that, The method includes: Obtain the initial cabling path for each network to be cabled; The initial routing path is subjected to global design rule violation detection, and based on the result of the global design rule violation detection, the initial routing path is transformed into multiple optional routing paths for the network to be routed. This includes: detecting global DRC for each initial routing path, associating DRC violation identifiers with the corresponding initial routing path; generating multiple optional routing paths for each initial routing path with a DRC violation identifier, wherein any of the optional routing paths connects all pins of the network to be routed and avoids violation information. For each of the optional routing paths, corresponding conflict constraints and connectivity constraints are generated, and the conflict constraints and connectivity constraints are solved using a preset solver. The optional routing path corresponding to the successfully solved result is determined as the target routing path for the network to be routed.
2. The method according to claim 1, characterized in that, Obtaining the initial cabling path corresponding to each network to be cabled includes: In response to the network to be wired being divided into a partially connected state or an unwired state, an initial wiring path is generated for the network to be wired.
3. The method according to claim 1, characterized in that, The step of obtaining the initial wiring path corresponding to each network to be wired includes: in response to the network to be wired being in a fully connected state, correcting the fully connected network to be wired to obtain the initial wiring path.
4. The method according to claim 1, characterized in that, Also includes: In response to the initial routing path not containing violation information, corresponding conflict constraints and connectivity constraints are generated for the initial routing path.
5. The method according to claim 1, characterized in that, Before generating conflict constraints and connectivity constraints for the optional routing paths, the method further includes filtering the optional routing paths.
6. The method according to claim 1, characterized in that, The method further includes converting the conflict constraints and connectivity constraints into an input form corresponding to the objective solver.
7. The method according to claim 1, characterized in that, After solving the conflict constraints and connectivity constraints using the preset solver, if the solution fails, the initial routing paths between all networks to be routed are checked.
8. An artificial intelligence-assisted wiring device, characterized in that, The device includes: The initial wiring path acquisition unit is used to obtain the initial wiring path corresponding to each network to be wired. An optional routing path acquisition unit is configured to perform global design rule violation detection on the initial routing path and transform the initial routing path into multiple optional routing paths for the network to be routed based on the result of the global design rule violation detection. This includes: detecting global DRC for each initial routing path and associating DRC violation identifiers with the corresponding initial routing path; generating multiple optional routing paths for each initial routing path with a DRC violation identifier, wherein any of the optional routing paths connects all pins of the network to be routed and avoids violation information. The target routing path determination unit is used to generate corresponding conflict constraints and connectivity constraints for each of the optional routing paths, and to solve the conflict constraints and connectivity constraints using a preset solver, and to determine the optional routing path corresponding to the successfully solved result as the target routing path of the network to be routed.
9. An electronic device, characterized in that, Includes processor and memory; among which, The memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method as described in any one of claims 1-7.
10. A computer-readable storage medium storing one or more computer instructions thereon, characterized in that, The instruction is executed by the processor to implement the method as described in any one of claims 1-7.