A dual-interface smart card substrate layer and a dual-interface smart card

Abstract

The embodiment of the present application provides a kind of double-interface smart card substrate layer, double-interface smart card, the double-interface smart card substrate layer includes: bearing layer, antenna winding and chip module;Antenna winding and chip module are all carried by bearing layer;Strap module projection area, chip module projection area and antenna projection area are formed on the target surface of bearing layer;Chip module projection area and strap module projection area do not overlap;The position area of chip module projection area is: the area formed in the left and right edges of bearing layer, the area that does not overlap with strap module projection area and antenna projection area, and chip module projection area does not overlap with the central axis of the target surface of the bearing layer, can improve the mechanical reliability of chip, reduce cost.

Description

Technical Field

[0001] This invention relates to the field of chip devices, and more specifically, to chip devices comprising contact or contactless communication interfaces. Background Technology

[0002] Dual-interface smart cards are multifunctional cards that combine both contact and contactless communication interfaces. Because they combine the ease of use of contactless IC cards with the security and reliability of contact IC cards, dual-interface smart cards have been widely used in urban public transportation, highway toll collection, e-wallets, financial services, e-commerce and other fields.

[0003] Existing dual-interface smart cards assemble the smart card module, antenna, and card body together through lamination, milling, spot welding, and hot pressing. The functional circuits of the dual-interface module are concentrated in the module packaging position, which causes the chip to be subjected to excessive heat, pressure, and deformation during the card sealing process. At the same time, the mechanical reliability of the chip is insufficient, and the cost is too high. Summary of the Invention

[0004] To address the above problems, this invention proposes a dual-interface smart card substrate layer and a dual-interface smart card. Attached Figure Description

[0005] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0006] Figure 1 This is one of the top view schematic diagrams of the dual-interface smart card substrate layer structure in a specific embodiment of the present invention.

[0007] Figure 1A This is one of the schematic diagrams of the strip module projection area structure of the dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0008] Figure 1B This is a schematic diagram of the strip module structure of the dual-interface smart card according to a specific embodiment of the present invention.

[0009] Figure 1C This is the second schematic diagram of the projection area structure of the strip module of the dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0010] Figure 1D This is one of the schematic diagrams of the chip module structure of the dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0011] Figure 1EThis is the second schematic diagram of the chip module structure of the dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0012] Figure 1F yes Figure 1D One of the schematic diagrams of the cross-sectional structure along the AA direction.

[0013] Figure 1G yes Figure 1E A schematic diagram of the cross-sectional structure along the AA direction.

[0014] Figure 1H This is a schematic diagram of a card insertion bending test according to a specific implementation of the present invention.

[0015] Figure 1I This is a schematic diagram of the conductive channel layer relationship in the same-layer winding and etching method of the present invention.

[0016] Figure 1J This is a schematic diagram of the conductive channel layer relationship of different winding and etching methods of the present invention.

[0017] Figure 2 This is a schematic diagram of the preferred positions of the substrate layer chip modules corresponding to the antenna full-wrap of different / same layers in the dual-interface smart card of the present invention.

[0018] Figure 2A This is a schematic diagram of the preferred positions of the antenna 2 / 3 or 3 / 4 around the corresponding substrate layer chip module in a specific embodiment of the dual-interface smart card of the present invention.

[0019] Figure 2B This is a schematic diagram showing the preferred positions of the substrate layer chip modules corresponding to the different layers of the dual-interface smart card and the antenna full-wrap in a specific embodiment of the present invention.

[0020] Figure 3 This is one of the schematic diagrams of the substrate layer structure corresponding to the co-layer antenna half-wrap of the dual-interface smart card in a specific embodiment of the present invention.

[0021] Figure 3A This is a schematic diagram of the preferred position of the substrate layer chip module corresponding to the antenna half-wrap in the same layer of the dual-interface smart card in a specific embodiment of the present invention.

[0022] Figure 3B This is the second schematic diagram of the substrate layer structure corresponding to the half-wrap antenna of the dual-interface smart card in a specific embodiment of the present invention.

[0023] Figure 3C This is the third schematic diagram of the substrate layer structure corresponding to the same layer of the dual-interface smart card and the antenna half-wrap in a specific implementation of the present invention.

[0024] Figure 4 This is one of the schematic diagrams of the substrate layer structure corresponding to the antenna half-wrap of different layers in the dual-interface smart card of the present invention.

[0025] Figure 4A This is one of the preferred positions of the substrate layer chip module corresponding to the antenna half-wrap of different layers in a dual-interface smart card according to a specific implementation of the present invention.

[0026] Figure 4B This is the second schematic diagram of the substrate layer structure corresponding to the antenna half-wrap of different layers in the dual-interface smart card of this invention.

[0027] Figure 4C This is the second schematic diagram of the preferred positions of the substrate layer chip modules corresponding to the antenna half-wrap of different layers in the dual-interface smart card of the present invention.

[0028] Figure 4D This is the third schematic diagram of the substrate layer structure corresponding to the antenna half-wrap of different layers in the dual-interface smart card of this invention.

[0029] Figure 4E This is the fourth schematic diagram of the substrate layer structure corresponding to the antenna half-wrap of different layers in the dual-interface smart card of this invention.

[0030] Figure 4F yes Figure 2B or Figure 4 One of the cross-sectional views along line AA.

[0031] Figure 4G This is one of the top views of the dual-interface smart card of this invention. Detailed Implementation

[0032] In the following description, numerous specific details are set forth in order to provide a thorough understanding of various illustrative embodiments of the invention. However, those skilled in the art will understand that embodiments of the invention can be practiced without some or all of these specific details. It should be understood that the terminology used herein is for descriptive purposes only and is not intended to limit the scope of the invention. In the drawings, the same reference numerals refer to the same or similar functions or features in several figures.

[0033] It should be understood that the terms "comprising," "including," and "having" are intended to be open-ended, meaning that there may be additional elements besides those listed. The use of reference numerals such as first, second, third, and fourth should not be construed as imposing any order of position or time among the multiple definitions. Furthermore, terms such as "top," "bottom," "side," "below," and "vertical" used herein are merely for descriptive convenience and refer to the orientation of the components as shown in the figures. It should be understood that any orientation of the components described herein is within the scope of this invention.

[0034] General Introduction to Separation:

[0035] Existing dual-interface smart cards concentrate the dual-interface module's functional circuitry at the module packaging location. This integration method, where the stripe module and chip are in the same area, exposes the chip to excessive heat, pressure, and deformation during card sealing and use. Furthermore, the chip's mechanical reliability is insufficient, and the cost is too high. To address this issue, this invention proposes a dual-interface smart card comprising a substrate layer, a stripe module, and a supplementary support layer. The substrate layer includes a carrier layer, a first connection structure, an antenna, and a chip module. The first connection structure, antenna, and chip module are all carried by the carrier layer, and the first connection structure and the antenna are electrically connected to the chip module.

[0036] The projection area of ​​the chip module on the target surface of the carrier layer and the projection area of ​​the strip module of the carrier layer do not overlap. The projection area of ​​the strip module of the carrier layer is the projection area of ​​the strip module of the dual-interface smart card on the target surface of the carrier layer after the strip module is installed. The position of the projection area of ​​the strip module conforms to the industry standard for dual-interface smart cards.

[0037] The target surface of the bearing layer is one of the surfaces with the largest area of ​​the bearing layer.

[0038] See Figure 1 This is one of the top-view schematic diagrams of the dual-interface smart card substrate layer structure according to a specific embodiment of the present invention. The substrate layer 100 of this embodiment includes a carrier layer, a strip module projection area 110, a chip module 120, an antenna 130, and a first connection structure. The carrier layer is a single-layer or multi-layer film structure. The film layer structure constituting the carrier layer is called a sub-substrate layer, used to support other structures of the substrate layer. The first connection structure and the antenna are collectively referred to as a conductive channel. The first connection structure is a connection line between the strip module projection area 110 and the chip module 120, used to realize the electrical connection between the strip module and the chip. The first connection structure includes an inner lead and an inner lead connecting line. The inner lead is electrically connected to the chip module and the inner lead connecting line, respectively. The inner lead connecting line is used to realize the electrical connection with the strip module after installation (see [reference]). Figure 1I and Figure 1J The antenna 130 includes antenna windings (i.e., Figure 1 (intermediate coil) and antenna leads (i.e.) Figure 1The antenna leads are the connection lines between the antenna 130 and the chip module 120. The antenna and the first connection structure can be generated by methods including, but not limited to, winding or etching. For the winding method, both the first connection structure and the antenna are enameled conductive wires. The inner leads and inner lead connecting lines of the first connection structure are integrally formed, and the antenna winding and antenna leads are integrally formed. For the etching method, both the first connection structure and the antenna are conductive metal foils. The inner leads and inner lead connecting lines of the first connection structure can be integrally formed or separately set, and the antenna winding and antenna leads are separately set. In this embodiment, the enameled conductive wire is preferably made of copper, and the conductive metal foil is preferably made of aluminum or copper. However, it is worth noting that other suitable materials can also be used for the enameled conductive wire and conductive metal foil, and this embodiment does not specifically limit this. It should be noted that antenna winding refers to a coil set up to form resonance, and does not limit the material of the antenna. That is, antennas using either the winding method or the etching method have an antenna winding structure, and the same applies to antenna leads. Figure 1 The diagram illustrates a wire routing method, but it is for illustrative purposes only. It should be understood that the same principle applies to etching routing methods, and this should not be taken as a definitive representation. Figure 1 The wiring method shown is defined.

[0039] Based on the positional relationship between the antenna and the first connection structure, the following two scenarios can be identified:

[0040] Same layer: For the method of winding enameled conductive wire, the first connection structure and the antenna are embedded in the same sub-substrate layer; for the method of etching and wiring conductive metal foil, the first connection structure and the antenna are located in the same plane. Figure 1I (A) and (B) respectively illustrate one of the winding and etching methods in the same layer of the present invention.

[0041] Different layers: For the winding method of enameled conductive wire, the first connection structure and the antenna are located in different sub-substrate layers; for the etching and wiring method of conductive metal foil, at least one of the inner lead and inner lead connection line of the first connection structure, the antenna winding and antenna lead in the antenna is located in a different plane from the other three. Figure 1J (A) and (B) respectively illustrate one of the winding and etching methods for different layers in the embodiments of the present invention.

[0042] The carrier layer is a single-layer or multi-layer film structure, that is, it contains one or more sub-substrate layers, preferably flexible films such as PVC, PC, or PET. Based on the positional relationship between the conductive channels and the sub-substrate layers, the sub-substrate layers can be divided into at least two categories: target sub-substrate layers and additional sub-substrate layers; wherein, the target sub-substrate layer is a sub-substrate layer containing conductive channels. Specifically, when the conductive channels are wire-wound, the conductive channels are embedded in the target sub-substrate layer (see...). Figure 1I (A), Figure 1J (A)) When the conductive channel is etched, the conductive channel is attached to the surface of the target sub-substrate layer (see [reference]). Figure 1I (B), Figure 1J (B) The additional sub-substrate layer is a sub-substrate layer that does not contain conductive channels. Specifically, when the conductive channel is wire-wound, even if the conductive channel in the additional sub-substrate layer is in physical contact with the conductive channel in the target sub-substrate layer after the target sub-substrate layer and the additional sub-substrate layer are pressed together, the additional sub-substrate layer is not considered to contain conductive channels. This is because the wire-wound process will inevitably embed the conductive channel into a sub-substrate layer. When the conductive channel is etched, the additional sub-substrate layer and the conductive channel do not have physical contact. In the case of wire-wound in the same layer, the target sub-substrate layer is one layer. In the case of etching in the same layer, the target sub-substrate layer is at least one layer and at most two layers. In the case of wire-wound in different layers, the target sub-substrate layer is two layers. In the case of etching in different layers, the target sub-substrate layer is at least one layer and at most three layers. Regardless of any combination of wire-wound or etching, same layer or different layers, the additional sub-substrate layer is not necessary. However, when an additional sub-substrate layer exists, it can be one or more layers.

[0043] Based on this, under different etching conditions, when the antenna leads and antenna windings are located on different planes, vias are set in the target sub-substrate layer and filled with conductive filler to achieve electrical connection between the antenna leads and antenna windings; similarly, when the inner leads and inner lead connecting lines are located on different planes, vias are set in the target sub-substrate layer and filled with conductive filler to achieve electrical connection between the inner leads and inner lead connecting lines.

[0044] The strip module of this invention includes contact pads, a support layer, and multiple conductive pads. The contact pads and conductive pads are located on both sides of the support layer and are electrically connected. The contact pads include effective contacts conforming to the ISO 7816 protocol. See also... Figure 1A This is one of the schematic diagrams of the strip module projection area structure of the dual-interface smart card substrate layer in a specific embodiment of the present invention, corresponding to the winding method. Figure 1B This is a schematic diagram of the strip module structure of a dual-interface smart card according to a specific embodiment of the present invention. As an example, Figure 1B Only the 8-pin module solution is shown here; the same applies to the 6-pin module solution, which will not be detailed further. Figure 1A As shown, the projection area of ​​the strip module includes five tightly wound first connection structure terminals (i.e., first connection structure terminals used to connect the conductive pads of the strip module). The projection area corresponding to each tightly wound first connection structure terminal matches the projection area corresponding to the effective contact after the strip module is installed. Figure 1BAs shown, the strip module has conductive pads on its surface corresponding to the effective contact points, and these conductive pads are electrically connected to the corresponding effective contacts. The tightly wound first connection structure terminal can be electrically connected to the corresponding conductive pad of the strip module via conductive adhesive, thereby achieving electrical connection with the effective contacts of the strip module. Preferably, the conductive pads are angled, which increases the contact area with the tightly wound first connection structure terminal and improves the reliability of the electrical connection. It is worth noting that the conductive pads are actually three-dimensional structures, and their height can be adjusted according to design requirements. The conductive pads can be made of metal materials such as copper or aluminum.

[0045] See Figure 1C This is the second schematic diagram of the strip module projection area structure of the dual-interface smart card substrate layer in a specific embodiment of the present invention, corresponding to the etching method. For example... Figure 1C As shown, the projection area of ​​the strip module includes five etched pad-shaped first connection structure terminals (i.e., first connection structure terminals for connecting the conductive pads of the strip module). The projection area corresponding to each etched pad-shaped first connection structure terminal matches the projection area corresponding to the effective contact after the strip module is installed. The strip module still adopts... Figure 1B As shown in the structure, the first connection structure terminals in the form of each etched pad can be electrically connected to the corresponding conductive pads of the strip module by soldering with conductive glue or solder balls, thereby realizing the electrical connection with the effective contact of the strip module.

[0046] Based on the above, the chip module 120 is mounted on the substrate layer, and its packaging form includes, but is not limited to, COB (chip-on-board) packaging and WLCSP (Wafer Level Chip Scale Packaging). For example... Figure 1D This is one of the structural diagrams of chip module 120 when using COB packaging; for example... Figure 1E This is one of the structural diagrams of chip module 120 when it is packaged in WLCSP.

[0047] See Figure 1DThe COB-packaged chip module 120 includes a substrate and a chip. A target surface of the substrate is used to mount the chip, and this target surface is one of the largest surfaces of the substrate. Preferably, the chip is mounted at the center of the target surface of the substrate, i.e., the line connecting the center point of the chip and the center point of the substrate is perpendicular to the target surface of the substrate. The target surface of the substrate also has multiple chip module contact pads to achieve electrical connection between the chip and the antenna and the first connection structure. Based on this, electrical connection between the chip and the strip module and the antenna can be achieved, thereby realizing contact communication and contactless communication of the dual-interface smart card. It is worth noting that, to ensure the basic contact and contactless functions of the smart card, the number of chip module contact pads includes at least 7 sets: at least 2 sets are used to achieve electrical connection between the two free ends of the chip and the antenna, and at least 5 sets are used to achieve electrical connection between the chip and the effective contacts of the strip module. Figure 1D The number of contact pads in the chip module can be adjusted according to actual application needs. Figure 1D The number of chip module contact pad groups shown is for illustrative purposes only. It is worth noting that each chip module contact pad group includes one chip contact pad and one conductive channel contact pad. The chip contact pad and the conductive channel contact pad can be integrally formed or can be two separate contact pads electrically connected by a wire or other conductive structure. The chip contact pad and the conductive channel contact pad are made of the same conductive material and can be manufactured using the same process. See also... Figure 1F ,for Figure 1D One of the schematic diagrams of the cross-sectional structure along the AA direction. For example... Figure 1F As shown, the chip contact pad is connected to the chip pins via chip interconnects. After the connection is complete, the chip, chip interconnects, and chip contact pads are encapsulated with encapsulating adhesive, which can be applied using processes such as epoxy resin or black glue. The conductive channel contact pad is used to electrically connect the first connection structure terminal (the terminal located in the chip module mounting area) or the antenna terminal. It is understood that the first connection structure terminal and the antenna terminal are not limited to the conductive channel endpoints of the first connection structure and the antenna; the terminal can be understood as a section of conductive channel of the first connection structure or the antenna near the projection area of ​​the strip module or near the conductive channel contact pad of the chip module.

[0048] Preferably, the plurality of chip module contact pads are evenly distributed around the chip. This shortens the length of the chip connection lines and optimizes the first connection structure and antenna arrangement. Of course, depending on the actual application requirements, the plurality of chip module contact pads can also adopt other layouts, such as being arranged side by side on one side of the chip, or having the chip module contact pads connected to the antenna and the chip module contact pads connected to the strip module arranged separately. This embodiment of the invention does not specifically limit these arrangements.

[0049] Optionally, the chip can also be flip-chip mounted on the target surface of the substrate. In flip-chip mounting, the chip's pins can be directly electrically connected to the chip contact pads on the substrate via solder balls. Based on this, compared to... Figure 1F As shown, in this embodiment of the invention, the electrical connection between the chip pins and the chip contact pad can be achieved without setting up chip connection lines.

[0050] It is worth noting that when the chip module 120 is installed, in the chip module installation area, the terminals of the antenna and the first connection structure overlap with the matching conductive channel contact pads on the chip module in the orthogonal projection direction of the target surface of the carrier layer. Based on this, this embodiment of the invention electrically connects one side terminal of the antenna and the first connection structure to the matching conductive channel contact pads of the chip module. The electrical connection can be achieved by welding, conductive adhesive bonding, or conductive filler connection. Specifically, the welding method can be spot welding, etc., and this embodiment of the invention does not specifically limit this. The chip module substrate can be a flexible PCB board or epoxy glass cloth, or a composite carrier material, such as a metal base plate supporting PVC or PE materials. Based on this, it can provide higher stress strength than PVC material alone, ensuring the reliability of the chip installation and use process, while reducing costs.

[0051] See Figure 1E The WLCSP-packaged chip module 120 consists only of the chip package and solder balls; the chip pins can be electrically connected to external modules via the solder balls. It is understandable that... Figure 1E The number and position of the solder balls can be adjusted as needed in practical applications, and this embodiment of the invention does not impose specific limitations on this. See also Figure 1G ,for Figure 1E A cross-sectional view of the structure along the AA direction is shown. The WLCSP package size is only 0%-20% larger than the bare chip size, and its thickness is thinner. This method can minimize the chip module's footprint while meeting the manufacturing process requirements of dual-interface smart cards. The solder ball array of the WLCSP packaged chip is electrically connected to the antenna and the terminals (conductive metal foil etched wiring) of the first connection structure designed in the substrate layer through soldering or conductive adhesive bonding. Precise soldering processes, such as reflow soldering or ultrasonic soldering, ensure the reliability and conductivity of the connection; anisotropic conductive adhesive is used to electrically connect the WLCSP packaged chip to the antenna and the terminals of the first connection structure, which is simpler and improves production efficiency. WLCSP packaging allows the chip module 120 to be embedded in the substrate layer with minimal footprint while maintaining excellent electrical performance and mechanical stability. Through precise positioning and reliable electrical connections, WLCSP packaging ensures the overall performance of the dual-interface smart card while extending the chip's lifespan, meeting the dual requirements of high performance and high reliability for modern dual-interface smart cards.

[0052] Preferably, for the wire-wound method, the chip module 120 is packaged using COB packaging; for the etching method, the chip module 120 can be packaged using either COB packaging or WLCSP packaging.

[0053] Constraint diagram: Location distribution of chip modules

[0054] Based on the aforementioned substrate layer structure, this embodiment of the invention maximizes chip lifespan while ensuring the mechanical and electrical performance of the dual-interface smart card by optimizing the chip module's location. Specifically, this embodiment of the invention generates multiple corresponding constraints to determine the optimal location of the chip module based on a comprehensive consideration of mechanical performance, electrical performance, and chip lifespan.

[0055] To facilitate the description of the planar positional relationships in the process of determining the preferred location of the chip module, see [link to relevant documentation]. Figure 1 This invention is described based on the orthographic projection areas formed on the target surface of the substrate layer 100 by the strip module, chip module 120, antenna 130, etc., namely the strip module projection area, chip module projection area, and antenna projection area. It is understood that the orthographic projection area is the area obtained by projecting along the normal direction of the target surface of the substrate layer 100. It is worth noting that the antenna projection area refers to the orthographic projection area corresponding to the antenna winding, excluding the orthographic projection area corresponding to the antenna leads. Based on this, the preferred position of the substrate layer chip module projection area is further determined.

[0056] The determination of the preferred location of the chip module projection area includes constraint areas generated by multiple constraint conditions. Optionally, the constraint areas may include, but are not limited to, the strip module projection area, antenna projection area, first bending area, second bending area, third bending area, fourth bending area, resistance projection area, and embossed projection area. The strip module projection area is the orthographic projection area of ​​the strip module on the target surface of the carrier layer after installation; the antenna projection area is the orthographic projection area corresponding to the antenna winding. The first bending area is the orthographic projection area corresponding to the area between the left edge of the dual-interface smart card (left edge of the carrier layer) and the first bending cutoff line during the card insertion bending test. The distance between the first bending cutoff line and the left edge of the dual-interface smart card is determined based on the second preset insertion length and the second preset radius of curvature of the card insertion bending test. The second bending area is the orthographic projection area corresponding to the area between the right edge of the dual-interface smart card (right edge of the carrier layer) and the second bending cutoff line during the card insertion bending test. The distance between the second bending cutoff line and the right edge of the dual-interface smart card is determined based on the first preset insertion length and the second preset radius of curvature of the card insertion bending test. The preset insertion length and the first preset radius of curvature for the card insertion bending test are determined; the third bending region is the orthographic projection region corresponding to the area between the upper edge of the dual-interface smart card (upper edge of the carrier layer) and the third bending cutoff line when the dual-interface smart card is inserted and bent, and the distance between the third bending cutoff line and the upper edge of the dual-interface smart card is determined according to the third preset insertion length and the third preset radius of curvature for the card insertion bending test; the fourth bending region is the orthographic projection region corresponding to the area between the lower edge of the dual-interface smart card (lower edge of the carrier layer) and the fourth bending cutoff line when the dual-interface smart card is inserted and bent, and the distance between the fourth bending cutoff line and the lower edge of the dual-interface smart card is determined according to the fourth preset insertion length and the fourth preset radius of curvature for the card insertion bending test; the resistance projection region is the target half-region where the strip module projection region is located in the two half-regions obtained by dividing the target surface of the carrier layer by the vertical central axis; the embossed projection region is the orthographic projection region of the carrier layer corresponding to the embossed region when the smart card is embossed. The constraint region is the area that the chip module projection area cannot be set or is restricted from being set. By selecting one or more constraint regions, the area that the chip module projection area can be set is finally determined.

[0057] The present invention provides a solution for separating the strip module and the chip. In other words, all embodiments of the present invention are implemented on the basis that the projection areas of the chip module and the strip module do not overlap on the orthographic projection areas of the target surface of the carrier layer.

[0058] In addition, this embodiment of the invention takes into account the impact of chip placement on antenna performance. If the projection area of ​​the chip module coincides with the antenna, the installation of the chip module 120 will affect the antenna performance or even cause antenna damage. Based on this, this embodiment of the invention generates a first constraint: the projection area of ​​the chip module avoids the projection area of ​​the antenna. Thus, the installation of the chip module 120 can be avoided from affecting the antenna performance or damaging the antenna.

[0059] This invention takes into account the torsion test and potential bending damage that will occur after the dual-interface smart card is manufactured. During the torsion test and in the event of bending damage, the torque is greatest along the central axis of the dual-interface smart card. Figure 2-Figure 2B As shown, including the vertical and horizontal central axes, if the chip module is located on the central axis of the dual-interface smart card, it will face a greater risk of damage. Based on this, the embodiment of the present invention generates a second constraint: the projection area of ​​the chip module avoids the central axis of the smart card. Based on this, damage to the chip can be avoided during the torsion test and bending process.

[0060] This invention considers the pressure and bending effects on the card caused by scenarios such as holding, gripping, and inserting / removing the card when using a dual-interface smart card. It is understood that the card's edges are areas with a high probability of pressure and bending during these scenarios. When the chip module is located in this area, the risk of damage increases. Therefore, a card insertion test fixture is designed and manufactured. This fixture is used to perform card insertion bending tests on the dual-interface smart card to simulate the potential impact areas of the aforementioned usage scenarios. When performing the card insertion bending test, refer to... Figure 1H As shown, the dual-interface smart card needs to be inserted into the card insertion test tool with a preset insertion length l, and then bent along the arc surface of the card insertion test tool with a radius of curvature r until the surface of the dual-interface smart card and the surface of the card insertion test tool are completely in contact. The area covered by the bend simulates the area where the card is most likely to be bent in actual use.

[0061] To avoid the impact of bending tests on the chip module, the projection area of ​​the chip module typically avoids the first bending area, which is the area where the left edge of the dual-interface smart card contacts the curved surface of the card insertion test tool after insertion. The first bending area is the orthographic projection area corresponding to the region between the left edge of the dual-interface smart card and the first bending cutoff line during the card insertion bending test. The distance between the first bending cutoff line and the left edge of the dual-interface smart card is determined based on the second preset insertion length and the second preset radius of curvature of the card insertion bending test. Based on this, the embodiment of the present invention generates a third constraint condition, which is: the projection area of ​​the chip module avoids the first bending area, the first bending area is the region between the left edge of the carrier layer and the first bending cutoff line, and the distance between the first bending cutoff line and the left edge of the carrier layer is determined based on the second preset insertion length and the second preset radius of curvature of the card insertion bending test; along the direction of the horizontal central axis, the left edge of the carrier layer is the edge of the carrier layer that is closest to the projection area of ​​the strip module; based on this, damage to the chip can be avoided during the card insertion bending test.

[0062] As one possible implementation, the distance L2 between the first bend cutoff line and the left edge of the dual-interface smart card can be calculated using the following formula: L2=l2+r2×π×1 / 2, where l2 is the second preset insertion length and r2 is the second preset radius of curvature.

[0063] As an example, the second preset insertion length is 1-3mm. Specifically, the second preset insertion length can be 1mm, 1.5mm, 2mm, 2.5mm, or 3mm. The range of the second preset radius of curvature is 5mm-20mm. Specifically, the second preset radius of curvature can be 5mm, 8mm, 10mm, 12mm, 15mm, 18mm, or 20mm.

[0064] Similarly, to avoid the impact of bending simulation testing on the chip module, the projection area of ​​the chip module typically avoids the second bending area, which is the area where the right edge of the dual-interface smart card contacts the curved surface of the card insertion test fixture after insertion. The second bending area is the orthographic projection area corresponding to the region between the right edge of the dual-interface smart card and the second bending cutoff line during the card insertion bending test. The distance between the second bending cutoff line and the right edge of the dual-interface smart card is determined based on the first preset insertion length and the first preset radius of curvature of the card insertion bending test. Based on this, the embodiment of the present invention generates a fourth constraint condition, which is: the projection area of ​​the chip module avoids the second bending area, the second bending area is the region between the right edge of the carrier layer and the second bending cutoff line, and the distance between the second bending cutoff line and the right edge of the carrier layer is determined based on the first preset insertion length and the first preset radius of curvature of the card insertion bending test; along the direction of the horizontal central axis, the right edge of the carrier layer is the edge of the carrier layer that is farthest from the projection area of ​​the strip module; based on this, damage to the chip can be avoided during the card insertion bending test.

[0065] As one possible implementation, the distance L1 between the second bend cutoff line and the left edge of the dual-interface smart card can be calculated using the following formula: L1=l1+r1×π×1 / 2, where l1 is the first preset insertion length and r1 is the first preset radius of curvature.

[0066] As an example, the first preset insertion length is 1-3mm, specifically, the first preset insertion length can be 1mm, 1.5mm, 2mm, 2.5mm, or 3mm, and the first preset radius of curvature ranges from 5mm to 20mm, specifically, the first preset radius of curvature can be 5mm, 8mm, 10mm, 12mm, 15mm, 18mm, or 20mm.

[0067] Similarly, to avoid the impact of bending tests on the chip module, the projection area of ​​the chip module typically avoids the third bending area, which is the area where the upper edge of the dual-interface smart card contacts the curved surface of the card insertion test fixture after the card insertion test fixture is inserted. The third bending area is the orthographic projection area corresponding to the area between the upper edge of the dual-interface smart card and the third bending cutoff line during the card insertion bending test. The distance between the third bending cutoff line and the upper edge of the dual-interface smart card is determined based on the third preset insertion length and the third preset radius of curvature of the card insertion bending test. Based on this, the embodiment of the present invention generates a fifth constraint condition: the chip module projection area avoids the third bending area, the third bending area is the area between the upper edge of the carrier layer and the third bending cutoff line, and the distance between the third bending cutoff line and the upper edge of the carrier layer is determined based on the preset insertion length and the radius of curvature of the card insertion test fixture; along the direction perpendicular to the central axis, the upper edge of the carrier layer is the edge of the carrier layer closest to the projection area of ​​the strip module; based on this, damage to the chip can be avoided during the card insertion bending test.

[0068] As one possible implementation, the distance L3 between the third bend cutoff line and the left edge of the dual-interface smart card can be calculated using the following formula: L3=l3+r3×π×1 / 2, where l3 is the second preset insertion length and r3 is the second preset radius of curvature.

[0069] As an example, the third preset insertion length is 1-3mm, specifically, the third preset insertion length can be 1mm, 1.5mm, 2mm, 2.5mm, or 3mm, and the third preset radius of curvature ranges from 5mm to 15mm, specifically, the third preset radius of curvature can be 5mm, 8mm, 10mm, 12mm, or 15mm.

[0070] Similarly, to avoid the impact of bending tests on the chip module, the projection area of ​​the chip module usually avoids the fourth bending area, which is the area where the upper edge of the dual-interface smart card contacts the curved surface of the card insertion test tool after the card insertion test tool is inserted. The fourth bending area is the orthographic projection area corresponding to the area between the lower edge of the dual-interface smart card and the fourth bending cutoff line when the dual-interface smart card is subjected to card insertion bending test. The distance between the fourth bending cutoff line and the lower edge of the dual-interface smart card is determined according to the fourth preset insertion length and the fourth preset radius of curvature of the card insertion bending test. Based on this, the embodiments of the present invention generate a sixth constraint condition: the sixth constraint condition is that the chip module projection area avoids the fourth bending area, the fourth bending area is the area between the lower edge of the carrier layer and the fourth bending cutoff line, and the distance between the fourth bending cutoff line and the lower edge of the carrier layer is determined according to the preset insertion length of the card bending test and the radius of curvature of the card bending test tool; along the direction of the vertical central axis, the lower edge of the carrier layer is the edge of the carrier layer that is farthest from the projection area of ​​the strip module; based on this, damage to the chip can be avoided during the card bending test.

[0071] As one possible implementation, the distance L4 between the fourth bend cutoff line and the left edge of the dual-interface smart card can be calculated using the following formula: L4=l4+r4×π×1 / 2, where l4 is the fourth preset insertion length and r4 is the fourth preset radius of curvature.

[0072] As an example, the fourth preset insertion length is 1-3mm. Specifically, the fourth preset insertion length can be 1mm, 1.5mm, 2mm, 2.5mm, or 3mm. The fourth preset radius of curvature is in the range of 5mm-15mm. Specifically, the fourth preset radius of curvature can be 5mm, 8mm, 10mm, 12mm, or 15mm.

[0073] This invention, through research, has found that during the use of dual-interface smart cards, the chip is subjected to continuous pressure after entering the card slot, increasing the resistance to card insertion and removal. Prolonged pressure also affects the chip's lifespan. Positioning the chip module on the right side of the vertical central axis is preferable to placing the chip on the left side of the vertical central axis (i.e.,...). Figure 2-Figure 2B The resistance projection area shown will significantly shorten the chip's compression stroke, reducing insertion resistance and extending chip lifespan. Based on this, the embodiments of the present invention further add a seventh constraint: the chip module projection area avoids the left side of the vertical central axis, i.e., the resistance projection area. Therefore, while ensuring the electrical performance of the dual-interface smart card, it is possible to reduce insertion resistance and maximize chip lifespan.

[0074] Building upon the above, the smart card may require embossing during manufacturing to highlight information such as the card number, cardholder's name, and expiration date. This embodiment of the invention considers the risk of chip damage during embossing in the dual-interface smart card manufacturing process and generates an eighth constraint: the chip module projection area avoids the embossed projection area, where the embossed projection area is the orthogonal projection area of ​​the carrier layer corresponding to the smart card's embossed area. Based on this, chip damage during the embossing process can be avoided.

[0075] Table 1 summarizes the various constraints and their corresponding locations and avoidance ranges.

[0076] Table 1. Constraints and their corresponding locations and avoidance ranges.

[0077]

[0078] To facilitate characterizing the configurable area of ​​the chip module, based on the aforementioned eight constraints (first, second, third, fourth, fifth, sixth, seventh, or eighth constraint), and according to the corresponding boundaries and intersections of each constraint (see Table 2), the orthographic projection area of ​​the dual-interface smart card / bearing layer can be defined as eight regions (see Table 3), namely Region 1, Region 2, Region 3, Region 4, Region 5, Region 6, Region 7, and Region 8. These regions are related to the aforementioned constraints. By combining these regions according to different combinations of constraints to be considered, the optimal position of the chip module projection area can be determined. It is worth noting that when the antenna projection area is close to the edge of the dual-interface smart card, the space between the card edge and the outer edge of the antenna projection area is too small to allow for chip module installation; similarly, when the semi-circular antenna avoids the strip module (see Table 3), the optimal position of the chip module projection area can be determined. Figure 3A , 4C The left side of the strip module projection area is adjacent to the card edge, and the space between them is too small to allow for the installation of the chip module. To ensure the performance of both the antenna and the chip, the chip module settings in this invention all satisfy the first constraint condition, namely, avoiding the antenna projection area. Therefore, the area where the chip module projection area can be set effectively excludes the portion overlapping with the strip module projection area and the antenna projection area, as well as the excessively small area between the card edge and the outer edge of the antenna projection area, and the small area from the left side of the strip module projection area adjacent to the card edge to the card edge.

[0079] When all constraints are met, and the smart card is embossed, the preferred location region of the chip module projection area can be determined in this embodiment of the invention. This region is the area formed between the upper edge of the embossed projection area, the vertical central axis, the second bend cutoff line, and the third bend cutoff line, and does not overlap with the antenna projection. Furthermore, the chip module projection area does not intersect with the central axis of the target surface of the bearing layer. Within this region, the area above the horizontal central axis is designated as Region 1, and the area below the horizontal central axis is designated as Region 2-1 (the same applies to subsequent embodiments). For the antenna full-wrap scheme (see...),... Figure 2 , 2B The preferred location area for the chip module is region 1 formed by points A8, A9, A12, and A11, and region 2-1 (with embossing) formed by A11, A12, B2, and B1. When the smart card does not have embossing, the preferred location area for the chip module projection area can be determined in this embodiment of the invention, namely, the area formed between the vertical central axis, the second bend cutoff line, the third bend cutoff line, and the fourth bend cutoff line, which does not overlap with the antenna projection area, and the chip module projection area does not overlap with the central axis of the target surface of the bearing layer; in this area, the area above the horizontal central axis is determined as region 1, and the area below the horizontal central axis is determined as region 2-2 (the same applies to subsequent embodiments). For the antenna full-wrap scheme (see...), Figure 2 , 2B The preferred location area of ​​the chip module is region 1, which is composed of A11, A12, A9, and A8, and region 2-2, which is composed of A11, A12, B6, and B5 (without embossing). Region 2-1 and region 2-2 together constitute region 2.

[0080] Optionally, the shape of the chip module 120 is preferably rectangular or rectangular, and the range of the chip module's projection area is defined by the four corner points M1, M2, M3, M4 and the boundary. For the chip module's projection area to satisfy the constraints, it must be ensured that all boundaries and all four corner points of the chip module satisfy the constraints of that area. For example, when all constraints are satisfied simultaneously, the chip module's projection area is completely located within region 1 or region 2.

[0081] It is worth noting that the above-mentioned solution that simultaneously satisfies all constraints is the optimal implementation of this invention. In practical applications, provided that the chip module does not overlap with the projection area of ​​the strip module, only the first constraint can be considered, namely, the chip module avoids the projection areas of the antenna and the strip module, which is the maximum range that the chip module can be set to. Alternatively, in addition to considering the first constraint, other constraints can be combined, that is, the first constraint can be arbitrarily set and combined with the second, third, fourth, fifth, sixth, seventh, or / and eighth constraint (e.g., if the smart card has embossed markings, then the eighth constraint exists). That is, provided that the projection area of ​​the chip module does not overlap with the projection areas of the strip module and the antenna, it can be located in at least one of the following areas: the drag projection area, the horizontal or vertical central axis, the first bending area, the second bending area, the third bending area, or the fourth bending area. However, when the chip module projection area is located in the resistance projection area, on the horizontal or vertical central axis, or in the first, second, third, or fourth bending area, the material or structure of the chip module 120 needs to be reinforced to prevent damage. For example, using a more elastic encapsulating adhesive after solidification, such as black glue or UV glue, can help resist bending and compression. Alternatively, a more flexible substrate material can be used, or the overall thickness of the chip module can be reduced to minimize breakage caused by inconsistent deformation during compression and bending. When the dual-interface smart card has embossed printing, the chip module projection area is not located in the embossed projection area.

[0082] Region 3 is defined as the area bounded horizontally by the left edge of the supporting layer to the first bend cutoff line and vertically by the upper and lower edges of the supporting layer, corresponding to the first bending region. This region does not overlap with the strip module projection area and the antenna projection area. For the antenna full-wrap scheme (see...), Figure 2 , 2B Region 3 is defined by A1, A2, B9, and B8 (the region does not include the portion overlapping with the projection area of ​​the strip module; in the following embodiments, the regions covering all or part of the projection area of ​​the strip module are treated similarly and will not be specifically described again); the region corresponding to the second bending region, defined horizontally from the right edge of the bearing layer to the second bending cutoff line and vertically by the upper and lower edges of the bearing layer, that does not overlap with the antenna projection area is defined as region 4; for the antenna full-wrap scheme (see... Figure 2 , 2B Region 4 is defined by A4, A5, B12, and B11; Region 5 is defined as the area in the vertical direction bounded by the upper edge of the bearing layer to the cutoff line of the third bend, and in the horizontal direction bounded by the left and right edges of the bearing layer, which does not overlap with the antenna projection area; for the antenna full-wrap scheme (see...), Figure 2 ,2B Region 5 is defined by A1, A5, A10, and A6; the region corresponding to the fourth bending region, defined vertically by the lower edge of the supporting layer to the fourth bending cutoff line and horizontally by the left and right edges of the supporting layer, that does not overlap with the antenna projection region is defined as region 6; for the antenna full-wrap scheme (see...), Figure 2 , 2B Region 6 is defined by B3, B7, B12, and B8; the region formed between the left edge of the bearing layer corresponding to the drag projection region and the vertical central axis, as well as the upper and lower edges of the bearing layer, that does not overlap with the strip module projection region and the antenna projection region is defined as Region 7; for the antenna full-wrap scheme (see...), Figure 2 , 2B Region 7 is determined by A1, A3, B10, and B8; when the dual-interface smart card has an embossed projection area, the region that does not overlap with the antenna projection area is defined as region 8, which is the area formed between the upper edge of the embossed projection area and the lower edge of the carrier layer and the left and right edges of the carrier layer; for the antenna full-wrap scheme (see... Figure 2 , 2B Region 8 is defined by A13, A15, B12, and B8. The horizontal central axis defines line segment 9, and the vertical central axis defines line segment 10. Figure 2-Figure 2B Line segment 9, which is formed by endpoints A3 and B10, and line segment 10, which is formed by endpoints A16 and A17.

[0083] For antenna 3 / 4, 2 / 3 wrap, half-wrap to avoid the strip module projection area, and half-wrap without avoiding the strip module projection area, the smart card can still be divided into the above 8 areas. The definition of each area remains the same, but the representation of the area will change due to the positional relationship between the antenna and the area boundary, as shown in Table 3. When the antenna is half-wrapped, the lower outer edge of the antenna projection area is set close to the horizontal central axis.

[0084] Table 2 List of Regional Boundaries and Intersections

[0085]

[0086]

[0087] Table 3. Projection area of ​​dual-interface smart card / carrier layer

[0088]

[0089]

[0090] In Table 3 above, the regions listed with * corresponding to the constraint conditions must exclude areas overlapping with the stripe module projection area and the antenna projection area. Additionally, areas too small between the card edge and the outer edge of the antenna projection area when the antenna projection area is near the smart card edge, and small areas from the left side of the stripe module projection area to the card edge must also be excluded. For the characterization of the full-around antenna case, the regions listed must exclude areas overlapping with the stripe module projection area. See [link to relevant documentation] for details. Figure 2 , 2B ***The regions listed for the representation of cases 2 / 3 or 3 / 4 must exclude areas that overlap with the projection region of the strip module. See details in [link to relevant documentation]. Figure 2A The regions listed for characterizing the semi-circular antenna's avoidance of the strip module's projection area must exclude areas overlapping with the strip module's projection area. See [link to documentation] for details. Figure 3A , 4C The regions listed for the description of the situation where a semi-circular antenna does not avoid the projection area of ​​a strip module must exclude areas that overlap with the projection area of ​​the strip module. See [link to relevant documentation] for details. Figure 4A .

[0091] As described above, the first constraint can be combined with the second, third, fourth, fifth, sixth, seventh, and / or eighth constraints in various ways. For example, the first constraint can be combined with the third constraint, or with the second, fourth, and fifth constraints, etc. Based on the combination of constraints, the area that can be set in the chip module is clearly defined. Due to the large number of combinations, they will not be listed exhaustively here. The preferred combinations of constraints in the embodiments of this application will be described in detail below.

[0092] Considering only the first and fourth constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, and the second bending area; that is, the area formed from the left edge of the carrier layer to the second bending cutoff line and the upper and lower edges of the carrier layer, and does not overlap with the antenna projection area and the strip module projection area; specifically, the portion of the area formed by the aforementioned regions 1, 2-2, 3, 5, 6, and 7 that does not overlap with region 4. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A1, A4, B11, and B8 that does not overlap with the projected area of ​​the strip module. No embossing is set at this time.

[0093] Considering the first, fourth, and second constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, and the horizontal and vertical central axis; that is, the area formed from the left edge of the support layer to the second bend cutoff line and the upper and lower edges of the support layer, and does not overlap with the antenna projection area and the strip module projection area, and the chip module projection area does not overlap with the central axis. Specifically, it refers to the portion of the area composed of the aforementioned regions 1, 2-2, 3, 5, 6, and 7 that does not overlap with region 4, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A1, A4, B11, and B8 that does not overlap with the projection area of ​​the strip module, line segment 9, and line segment 10. No embossing is set at this time.

[0094] Considering the first, fourth, and third constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, and the first bend area; that is, the area formed between the first bend cutoff line and the second bend cutoff line and the upper and lower edges of the carrier layer, which does not overlap with the antenna projection area and the strip module projection area. Specifically, it is the portion of the area formed by the aforementioned regions 1, 2-2, 5, 6, and 7 that does not overlap with regions 3 and 4. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A2, A4, B11, and B9 that does not overlap with the projected area of ​​the strip module. No embossing is set at this time.

[0095] Considering the first, fourth, and fifth constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, and the third bend area; that is, the area formed horizontally from the left edge of the support layer to the second bend cutoff line, and vertically from the third bend cutoff line to the lower edge of the support layer, which does not overlap with the antenna projection area and the strip module projection area. Specifically, it is the portion of the area composed of the aforementioned regions 1, 2-2, 3, 6, and 7 that does not overlap with regions 4 and 5. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A6, A9, B11, and B8 that does not overlap with the projected area of ​​the strip module. No embossing is set at this time.

[0096] Considering the first, fourth, and sixth constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, and the fourth bend area; that is, the area formed horizontally from the left edge of the support layer to the second bend cutoff line, and vertically from the upper edge of the support layer to the fourth bend cutoff line, which does not overlap with the antenna projection area and the strip module projection area. Specifically, it is the portion of the area composed of the aforementioned regions 1, 2-2, 3, 5, and 7 that does not overlap with regions 4 and 6. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A1, A4, B6, and B3 that does not overlap with the projected area of ​​the strip module. No embossing is set at this time.

[0097] Considering the first, fourth, and seventh constraints, the preferred location of the chip module projection area is: the area where the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, and the drag projection area; that is, the area between the vertical central axis and the second bending cutoff line and the upper and lower edges of the bearing layer, and the area that does not overlap with the antenna projection area. Specifically, this refers to the portions of regions 1, 2-2, 5, and 6 that do not overlap with regions 4 and 7. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the rectangular area defined by A3, A4, B11, and B10. No embossing is applied at this point. Since the resistance projection area completely covers the first bending area, the aforementioned area is the same as in the cases considering the first, fourth, third, and seventh constraints. No embossing is applied at this point.

[0098] Considering the first, fourth, second, and third constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, and the horizontal and vertical central axis. Specifically, it is the area formed between the first bend cutoff line and the second bend cutoff line and the upper and lower edges of the support layer, and does not overlap with the antenna projection area or the strip module projection area. Furthermore, the chip module projection area does not overlap with the central axis. Specifically, this refers to the portion of the area formed by regions 1, 2-2, 5, 6, and 7 that does not overlap with regions 3, 4, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A2, A4, B11, and B9 that does not overlap with the projection area of ​​the strip module, line segment 9, and line segment 10. No embossing is set at this time.

[0099] Considering the first, fourth, second, and fifth constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the third bend area, and the horizontal and vertical central axis. Specifically, it is the area formed by the horizontal direction from the left edge of the support layer to the second bend cutoff line, and the vertical direction from the third bend cutoff line to the lower edge of the support layer, and does not overlap with the antenna projection area or the strip module projection area. Furthermore, the chip module projection area does not overlap with the central axis. Specifically, it refers to the portion of the area formed by regions 1, 2-2, 3, 6, and 7 that does not overlap with regions 4, 5, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A6, A9, B11, and B8 that does not overlap with the projection area of ​​the strip module, line segment 9, and line segment 10. No embossing is set at this time.

[0100] Considering the first, fourth, second, and sixth constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the fourth bend area, and the horizontal and vertical central axes. Specifically, it is the area from the left edge of the horizontal support layer to the second bend cutoff line, and from the upper edge of the vertical support layer to the fourth bend cutoff line, and does not overlap with the antenna projection area or the strip module projection area. Furthermore, the chip module projection area does not overlap with the central axis. Specifically, it refers to the portion of the area formed by regions 1, 2-2, 3, and 5, and region 7, that does not overlap with regions 4, 6, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A1, A4, B6, and B3 that does not overlap with the projection area of ​​the strip module, line segment 9, or line segment 10. No embossing is set at this time.

[0101] Considering the first, fourth, second, and seventh constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the drag projection area, and the central axis; that is, the area from the vertical central axis to the second bend cutoff line and the upper and lower edges of the bearing layer, which does not overlap with the antenna projection area, and the chip module projection area does not overlap with the central axis. Specifically, this refers to the portion of the area formed by the aforementioned regions 1, 2-2, 5, and 6 that does not overlap with regions 4, 7, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...), Figure 2 , 2BThis refers to the area within the rectangle defined by A3, A4, B11, and B10 that does not overlap with line segments 9 and 10. Since the resistance projection area completely covers the first bending area, the aforementioned area is the same as in the cases considering the first, fourth, second, third, and seventh constraints. No embossing is applied at this time.

[0102] Considering the first, fourth, second, third, and fifth constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, the third bend area, and the central axis. Specifically, it is the area formed horizontally from the first bend cutoff line to the second bend cutoff line, and vertically from the third bend cutoff line to the lower edge of the support layer, and does not overlap with the antenna projection area or the strip module projection area. Furthermore, the chip module projection area does not overlap with the central axis. Specifically, this refers to the portion of the area formed by regions 1, 2-2, 6, and 7 that does not overlap with regions 3, 4, 5, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A7, A9, B11, and B9 that does not overlap with the projection area of ​​the strip module, line segment 9, or line segment 10. No embossing is set at this time.

[0103] Considering the first, fourth, second, third, and sixth constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, the fourth bend area, and the central axis. Specifically, it is the area formed horizontally from the first bend cutoff line to the second bend cutoff line, and vertically from the upper edge of the support layer to the fourth bend cutoff line, without overlapping with the antenna projection area and the strip module projection area, and the chip module projection area does not overlap with the central axis. Specifically, this refers to the portion of the area formed by regions 1, 2-2, 5, and 7 that does not overlap with regions 3, 4, 6, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A2, A4, B6, and B4 that does not overlap with the projection area of ​​the strip module, line segment 9, or line segment 10. No embossing is set at this time.

[0104] Considering the first, fourth, second, third, fifth, and sixth constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, the third bend area, the fourth bend area, and the central axis. Specifically, it is the area formed horizontally from the first bend cutoff line to the second bend cutoff line, and vertically from the third bend cutoff line to the fourth bend cutoff line, where it does not overlap with the antenna projection area or the strip module projection area, and the chip module projection area does not overlap with the central axis. Specifically, this refers to the portions of regions 1, 2-2, and 7 that do not overlap with regions 3, 4, 5, 6, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A7, A9, B6, and B4 that does not overlap with the projection area of ​​the strip module, line segment 9, or line segment 10. No embossing is set at this time.

[0105] Considering the first, fourth, second, third, fifth, and seventh constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the third bend area, and the drag projection area. Specifically, it is the area formed horizontally from the vertical central axis to the second bend cutoff line, and vertically from the third bend cutoff line to the lower edge of the support layer, without overlapping with the antenna projection area, and the chip module projection area does not intersect with the central axis. Specifically, it refers to the portion of the area formed by the aforementioned regions 1, 2-2, and 6 that does not overlap with regions 3, 4, 5, 7, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A8, A9, B11, and B10 that does not overlap with the projection area of ​​the strip module, line segment 9, and line segment 10. Since the resistance projection area completely covers the first bending area, the aforementioned area is the same as in the case considering the first, fourth, second, fifth, and seventh constraints. No embossing is applied at this time.

[0106] Considering the first, fourth, second, fifth, and sixth constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the third bend area, and the fourth bend area. Specifically, it is the area formed horizontally from the left edge of the support layer to the second bend cutoff line, and vertically from the third bend cutoff line to the fourth bend cutoff line, where it does not overlap with the antenna projection area or the strip module projection area, and the chip module projection area does not overlap with the central axis. Specifically, this refers to the portions of regions 1, 2-2, and 7 that do not overlap with regions 4, 5, 6, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A6, A9, B6, and B3 that does not overlap with the projection area of ​​the strip module, line segment 9, or line segment 10. No embossing is set at this time.

[0107] Considering the first, fourth, second, sixth, and seventh constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the fourth bend area, and the drag projection area. Specifically, it is the area formed horizontally from the vertical central axis to the second bend cutoff line, and vertically from the upper edge of the bearing area to the fourth bend cutoff line, that does not overlap with the antenna projection area, and the chip module projection area does not overlap with the central axis. Specifically, it refers to the portion of the area formed by the aforementioned regions 1, 2-2, and 5 that does not overlap with regions 3, 4, 6, 7, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A3, A4, B11, and B10 that does not overlap with the projection area of ​​the strip module, line segment 9, and line segment 10. No embossing is applied in this case. Since the resistance projection area completely covers the first bending area, the aforementioned area is the same as in the case considering the first, fourth, second, third, sixth, and seventh constraints. No embossing is applied in this case either.

[0108] Considering the first, fourth, third, and fifth constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, and the third bend area; that is, the area formed horizontally from the first bend cutoff line to the second bend cutoff line, and vertically from the third bend cutoff line to the lower edge of the carrier layer, and does not overlap with the antenna projection area and the strip module projection area. Specifically, it is the portion of the area formed by the aforementioned areas 1, 2-2, 6, and 7 that does not overlap with areas 3, 4, and 5. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A7, A9, B11, and B9 that does not overlap with the projected area of ​​the strip module. No embossing is set at this time.

[0109] Considering the first, fourth, third, and sixth constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, and the fourth bend area; that is, the area formed horizontally from the first bend cutoff line to the second bend cutoff line, and vertically from the upper edge of the carrier layer to the fourth bend cutoff line, and does not overlap with the antenna projection area and the strip module projection area. Specifically, it is the portion of the area formed by the aforementioned areas 1, 2-2, 5, and 7 that does not overlap with areas 3, 4, and 6. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A2, A4, B6, and B4 that does not overlap with the projected area of ​​the strip module. No embossing is set at this time.

[0110] Considering the first, fourth, third, fifth, and sixth constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, the third bend area, and the fourth bend area; that is, the area formed horizontally from the first bend cutoff line to the second bend cutoff line, and vertically from the third bend cutoff line to the fourth bend cutoff line, and does not overlap with the antenna projection area and the strip module projection area. Specifically, it refers to the portion of the area formed by the aforementioned areas 1, 2-2, and 7 that does not overlap with areas 3, 4, 5, and 6. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A7, A9, B6, and B4 that does not overlap with the projected area of ​​the strip module. No embossing is set at this time.

[0111] Considering the first, fourth, third, fifth, and seventh constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, the third bend area, and the drag projection area; that is, the area formed horizontally from the vertical central axis to the second bend cutoff line, and vertically from the third bend cutoff line to the lower edge of the support layer, which does not overlap with the antenna projection area. Specifically, it is the portion of the area formed by the aforementioned areas 1, 2-2, and 6 that does not overlap with areas 3, 4, 5, and 7. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A8, A9, B11, and B10 that does not overlap with the projected area of ​​the strip module. Since the resistance projection area completely covers the first bending area, the aforementioned area is the same as in the cases considering the first, fourth, fifth, and seventh constraints. No embossing is applied in this case.

[0112] Considering the first, fourth, third, sixth, and seventh constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the fourth bend area, and the drag projection area; that is, the area formed horizontally from the vertical central axis to the second bend cutoff line, and vertically from the upper edge of the support layer to the fourth bend cutoff line, which does not overlap with the antenna projection area. Specifically, it is the portion of the area formed by the aforementioned areas 1, 2-2, and 5 that does not overlap with areas 3, 4, 6, and 7. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A3, A4, B6, and B5 that does not overlap with the projected area of ​​the strip module. Since the resistance projection area completely covers the first bending area, the aforementioned area is the same as under the first, fourth, sixth, and seventh constraint conditions. No embossing is applied in this case.

[0113] Considering the first, fourth, third, fifth, sixth, and seventh constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the third bend area, the fourth bend area, and the drag projection area; that is, the area formed horizontally from the vertical central axis to the second bend cutoff line, and vertically from the third bend cutoff line to the fourth bend cutoff line, and does not overlap with the antenna projection area. Specifically, it is the area jointly formed by the aforementioned region 1 and region 2-2. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the rectangular area defined by A8, A9, B6, and B5. Since the resistance projection area completely covers the first bending area, the aforementioned area is the same as under the first, fourth, fifth, sixth, and seventh constraint conditions. No embossing is applied in this case.

[0114] Considering the first, fourth, fifth, and sixth constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the third bend area, and the fourth bend area; that is, the area formed horizontally from the left edge of the bearing area to the second bend cutoff line, and vertically from the third bend cutoff line to the fourth bend cutoff line, and does not overlap with the antenna projection area and the strip module projection area. Specifically, it is the portion of the area formed by the aforementioned areas 1, 2-2, 3, and 7 that does not overlap with areas 4, 5, and 6. For the antenna full-wrap scheme (see...),... Figure 2 , 2B ), that is, the area in the rectangle determined by A6, A9, B6, and B3 that does not overlap with the projection area of ​​the strip module.

[0115] When embossing exists, in addition to the constraints considered in each of the above embodiments, an eighth constraint also needs to be considered. That is, the chip module also needs to avoid the embossed projection area. Therefore, the preferred position of the chip module will change from the original embodiment. Specifically, the lower edge cutoff condition of the preferred position of the chip module is replaced with the "upper edge of the embossed projection area," a condition of not overlapping with region 8 is added, and region 2-2 is replaced with region 2-1. For example, when embossing exists, in addition to considering the first and fourth constraints, the eighth constraint also needs to be considered. That is, the chip module also needs to avoid the embossed projection area. The preferred position area of ​​the chip module projection area is: horizontally from the left edge of the carrier layer to the second bend cutoff line, and vertically from the upper edge of the carrier layer to the upper edge of the embossed projection area, the area that does not overlap with the antenna projection area and the strip module projection area. Specifically, it refers to the parts of regions 1, 2-1, 3, 5, 6, and 7 that do not overlap with regions 4 and 8. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the region within the rectangle defined by A1, A4, B2, and A13 that does not overlap with the projected area of ​​the strip module. Based on the first and fourth constraint conditions, combined with other constraint conditions and in embodiments with raised printing, the possible location areas for the chip module are shown in Table 5.

[0116] According to the aforementioned optimal implementation, when embossing exists, and all constraints from the first to the eighth are satisfied, the preferred location of the chip module projection area is the region where region 1 and region 2-1 do not overlap with line segments 9 and 10. Since the resistance projection area completely covers the first bending region, the aforementioned region is the same as the case considering the first, fourth, second, fifth, sixth, seventh, and eighth constraints. When embossing does not exist, and all constraints from the first to the seventh are satisfied, the preferred location of the chip module projection area is the region where region 1 and region 2-2 do not overlap with the region where line segments 9 and 10 overlap. Since the resistance projection area completely covers the first bending region, the aforementioned region is the same as the case considering the first, fourth, second, fifth, sixth, and seventh constraints.

[0117] In this embodiment of the invention, when the smart card includes a magnetic stripe, the multiple orthographic projection areas also include a magnetic stripe projection area, which is the orthographic projection area corresponding to the magnetic stripe mounting area of ​​the carrier layer. Preferably, the chip module projection area does not overlap with the magnetic stripe area; however, given the current magnetic stripe manufacturing process and the fact that magnetic stripe card swiping does not cause damage to the chip module, the chip module projection area and the magnetic stripe area may overlap. (Refer to...) Figure 2 As shown. When the manufacturing process or card-swiping method of the magnetic stripe may adversely affect the chip module, the magnetic stripe area will also become a constraint, and the chip module projection area should avoid the magnetic stripe area; when the chip module projection area overlaps with the magnetic stripe projection area, it is necessary to enhance the chip module's resistance to pressure and bending.

[0118] See Figure 2 This is a schematic diagram illustrating the preferred positions of the substrate layer chip modules corresponding to different / same-layer antenna full-wrap configurations in a dual-interface smart card according to a specific embodiment of the present invention. (See also...) Figure 2A This is a schematic diagram illustrating the preferred positions of antennas 2 / 3 or 3 / 4 around the corresponding substrate layer chip module in a dual-interface smart card according to a specific embodiment of the present invention.

[0119] See Figure 2B and Figure 4 This is a schematic diagram showing the preferred positions of the substrate layer chip modules corresponding to different layers of the dual-interface smart card and the antenna full-wrap, as described in a specific embodiment of the present invention. Combined with... Figure 2B It can be seen that when the antenna and the first connection structure are set on different layers, the embodiments of the present invention can allow the antenna projection area to overlap with the strip module projection area without affecting the normal use of the antenna and the strip module, while ensuring the preferred position of the chip module projection area. Figure 4FThe diagram shows a cross-section where the projection area of ​​the strip module overlaps with the antenna. Similarly, when the antenna and the first connecting structure are set in different layers, and the antenna is 3 / 4 or 2 / 3 wound, the projection area of ​​the antenna and the projection area of ​​the strip module can overlap, but this is not illustrated again.

[0120] See Figure 3 This is one of the schematic diagrams of the substrate layer structure corresponding to the dual-interface smart card winding-same-layer-antenna half-winding in a specific embodiment of the present invention. Due to the large diameter of the winding wire, when the antenna is set in the same layer as the first connection structure, the antenna cannot pass under the projection area of ​​the strip module; otherwise, the thickness of the dual-interface smart card would be insufficient or its reliability would be reduced. Therefore, the antenna avoids the projection area of ​​the strip module. Based on this, see [reference needed]. Figure 3A This is a schematic diagram of the preferred position of the substrate layer chip module corresponding to the dual-interface smart card winding-same-layer-antenna half-winding in a specific embodiment of the present invention.

[0121] See Figure 4 This is one of the schematic diagrams of the substrate layer structure corresponding to the antenna half-wrap of different layers in a dual-interface smart card according to a specific embodiment of the present invention. In this case, since the antenna and the first connection structure are on different layers, the antenna does not need to avoid the projection area of ​​the strip module; that is, the antenna projection area and the strip module projection area can overlap. Based on this, 4A shows the preferred position of the substrate layer chip module corresponding to the antenna half-wrap of different layers in a dual-interface smart card according to a specific embodiment of the present invention. Considering future product requirements, in the case of different layers, the antenna can also avoid the strip module projection area, see [reference]. Figure 4B That is, the antenna projection area and the strip module projection area do not overlap. Based on this, see [link to relevant documentation]. Figure 4C The preferred positions of the substrate layer chip modules corresponding to the antenna half-wrap of different layers in the dual-interface smart card of the present invention are shown.

[0122] It is worth noting that in the above-mentioned different schemes involving full antenna winding, 3 / 4 winding, 2 / 3 winding, or half winding, combined with the first link structure and the antenna winding line set on the same or different layers, the method for determining the preferred position of the corresponding chip module projection area is the same. That is, the corresponding position and avoidance range defined by the constraint conditions (Table 1), the relationship between each orthographic projection area and the constraint conditions (columns 1-2 of Table 3), and the range conditions and areas that the chip module can be set in (columns 1-3 of Table 4; the same applies to constraint conditions not fully listed in Table 4) are the same. The only difference between the schemes is in determining the characterization of each area (columns 3-6 of Table 3, columns 4-7 of Table 4). Specifically, for the case of full antenna winding, the constraint condition position is referenced... Figure 2 and 2B The characterization of each orthographic projection region is shown in column 3 of Table 3, and the characterization of the configurable positions of the chip module projection region is shown in column 4 of Table 4. For the 2 / 3 or 3 / 4 antenna-around case, the constraint positions are referenced... Figure 2AThe characterization of each orthographic projection area is shown in column 4 of Table 3, and the configurable positions and characterizations of the chip module projection area are shown in column 5 of Table 4. For the case where the antenna partially avoids the strip module projection area, the constraint positions are as follows... Figure 3A and 4C The characterization of each orthographic projection area is shown in column 5 of Table 3, and the configurable positions and characterizations of the chip module projection area are shown in column 6 of Table 4. For the case where the antenna partially surrounds the strip module projection area without avoiding it, the constraint positions are as follows... Figure 4A For the characterization of each orthographic projection area, please refer to column 6 of Table 3. For the settable positions and characterization of the chip module projection area, please refer to column 7 of Table 4.

[0123] Table 4 Constraints satisfied by the chip module location (without embossing)

[0124]

[0125]

[0126]

[0127]

[0128]

[0129]

[0130] Table 5. Constraints satisfied by the chip module location (with embossed markings)

[0131]

[0132]

[0133]

[0134]

[0135]

[0136]

[0137] Tables 4 and 5 above are an incomplete list of constraint conditions, in which...

[0138] *The areas listed in the settable range conditions for the chip module must exclude areas that overlap with the projection areas of the strip module and the antenna. At the same time, the excessively small area between the card edge and the outer edge of the antenna projection area when the antenna projection area is near the edge of the smart card, as well as the small area from the left side of the strip module projection area to the card edge when it is near the card edge, must also be excluded.

[0139] The configurable areas listed for the chip module must exclude areas that overlap with the strip module projection area and the antenna projection area. Also exclude excessively small areas between the card edge and the outer edge of the antenna projection area when the antenna projection area is near the edge of the smart card, as well as small areas from the left side of the strip module projection area to the card edge when it is near the card edge.

[0140] ***The regions listed for characterizing the all-around antenna configuration exclude areas overlapping with the strip module's projection area. See [link to documentation] for details. Figure 2 , 2B ;

[0141] For cases 2 / 3 or 3 / 4, the regions listed should exclude those overlapping with the projection region of the strip module. See [link to relevant documentation] for details. Figure 2A ;

[0142] *****The regions listed for characterizing the semi-wrap antenna's avoidance of the strip module's projection area must exclude areas overlapping with the strip module's projection area. See [link to documentation] for details. Figure 3A , 4C ;

[0143] The examples illustrating the situation where a semi-circular antenna does not avoid the projection area of ​​a strip module all exclude areas that overlap with the projection area of ​​the strip module. For details, please refer to [link to relevant documentation]. Figure 4A .

[0144] It should be understood that, based on the above-described corresponding positions, avoidance ranges, and orthographic projection area divisions of the constraint conditions, and on the basis of satisfying the avoidance strip module projection area and the antenna module projection area corresponding to the first constraint condition, the positions that can be set for the chip module projection area obtained by any combination of other constraint conditions are all within the scope of disclosure and protection of this invention.

[0145] It should be noted that, when considering the combination of constraints under the sixth constraint, if the vertical position of the fourth bend cutoff line corresponding to the sixth constraint is lower than the upper edge of the embossed projection area, that is, the embossed projection area completely covers the fourth bend area, the settable range conditions, area, and characteristics of the chip module projection area in the preferred embodiment of this application are shown in Table 5; at this time, whether or not the sixth constraint is considered will not affect the final set area of ​​the chip module projection area, but in order to correspond the constraints in Table 5 with those in Table 4, Table 5 also lists the cases considering the sixth constraint, so the final set area of ​​the chip module projection area will be the same in some cases in Table 5; when the vertical position of the fourth bend cutoff line corresponding to the sixth constraint is higher than the upper edge of the embossed projection area, that is, the fourth bend area completely covers the embossed projection area, the settable range conditions, area, and characteristics of the chip module projection area in the preferred embodiment of this application are shown in Table 4 in the case of the sixth constraint;

[0146] It should be noted that when the formula parameters for determining the position of the bend cutoff line change, the relationship between each bend cutoff line and the antenna projection area may change, thereby causing changes in the characterization of each projection area and the position and characterization of the chip module projection area. Furthermore, the above embodiments only show the specific areas where the chip module can be set under conventional winding methods; the shape of the antenna winding can be varied as needed. It should be understood that regardless of the relationship between the antenna projection area and the boundary lines of each area, or the shape of the antenna winding, the corresponding positions and avoidance ranges defined by the above-mentioned constraints, the relationship between each projection area and the constraints, and the range and area where the chip module can be set will not change. Based on the corresponding positions and avoidance ranges defined by the constraints, and combined with the setting of the constraints, the preferred position for setting the chip module can be obtained when the chip module does not overlap with the projection area of ​​the strip module and the constraint area, which is within the scope of the description, disclosure, and protection of this application.

[0147] The location of the chip module affects the positional relationship between the first connection structure and the antenna winding on the orthographic projection area of ​​the carrier layer. For the case where the antenna partially avoids the projection area of ​​the strip module, see [reference needed]. Figure 3B and Figure 4D When the chip module is located in the area inside the antenna winding (corresponding to respectively) Figure 3A The region comprised of A1, A5, B12, and B8. Figure 3A When connecting the first connection structure to the chip module (in the area consisting of A1, A5, B12, and B8), the first connection structure needs to cross the antenna winding. Preferably, the crossing point is located at an antenna bend or in an area with low antenna density to reduce mechanical stress damage caused by the overlap between the antenna and the first connection structure, thereby improving the reliability of the smart card; see also Figure 3C and Figure 4E When the chip module is located outside the antenna winding (respectively) Figure 3A The region formed by C6, C7, C13, and C12. Figure 4C When the area comprised of C6, C7, C13, and C12 is used, the first connection structure can connect to the chip module without crossing the antenna winding. However, some antenna leads will cross the antenna winding to connect the antenna terminals to the chip module. If the first connection structure is located outside the antenna winding area without crossing it, it should also not be placed in the embossed area to avoid damage from subsequent card embossing. Of course, in special designs, such as conductive metal foil etched antenna schemes, embossing damage can be overcome by widening the first connection structure. In this case, the first connection structure can be placed in the embossed area. This is a mature technology and will not be detailed here.

[0148] Correspondingly, for antennas with 2 / 3 or 3 / 4 windings, and for antennas with half-windings that do not avoid the projection area of ​​the strip module, when the antenna module is located inside the antenna winding, the first connection structure can connect to the chip module without crossing the antenna winding. However, some antenna leads will cross the antenna winding to connect the antenna terminals to the chip module. When the antenna module is located outside the antenna winding, the first connection structure needs to cross the antenna winding to connect to the chip module. Preferably, the crossing point is located at an antenna bend or in an area with low density to reduce mechanical stress damage caused by the overlap between the antenna and the first connection structure, thereby improving the reliability of the smart card. When the first connection structure crosses the antenna winding and is located outside the antenna winding area, it should also not be placed in the embossed area to avoid damage from subsequent card manufacturing embossing. Of course, in special designs, such as conductive metal foil etched antenna schemes, embossing damage can be overcome by widening the first connection structure, and the first connection structure can be placed in the embossed area. This scheme is a mature technology and will not be described in detail in this invention. These situations are not shown in the figures.

[0149] The dual-interface smart card of the present invention, based on all the above embodiments, further includes a supplementary support layer and a strip module on top of the substrate layer. The supplementary support layer is located on the outer surface of the dual-interface smart card and includes a first supplementary support layer and a second supplementary support layer, which are respectively pressed against the first and second surfaces of the substrate layer. The supplementary support layer can be made of materials such as PVC to form the upper and lower surfaces of the smart card, or other materials can be used; the embodiments of the present invention do not specifically limit this.

[0150] After the supplementary support layer is pressed and supported onto the smart card substrate layer, the strip module is installed in the strip module projection area. The strip module includes contact pads, a support layer, and multiple conductive pads arranged from top to bottom. By slotting the corresponding strip module projection area in the supplementary support layer and substrate layer to expose the terminals of the first connection structure, the strip module is installed in the strip module projection area. The conductive pads of the strip module are electrically connected to the matching first connection structure terminals in the substrate layer via anisotropic conductive adhesive or solder balls. The contact surface of the contact pads of the strip module is flush with the first surface of the supplementary support layer, i.e., located on the same plane. The contact surface of the contact pad refers to the surface of the contact pad that physically contacts an external terminal (e.g., a card reader) for communication. It is understood that the thickness of the support layer and conductive pads in the strip module can be adjusted according to process requirements.

[0151] It should be understood that the substrate layer of the dual-interface smart card in this application and the dual-interface smart card in the embodiments of this application have the same orthographic projection area on the target surface of the carrier layer, and the chip module can be set in a position that satisfies the constraints and combinations of constraints of all embodiments of the dual-interface smart card substrate layer described above.

Claims

1. A dual interface smart card substrate layer, characterized in that, include: The carrier layer, antenna winding, and chip module; Both the antenna winding and the chip module are carried by the carrier layer; Multiple orthographic projection areas are formed on the target surface of the carrier layer, including a strip module projection area, a chip module projection area, and an antenna projection area; the strip module projection area is the orthographic projection area corresponding to the strip module projection area of ​​the carrier layer, and the antenna projection area is the orthographic projection area corresponding to the antenna winding; the target surface of the carrier layer also includes a central axis, which includes a horizontal central axis and a vertical central axis; The projection areas of the chip module and the strip module do not overlap; The target surface of the bearing layer is one of the surfaces with the largest area of ​​the bearing layer; The position of the chip module projection area is determined based on target constraints in a preset set of constraints. These target constraints include a first constraint and a fourth constraint. The first constraint is that the chip module projection area avoids the antenna projection area. The fourth constraint is that the chip module projection area avoids a second bending area, which is the area between the right edge of the carrier layer and the second bending cutoff line. The distance between the second bending cutoff line and the right edge of the carrier layer is determined based on a first preset insertion length and a first preset radius of curvature for the card bending test. Along the horizontal central axis, the right edge of the carrier layer is the edge of the carrier layer furthest from the strip module projection area. The location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, and the second bending area, that is, the area formed from the left edge of the carrier layer to the second bending cutoff line and the upper and lower edges of the carrier layer, and does not overlap with the antenna projection area and the strip module projection area.

2. The dual-interface smart card substrate layer as described in claim 1, characterized in that, The target constraint also includes a second constraint, which is: the projection area of ​​the chip module avoids the central axis. The location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, and the horizontal and vertical central axes. That is, the area formed from the left edge of the bearing layer to the second bending cutoff line and the upper and lower edges of the bearing layer, the chip module projection area does not overlap with the antenna projection area and the strip module projection area, and the chip module projection area does not overlap with the central axis.

3. The dual-interface smart card substrate layer as described in claim 1, characterized in that, The target constraint also includes a third constraint: the chip module projection area avoids the first bending area, the first bending area is the area between the left edge of the carrier layer and the first bending cutoff line, and the distance between the first bending cutoff line and the left edge of the carrier layer is determined according to the second preset insertion length and the second preset radius of curvature of the card bending test; along the direction of the horizontal central axis, the left edge of the carrier layer is the edge of the carrier layer that is closest to the projection area of ​​the strip module; The location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area and the first bending area, that is, the area formed between the first bending cutoff line and the second bending cutoff line and the upper and lower edges of the bearing layer, and does not overlap with the antenna projection area and the strip module projection area.

4. The dual-interface smart card substrate layer as described in claim 1, characterized in that, The target constraint also includes a fifth constraint, which is: the chip module projection area avoids the third bending area, the third bending area is the area between the upper edge of the carrier layer and the third bending cutoff line, and the distance between the third bending cutoff line and the upper edge of the carrier layer is determined according to the third preset insertion length and the third preset radius of curvature of the card bending test; along the direction of the vertical central axis, the upper edge of the carrier layer is the edge of the carrier layer that is closest to the projection area of ​​the strip module; The location of the chip module projection area is defined as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, and the third bending area, that is, the area defined horizontally from the left edge of the carrier layer to the second bending cutoff line, and vertically from the third bending cutoff line to the lower edge of the carrier layer, and does not overlap with the antenna projection area and the strip module projection area.

5. The dual-interface smart card substrate layer as described in claim 1, characterized in that, The target constraint also includes a sixth constraint, which is: the chip module projection area avoids the fourth bending area, the fourth bending area is the area between the lower edge of the carrier layer and the fourth bending cutoff line, and the distance between the fourth bending cutoff line and the lower edge of the carrier layer is determined according to the fourth preset insertion length and the fourth preset radius of curvature of the card bending test; along the direction of the vertical central axis, the lower edge of the carrier layer is the edge of the carrier layer that is farthest from the projection area of ​​the strip module; The location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area and the fourth bending area, that is, the area formed in the horizontal direction from the left edge of the carrier layer to the second bending cutoff line, and in the vertical direction from the upper edge of the carrier layer to the fourth bending cutoff line, and does not overlap with the antenna projection area and the strip module projection area.

6. The dual-interface smart card substrate layer as described in claim 1, characterized in that, The target constraint condition also includes a seventh constraint condition, which is: the chip module projection area avoids the resistance projection area, and the resistance projection area is the half-region where the strip module projection area is located in the two half-regions obtained by dividing the target surface of the bearing layer through the vertical central axis. The location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area and the resistance projection area, that is, the area between the vertical central axis and the second bending cutoff line and the upper and lower edges of the bearing layer, and does not overlap with the antenna projection area.

7. The dual-interface smart card substrate layer as described in claim 2, characterized in that, The target constraint also includes a third constraint: the chip module projection area avoids the first bending area, the first bending area is the area between the left edge of the carrier layer and the first bending cutoff line, and the distance between the first bending cutoff line and the left edge of the carrier layer is determined according to the second preset insertion length and the second preset radius of curvature of the card bending test; along the direction of the horizontal central axis, the left edge of the carrier layer is the edge of the carrier layer that is closest to the projection area of ​​the strip module; The location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the first bending area, the horizontal central axis, and the vertical central axis. That is, the area formed between the first bending cutoff line and the second bending cutoff line and the upper and lower edges of the bearing layer, the chip module projection area does not overlap with the antenna projection area and the strip module projection area, and the chip module projection area does not overlap with the central axis.

8. The dual-interface smart card substrate layer as described in claim 2, characterized in that, The target constraint also includes a fifth constraint, which is: the chip module projection area avoids the third bending area, the third bending area is the area between the upper edge of the carrier layer and the third bending cutoff line, and the distance between the third bending cutoff line and the upper edge of the carrier layer is determined according to the third preset insertion length and the third preset radius of curvature of the card bending test; along the direction of the vertical central axis, the upper edge of the carrier layer is the edge of the carrier layer that is closest to the projection area of ​​the strip module; The location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the third bending area, the horizontal central axis, and the vertical central axis. That is, the area formed by the left edge of the bearing layer to the second bending cutoff line in the horizontal direction and the third bending cutoff line to the lower edge of the bearing layer in the vertical direction, and does not overlap with the antenna projection area and the strip module projection area, and the chip module projection area does not overlap with the central axis.

9. The dual-interface smart card substrate layer as described in claim 2, characterized in that, The target constraint also includes a sixth constraint, which is: the chip module projection area avoids the fourth bending area, the fourth bending area is the area between the lower edge of the carrier layer and the fourth bending cutoff line, and the distance between the fourth bending cutoff line and the lower edge of the carrier layer is determined according to the fourth preset insertion length and the fourth preset radius of curvature of the card bending test; along the direction of the vertical central axis, the lower edge of the carrier layer is the edge of the carrier layer that is farthest from the projection area of ​​the strip module; The location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the fourth bending area, and the horizontal and vertical central axes. That is, the area formed in the horizontal direction from the left edge of the bearing layer to the second bending cutoff line, and in the vertical direction from the upper edge of the bearing layer to the fourth bending cutoff line, does not overlap with the antenna projection area and the strip module projection area, and the chip module projection area does not overlap with the central axis.

10. The dual-interface smart card substrate layer as described in claim 2, characterized in that, The target constraint condition also includes a seventh constraint condition, which is: the chip module projection area avoids the resistance projection area, and the resistance projection area is the half-region where the strip module projection area is located in the two half-regions obtained by dividing the target surface of the bearing layer through the vertical central axis. The location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the resistance projection area, and the horizontal and vertical central axes, that is, the area from the vertical central axis to the second bending cutoff line and the upper and lower edges of the bearing layer, the area that does not overlap with the antenna projection area, and the chip module projection area does not overlap with the central axis.

11. The dual-interface smart card substrate layer as described in claim 7, characterized in that, The target constraint also includes a fifth constraint, which is: the chip module projection area avoids the third bending area, the third bending area is the area between the upper edge of the carrier layer and the third bending cutoff line, and the distance between the third bending cutoff line and the upper edge of the carrier layer is determined according to the third preset insertion length and the third preset radius of curvature of the card bending test; along the direction of the vertical central axis, the upper edge of the carrier layer is the edge of the carrier layer edge from which the strip module projection area is closest; The location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the first bending area, the third bending area, the horizontal central axis, and the vertical central axis. That is, the area formed in the horizontal direction from the first bending cutoff line to the second bending cutoff line, and in the vertical direction from the third bending cutoff line to the lower edge of the bearing layer, is an area that does not overlap with the antenna projection area and the strip module projection area, and the chip module projection area does not overlap with the central axis.

12. The dual-interface smart card substrate layer as described in claim 7, characterized in that, The target constraint also includes a sixth constraint, which is: the chip module projection area avoids the fourth bending area, the fourth bending area is the area between the lower edge of the carrier layer and the fourth bending cutoff line, and the distance between the fourth bending cutoff line and the lower edge of the carrier layer is determined according to the fourth preset insertion length and the fourth preset radius of curvature of the card bending test; along the direction of the vertical central axis, the lower edge of the carrier layer is the edge of the carrier layer that is farthest from the projection area of ​​the strip module; The location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the first bending area, the fourth bending area, and the horizontal and vertical central axes. That is, the area formed in the horizontal direction from the first bending cutoff line to the second bending cutoff line, and in the vertical direction from the upper edge of the bearing layer to the fourth bending cutoff line, is an area that does not overlap with the antenna projection area and the strip module projection area, and the chip module projection area does not overlap with the central axis.

13. The dual-interface smart card substrate layer as described in claim 8, characterized in that, The target constraint also includes a sixth constraint, which is: the chip module projection area avoids the fourth bending area, the fourth bending area is the area between the lower edge of the carrier layer and the fourth bending cutoff line, and the distance between the fourth bending cutoff line and the lower edge of the carrier layer is determined according to the fourth preset insertion length and the fourth preset radius of curvature of the card bending test; along the direction of the vertical central axis, the lower edge of the carrier layer is the edge of the carrier layer that is farthest from the projection area of ​​the strip module; The location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the third bending area, the fourth bending area, and the horizontal and vertical central axes. That is, the area formed in the horizontal direction from the left edge of the bearing layer to the second bending cutoff line, and in the vertical direction from the third bending cutoff line to the fourth bending cutoff line, is an area that does not overlap with the antenna projection area and the strip module projection area, and the chip module projection area does not overlap with the central axis.

14. The dual-interface smart card substrate layer as described in claim 8, characterized in that, The target constraint condition also includes a seventh constraint condition, which is: the chip module projection area avoids the resistance projection area, and the resistance projection area is the half-region where the strip module projection area is located in the two half-regions obtained by dividing the target surface of the bearing layer through the vertical central axis. The location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the third bending area, the resistance projection area, and the horizontal and vertical central axes. That is, the area formed in the horizontal direction from the vertical central axis to the second bending cutoff line, and in the vertical direction from the third bending cutoff line to the lower edge of the bearing layer, does not overlap with the antenna projection area, and the chip module projection area does not overlap with the central axis.

15. The dual-interface smart card substrate layer as described in claim 9, characterized in that, The target constraint condition also includes a seventh constraint condition, which is: the chip module projection area avoids the resistance projection area, and the resistance projection area is the half-region where the strip module projection area is located in the two half-regions obtained by dividing the target surface of the bearing layer through the vertical central axis. The location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the fourth bending area, the resistance projection area, and the horizontal and vertical central axes. That is, the area formed in the horizontal direction from the vertical central axis to the second bending cutoff line, and in the vertical direction from the upper edge of the bearing layer to the fourth bending cutoff line, does not overlap with the antenna projection area, and the chip module projection area does not overlap with the central axis.

16. The dual-interface smart card substrate layer as described in claim 11, characterized in that, The target constraint also includes a sixth constraint, which is: the chip module projection area avoids the fourth bending area, the fourth bending area is the area between the lower edge of the carrier layer and the fourth bending cutoff line, and the distance between the fourth bending cutoff line and the lower edge of the carrier layer is determined according to the fourth preset insertion length and the fourth preset radius of curvature of the card bending test; along the direction of the vertical central axis, the lower edge of the carrier layer is the edge of the carrier layer that is farthest from the projection area of ​​the strip module; The location of the chip module projection area is defined as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, the third bend area, the fourth bend area, and the horizontal and vertical central axes. That is, the area formed in the horizontal direction from the first bend cutoff line to the second bend cutoff line, and in the vertical direction from the third bend cutoff line to the fourth bend cutoff line, does not overlap with the antenna projection area and the strip module projection area, and the chip module projection area does not overlap with the central axis.

17. The dual-interface smart card substrate layer as described in claim 13, characterized in that, The target constraint condition also includes a seventh constraint condition, which is: the chip module projection area avoids the resistance projection area, and the resistance projection area is the half-region where the strip module projection area is located in the two half-regions obtained by dividing the target surface of the bearing layer through the vertical central axis. The location of the chip module projection area is defined as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the third bend area, the fourth bend area, the drag projection area, and the horizontal and vertical central axes. Specifically, it is the area formed horizontally from the vertical central axis to the second bend cutoff line, and vertically from the third bend cutoff line to the fourth bend cutoff line, and does not overlap with the antenna projection area. Furthermore, the chip module projection area does not overlap with the central axis.

18. The dual-interface smart card substrate layer as described in claim 3, characterized in that, The target constraint also includes a fifth constraint, which is: the chip module projection area avoids the third bending area, the third bending area is the area between the upper edge of the carrier layer and the third bending cutoff line, and the distance between the third bending cutoff line and the upper edge of the carrier layer is determined according to the third preset insertion length and the third preset radius of curvature of the card bending test; along the direction of the vertical central axis, the upper edge of the carrier layer is the edge of the carrier layer that is closest to the projection area of ​​the strip module; The location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the first bending area, and the third bending area, that is, the area formed in the horizontal direction from the first bending cutoff line to the second bending cutoff line, and in the vertical direction from the third bending cutoff line to the lower edge of the bearing layer, and does not overlap with the antenna projection area and the strip module projection area.

19. The dual-interface smart card substrate layer as described in claim 3, characterized in that, The target constraint also includes a sixth constraint, which is: the chip module projection area avoids the fourth bending area, the fourth bending area is the area between the lower edge of the carrier layer and the fourth bending cutoff line, and the distance between the fourth bending cutoff line and the lower edge of the carrier layer is determined according to the fourth preset insertion length and the fourth preset radius of curvature of the card bending test; along the direction of the vertical central axis, the lower edge of the carrier layer is the edge of the carrier layer that is farthest from the projection area of ​​the strip module; The location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the first bending area, and the fourth bending area, that is, the area formed in the horizontal direction from the first bending cutoff line to the second bending cutoff line, and in the vertical direction from the upper edge of the bearing layer to the fourth bending cutoff line, and does not overlap with the antenna projection area and the strip module projection area.

20. The dual-interface smart card substrate layer as described in claim 18, characterized in that, The target constraint also includes a sixth constraint, which is: the chip module projection area avoids the fourth bending area, the fourth bending area is the area between the lower edge of the carrier layer and the fourth bending cutoff line, and the distance between the fourth bending cutoff line and the lower edge of the carrier layer is determined according to the fourth preset insertion length and the fourth preset radius of curvature of the card bending test; along the direction of the vertical central axis, the lower edge of the carrier layer is the edge of the carrier layer that is farthest from the projection area of ​​the strip module; The location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the first bending area, the third bending area, and the fourth bending area, that is, the area formed in the horizontal direction from the first bending cutoff line to the second bending cutoff line, and in the vertical direction from the third bending cutoff line to the fourth bending cutoff line, and does not overlap with the antenna projection area and the strip module projection area.

21. The dual-interface smart card substrate layer as described in claim 4, characterized in that, The target constraint also includes a sixth constraint, which is: the chip module projection area avoids the fourth bending area, the fourth bending area is the area between the lower edge of the carrier layer and the fourth bending cutoff line, and the distance between the fourth bending cutoff line and the lower edge of the carrier layer is determined according to the fourth preset insertion length and the fourth preset radius of curvature of the card bending test; along the direction of the vertical central axis, the lower edge of the carrier layer is the edge of the carrier layer that is farthest from the projection area of ​​the strip module; The location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the third bending area, and the fourth bending area, that is, the area formed in the horizontal direction from the left edge of the bearing layer to the second bending cutoff line, and in the vertical direction from the third bending cutoff line to the fourth bending cutoff line, and does not overlap with the antenna projection area and the strip module projection area.

22. The dual-interface smart card substrate layer as described in claim 4, characterized in that, The target constraint condition also includes a seventh constraint condition, which is: the chip module projection area avoids the resistance projection area, and the resistance projection area is the half-region where the strip module projection area is located in the two half-regions obtained by dividing the target surface of the bearing layer through the vertical central axis. The location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the third bending area and the resistance projection area, that is, the area formed in the horizontal direction from the vertical central axis to the second bending cutoff line, and in the vertical direction from the third bending cutoff line to the lower edge of the bearing layer, and does not overlap with the antenna projection area.

23. The dual-interface smart card substrate layer as described in claim 21, characterized in that, The target constraint condition also includes a seventh constraint condition, which is: the chip module projection area avoids the resistance projection area, and the resistance projection area is the half-region where the strip module projection area is located in the two half-regions obtained by dividing the target surface of the bearing layer through the vertical central axis. The location area of ​​the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the third bending area, the fourth bending area, and the resistance projection area, that is, the area formed in the horizontal direction from the vertical central axis to the second bending cutoff line, and in the vertical direction from the third bending cutoff line to the fourth bending cutoff line, and does not overlap with the antenna projection area.

24. The dual-interface smart card substrate layer as described in claim 5, characterized in that, The target constraint condition also includes a seventh constraint condition, which is: the chip module projection area avoids the resistance projection area, and the resistance projection area is the half-region where the strip module projection area is located in the two half-regions obtained by dividing the target surface of the bearing layer through the vertical central axis. The location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, the fourth bending area and the resistance projection area, that is, the area formed in the horizontal direction from the vertical central axis to the second bending cutoff line, and in the vertical direction from the upper edge of the bearing layer to the fourth bending cutoff line, and does not overlap with the antenna projection area.

25. The dual-interface smart card substrate layer as described in any one of claims 1-24, characterized in that, The distance between the second bend cutoff line and the right edge of the bearing layer L1 The following formula is used for calculation: L1=l 1 +r 1 ×π×1 / 2 ,in, l 1 The first preset insertion length, r 1 The first preset radius of curvature.

26. The dual-interface smart card substrate layer as described in any one of claims 3, 7, 11, 12, 16, 18-20, characterized in that, The distance between the first bend cutoff line and the right edge of the bearing layer L2 The following formula is used for calculation: L2=l 2 +r 2 ×π×1 / 2 ,in, l 2 The second preset insertion length, r 2 This is the second preset radius of curvature.

27. The dual-interface smart card substrate layer as described in claim 25 or 26, characterized in that, The first preset insertion length range or the second preset insertion length range is 1-3mm, and the first preset radius of curvature or the second preset radius of curvature ranges from 5mm to 20mm.

28. The dual-interface smart card substrate layer as described in any one of claims 4, 8, 11, 13, 14, 16-18, and 20-23, characterized in that, The distance between the third bend cutoff line and the right edge of the bearing layer L3 The following formula is used for calculation: L3=l 3 +r 3 ×π×1 / 2 ,in, l 3 The third preset insertion length, r 3 The third preset radius of curvature.

29. The dual-interface smart card substrate layer as described in any one of claims 5, 9, 12, 13, 15-17, 19-21, 23, and 24, characterized in that, The distance between the fourth bend cutoff line and the right edge of the bearing layer L4 The following formula is used for calculation: L4=l 4 +r 4 ×π×1 / 2 ,in, l 4 The fourth preset insertion length, r 4 This is the fourth preset radius of curvature.

30. The dual-interface smart card substrate layer as described in claim 28 or 29, characterized in that, The third or fourth preset insertion length range is 1-3mm, and the third or fourth preset radius of curvature ranges from 5mm to 15mm.

31. The dual-interface smart card substrate layer as described in any one of claims 1-30, characterized in that, The target constraint condition also includes an eighth constraint condition, which is: when there is embossing, the projection area of ​​the chip module avoids the embossed projection area, and the embossed projection area is the orthographic projection area corresponding to the embossed area of ​​the carrier layer. The projection area of ​​the chip module also avoids the embossed projection area.

32. A dual-interface smart card, characterized in that, Includes a strip module and a dual-interface smart card substrate layer as described in any one of claims 1-31; The strip module is carried by the dual-interface smart card substrate layer.

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