Coding method and device, decoding method and device, equipment and storage medium

Abstract

The invention discloses a coding method and device, a decoding method and device, equipment and a storage medium, and belongs to the technical field of communication. The coding method comprises the following steps: acquiring an information bit sequence; encoding the information bit sequence by using a GLDPC code as an inner code and a polarization code as an outer code to obtain a cascade encoding codeword, the cascade encoding codeword comprising a plurality of sub-codes, and each of the plurality of sub-codes being an algebraic geometric code; and outputting the cascaded coding codeword. The coding and decoding method is beneficial to improving the performance of the cascaded codes and improving the reliability of a coding and decoding system.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to an encoding method and apparatus, a decoding method and apparatus, a device, and a storage medium. Background Technology

[0002] In channel coding techniques, concatenated codes can achieve higher coding gain and lower decoding latency. Concatenated codes typically consist of an inner code and an outer code. The inner code can efficiently correct most errors in the physical channel, and then the outer code corrects residual errors, thereby meeting the requirements of high-speed, low-error-rate communication.

[0003] In related technologies, the transmitting end encodes the information bit sequence to be encoded using low-density parity-check (LDPC) code as the inner code and polar code as the outer code, and then obtains the encoded codeword. The receiving end receives the channel received soft information, decodes the channel received soft information, and obtains the decoded information bit sequence.

[0004] In this encoding and decoding method, the limited error correction capability of LDPC codes results in limited encoding and decoding performance. Summary of the Invention

[0005] This application provides an encoding method and apparatus, a decoding method and apparatus, a device, and a storage medium, which can improve the error correction capability of codewords and reduce the bit error rate of data transmission.

[0006] In a first aspect, an encoding method is provided, the encoding method comprising: acquiring an information bit sequence; encoding the information bit sequence with a generalized low-density parity check (GLDPC) code as the inner code and a polar code as the outer code to obtain a concatenated encoded codeword, wherein the GLDPC code includes multiple sub-codes, each of the multiple sub-codes being an algebraic geometric code; and outputting the concatenated encoded codeword.

[0007] In this application, GLDPC codes are used as the inner code and polar codes as the outer code to encode the information bit sequence. Since GLDPC codes have stronger error correction capabilities compared to LDPC codes, the encoding method of this application embodiment can improve the reliability of the encoding and decoding system. Furthermore, using polar codes as the outer code can effectively utilize the soft information output during the GLDPC code decoding process, thereby improving the performance of the concatenated code.

[0008] Optionally, the GLDPC code can be either a block code or a convolutional code. During implementation, the type of GLDPC code can be flexibly selected according to actual needs. For example, a block code can be used for packet transmission scenarios, while a convolutional code can be used for continuous communication scenarios (i.e., communication duration is long, such as more than a day).

[0009] When the GLDPC code is a block code, the encoding of the information bit sequence with GLDPC as the inner code and polar code as the outer code includes: first, polar code encoding the information bit sequence to obtain a first coded codeword; then, interleaving the first coded codeword to obtain a second coded codeword; and finally, GLDPC code encoding the second coded codeword to obtain the concatenated coded codeword.

[0010] When the GLDPC code is a convolutional code, the encoding of the information bit sequence using the GLDPC code as the inner code and the polar code as the outer code includes: generating N blocks to be encoded based on the information bit sequence, wherein the information bit sequence includes N subsequences, each subsequence including multiple bits in consecutive positions in the information bit sequence, and in the first N-1 blocks to be encoded, each block to be encoded includes X1 information bits and X2 overhead bits, wherein the X1 information bits of each block to be encoded in the first N-1 blocks to be encoded... The information bits belong to one of the N subsequences. The X2 overhead bits in the i-th block to be encoded are obtained by encoding all bits in the (i-1)-th block to be encoded and the X1 information bits in the i-th block to be encoded, where X1, X2, and i are all integers greater than 1. The information bits in the N blocks to be encoded are polar-coded to obtain the first codeword. The first codeword is interleaved to obtain the second codeword. The second codeword is GLDPC-coded to obtain the concatenated codeword.

[0011] In both implementations, by setting an interleaver between the internal code encoding and the external code encoding, the adverse effects of sudden errors in the internal code decoding result can be reduced, thereby improving the reliability of the decoding result.

[0012] Optionally, the first encoded codeword includes multiple bit groups, each bit group including y consecutive bits in the first encoded codeword, where y is greater than 1 and y is an integer. The interleaving of the first encoded codeword to obtain the second encoded codeword includes: cyclically shifting each of the multiple bit groups to obtain the second encoded codeword, wherein the shift bits for different bit groups are different. This interleaving method is simple and easy to implement.

[0013] Secondly, a decoding method is provided, comprising: receiving a channel soft information sequence; decoding the channel soft information sequence using an iterative decoding technique of an inner code to obtain a first decoding result, wherein the inner code is a generalized low-density parity-check (GLDPC) code, the GLDPC code includes multiple sub-codes, each of the multiple sub-codes being an algebraic geometric code; and performing outer code decoding based on the first decoding result to obtain a second decoding result, wherein the outer code is a polar code.

[0014] Optionally, the first decoding result includes a hard decision result and a shutdown flag of the channel soft information sequence. The shutdown flag includes multiple flag bits, each corresponding one-to-one with one of the multiple subcodes. Each flag bit is used to indicate whether the corresponding subcode was correctly decoded when the hard decision result was generated. The external code decoding based on the first decoding result includes: generating an output soft information sequence based on the hard decision result and the shutdown flag. The output soft information sequence includes multiple soft values, each corresponding one-to-one with a hard decision bit in the hard decision result, wherein the magnitude of each soft value is related to the shutdown flag associated with the hard decision bit corresponding to that soft value; and performing external code decoding based on the output soft information sequence.

[0015] When decoding external codes, effectively utilizing the soft information of internal codes to iteratively decode the hard decision results and shutdown flags output can improve the accuracy of decoding.

[0016] Optionally, generating the output soft information sequence based on the hard decision result and the shutdown flag includes: generating the soft value corresponding to each hard decision bit in the hard decision result in the following manner: obtaining the identifier bit corresponding to the subcode where the first bit is located, where the first bit is any hard decision bit in the hard decision result; when there is an identifier bit among the identifier bits corresponding to the subcode where the first bit is located that indicates correct decoding, determining the soft value corresponding to the first bit as the first soft value; or, when all the identifier bits corresponding to the subcode where the first bit is located are identifier bits that indicate incorrect decoding, determining the soft value corresponding to the first bit as the second soft value; wherein, the absolute value of the second soft value is less than the absolute value of the first soft value.

[0017] When the flag bit indicates correct decoding, it means that the hard decision result of the corresponding subcode is highly reliable. In this case, the corresponding first soft value is larger. When the flag bit indicates incorrect decoding, it means that the hard decision result of the corresponding subcode is relatively unreliable. In this case, the corresponding second soft value is smaller.

[0018] Optionally, the first soft value is equal to the product of the first coefficient and the difference between twice the bit value of the first bit and 1; the second soft value is equal to the product of the second coefficient and the difference between twice the bit value of the first bit and 1, wherein the first coefficient is greater than the second coefficient. This method of determining the soft value corresponding to the hard decision bit is simple and has low implementation complexity.

[0019] Optionally, the method further includes: establishing a channel model based on the output soft information; and determining the set of frozen bit positions and the set of information bit positions for the outer code encoding based on the channel model. Determining the set of frozen bit positions and the set of information bit positions for the outer code encoding based on the output soft information during the inner code decoding process is beneficial for improving the performance of concatenated coding.

[0020] Thirdly, an encoding apparatus is provided, which has the function of implementing the method described in the first aspect or any of the alternative embodiments of the first aspect. The function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described function.

[0021] Fourthly, a decoding apparatus is provided, which has the function of implementing the method described in the second aspect or any of the alternative methods of the second aspect. The function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described function.

[0022] Fifthly, a computer device is provided, the computer device including a processor and a memory; the processor is configured to execute instructions stored in the memory to cause the computer device to perform the methods described in the first or second aspect above.

[0023] Optionally, the processor may be one or more, and the processor may be a multi-core processor, and the memory may be one or more.

[0024] Optionally, the memory may be integrated with the processor, or the memory may be separated from the processor.

[0025] In the specific implementation process, the memory can be a non-transitory memory, such as read-only memory (ROM), which can be integrated with the processor on the same chip or set on different chips. This application does not limit the type of memory or the way the memory and processor are set.

[0026] In a sixth aspect, a computer-readable storage medium is provided, the storage medium storing at least one instruction, the instruction being loaded and executed by a computer device to cause the computer device to implement the method of the first or second aspect described above.

[0027] In a seventh aspect, a computer program (product) is provided, the computer program (product) comprising: computer program code, wherein when the computer program code is run by a computer device, the computer device performs the method described in the first or second aspect above.

[0028] Eighthly, a communication system is provided, the communication system comprising: a transmitting device and a receiving device, the transmitting device being configured to implement the method in the first aspect above, and the receiving device being configured to implement the method in the second aspect above; the transmitting device includes the encoding device in the third aspect above, and the receiving device includes the decoding device in the fourth aspect above.

[0029] In a ninth aspect, a chip is provided, the chip including a processor and a communication interface. The processor is configured to execute instructions to cause the chip to perform the encoding method described in the first aspect, or to perform the decoding method described in the second aspect. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of a communication system provided in an embodiment of this application;

[0031] Figure 2 This is a flowchart illustrating an encoding method provided in an embodiment of this application;

[0032] Figure 3 This is a schematic diagram of a product code provided in an embodiment of this application;

[0033] Figure 4 This is a flowchart illustrating another encoding method provided in an embodiment of this application;

[0034] Figure 5 This is a schematic diagram of the ladder code provided in the embodiments of this application;

[0035] Figure 6 This is a flowchart illustrating a decoding method provided in an embodiment of this application;

[0036] Figure 7 This is a schematic diagram of the structure of an encoding device provided in an embodiment of this application;

[0037] Figure 8 This is a schematic diagram of the structure of a decoding device provided in an embodiment of this application;

[0038] Figure 9This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0039] To facilitate understanding of the embodiments of this application, some technical terms involved in the embodiments of this application will be explained below.

[0040] Concatenated codes: For systems with multiple encodings, each level of encoding is considered as a single, unified code, which is called a concatenated code. In the embodiments of this application, the concatenated code is obtained by concatenating inner and outer codes.

[0041] Block coding: A binary information sequence is divided into fixed-length blocks, resulting in multiple message blocks, each consisting of k bits. Each message block is denoted as u. The encoder converts the input message block u into an n-dimensional binary vector v according to certain rules, where n > k. v is called the codeword of u, and the codeword has a total of 2^k bits. k These two k A set of codewords is a block code, and there is a one-to-one correspondence between message block u and codeword u.

[0042] Convolutional codes: A code segment consisting of k bits is encoded into an n-bit code group. The overhead bits generated by this encoding are related not only to the k bits of information but also to the m preceding bits of information. Here, m is a positive integer.

[0043] Subcode: also known as component code, is a short block code used to construct composite long codes in a structured manner.

[0044] Codeword: A codeword can include multiple rows and columns of bits. A column or a row of bits can form a subcode. That is, a codeword includes multiple subcodes, and each subcode includes multiple bits. Bits belonging to the same subcode are located in the same row or column of a codeword.

[0045] GLDPC codes are a conceptual extension of standard LDPC codes. LDPC codes use single bitparity check (SPC) codes as the component codes (i.e., subcodes) of the check node, while GLDPC codes use BCH (Bose Ray-Chaudhuri Hocquenghem) codes, Hamming codes, Reed Solomon (RS) codes, etc., as the component codes of the check node. Because these codes have better error correction and detection performance than SPC codes, GLDPC codes have higher error correction capabilities than standard LDPC codes.

[0046] Polar code: A type of linear block code that relies on polarization. Polarization allows bit positions to be ordered in a reliable order.

[0047] Staircase code: The subcodes defined in the ITU-T G.975.1 standard are two-dimensional convolutional codes that use algebraic geometric codes.

[0048] Interleaving: A processing method that transforms the order of a data sequence.

[0049] Shutdown flag: Used to indicate whether several subcodes in a long code need to be decoded in the current iteration of decoding.

[0050] Soft-decision decoding refers to a decoding process where each bit of data input to the decoder is represented by a floating-point value or a fixed-point value quantized into multiple possible values. The sign of this value indicates whether the bit is 0 or 1, and the absolute value indicates the reliability of the value. This input data is called soft information (or soft value), meaning it includes both the numerical value and the sign of the value. The decoder calculates and updates the soft information during the decoding process, and ultimately outputs the hard information.

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0052] This application provides an encoding and decoding method and apparatus that can be applied to various communication systems, especially fiber optic communication systems, such as long-distance wavelength division multiplexing (WDM) systems, passive optical network (PON) systems, metropolitan area networks, high-speed data centers, and other scenarios requiring low bit error rates.

[0053] Figure 1 This is a schematic diagram of the structure of a communication system provided in an embodiment of this application. For example... Figure 1 As shown, the communication system includes a transmitting device and a receiving device. The transmitting device encodes the information bit sequence using GLDPC code as the inner code and polar code as the outer code to obtain multiple concatenated coded codewords, and transmits these multiple concatenated coded codewords. These multiple concatenated coded codewords are transmitted as a code stream through the channel to the receiving device. The receiving device receives the channel output, which is the channel soft information sequence, and decodes the received soft information sequence to obtain the decoding result.

[0054] The transmitting device can be called an encoding device or a transmitting end, and the receiving device can be called a decoding device or a receiving end. In the embodiments of this application, the means for implementing the function of the transmitting device can be an optical communication device, or the means for implementing the function of the transmitting device can be a chip or a chip system; the means for implementing the function of the receiving device can be an optical communication device, or the means for implementing the function of the receiving device can be a chip or a chip system. The chip system includes multiple chips, or the chip system includes at least one chip and other discrete components.

[0055] The following describes the encoding method used by the transmitting device and the decoding method used by the receiving device.

[0056] This application provides an encoding method, comprising: acquiring an information bit sequence; encoding the information bit sequence using GLDPC code as the inner code and polar code as the outer code to obtain a concatenated coded codeword, the concatenated coded codeword comprising multiple sub-codes, each of which is an algebraic geometric code; and outputting the concatenated coded codeword. Correspondingly, this application also provides a decoding method, comprising: receiving a channel soft information sequence, the channel soft information sequence being obtained after the concatenated coded codeword has been transmitted through a channel; decoding the channel soft information sequence using an iterative decoding technique of the inner code to obtain a first decoding result, the inner code being a GLDPC code, the GLDPC code comprising multiple sub-codes, each of which is an algebraic geometric code; and performing outer code decoding based on the first decoding result to obtain a second decoding result, the outer code being a polar code.

[0057] Figure 2 This is a flowchart illustrating an encoding method provided in an embodiment of this application. This method can be executed by the aforementioned transmitting device. Figure 2 As shown, the encoding method includes:

[0058] 201: Obtain the information bit sequence.

[0059] The information bit sequence is a binary sequence to be encoded, and the length of the information bit sequence is k1, that is, the information bit sequence includes k1 bits.

[0060] In some examples, the information bit sequence includes data bits and check bits; in other examples, the information bit sequence includes only data bits and no check bits. Here, data bits refer to the bits used to carry information. Check bits refer to the bits used to verify the data bits, including but not limited to cyclic redundancy check (CRC) bits.

[0061] 202: Polar code encoding is performed on the information bit sequence to obtain the first coded codeword.

[0062] Here, the first encoded codeword can also be called the external codeword or the polar codeword. The length of the first encoded codeword can be n1, that is, the first encoded codeword includes n1 bits. Here, n1 and k1 are both integers, and n1 is greater than k1. Among the n1 bits, there are n1-k1 overhead bits and k1 information bits.

[0063] In some examples, the first encoded codeword can be in the form of a binary sequence.

[0064] In other examples, the first encoded codeword can be in matrix form. For instance, the n1 bits in the first encoded codeword are arranged in K2 rows and K1 columns, where K1 and K2 are both integers, and the product of K1 and K2 is equal to n1.

[0065] The first coded codeword in matrix form can be obtained as follows: after polar coding the information bit sequence, the first coded bit sequence is obtained; the first coded bit sequence is grouped according to the bit position to obtain multiple groups, each group including multiple bits with adjacent bit positions, and each group contains the same number of bits; each group is used as a row or column of a matrix to obtain the first coded codeword in matrix form.

[0066] For example, assuming the first encoded bit sequence consists of 64 bits, grouped into sets of 16 bits, a 4x16 matrix or a 16x4 matrix can be obtained. As another example, assuming the first encoded bit sequence consists of 64 bits, grouped into sets of 8 bits, an 8x8 matrix can be obtained.

[0067] In 202, the information bit sequence is polar-coded based on the set of frozen bit positions and the set of information bit positions of the polar code.

[0068] The set of frozen bit positions and the set of information bit positions for the polar code are predetermined before executing the method. Optionally, a channel model can be established based on the output soft information during the internal code decoding process, and then the set of frozen bit positions and the set of information bit positions for the polar code can be determined based on this channel model. The relevant content regarding the output soft information is described below.

[0069] 203: Interleave the first codeword to obtain the second codeword.

[0070] Since burst errors inevitably occur in the decoding results of the internal code, an interleaver is generally set between the internal code encoding and the external code encoding to improve the reliability of the decoding results.

[0071] In one possible implementation, for the first encoded codeword in matrix form, interleaving can be performed in step 203 by cyclically shifting each bit group of the first encoded codeword, with different shift numbers for different bit groups. This interleaving method is simple and easy to implement.

[0072] For example, suppose the first encoded codeword is a matrix with K2 rows and K1 columns, where each row corresponds to one of the aforementioned bit groups, and the number of shifts corresponding to the i-th row is either i or i-1. Here, i is an integer, greater than 0 and less than K1.

[0073] This application does not limit the interleaving method, as long as the j-th bit in each bit group is distributed non-equally in the first coded bit sequence corresponding to the first coded codeword. Here, j is an integer, and j is less than or equal to the number of bits contained in each bit group, i.e., less than or equal to K2.

[0074] 204: Encode the second codeword using GLDPC code to obtain the concatenated codeword.

[0075] GLDPC codes consist of multiple subcodes, each of which is an algebraic geometric code. These algebraic geometric codes include, but are not limited to, BCH codes, Hamming codes, or RS codes.

[0076] The length of the concatenated codeword can be n2, where n2 is an integer and greater than n1. Here, n2-n1 represents the overhead generated by the GLDPC code encoding.

[0077] This can be achieved by using the aforementioned steps 202-204, which encode the information bit sequence using GLDPC code as the inner code and polar code as the outer code to obtain concatenated codewords.

[0078] Optionally, the GLDPC code is a block code, and the type of GLDPC code can be flexibly selected according to actual needs during implementation.

[0079] In one possible implementation, the GLDPC code is a turbo product code (TPC) code. A product code is a block code, as shown in the image below. Figure 3 As shown, the product code includes multiple horizontal subcodes 3a and multiple vertical subcodes 3b. The horizontal subcodes 3a are first-generation algebraic geometric codes, and the vertical subcodes 3b are second-generation algebraic geometric codes. In some examples, the first-generation and second-generation geometric codes are the same. For example, both the first-generation and second-generation geometric codes are BCH codes. In other examples, the first-generation and second-generation geometric codes are different. For example, the first-generation geometric code is a BCH code, and the second-generation geometric code is an RS code.

[0080] The product code encoding of the second codeword includes the following steps:

[0081] The first step is to encode each first subsequence with the first subcode to obtain the first subcode;

[0082] The second step is to encode each second subsequence with a second subcode to obtain the second subcode.

[0083] In this configuration, the first subcode is a horizontal subcode, and the second subcode is a vertical subcode; or, the first subcode is a vertical subcode, and the second subcode is a horizontal subcode. That is, in the product code encoding process, horizontal subcode encoding can be performed first, or vertical subcode encoding can be performed first, and the resulting encoding result (i.e., concatenated codeword) is the same.

[0084] When the first subcode is a horizontal subcode and the second subcode is a vertical subcode, the first subsequence is a row of bits in the first encoded codeword in matrix form, and the second subsequence is a column of bits in the first encoded codeword in matrix form. When the first subcode is a vertical subcode and the second subcode is a horizontal subcode, the first subsequence is a column of bits in the first encoded codeword in matrix form, and the second subsequence is a row of bits in the first encoded codeword in matrix form.

[0085] Figure 3 In this structure, each row of information bits forms a first subsequence, and each row of bits (including information bits and overhead bits) forms a first subcode. Each first subcode consists of N1 bits, of which K1 are information bits, and N1-K1 overhead bits are located to the right of the information bits. Each column of information bits forms a second subsequence, and each column of bits (including information bits and overhead bits) forms a second subcode. Each second subcode consists of N2 bits, of which K2 are information bits, and N2-K2 overhead bits are located below the information bits. The product of N1 and N2 equals n2.

[0086] 205: Output concatenated codewords.

[0087] Using 205, concatenated coded codewords can be sent to the receiving device via the channel.

[0088] This application embodiment encodes the information bit sequence using GLDPC code as the inner code and polar code as the outer code. Since GLDPC code has stronger error correction capabilities compared to LDPC code, the encoding method of this application embodiment can improve the reliability of the encoding / decoding system. Furthermore, using polar code as the outer code can effectively utilize the soft information output during the GLDPC code decoding process, thereby improving the performance of the concatenated code.

[0089] Furthermore, GLDPC codes with algebraic geometric codes as subcodes offer flexible codeword design and feature low power consumption and high performance; while using polar codes as outer codes can effectively reduce the error plane of GLDPC codes, thereby improving system performance.

[0090] In this embodiment, the GLDPC code is a block code, which is suitable for communication scenarios involving packet transmission.

[0091] Figure 4 This is a flowchart illustrating another encoding method provided in an embodiment of this application. This method can be executed by the aforementioned transmitting device. Figure 2 The difference in the illustrated embodiment is that, in this method, the GLDPC code is a convolutional code. For example... Figure 4 As shown, the encoding method includes:

[0092] 301: Obtain the information bit sequence.

[0093] The information bit sequence is a binary sequence with a length of k1, meaning it consists of k1 bits.

[0094] For details regarding the information bit sequence, please refer to section 201; a detailed description is omitted here.

[0095] 302: Generate N blocks to be encoded based on the information bit sequence.

[0096] In this process, the N blocks to be encoded are arranged according to the ladder code construction. That is, firstly, through step 302, the information bit sequence is sorted according to the ladder code construction, and then the sorted information bit sequence is encoded using an external code. Here, N is an integer greater than 1, for example, it can be 2-20.

[0097] In the first N-1 blocks to be encoded, each block includes X1 information bits and X2 overhead bits. The last block to be encoded includes X3 information bits. Here, X3 is a positive integer, and X3 = k1 - (N-1) * X1.

[0098] In the first N-1 blocks to be encoded, all bits in each block are arranged in a matrix, X1 information bits are arranged in a matrix, and X2 overhead bits are located on one side of the X1 information bits.

[0099] Figure 5 This is a schematic diagram of a ladder code provided in an embodiment of this application. Figure 5 It shows the positional relationship of bits in multiple blocks to be encoded. Figure 5 In the diagram, each box represents a block to be encoded, or an encoding window. Blank spaces represent information bits, and grid lines represent overhead bits. Figure 5As can be seen, in each block to be encoded, the overhead bits are located to the right of the information bits (e.g., the block to be encoded to the right of the first row) or below the information bits (e.g., the block to be encoded to the left of the first row).

[0100] The information bit sequence consists of N subsequences. Each of the first N-1 subsequences contains X1 consecutive information bits from the information bit sequence, and the information bits in different subsequences are different. The last subsequence contains X3 information bits. In the first N-1 blocks to be encoded, the X1 information bits in each block are the X1 information bits from one of the subsequences in the first N-1 subsequences. The X3 information bits in the last block to be encoded (i.e., the Nth block to be encoded) belong to the last subsequence. Therefore, the information bits in each block to be encoded belong to a unique subsequence. For the i-th block to be encoded, the X2 overhead bits are obtained by encoding the information bits in the i-th block and all bits in the (i-1)-th block to be encoded. Here, i is an integer greater than 1.

[0101] This embodiment and Figure 2 The difference in the illustrated embodiment is that the GLDPC code used as the inner code is a convolutional code. Therefore, the information bits in each subsequence need to be encoded together with the information bits in the preceding subsequences using the outer code. Here, the number of blocks to be encoded is determined by the constraint length of the convolutional code and can be set as needed. The constraint length of the convolutional code is equal to N-1.

[0102] 303: Polar code encoding is performed on the information bits in N coded blocks to obtain the first coded codeword.

[0103] In 303, polar code encoding is performed on N blocks to be encoded based on the set of frozen bit positions and the set of information bit positions of the polar code.

[0104] The set of frozen bit positions and the set of information bit positions of the polar code can be determined based on the output soft information during the internal code decoding process.

[0105] By using 302 and 303, the information bit sequence can be polar encoded to obtain the first coded codeword.

[0106] The code length of the first encoded codeword can be N*N1 / 2*(K1-N1 / 2) bits. The information bit length k1 of the first encoded codeword is less than N*N1 / 2*(K1-N1 / 2) bits. The overhead bits of the first encoded codeword are located in the information bits of length N1 / 2*(K1-N1 / 2) in every Nth block to be encoded in the ladder code.

[0107] 304: Interleave the first codeword to obtain the second codeword.

[0108] The interleaving method can be found in step 203 above, and will not be repeated here.

[0109] 305: Encode the second codeword using GLDPC code to obtain the concatenated codeword.

[0110] The GLDPC code consists of multiple subcodes, each of which is an algebraic geometric code. The length of the concatenated codeword is n2, where n2 is greater than n1.

[0111] Figure 5 Each N1 / 2*N1 / 2 block in the code is an encoding window of the inner code. Each encoding window includes N1 / 2*(K1-N1 / 2) information bits and N1 / 2*(K1-N1 / 2) overhead bits. These N1 / 2*(K1-N1 / 2) overhead bits are obtained by encoding the N1 / 2*(K1-N1 / 2) information bits with the historical data in the previous block.

[0112] The encoding and transmission of ladder code from Figure 5 Proceed from the top left corner to the bottom right corner. For example, first... Figure 5 The two squares in the first row are encoded horizontally, and then the two squares in the middle column are encoded vertically. The encoded squares on the right of the first row are output. Then the two squares in the second row are encoded horizontally, and the encoded squares on the left of the second row are output. And so on.

[0113] In this embodiment, in the two blocks encoded simultaneously, each row or column of bits is a sub-code, and the code length of each sub-code is N1. Each encoding window corresponds to N1 / 2 sub-codes, which can be encoded sequentially or in parallel.

[0114] 306: Output concatenated codewords.

[0115] Using 306, concatenated coded codewords can be transmitted to the receiving device via the channel.

[0116] In this embodiment, GLDPC codes are convolutional codes, suitable for continuous communication scenarios. At the same code rate, convolutional codes outperform block codes.

[0117] Figure 6 This is a flowchart illustrating a decoding method provided in an embodiment of this application. This method can be executed by the aforementioned receiving device. Figure 6 As shown, the decoding method includes:

[0118] 401: Receive channel soft information sequence.

[0119] The channel soft information sequence includes multiple log likelihood ratio (LLR) values. Each LLR value corresponds to one bit.

[0120] The number of LLR values ​​in the channel soft information sequence is related to the size of the decoding window. For example, if the decoding window consists of n*n bits, then the number of LLR values ​​in the channel soft information sequence is also n*n.

[0121] 402: The channel soft information sequence is decoded using an iterative decoding technique based on the internal code to obtain the first decoding result.

[0122] The internal code is the aforementioned GLDPC code, and the relevant content can be found in step 204 above, which will not be described in detail here.

[0123] Optionally, the iterative decoding technique for the internal code can be either hard-decision iterative decoding or soft-information iterative decoding. Since soft-information iterative decoding has relatively high decoding performance, this application uses iterative decoding as an example for illustrative purposes.

[0124] For example, the soft information iterative decoding technique for internal codes can be a soft input soft output (SISO) decoding technique. The SISO decoding process is described below.

[0125] In the embodiments of this application, SISO decoding is performed on a subcode-by-subcode basis. For example, an n x n product codeword includes 2n subcodes, and SISO decoding needs to be performed on each of these 2n subcodes. As another example, a decoding window of a ladder code includes N1 / 2 subcodes, and SISO decoding needs to be performed on each of these 2n subcodes. The SISO decoding process for each subcode is described below.

[0126] First, the soft information of the subcode to be translated is obtained. This soft information includes the soft information of the value of each bit, and the soft information of each bit includes the value and its confidence level. Mathematically, it is expressed as the logarithm of the ratio of the posterior probability that each bit is equal to 1 to its posterior probability that it is equal to 0. A positive value indicates that the bit is more likely to be equal to 1, and a negative value indicates that the bit is more likely to be equal to 0. The absolute value of the value indicates the confidence level of the corresponding value; the larger the absolute value, the more reliable the value. Then, soft-decision decoding is performed based on the soft information of the subcode to obtain the hard-decision result. In implementation, a hard-decision result cache can be set up to store the latest hard-decision result for each subcode. The soft-decision decoding can employ any of the related technologies, and this application embodiment does not limit this.

[0127] In the first iteration, the soft information of the subcode to be decoded is a part of the channel soft information sequence, i.e., the LLR value corresponding to each bit of the subcode. In subsequent iterations (i.e., the second iteration and beyond), the soft information of the subcode is obtained based on the LLR value corresponding to each bit of the subcode and the extrinsic information generated in the previous iteration. For example, the soft information of each bit in the subcode is equal to the sum of the product of the extrinsic information corresponding to that bit and the weight coefficient, and the LLR value corresponding to that bit. The weight coefficient increases with the number of iterations. For instance, the extrinsic information generated in the previous iteration of the subcode is generated based on the hard decision result obtained in the previous iteration of the subcode. Thus, the decoding result of each soft decision decoding influences the next soft decision decoding through the extrinsic information.

[0128] For example, a GLDPC code includes multiple first subcodes and multiple second subcodes, one of which is a horizontal subcode, and the other is a vertical subcode. In the soft-decision iterative decoding process, the horizontal subcodes can be decoded first, or the vertical subcodes can be decoded first.

[0129] For example, the first subcode can be soft-determined to obtain the extrinsic information corresponding to it; then, based on the extrinsic information of the first subcode, the second subcode can be soft-determined to obtain the extrinsic information of the second subcode; then, based on the extrinsic information of the second subcode, the first subcode can be soft-determined... and so on, iterating until the maximum number of decoding iterations is reached. This maximum number of decoding iterations is a set value that can be set according to actual needs; this embodiment does not impose any limitations on it.

[0130] In implementation, two buffer units can be set up, namely the first buffer unit and the second buffer unit. The first buffer unit is used to store the LLR values ​​in the channel soft information sequence, and the second buffer unit is used to store the extrinsic information obtained after each soft decision decoding. During the decoding process of each inner codeword, the content stored in the first buffer unit remains unchanged, while the content stored in the second buffer unit is updated according to the extrinsic information obtained after each soft decision decoding.

[0131] To reduce decoding power consumption, a flag bit can be assigned to each subcode. This flag bit indicates whether the corresponding subcode has been correctly decoded, i.e., whether the hard decision result for that subcode is correct (or valid). If the flag bit indicates that the corresponding subcode has been correctly decoded, then soft decision decoding is not required for that subcode in this iteration. In this case, soft information is generated based on the hard decision result and the bit width of the soft information (e.g., the product of the sign value of the hard decision result and the bit width value of the soft information is used as the soft information), and the flag bit corresponding to that subcode is updated to indicate that the corresponding subcode has not been correctly decoded. This soft information is then used for soft decision decoding in the next iteration of that subcode, and then the process jumps to the next subcode to be decoded. If the flag bit indicates that the corresponding subcode has not been correctly decoded, then soft decision decoding needs to continue for that subcode in this iteration, improving decoding performance. In other words, if this flag bit is not set, the number of soft-decision decodings for each subcode is equal to the maximum number of decoding iterations. However, if this flag bit is set, some subcodes may obtain the correct hard-decision result when the number of soft-decision decodings is less than the maximum number of decoding iterations. In some iteration decoding processes, soft-decision decoding is not required, thereby saving decoding times and reducing decoding power consumption.

[0132] In some examples, when the flag bit is 0, it indicates that the subcode needs to be soft-determined in this iteration, meaning that the subcode has not been correctly decoded; when the flag bit is 1, it indicates that the subcode does not need to be soft-determined in this iteration, meaning that the subcode has been correctly decoded.

[0133] When each subcode is assigned an identifier bit, before obtaining the soft information of the subcode to be translated, it is necessary to first obtain the identifier bit corresponding to the subcode to be translated, and determine whether soft decision decoding of the subcode to be translated is required based on the identifier bit. If soft decision decoding of the subcode to be translated is required, then the soft information of the subcode to be translated is obtained; if soft decision decoding of the subcode to be translated is not required, then the soft information of the subcode to be translated is obtained, and then the process moves on to the next subcode to be translated.

[0134] After each iteration of decoding each subcode, a new hard decision result is obtained. If the new hard decision result is correct, the corresponding flag bit of the subcode is set to 1; if the new hard decision result is incorrect, the corresponding flag bit of the subcode is set to 0.

[0135] Whether the new hard decision result is correct can be determined based on the new hard decision result and the parity-check matrix. In some examples, the product of the parity-check matrix and the new hard decision result is calculated; if the product equals 0, the new hard decision result is correct. Conversely, if the product is not equal to 0, the new hard decision result is incorrect. For example, if the subcode is a BCH subcode, the correctness of the new decision result can be determined based on the syndrome of the BCH subcode.

[0136] After each soft-decision decoding, it is determined whether the maximum number of decoding iterations has been reached. If the maximum number of decoding iterations has not been reached, the process moves to the next subcode. When the maximum number of decoding iterations has been reached, the hard-decision result and identifier bits of the subcode to be decoded are output. Here, the output hard-decision result is the hard-decision result corresponding to the last soft-decision decoding of the subcode to be decoded. The hard-decision result includes multiple hard-decision bits, and the number of hard-decision bits is the same as the number of LLR values, with a one-to-one correspondence.

[0137] In this embodiment of the application, the aforementioned first decoding result includes the hard decision result of each sub-code corresponding to the channel soft information sequence and the shutdown identifier corresponding to the channel soft information sequence. The shutdown identifier includes multiple identifier bits, which correspond one-to-one with the aforementioned multiple sub-codes. Each identifier bit is used to indicate whether the corresponding sub-code is correctly decoded when the hard decision result is generated.

[0138] Alternatively, the GLDPC code can be a block code or a convolutional code.

[0139] For example, a block code is a product code. When the GLDPC code is a product code, SISO decoding of the horizontal subcode and SISO decoding of the vertical subcode are performed on each codeword to obtain the hard decision result and shutdown flag corresponding to each codeword.

[0140] Convolutional codes, such as ladder codes, are used. When the GLDPC code is a ladder code, multiple subcodes within the sliding window are jointly decoded. The sliding window comprises multiple decoding windows; the number of decoding windows within the sliding window can be called the dimension of the sliding window. The dimension of the sliding window is greater than or equal to 2, and the size of the decoding window is equal to the size of the aforementioned encoding window. The dimension of the sliding window can be set according to actual needs; this application does not impose any restrictions on it, for example, it can be 2, 4, or 6, etc. Each time the sliding window slides, it outputs the hard decision result and shutdown flag of one decoding window.

[0141] Assume the sliding window for decoding has a dimension of 4. Figure 5Each square in the code represents a decoding window. Arrows 1, 2, and 3 indicate the order of iterative decoding. The rightmost square at the bottom contains a sequence of channel soft information of length N1 / 2*N1 / 2. The other three squares contain stored historical soft information. 1 indicates SISO decoding of the horizontal subcodes in the two squares below; 2 indicates SISO decoding of the vertical subcodes in the two squares in the middle column; and 3 indicates SISO decoding of the horizontal subcodes in the two squares above. Steps 1, 2, and 3 can be executed sequentially or in parallel. After decoding is complete, the hard decision result and shutdown flag of the upper left square are output.

[0142] SISO decoding of horizontal subcodes refers to performing soft-decision decoding on each subcode row by row. For example, soft-decision decoding is performed on the first row of subcodes first, then on the second row, and so on until all row subcodes have been soft-decision decoded. Alternatively, soft-decision decoding can be performed on each row of subcodes in parallel. SISO decoding of vertical subcodes refers to performing soft-decision decoding on each subcode column by column. For example, soft-decision decoding is performed on the first column of subcodes first, then on the second column, and so on until all column subcodes have been soft-decision decoded. Alternatively, soft-decision decoding can be performed on each column of subcodes in parallel.

[0143] 403: Based on the first decoding result, perform external code decoding to obtain the second decoding result.

[0144] The outer code is a polar code.

[0145] In some examples, 403 includes the following two steps: First, based on the hard decision result and the shutdown flag, an output soft information sequence is generated, which includes multiple soft values ​​and corresponds one-to-one with the hard decision bits contained in the hard decision result; Second, the external code is decoded based on the output soft information sequence to obtain a second decoding result.

[0146] Optionally, in this first step, the soft value corresponding to each hard decision bit in the hard decision result is generated in the following manner:

[0147] Obtain the identifier bit corresponding to the subcode containing the first bit, where the first bit is any hard decision bit in the hard decision result;

[0148] When the identifier bits corresponding to the subcode containing the first bit contain an identifier bit used to indicate correct decoding, the soft value corresponding to the first bit is determined as the first soft value; or, when all the identifier bits corresponding to the subcode containing the first bit are identifier bits that have not been correctly decoded, the soft value corresponding to the first bit is determined as the second soft value; wherein, the absolute value of the second soft value is less than the absolute value of the first soft value.

[0149] When a flag bit indicates correct decoding, the reliability of the hard decision result corresponding to that bit is relatively high, and the corresponding first soft value is larger. Conversely, when all flag bits indicate incorrect decoding, the reliability of the hard decision result corresponding to that bit is relatively low, and the corresponding second soft value is smaller.

[0150] Optionally, the first soft value is equal to the product of the first coefficient and the difference between twice the bit value of the first bit (i.e., the hard decision result of the first bit) and 1; the second soft value is equal to the product of the second coefficient and the difference between twice the bit value of the first bit and 1, where the first coefficient is greater than the second coefficient. This method of determining the soft value corresponding to the hard decision bit is simple and has low implementation complexity. Furthermore, it offers high decoding performance. Here, decoding performance can refer to the bit error rate.

[0151] In other words, the soft value of each bit can be determined using the following formula.

[0152]

[0153] Where k represents the i-th bit, SI(k) represents the soft value of the k-th bit, HD(k) represents the hard decision result of the k-th bit, β is the first coefficient, α is the second coefficient, Ф represents the set of all subcodes associated with this bit, and f i The identifier bits that represent these subcodes.

[0154] The values ​​of β and α can be set according to actual needs, for example, based on the bit width (i.e., number of bits) of the soft value. When the bit width of the soft value is 5 bits, the range of the soft value is -31 to 32. In this case, the values ​​of β and α are between 0 and 32.

[0155] Alternatively, in other embodiments, when all the identifier bits corresponding to the subcode containing the first bit are identifier bits indicating correct decoding, the soft value corresponding to the first bit is determined as a first soft value; when all the identifier bits corresponding to the subcode containing the first bit are identifier bits indicating incorrect decoding, the soft value corresponding to the first bit is determined as a second soft value; when the identifier bits corresponding to the subcode containing the first bit are partly identifier bits indicating correct decoding and partly identifier bits indicating incorrect decoding, the soft value corresponding to the first bit is determined as a third soft value. The absolute value of the second soft value is less than the absolute value of the third soft value, and the absolute value of the third soft value is less than the absolute value of the first soft value.

[0156] In this second step, deinterleaving can be performed first, and then the external code can be decoded using either the successive cancellation (SC) decoding algorithm or the SC list (SCL) decoding algorithm.

[0157] The unintertwining process is the reverse of the intertwining process described above.

[0158] It should also be noted that, in addition to ladder codes, GLDPC can also be a generalized convolutional LDPC that uses algebraic geometric codes as subcodes, such as open forward error correction (OFEC) codes or zipper codes.

[0159] This application embodiment encodes the information bit sequence using GLDPC code as the inner code and polar code as the outer code. Since GLDPC code has stronger error correction capabilities compared to LDPC code, the encoding method of this application embodiment can improve the reliability of the encoding / decoding system. Furthermore, using polar code as the outer code can effectively utilize the soft information output during the GLDPC code decoding process, thereby improving the performance of the concatenated code.

[0160] Furthermore, GLDPC codes with algebraic geometric codes as subcodes offer flexible codeword design and feature low power consumption and high performance; while using polar codes as outer codes can effectively reduce the error plane of GLDPC codes, thereby improving system performance.

[0161] Furthermore, during external code decoding, the soft information of the internal code can be effectively utilized to iteratively decode the hard decision results and shutdown flags output, thereby improving the decoding accuracy.

[0162] Optionally, the method further includes: establishing a channel model based on the output soft information; and determining the set of frozen bit positions and the set of information bit positions for the outer code encoding based on the channel model. Determining the set of frozen bit positions and the set of information bit positions for the outer code encoding based on the output soft information during the inner code decoding process is beneficial for improving the performance of concatenated coding.

[0163] The process of establishing a channel model based on the output soft information includes: establishing the channel model based on the statistical characteristics of the output soft information. These statistical characteristics include the variance of the soft values, the mean of the absolute values ​​of the soft values, or the distribution of the number of bit errors.

[0164] The channel model includes multiple polarization sub-channels and the reliability of each polarization sub-channel. The reliability of each polarization sub-channel can be measured using the Bhattacharyya parameter method, the density evolution (DE) method, or the Gaussian approximation method.

[0165] Based on the channel model, the set of frozen bit positions and the set of information bit positions for the external code encoding are determined. Specifically, the bit positions corresponding to the polarization sub-channels with higher reliability are determined as information bit positions, and the bit positions corresponding to the polarization sub-channels with lower reliability are determined as frozen bit positions.

[0166] It should be noted that the set of frozen bit positions and the set of information bit positions for the external code encoding do not need to be updated in real time; they can be predetermined before the encoding and decoding methods provided in this application are executed. In implementation, an initial set of frozen bit positions and an initial set of information bit positions can be predetermined. Encoding and decoding are performed according to these initial sets of frozen bit positions and initial sets of information bit positions. Then, based on the output soft information during the internal code decoding process, a channel model is established, and the initial set of frozen bit positions and the initial set of information bit positions are optimized according to the channel model to obtain the set of frozen bit positions and the set of information bit positions.

[0167] This application also provides an encoding device. Figure 7 This is a schematic diagram of the structure of an encoding device provided in an embodiment of this application. Figure 7 As shown, the device 700 includes: an acquisition module 701, an encoding module 702, and an output module 703. The acquisition module 701 is used to acquire an information bit sequence. The encoding module 702 is used to encode the information bit sequence using a generalized low-density parity-check (GLDPC) code as the inner code and a polar code as the outer code to obtain a concatenated codeword. The concatenated codeword includes multiple sub-codes, each of which is an algebraic geometric code. The output module 703 is used to output the concatenated codeword.

[0168] Optionally, the GLDPC code is a block code; the encoding module includes: an outer code encoding unit for polar code encoding the information bit sequence to obtain a first encoded codeword; an interleaving unit for interleaving the first encoded codeword to obtain a second encoded codeword; and an inner code encoding unit for GLDPC code encoding the second encoded codeword to obtain the concatenated encoded codeword.

[0169] Optionally, the GLDPC code is a convolutional code; the information bit sequence includes N subsequences, each subsequence including multiple bits in consecutive positions within the information bit sequence, where N is an integer greater than 1; the encoding module includes: a preprocessing unit, configured to generate N blocks to be encoded based on the information bit sequence, wherein in the first N-1 blocks of the N blocks to be encoded, each block to be encoded includes X1 information bits and X2 overhead bits, the X1 information bits in each block to be encoded belonging to one of the N subsequences, wherein the first N-1 blocks to be encoded include X1 information bits and X2 overhead bits. The X2 overhead bits in the i-th block to be encoded are obtained by encoding all bits in the (i-1)-th block to be encoded and the X1 information bits in the i-th block to be encoded, where X1, X2, and i are all integers greater than 1; the outer code encoding unit is used to encode the information bits in the N blocks to be encoded using polar codes to obtain the first codeword; the interleaving unit is used to interleave the first codeword to obtain the second codeword; the inner code encoding unit is used to encode the second codeword using GLDPC codes to obtain the concatenated codeword.

[0170] Optionally, the first encoded codeword includes multiple bit groups, each bit group including y consecutive bits in the first encoded codeword, where y is greater than 1 and y is an integer; the interleaving unit is used to cyclically shift each bit group in the multiple bit groups to obtain the second encoded codeword, wherein the number of shift bits for different bit groups is different.

[0171] It should be noted that, in other embodiments, the acquisition module can be used to execute any step in the encoding method, the encoding module can be used to execute any step in the encoding method, and the output module can be used to execute any step in the encoding method. The steps implemented by the acquisition module, the encoding module, and the output module can be specified as needed. By implementing different steps in the encoding method through the acquisition module, the encoding module, and the output module, all functions of the encoding device can be realized.

[0172] This application also provides a decoding device. Figure 8 This is a schematic diagram of the structure of an encoding device provided in an embodiment of this application. Figure 8As shown, the device 800 includes: a receiving module 801, an inner code decoding module 802, and an outer code decoding module 803. The receiving module 801 receives a channel soft information sequence. The inner code decoding module 802 decodes the channel soft information sequence using an iterative decoding technique to obtain a first decoding result. The inner code is a generalized low-density parity-check (GLDPC) code, which includes multiple sub-codes, each of which is an algebraic geometric code. The outer code decoding module 803 performs outer code decoding based on the first decoding result to obtain a second decoding result. The outer code is a polar code.

[0173] Optionally, the first decoding result includes a hard decision result and a shutdown identifier of the channel soft information sequence. The shutdown identifier includes multiple identifier bits, each of which corresponds one-to-one with the multiple sub-codes. Each identifier bit is used to indicate whether the corresponding sub-code was correctly decoded when the hard decision result was generated. The external code decoding module 803 is used to generate an output soft information sequence based on the hard decision result and the shutdown identifier. The output soft information sequence includes multiple soft values, each of which corresponds one-to-one with the hard decision bits contained in the hard decision result. External code decoding is performed based on the output soft information sequence, wherein the size of each soft value is related to the shutdown identifier associated with the hard decision bit corresponding to that soft value.

[0174] Optionally, the external code decoding module 803 generates the soft value corresponding to each hard decision bit in the hard decision result in the following manner: obtaining the identifier bit corresponding to the sub-code where the first bit is located, where the first bit is any hard decision bit in the hard decision result; when there is an identifier bit in the identifier bit corresponding to the sub-code where the first bit is located that indicates correct decoding, the soft value corresponding to the first bit is determined as the first soft value; or, when all the identifier bits corresponding to the sub-code where the first bit is located are identifier bits that indicate incorrect decoding, the soft value corresponding to the first bit is determined as the second soft value; wherein, the absolute value of the second soft value is less than the absolute value of the first soft value.

[0175] Optionally, the first soft value is equal to the product of the first coefficient and the difference between twice the bit value of the first bit and 1; the second soft value is equal to the product of the second coefficient and the difference between twice the bit value of the first bit and 1, wherein the first coefficient is greater than the second coefficient.

[0176] It should be noted that, in other embodiments, the receiving module can be used to execute any step in the decoding method, the internal code decoding module can be used to execute any step in the decoding method, and the external code decoding module can be used to execute any step in the decoding method. The steps implemented by the receiving module, the internal code decoding module, and the external code decoding module can be specified as needed. The full functionality of the decoding device is achieved by implementing different steps in the decoding method through the receiving module, the internal code decoding module, and the external code decoding module.

[0177] The descriptions of the processes corresponding to the above-mentioned figures each have their own emphasis. For parts of a process that are not described in detail, please refer to the relevant descriptions of other processes.

[0178] This application also provides a computer device 100. For example... Figure 9 As shown, the computer device 100 includes a bus 102, a processor 104, a memory 106, and a communication interface 108. The processor 104, the memory 106, and the communication interface 108 communicate with each other via the bus 102. The computer device 100 can be a server or a terminal device. It should be understood that this application does not limit the number of processors and memories in the computer device 100.

[0179] Bus 102 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 9 The bus 102 may be represented by a single line, but this does not mean that there is only one bus or one type of bus. The bus 102 may include a path for transmitting information between various components of the computer device 100 (e.g., memory 106, processor 104, communication interface 108).

[0180] The processor 104 may include any one or more processors such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0181] Memory 106 may include volatile memory, such as random access memory (RAM). Processor 104 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0182] The memory 106 stores executable program code, and the processor 104 executes this executable program code to implement the functions of the aforementioned acquisition module, encoding module, and output module, thereby implementing the encoding method. That is, the memory 106 stores instructions for executing the encoding method. Alternatively, the memory 106 stores executable program code, and the processor 104 executes this executable program code to implement the functions of the aforementioned receiving module, internal code decoding module, and external code decoding module, thereby implementing the decoding method. That is, the memory 106 stores instructions for executing the decoding method.

[0183] The communication interface 108 uses transceiver modules such as, but not limited to, network interface cards and transceivers to enable communication between the computer device 100 and other devices or communication networks.

[0184] This application also provides a computer program product containing instructions. The computer program product may be a software or program product containing instructions, capable of running on a computer device or stored on any usable medium. When the computer program product is run on at least one computer device, it causes the at least one computer device to perform the aforementioned encoding or decoding method.

[0185] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer device can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct a computer device to perform the aforementioned encoding or decoding method.

[0186] This application also provides a chip. The chip includes a processor and a communication interface, the communication interface being connected to the processor; the processor is used to execute instructions so that the chip performs the aforementioned encoding or decoding method.

[0187] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. An encoding method, characterized in that, include: Obtain the information bit sequence; The information bit sequence is encoded using a generalized low-density parity-check (GLDPC) code as the inner code and a polar code as the outer code to obtain a concatenated codeword. The GLDPC code includes multiple sub-codes, and each of the multiple sub-codes is an algebraic geometric code. Output the concatenated codeword.

2. The method according to claim 1, characterized in that, The GLDPC code is a block code; The encoding of the information bit sequence using Generalized Low-Density Parity-Check (GLDPC) code as the inner code and polar code as the outer code includes: The information bit sequence is polar-coded to obtain the first coded codeword; Interleave the first encoded codeword to obtain the second encoded codeword; The second encoded codeword is encoded using GLDPC code to obtain the concatenated encoded codeword.

3. The method according to claim 1, characterized in that, The GLDPC code is a convolutional code; the information bit sequence includes N subsequences, each of the N subsequences includes multiple bits in consecutive positions in the information bit sequence, where N is an integer greater than 1; The encoding of the information bit sequence using a generalized low-density parity-check (GLDPC) code as the inner code and a polar code as the outer code includes: Based on the information bit sequence, N blocks to be encoded are generated. In the first N-1 blocks to be encoded, each block includes X1 information bits and X2 overhead bits. The X1 information bits in each block to be encoded belong to one of the N sub-sequences. The X2 overhead bits in the i-th block to be encoded are obtained by encoding all bits in the (i-1)-th block to be encoded and the X1 information bits in the i-th block to be encoded. X2 and i are both integers greater than 1. Polar code encoding is performed on the information bits in the N blocks to be encoded to obtain the first encoded codeword; Interleave the first encoded codeword to obtain the second encoded codeword; The second encoded codeword is encoded using GLDPC code to obtain the concatenated encoded codeword.

4. The method according to claim 2 or 3, characterized in that, The first encoded codeword includes multiple bit groups, each of the multiple bit groups including y consecutive bits in the first encoded codeword, where y is greater than 1 and y is an integer; The process of interleaving the first encoded codeword to obtain the second encoded codeword includes: The second encoded codeword is obtained by cyclically shifting each of the plurality of bit groups, wherein the number of shifts is different for different bit groups.

5. A decoding method, characterized in that, include: Receive channel soft information sequence; The channel soft information sequence is decoded using an iterative decoding technique with an inner code to obtain a first decoding result. The inner code is a generalized low-density parity-check (GLDPC) code, which includes multiple subcodes, each of which is an algebraic geometric code. Based on the first decoding result, the outer code is decoded to obtain the second decoding result, wherein the outer code is a polar code.

6. The method according to claim 5, characterized in that, The first decoding result includes a hard decision result of the channel soft information sequence and a shutdown identifier. The shutdown identifier includes multiple identifier bits, which correspond one-to-one with the multiple subcodes. Each identifier bit is used to indicate whether the corresponding subcode is correctly decoded when the hard decision result is generated. The step of performing external code decoding based on the first decoding result includes: Based on the hard decision result and the shutdown flag, an output soft information sequence is generated. The output soft information sequence includes multiple soft values, and each soft value in the output soft information sequence corresponds one-to-one with the hard decision bit contained in the hard decision result. The size of each soft value is related to the shutdown flag associated with the hard decision bit corresponding to the soft value. The external code is decoded based on the output soft information sequence.

7. The method according to claim 6, characterized in that, The step of generating an output soft information sequence based on the hard decision result and the shutdown flag includes: The soft value corresponding to each hard decision bit in the hard decision result is generated in the following manner: Obtain the identifier bit corresponding to the subcode containing the first bit, where the first bit is any hard decision bit in the hard decision result; When the identifier bits corresponding to the subcode containing the first bit contain an identifier bit used to indicate correct decoding, the soft value corresponding to the first bit is determined as the first soft value; or, When all the identifier bits corresponding to the subcode containing the first bit are identifier bits used to indicate that the decoding was not correct, the soft value corresponding to the first bit is determined as the second soft value. The absolute value of the second soft value is less than the absolute value of the first soft value.

8. The method according to claim 7, characterized in that, The first soft value is equal to the product of the first coefficient and the difference between twice the bit value of the first bit and 1; The second soft value is equal to the product of the second coefficient and the difference between twice the bit value of the first bit and 1, where the first coefficient is greater than the second coefficient.

9. The method according to any one of claims 6 to 8, characterized in that, The method further includes: Based on the output soft information, a channel model is established; Based on the channel model, determine the set of frozen bit positions and the set of information bit positions for the external code encoding.

10. The method according to any one of claims 5 to 9, characterized in that, The GLDPC code is either a block code or a convolutional code.

11. An encoding device, characterized in that, include: The acquisition module is used to acquire the information bit sequence; The encoding module is used to encode the information bit sequence with a generalized low-density parity-check (GLDPC) code as the inner code and a polar code as the outer code to obtain a concatenated code codeword. The concatenated code codeword includes multiple sub-codes, and each of the multiple sub-codes is an algebraic geometric code. The output module is used to output the concatenated codewords.

12. The apparatus according to claim 11, characterized in that, The GLDPC code is a block code; The encoding module includes: An external code encoding unit is used to perform polar code encoding on the information bit sequence to obtain a first encoded codeword; An interleaving unit is used to interleave the first coded codeword to obtain a second coded codeword; An internal code encoding unit is used to encode the second encoded codeword using GLDPC code to obtain the concatenated encoded codeword.

13. The apparatus according to claim 11, characterized in that, The GLDPC code is a convolutional code; the information bit sequence includes N subsequences, each of the N subsequences includes multiple bits in consecutive positions in the information bit sequence, where N is an integer greater than 1; The encoding module includes: A preprocessing unit is configured to generate N blocks to be encoded based on the information bit sequence. In the first N-1 blocks to be encoded, each block includes X1 information bits and X2 overhead bits. The X1 information bits in each block to be encoded belong to one of the N subsequences. The X2 overhead bits in the i-th block to be encoded are obtained by encoding all bits in the (i-1)-th block to be encoded and the X1 information bits in the i-th block to be encoded. X1, X2, and i are all integers greater than 1. An external code encoding unit is used to perform polar code encoding on the information bits in the N blocks to be encoded to obtain the first encoded codeword; An interleaving unit is used to interleave the first coded codeword to obtain a second coded codeword; An internal code encoding unit is used to encode the second encoded codeword using GLDPC code to obtain the concatenated encoded codeword.

14. The apparatus according to claim 12 or 13, characterized in that, The first encoded codeword includes multiple bit groups, each of the multiple bit groups including y consecutive bits in the first encoded codeword, where y is greater than 1 and y is an integer; The interleaving unit is used to cyclically shift each of the plurality of bit groups to obtain the second encoded codeword, wherein the number of shift bits is different for different bit groups.

15. A decoding device, characterized in that, include: The receiving module is used to receive the channel soft information sequence; The inner code decoding module is used to decode the channel soft information sequence using the iterative decoding technology of the inner code to obtain the first decoding result. The inner code is a generalized low-density parity-check (GLDPC) code. The GLDPC code includes multiple subcodes, and each of the multiple subcodes is an algebraic geometric code. The external code decoding module is used to perform external code decoding based on the first decoding result to obtain a second decoding result, wherein the external code is a polar code.

16. The apparatus according to claim 15, characterized in that, The first decoding result includes a hard decision result of the channel soft information sequence and a shutdown identifier. The shutdown identifier includes multiple identifier bits, which correspond one-to-one with the multiple subcodes. Each identifier bit is used to indicate whether the corresponding subcode is correctly decoded when the hard decision result is generated. The external code decoding module is used to generate an output soft information sequence based on the hard decision result and the shutdown flag. The output soft information sequence includes multiple soft values, and each soft value in the output soft information sequence corresponds one-to-one with the hard decision bit contained in the hard decision result. The size of each soft value is related to the shutdown flag associated with the hard decision bit corresponding to the soft value. External code decoding is performed based on the output soft information sequence.

17. The apparatus according to claim 16, characterized in that, The external code decoding module generates the soft value corresponding to each hard decision bit in the hard decision result using the following method: Obtain the identifier bit corresponding to the subcode containing the first bit, where the first bit is any hard decision bit in the hard decision result; When the identifier bits corresponding to the subcode containing the first bit contain an identifier bit used to indicate correct decoding, the soft value corresponding to the first bit is determined as the first soft value; or, When all the identifier bits corresponding to the subcode containing the first bit are identifier bits used to indicate that the decoding was not correct, the soft value corresponding to the first bit is determined as the second soft value. The absolute value of the second soft value is less than the absolute value of the first soft value.

18. The apparatus according to claim 17, characterized in that, The first soft value is equal to the product of the first coefficient and the difference between twice the bit value of the first bit and 1; the second soft value is equal to the product of the second coefficient and the difference between twice the bit value of the first bit and 1, wherein the first coefficient is greater than the second coefficient.

19. The apparatus according to any one of claims 15 to 18, characterized in that, The GLDPC code is either a block code or a convolutional code.

20. A computer device, characterized in that, It includes a processor and a memory; the processor is configured to execute instructions stored in the memory to cause the computer device to perform the encoding method as described in any one of claims 1 to 4, or to perform the decoding method as described in any one of claims 5 to 10.

21. A computer-readable storage medium, characterized in that, The computer storage medium stores at least one instruction, which is loaded and executed by a computer device to enable the computer device to implement the encoding method as described in any one of claims 1 to 4, or to implement the decoding method as described in any one of claims 5 to 10.

22. A computer program product, characterized in that, The computer program product includes: computer program code, which is loaded and executed by a computer device to enable the computer device to implement the encoding method as described in any one of claims 1 to 4, or to implement the decoding method as described in any one of claims 5 to 10.

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