A digital multi-beam synthesis method

Abstract

The application relates to a digital multi-beam synthesis method, which calculates weighting coefficients in real time through an FPGA signal processing unit and delivers the weighting coefficients to a digital beam forming unit, so that the beam pointing direction is adjusted in real time, thereby solving the problem that the flexibility of the beam pointing direction is limited. Meanwhile, in the digital multi-beam forming process, the beam coherence synthesis, pointing direction, width and sidelobe level are controlled through a beam forming matrix, so that spatial filtering and interference suppression are realized, the flexibility of beam forming is improved, the anti-interference capability of the system is enhanced, and through real-time adjustment of the beam parameters, the system can better adapt to a complex electromagnetic environment and improve the anti-interference performance of the system. Through real-time calculation and delivery of the weighting coefficients by the FPGA signal processing unit, the digital beam forming unit performs beam forming in the digital domain, and the complexity and delay of signal processing can be effectively reduced.

Description

Technical Field

[0001] This application relates to the technical field of spaceborne satellite communication, and in particular to a digital multi-beam synthesis method. Background Technology

[0002] In fields such as communications and radar, beamforming technology is crucial for the directional transmission and reception of signals, but existing technologies have many shortcomings. Firstly, dedicated DBF chips for implementing beamforming algorithms suffer from limited flexibility, fixed algorithm functions that are difficult to modify, and long iteration cycles. Secondly, as the number of transmit and receive channels increases, the overall cost, development, and maintenance costs of digital phased arrays rise significantly. Thirdly, despite their radiation resistance, some signal processing and key algorithms still rely on FPGA units, and the cascaded data link processing architecture reduces system reliability.

[0003] On the other hand, while FPGA-based digital multibeamforming algorithms offer high flexibility, rapid algorithm adjustment, short development cycles, and support for multiple algorithm functions, they are limited by chip logic resources, resulting in high processing latency and the need for multi-stage pipelines, leading to high system power consumption. In large-scale phased array applications, the development difficulty increases dramatically, making it difficult to adapt to complex scenarios.

[0004] From the perspective of multi-beam array architecture, analog multi-beam architectures rely on RF or IF analog circuits and front-end processors, processing signals in real time through phase shifters and VGAs. They offer advantages such as low latency and high real-time performance, but lack flexibility, cannot reconstruct beams in software, and analog devices are highly susceptible to environmental influences, requiring regular calibration and resulting in high maintenance costs. Hybrid multi-beam architectures combine analog and digital beamforming, dividing the large-scale antenna array into subarrays. Within each subarray, phase shifters and VGAs control signals, which are then converted by an ADC / DAC, and a digital processor performs weighted summation to generate a narrow beam. This architecture has low hardware complexity and cost, high flexibility and real-time performance, and can meet microsecond-level beam switching requirements. However, the reduced effective aperture leads to decreased beam gain and limited scanning range, and the analog link still requires regular calibration. All-digital multi-beam architectures place beamforming functionality entirely in the digital domain, with each element corresponding to an independent RF transceiver channel, and the digital domain weighted summation generates an independent beam. Its advantages lie in the fact that the beam pointing, shape and number can be reconfigured in real time by software, the beam switching time is extremely short, the flexibility is high, the anti-interference performance is excellent, and the system reliability is high. However, it is expensive, consumes a lot of power, and has extremely high requirements for the performance of digital processing units.

[0005] In summary, existing traditional beamforming technologies have significant shortcomings in terms of flexibility, power consumption, latency, and reliability, making it difficult to meet the needs of large-scale application scenarios such as multi-user mobile phone direct satellite connections. Therefore, there is an urgent need for a new beamforming technology solution to improve beam pointing flexibility, reduce power consumption and latency, enhance system reliability, and better adapt to the development needs of future communication and other fields. Summary of the Invention

[0006] Therefore, it is necessary to provide a digital multi-beam synthesis method that can improve beam pointing flexibility, reduce power consumption, reduce latency, and enhance reliability in response to the aforementioned technical problems.

[0007] A digital multi-beamforming method is disclosed, which is applied to the baseband module of a spaceborne digital phased array, including a radio frequency transceiver unit, an FPGA signal processing unit, an FPGA management unit, a digital beamforming unit, and a 10G optical module unit; the digital beamforming unit integrates 32 GPIO interfaces and 16 LVDS interfaces connected to the FPGA signal processing unit.

[0008] The method includes:

[0009] When receiving signals, the target frequency band signals of each receiving channel are extracted by the radio frequency transceiver unit and transmitted to the digital beamforming unit.

[0010] The digital beamforming unit performs amplitude and phase weighting on the target frequency band signals of each receiving channel to generate corresponding digital multi-beams; during the digital multi-beam generation process, the beamforming matrix controls the beam coherent synthesis, pointing, width and sidelobe level to achieve spatial filtering and interference suppression.

[0011] The generated digital multibeams are processed and aggregated by the FPGA signal processing unit, and then the data is aggregated to the external module by the 10G optical module unit and then transmitted to the satellite platform.

[0012] When transmitting signals, user data is sent to the external module via the satellite platform. After being received by the 10G optical module unit, the data is transmitted to the FPGA signal processing unit.

[0013] The FPGA signal processing unit calculates the complex weighting coefficients of each transmission channel based on the spatial location of the target ground coverage area sent by the satellite platform, and sends the complex weighting coefficients to the digital beamforming unit.

[0014] The digital beamforming unit generates narrow beams corresponding to each transmission channel based on complex weighting coefficients to focus energy on the target area, controls the sidelobe level of the narrow beams, copies user data to all transmission channels, and applies preset weighting coefficients to the user data of each transmission channel to adjust the amplitude and phase of the narrow beams corresponding to each transmission channel; the complex weighting coefficients of the narrow beams corresponding to each transmission channel are superimposed and synthesized to form the digital signals to be transmitted in each transmission channel.

[0015] The radio frequency transceiver unit converts the digital signal to be transmitted into an analog signal and then outputs it.

[0016] In one embodiment, the method further includes:

[0017] To compensate for the amplitude and phase errors between each receiving or transmitting channel, the same source radio frequency signals are distributed through the radio frequency transceiver unit and the 64-channel power divider to calibrate the phase error to within 2°.

[0018] In one embodiment, the FPGA management unit performs on-orbit refresh, reconstruction, and status monitoring of the FPGA signal processing unit through the Slave SelectMAP interface.

[0019] In one embodiment, the radio frequency transceiver unit is an integrated radio frequency transceiver that combines an upconverter, a downconverter, a tunable filter, an ADC, and a DAC.

[0020] In one embodiment, the target frequency band signal of each receiving channel is extracted by the radio frequency transceiver unit and transmitted to the digital beamforming unit, including:

[0021] The radio frequency transceiver unit integrates a downconverter, a tunable filter, and an ADC to sample and decimate the radio frequency signals received by each receiving channel, thereby achieving spectrum separation and extracting the target frequency band signal of each receiving channel.

[0022] The target frequency band signals of each receiving channel are transmitted to the digital beamforming unit.

[0023] In one embodiment, the FPGA signal processing unit is provided with two RS422 interfaces between itself and the external module, including one RS422 interface and the other RS422 interface. The first RS422 interface is used for remote control, telemetry and online reconfiguration functions, and the second RS422 interface is used to receive PSS pulse signals sent by the external module.

[0024] In one embodiment, after the baseband module is powered on or reset, the configuration error of the configuration state machine of the FPGA signal processing unit is processed, and the watchdog timer is initialized.

[0025] In one embodiment, handling configuration errors in the configuration state machine of the FPGA signal processing unit and initializing the watchdog timer includes:

[0026] Pulling the PROGRAM_B pin of the FPGA signal processing unit low initiates the clearing of the configuration register. After 1ms, the PROGRAM_B pin is pulled high to exit the configuration register state clearing process and initialize the FPGA configuration logic. If the INIT_B pin goes high, it indicates successful initialization, and FPGA configuration read / write is performed to load the configuration program. If the FPGA's DONE pin goes high, it indicates that the configuration program has been loaded correctly. After the configuration program is loaded correctly, the FPGA watchdog counter monitors the FPGA's operating status.

[0027] A counter is designed for each state during the configuration loading process. If the counter overflows, the state is redirected to the configuration error handling unit, which then corrects the configuration loading.

[0028] In one embodiment, during digital multibeam generation, beam parameters are optimized in real time using gradient descent or a genetic algorithm.

[0029] In one embodiment, the radio frequency transceiver unit converts the digital signal to be transmitted into an analog signal and outputs it, including:

[0030] The radio frequency transceiver unit performs interpolation, filtering, and DAC refresh on the digital signal to be transmitted, converting the digital signal to be transmitted into an analog signal.

[0031] The analog signal is modulated to a predetermined radio frequency transmission point by up-conversion and then output.

[0032] The aforementioned digital multi-beamforming method utilizes a baseband module that integrates 32 GPIO interfaces and 16 LVDS interfaces within a digital beamforming unit, connected to an FPGA signal processing unit. This allows for the configuration and distribution of weighting coefficients via multiple high-speed parallel data interfaces, ensuring the weighting coefficients take effect within 10 ns. The FPGA signal processing unit calculates and distributes weighting coefficients to the digital beamforming unit in real time, thereby adjusting the beam pointing in real-time. This addresses the limitation on beam pointing flexibility when implementing beamforming algorithms using dedicated DBF chips. Simultaneously, during digital multi-beam generation, the digital beamforming unit controls beam coherence synthesis, pointing, width, and sidelobe levels through a beamforming matrix to achieve spatial filtering and interference suppression. This improves beamforming flexibility, enhances system anti-interference capabilities, and, through real-time beam parameter adjustment, better adapts to complex electromagnetic environments, further improving the system's anti-interference performance.

[0033] By using an FPGA signal processing unit to calculate and distribute weighting coefficients in real time, the digital beamforming unit performs beamforming in the digital domain. This effectively reduces signal processing complexity and latency, and decreases reliance on dedicated DBF chips, avoiding reliability issues associated with cascaded data link architectures. Simultaneously, by optimizing the control of the beamforming matrix, system power consumption can be reduced while maintaining beam performance. Furthermore, real-time adjustment of beam pointing and parameters can further optimize system performance, reducing power consumption and latency. On the other hand, since the digital beamforming unit performs beamforming in the digital domain, it reduces the use of analog components, lowers amplitude and phase errors caused by environmental factors, and improves system reliability. Attached Figure Description

[0034] Figure 1 This is an application scenario diagram of the digital multibeam synthesis method in one embodiment;

[0035] Figure 2 This is a flowchart illustrating a digital multibeam synthesis method in one embodiment;

[0036] Figure 3 This is a schematic diagram of the software design of the baseband module in one embodiment;

[0037] Figure 4 This is a structural design diagram of the baseband module in one embodiment. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0039] The digital multibeam synthesis method provided in this application can be applied to, for example... Figure 1 In the application environment shown, the user terminal 102 and the satellite platform 104 interact with each other via signals. The user terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices, and the satellite platform 104 can be an onboard satellite.

[0040] In one embodiment, such as Figure 2 As shown, a digital multibeam synthesis method is provided, which is applied to... Figure 1Taking a satellite platform as an example, the satellite platform interacts with external modules, which are connected to a baseband module. The baseband module includes a radio frequency transceiver unit, an FPGA signal processing unit, an FPGA management unit, a digital beamforming unit, and a 10G optical module unit. The digital beamforming unit integrates 32 GPIO interfaces and 16 LVDS interfaces, which are connected to the FPGA signal processing unit. The method includes the following steps:

[0041] Step 101: When receiving signals, the target frequency band signals of each receiving channel are extracted by the radio frequency transceiver unit and transmitted to the digital beamforming unit.

[0042] Step 102: The digital beamforming unit performs amplitude and phase weighting on the target frequency band signals of each receiving channel to generate corresponding digital multi-beams; during the digital multi-beam generation process, the beamforming matrix controls the beam coherent synthesis, pointing, width and sidelobe level to achieve spatial filtering and interference suppression.

[0043] Step 103: The generated digital multibeams are processed and aggregated by the FPGA signal processing unit, and then the data is aggregated to the external module by the 10G optical module unit and then transmitted to the satellite platform.

[0044] Step 104: When transmitting a signal, user data is sent to the external module via the satellite platform. After being received by the 10G optical module unit, the data is transmitted to the FPGA signal processing unit.

[0045] Step 105: The FPGA signal processing unit calculates the complex weighting coefficients of each transmission channel based on the spatial location of the target ground coverage area sent by the satellite platform, and sends the complex weighting coefficients to the digital beamforming unit.

[0046] Step 106: The digital beamforming unit generates narrow beams corresponding to each transmission channel based on complex weighting coefficients to focus energy on the target area, controls the sidelobe level of the narrow beams, copies user data to all transmission channels, and applies preset weighting coefficients to the user data of each transmission channel to adjust the amplitude and phase of the narrow beams corresponding to each transmission channel; the complex weighting coefficients of the narrow beams corresponding to each transmission channel are superimposed and synthesized to form the digital signals to be transmitted in each transmission channel.

[0047] Step 107: The radio frequency transceiver unit converts the digital signal to be transmitted into an analog signal and then outputs it.

[0048] In the aforementioned digital multi-beamforming method, a 32-channel GPIO interface and a 16-channel LVDS interface are integrated into the digital beamforming unit and connected to the FPGA signal processing unit. Multiple high-speed parallel data interfaces are used to configure and distribute weighting coefficients, ensuring the weighting coefficients take effect within 10ns. The FPGA signal processing unit calculates and distributes the weighting coefficients to the digital beamforming unit in real time, thereby adjusting the beam pointing in real time. This addresses the limitation on beam pointing flexibility when implementing beamforming algorithms using dedicated DBF chips. Simultaneously, during digital multi-beam generation, the digital beamforming unit controls beam coherence synthesis, pointing, width, and sidelobe level through a beamforming matrix to achieve spatial filtering and interference suppression. This improves beamforming flexibility, enhances the system's anti-interference capability, and, by adjusting beam parameters in real time, better adapts to complex electromagnetic environments, improving the system's anti-interference performance.

[0049] By using an FPGA signal processing unit to calculate and distribute weighting coefficients in real time, the digital beamforming unit performs beamforming in the digital domain. This effectively reduces signal processing complexity and latency, and decreases reliance on dedicated DBF chips, avoiding reliability issues associated with cascaded data link architectures. Simultaneously, by optimizing the control of the beamforming matrix, system power consumption can be reduced while maintaining beam performance. Furthermore, real-time adjustment of beam pointing and parameters can further optimize system performance, reducing power consumption and latency. On the other hand, since the digital beamforming unit performs beamforming in the digital domain, it reduces the use of analog components, lowers amplitude and phase errors caused by environmental factors, and improves system reliability.

[0050] Reference Figure 4 In the baseband module, the 10G optical module unit's main function is to communicate with external modules, which then distribute the received satellite platform data stream to each baseband module. The FPGA signal processing unit consists of a signal processing FPGA with ample logic and I / O resources and its peripheral circuitry. The digital beamforming (DBF) unit consists of a fully digital DBF chip and its peripheral circuitry. The DBF chip supports programmable channel count, beam count, and bandwidth for flexible adjustment in different operating scenarios and applications. It also supports multi-device synchronization, enabling synchronized signal processing in the digital domain of multiple baseband modules to support large-scale antenna array applications. The FPGA signal processing unit and the DBF chip communicate via a JESD204B interface for data reception and transmission. Weighting coefficients from the DBF chip are distributed through multiple high-speed parallel data interfaces, with the weighting coefficients taking effect within 10ns.

[0051] In one embodiment, the method further includes: compensating for amplitude and phase errors between each receiving channel or transmitting channel, and distributing co-source radio frequency signals through a radio frequency transceiver unit and a 64-channel power divider to calibrate the phase error to within 2°.

[0052] Specifically, when calibrating the amplitude and phase of the baseband module separately, calibration is performed by distributing the same source RF signal through the RF signal generator and 64-channel power divider of the RF transceiver unit. However, when facing large-scale array applications, the calibration of the receiving channel can be performed by looping the RF transmitting channel back to the receiving channel. Loopback calibration can be achieved using a spatially coupled antenna unit, which greatly reduces the difficulty of operation.

[0053] In this embodiment, an automated amplitude and phase error compensation mechanism is used to calibrate the phase error of each receiving channel to within 2°, thereby achieving excellent channel phase consistency performance, reducing the need for manual calibration and lowering maintenance costs.

[0054] In one embodiment, the FPGA management unit performs on-orbit refresh, reconstruction, and status monitoring of the FPGA signal processing unit through the Slave SelectMAP interface.

[0055] In this embodiment, the refresh process mainly processes the configuration area of ​​the FPGA. It can repair the configuration area in real time for single event latch-up (SEU) faults in the configuration area, thereby ensuring that all functions are not interrupted.

[0056] Reference Figure 4 In one embodiment, the baseband module further includes a Flash storage unit. The Flash storage unit consists of two high-capacity Flash memories that support parallel storage. The storage capacity is partitioned into multiple copies for storage, and a triple-modular redundancy design is implemented. The FPGA management unit enables online reconstruction and refresh of the FPGA signal processing unit.

[0057] The FPGA management unit consists of a single radiation-immune Flash-type FPGA processor and its peripheral circuitry. The FPGA management unit's startup program is stored in its internal RAM to avoid risks such as single-event upsets. The FPGA signal processing unit's program software is stored in Flash memory. The Flash memory and the FPGA management unit communicate via a parallel data interface to read, write, and verify the loaded program.

[0058] When the FPGA signal processing unit is software reset, key parameters can be recovered from the Flash memory attached to the FPGA management module, ensuring the reliability of operation in a spaceborne environment.

[0059] In one embodiment, the radio frequency transceiver unit is an integrated transceiver unit that combines an upconverter, a downconverter, a tunable filter, an ADC, and a DAC.

[0060] In this embodiment, the integration of up / down converters, tunable filters, and other functional modules greatly simplifies the RF link design. The zero-IF architecture sampling reduces the power consumption of the RF transceiver and improves the amplitude and phase consistency between channels.

[0061] In one embodiment, the RF transceiver unit is an 8-transmit / 8-receive RF transceiver integrating an up-converter, down-converter, tunable filter, ADC, and DAC. This single-chip RF transceiver integrates 8 RF receive channels and 8 RF transmit channels, primarily used for synchronous sampling and transmission of S-band RF signals.

[0062] In this embodiment, the transceiver channels can support 64-channel 64-beamforming and shaping respectively. Each transceiver channel can be independently controlled and enabled. The number of channels and beams can be adjusted in real time for different application scenarios to reduce power consumption.

[0063] In one embodiment, the target frequency band signal of each receiving channel is extracted by the radio frequency transceiver unit and transmitted to the digital beamforming unit, including:

[0064] The downconverter, tunable filter, and ADC integrated in the RF transceiver unit sample and decimate the RF signals received by each receiving channel to achieve spectrum separation and extract the target frequency band signal of each receiving channel.

[0065] The target frequency band signals of each receiving channel are transmitted to the digital beamforming unit.

[0066] Reference Figure 4 In one embodiment, the FPGA signal processing unit is provided with two RS422 interfaces between itself and the external module, including one RS422 interface and the other RS422 interface. The first RS422 interface is used for remote control, telemetry and online reconfiguration functions, and the second RS422 interface is used to receive PSS pulse signals sent by the external module.

[0067] The PPS signal in this embodiment can achieve nanosecond-level time synchronization accuracy and can be used for processes such as system clock synchronization and data timestamp synchronization.

[0068] In one embodiment, the baseband module also includes a clock management unit, whose main function is to provide the system operating clock for the FPGA management unit and the FPGA signal processing unit. A separate JESD204B clock network needs to be designed for the high-speed serial JESD204B interface between the RF transceiver unit, digital beamforming unit, and FPGA signal processing unit to support synchronization of critical processes such as multi-channel analog-to-digital signal conversion. Synchronization of signal sampling and processing between chips is achieved through edge-aligned SYSREF signals. The clock source required by JESD204B is designed with a separate RF interface for input from an external module, and a separate synchronization clock SYNC signal and device clock DCLK signal link are designed to support larger-scale antenna array applications.

[0069] Reference Figure 3 In one embodiment, after the baseband module is powered on or reset, the configuration error of the configuration state machine of the FPGA signal processing unit is processed and the watchdog is initialized.

[0070] In one embodiment, handling configuration errors in the configuration state machine of the FPGA signal processing unit and initializing the watchdog timer includes:

[0071] Pulling the PROGRAM_B pin of the FPGA signal processing unit low initiates the clearing of the configuration register. After 1ms, the PROGRAM_B pin is pulled high to exit the configuration register state clearing process and initialize the FPGA configuration logic. If the INIT_B pin goes high, it indicates successful initialization, and FPGA configuration read / write is performed to load the configuration program. If the FPGA's DONE pin goes high, it indicates that the configuration program has been loaded correctly. After the configuration program has been loaded correctly, the FPGA watchdog counter monitors the FPGA's operating status.

[0072] In one embodiment, a counter is designed for each state during the configuration loading process. If the counter overflows, the state is switched to the configuration error handling unit, which corrects the configuration loading.

[0073] In one embodiment, during digital multibeam generation, beam parameters are optimized in real time using gradient descent or a genetic algorithm.

[0074] In this embodiment, beam parameters are optimized in real time using gradient descent or genetic algorithms to adjust channel division, communication bandwidth, beam gain, and directivity. Combined with adaptive null techniques, external interference is suppressed, further enhancing anti-interference capabilities.

[0075] In one embodiment, the radio frequency transceiver unit converts the digital signal to be transmitted into an analog signal and outputs it, including:

[0076] The radio frequency transceiver unit performs interpolation, filtering, and DAC refresh on the digital signal to be transmitted, converting the digital signal to be transmitted into an analog signal.

[0077] The analog signal is modulated to a predetermined radio frequency transmission point by up-conversion and then output.

[0078] It should be understood that, although Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 2 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0079] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method of digital multi-beam synthesis, characterized by, The method is applied to the baseband module in a spaceborne digital phased array, including a radio frequency transceiver unit, an FPGA signal processing unit, an FPGA management unit, a digital beamforming unit, and a 10G optical module unit. The digital beamforming unit integrates 32 GPIO interfaces and 16 LVDS interfaces, which are connected to the FPGA signal processing unit. The method includes: When receiving signals, the target frequency band signals of each receiving channel are extracted by the radio frequency transceiver unit and transmitted to the digital beamforming unit. The digital beamforming unit performs amplitude and phase weighting on the target frequency band signals of each receiving channel to generate corresponding digital multi-beams; during the digital multi-beam generation process, the beamforming matrix controls the beam coherent synthesis, pointing, width and sidelobe level to achieve spatial filtering and interference suppression. The generated digital multibeams are processed and aggregated by the FPGA signal processing unit, and then the data is aggregated to an external module by the 10G optical module unit before being transmitted to the satellite platform. When transmitting signals, user data is sent to the external module via the satellite platform. After being received by the 10G optical module unit, the data is transmitted to the FPGA signal processing unit. The FPGA signal processing unit calculates the complex weighting coefficients of each transmission channel based on the spatial location of the target ground coverage area sent by the satellite platform, and sends the complex weighting coefficients to the digital beamforming unit. The digital beamforming unit generates narrow beams corresponding to each transmission channel based on complex weighting coefficients to focus energy on the target area, controls the sidelobe level of the narrow beams, copies user data to all transmission channels, and applies preset weighting coefficients to the user data of each transmission channel to adjust the amplitude and phase of the narrow beams corresponding to each transmission channel; the complex weighting coefficients of the narrow beams corresponding to each transmission channel are superimposed and synthesized to form the digital signals to be transmitted in each transmission channel. The radio frequency transceiver unit converts the digital signal to be transmitted into an analog signal and then outputs it.

2. The method of claim 1, wherein, The method further includes: To compensate for the amplitude and phase errors between each receiving or transmitting channel, the same source radio frequency signals are distributed through the radio frequency transceiver unit and the 64-channel power divider to calibrate the phase error to within 2°.

3. The method of claim 1, wherein, The FPGA management unit performs on-orbit refresh, reconstruction, and status monitoring of the FPGA signal processing unit through the Slave SelectMAP interface.

4. The method of claim 1, wherein, The radio frequency transceiver unit is an integrated radio frequency transceiver that combines an upconverter, a downconverter, a tunable filter, an ADC, and a DAC.

5. The method of claim 4, wherein, The radio frequency transceiver unit extracts the target frequency band signal of each receiving channel and transmits it to the digital beamforming unit, including: The radio frequency transceiver unit integrates a downconverter, a tunable filter, and an ADC to sample and decimate the radio frequency signals received by each receiving channel, thereby achieving spectrum separation and extracting the target frequency band signal of each receiving channel. The target frequency band signals of each receiving channel are transmitted to the digital beamforming unit.

6. The method of claim 1, wherein, The FPGA signal processing unit is provided with two RS422 interfaces between itself and the external module, including one RS422 interface and the other RS422 interface. The first RS422 interface is used for remote control, telemetry and online reconfiguration functions, and the second RS422 interface is used to receive PSS pulse signals sent by the external module.

7. The method of claim 1, wherein, After the baseband module is powered on or reset, it processes the configuration errors of the configuration state machine of the FPGA signal processing unit and initializes the watchdog timer.

8. The method of claim 7, wherein, The process of handling configuration errors in the configuration state machine of the FPGA signal processing unit and initializing the watchdog timer includes: Pulling the PROGRAM_B pin of the FPGA signal processing unit low initiates the clearing of the configuration register. After 1ms, the PROGRAM_B pin is pulled high to exit the configuration register state clearing process and initialize the FPGA configuration logic. If the INIT_B pin goes high, it indicates successful initialization, and FPGA configuration read / write is performed to load the configuration program. If the FPGA's DONE pin goes high, it indicates that the configuration program has been loaded correctly. After the configuration program is loaded correctly, the FPGA watchdog counter monitors the FPGA's operating status. A counter is designed for each state during the configuration loading process. If the counter overflows, the state is redirected to the configuration error handling unit, which then corrects the configuration loading.

9. The method of claim 1, wherein, In the process of digital multibeam generation, beam parameters are optimized in real time through gradient descent or genetic algorithms.

10. The method of claim 4, wherein, The radio frequency transceiver unit converts the digital signal to be transmitted into an analog signal and then outputs it, including: The radio frequency transceiver unit performs interpolation, filtering, and DAC refresh on the digital signal to be transmitted, converting the digital signal to be transmitted into an analog signal. The analog signal is modulated to a predetermined radio frequency transmission point by up-conversion and then output.

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