Seeker signal processing method based on FPGA and DSP and related equipment

Abstract

The invention provides a seeker signal processing method based on an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor) and related equipment, and relates to the field of communication transmission. The method comprises the following steps: receiving an image data stream, and carrying out hard synchronization on an FPGA, a master DSP and a slave DSP; performing first data processing on the image data stream by utilizing the FPGA; performing data extraction on the image data stream and the data packet corresponding to the image data stream by using the FPGA to obtain extracted data, and respectively sending the extracted data to the master DSP and the slave DSP; performing second data processing on the extracted data by using the master DSP, and performing third data processing on the extracted data by using the slave DSP; the main DSP is used for sending second to-be-displayed data to the FPGA through the first multiplexer, the slave DSP is used for sending third to-be-displayed data to the FPGA through the second multiplexer, the FPGA is used for transmitting the first to-be-displayed data, the second to-be-displayed data and the third to-be-displayed data to the storage module and the display module, and efficient and real-time data transmission can be achieved.

Description

Technical Field

[0001] This application relates to the field of communication transmission technology, specifically to a seeker signal processing method and related equipment based on FPGA and DSP. Background Technology

[0002] Modern guidance systems place stringent demands on seeker data processing, requiring them to handle massive amounts of high-speed data from high-resolution imaging and radar echoes, as well as real-time requirements in complex scenarios involving interference. Among related technologies, FPGAs (Field-Programmable Gate Arrays) are used for data processing. FPGAs, with their parallel hardware architecture, high-speed interface adaptability, and radiation-hardened characteristics, have become key components for seekers to achieve core functions such as real-time image preprocessing and multi-mode data fusion, driving the evolution of guidance systems towards higher precision and intelligence. However, with increasingly complex scenarios, the aforementioned single FPGA processing architecture is gradually reaching its computational power bottleneck, making it difficult to meet the demands of high-performance, real-time data transmission and processing. Summary of the Invention

[0003] This application provides a seeker signal processing method and related equipment based on FPGA and DSP, which can achieve efficient and real-time data transmission.

[0004] The technical solution of this application embodiment is as follows: In a first aspect, embodiments of this application provide a seeker signal processing method based on FPGA and DSP, the method comprising: It receives the image data stream acquired by the seeker and performs hard synchronization on the FPGA, main DSP, and slave DSP; The image data stream is processed using the FPGA to obtain first data to be displayed. The FPGA is used to extract data from the image data stream and the corresponding data packets to obtain extracted data. The extracted image and instructions in the extracted data are sent to the main DSP through a preset first multiplexer, and the extracted image in the extracted data is sent to the slave DSP through a preset second multiplexer. When the data packets meet the preset number of packets, a doorbell packet is sent to the main DSP and the slave DSP respectively. The doorbell packet is used to indicate that a frame of data transmission is completed. The main DSP performs a second data processing on the extracted data to obtain a second data to be displayed, and the slave DSP performs a third data processing on the extracted data to obtain a third data to be displayed. The second data processing includes loading the extracted image, overlaying the character information of the extracted image, and forwarding instructions. The third data processing includes scaling the extracted image and quantizing the data of the extracted image. The main DSP sends the second data to be displayed to the FPGA through the first multiplexer, and the slave DSP sends the third data to be displayed to the FPGA through the second multiplexer. The FPGA then transmits the first data to be displayed, the second data to be displayed, and the third data to be displayed to the storage module and the display module.

[0005] In the above technical solution, the image data stream acquired by the receiving head provides the foundation for subsequent efficient and real-time data processing. Hard synchronization of the FPGA, main DSP, and slave DSP eliminates errors and improves processing accuracy and system stability. The FPGA performs initial data processing on the image data stream to obtain the first data to be displayed, enabling timely response to data processing needs and meeting real-time processing requirements. The FPGA extracts data from the image data stream and its corresponding data packets, obtaining extracted data. A preset first multiplexer sends the extracted image and instructions from the extracted data to the main DSP, and a preset second multiplexer sends the extracted image from the extracted data to the slave DSP. When the data packets meet a preset number, a doorbell packet is sent to both the main and slave DSPs. The doorbell packet indicates the completion of a data transmission frame, achieving efficient data transmission through multiplexing. The selector distributes data to the main DSP and slave DSP, enabling parallel data processing, improving computing power, and achieving efficient data processing. The main DSP performs a second data processing step on the extracted data to obtain the second data to be displayed, and the slave DSP performs a third data processing step to obtain the third data to be displayed. The second data processing includes loading the extracted image, overlaying character information from the extracted image, and forwarding instructions. The third data processing includes scaling the extracted image and quantizing the extracted image data. By performing image processing at different levels, the requirements for improved computing power and real-time processing can be met. The main DSP sends the second data to be displayed to the FPGA through a first multiplexer, and the slave DSP sends the third data to the FPGA through a second multiplexer. The FPGA then transmits the first, second, and third data to the storage and display modules. This achieves efficient and real-time data transmission and image processing.

[0006] In some embodiments of this application, the step of using the master DSP to send the second data to be displayed to the FPGA through the first multiplexer, and using the slave DSP to send the third data to be displayed to the FPGA through the second multiplexer, includes: The main DSP sends the second data to be displayed to the first multiplexer, and the first multiplexer parses the second data to be displayed to obtain the first parsed data; The third data to be displayed is sent from the DSP to the second multiplexer, and the second multiplexer parses the third data to be displayed to obtain the second parsed data; The first multiplexer sends the first parsed data to the FPGA, and the second multiplexer sends the second parsed data to the FPGA, so that the FPGA sends the first parsed data to the corresponding address in the storage module for storage, and sends the second parsed data to the corresponding address in the storage module for storage.

[0007] In some embodiments of this application, the hard synchronization of the FPGA, master DSP, and slave DSP includes: using the FPGA to acquire the level signal corresponding to the image data stream, performing anti-jitter processing on the level signal for a preset period to obtain a synchronization signal; When the synchronization signal is high, the flag signal corresponding to the high level is pulled high to obtain the first flag signal; when the synchronization signal is low, the flag signal corresponding to the low level is pulled low to obtain the second flag signal. When the second flag signal is converted to the first flag signal, signal synchronization is performed on the master DSP and the slave DSP.

[0008] In some embodiments of this application, the step of using the FPGA to perform first data processing on the image data stream to obtain first data to be displayed includes: The FPGA is used to perform pixel frequency statistics on the image data stream to obtain multiple cumulative pixel statistics and the total number of pixels. Divide each of the cumulative pixel statistics by the total number of pixels to obtain the cumulative percentage corresponding to each of the cumulative pixel statistics; Find the minimum gray value from each of the accumulated pixel statistics. If the accumulated percentage corresponding to the minimum gray value is greater than a preset first percentage threshold, the minimum gray value is taken as the low threshold. Find the maximum gray value from each of the cumulative pixel statistics. If the cumulative percentage corresponding to the maximum gray value is greater than a preset second percentage threshold, the maximum gray value is taken as a high threshold. The sum of the first percentage threshold and the second percentage threshold is equal to the cumulative percentage corresponding to pixel 255. Image processing is performed based on the high threshold and the low threshold to obtain the first data to be displayed.

[0009] In some embodiments of this application, the step of performing image processing based on the high threshold and the low threshold to obtain the first data to be displayed includes: Based on the high threshold and the low threshold, the image is stretched using a preset stretching algorithm to obtain stretched pixel values; the stretched pixel values ​​are then used to form the first data to be displayed. The stretching algorithm formula is as follows: Where u_gs represents the stretched pixel value, H represents the high threshold, L represents the low threshold, and gs represents the grayscale value.

[0010] In some embodiments of this application, when there are two channels for receiving the image data stream, after receiving the image data stream acquired by the seeker, the method further includes: Determine whether the image data stream has an image frame header. If an image frame header exists, add a frame header synchronization flag to the image data stream. Reassemble the image data stream according to the frame header synchronization flag to obtain two sets of reassembled image data streams. The two sets of reconstructed image data streams are respectively queued and buffered to obtain a first buffer queue and a second buffer queue; The reconstructed image data stream in the first buffer queue and the reconstructed image data stream in the second buffer queue are synchronized in the clock domain to obtain an image sequence; Determine whether the image sequence is a complete frame. If it is a complete frame, send the image sequence to the FPGA and use the image sequence as the image data stream to perform the hard synchronization step on the FPGA, master DSP and slave DSP.

[0011] In some embodiments of this application, after determining whether the reconstructed image data stream is a complete frame based on the image sequence, the method further includes: In the absence of complete frames, the image sequence is padded with broken frames. The steps of determining whether the image data stream has an image frame header, adding a frame header synchronization flag to the image data stream if an image frame header exists, and reconstructing the image data stream according to the frame header synchronization flag to obtain two sets of reconstructed image data streams are performed.

[0012] Secondly, embodiments of this application provide a seeker signal processing system based on FPGA and DSP, the system comprising: The receiving and synchronization module is used to receive the image data stream acquired by the seeker and perform hard synchronization of the FPGA, the main DSP, and the slave DSP. The first data processing module is used to perform first data processing on the image data stream using the FPGA to obtain first data to be displayed. The first data transmission module is used to extract data from the image data stream and the corresponding data packets using the FPGA to obtain extracted data. The extracted image and instructions in the extracted data are sent to the main DSP through a preset first multiplexer, and the extracted image in the extracted data is sent to the slave DSP through a preset second multiplexer. When the data packets meet the preset number of packets, a doorbell packet is sent to the main DSP and the slave DSP respectively. The doorbell packet is used to indicate that a frame of data transmission is completed. The second data processing module is used to perform second data processing on the extracted data using the main DSP to obtain second data to be displayed, and to perform third data processing on the extracted data using the slave DSP to obtain third data to be displayed. The second data processing process includes loading the extracted image, overlaying the character information of the extracted image, and forwarding instructions. The third data processing process includes scaling the extracted image and quantizing the data of the extracted image. The second data transmission module is used to send the second data to be displayed to the FPGA through the first multiplexer using the main DSP, send the third data to be displayed to the FPGA through the second multiplexer using the slave DSP, and transmit the first data to be displayed, the second data to be displayed, and the third data to be displayed to the storage module and the display module using the FPGA.

[0013] Thirdly, embodiments of this application provide an electronic device including a processor, a memory, a user interface, a communication bus, and a network interface. The processor, the memory, the user interface, and the network interface are respectively connected to the communication bus. The memory is used to store instructions. The user interface and the network interface are used to communicate with other devices. The processor is used to execute the instructions stored in the memory to cause the electronic device to perform the method described in any one of the first aspects.

[0014] Fourthly, embodiments of this application provide a computer-readable storage medium storing instructions that, when executed, perform the method described in any one of the methods provided in the first aspect above.

[0015] In summary, one or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages: 1. By first receiving the image data stream acquired by the seeker, a foundation is laid for subsequent efficient and real-time data processing. Hard synchronization of the FPGA, main DSP, and slave DSP eliminates errors and improves processing accuracy and system stability. The FPGA performs initial data processing on the image data stream to obtain the first data to be displayed, enabling timely response to data processing needs and meeting real-time processing requirements. The FPGA extracts data from the image data stream and its corresponding data packets, obtaining extracted data. A preset first multiplexer sends the extracted image and instructions from the extracted data to the main DSP, and a preset second multiplexer sends the extracted image from the extracted data to the slave DSP. When the data packets meet the preset number, a doorbell packet is sent to both the main and slave DSPs. The doorbell packet indicates the completion of one frame of data transmission, achieving efficient data transmission through multiplexing. The selector distributes data to the main DSP and slave DSP, enabling parallel data processing, improving computing power, and achieving efficient data processing. The main DSP performs a second data processing step on the extracted data to obtain the second data to be displayed, and the slave DSP performs a third data processing step to obtain the third data to be displayed. The second data processing includes loading the extracted image, overlaying character information from the extracted image, and forwarding instructions. The third data processing includes scaling the extracted image and quantizing the extracted image data. By performing image processing at different levels, the requirements for improved computing power and real-time processing can be met. The main DSP sends the second data to be displayed to the FPGA through a first multiplexer, and the slave DSP sends the third data to the FPGA through a second multiplexer. The FPGA then transmits the first, second, and third data to the storage and display modules. This achieves efficient and real-time data transmission and processing of image data streams. Therefore, it effectively solves the problem that a single framework in related technologies cannot meet the requirements of high-performance, real-time data transmission and processing.

[0016] 2. By acquiring the level and pulling the high level high and the low level low, the image data stream is transmitted to the dual DSP when the rising edge occurs. This not only enables real-time processing but also facilitates subsequent parallel processing using the dual DSP, thereby improving processing performance.

[0017] 3. By recombining the data, frame synchronization is achieved, which facilitates subsequent data transmission and image processing. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating a seeker signal processing method based on FPGA and DSP provided in one embodiment of this application; Figure 2This is a schematic diagram of the overall module of a seeker signal processing method based on FPGA and DSP provided in one embodiment of this application; Figure 3 This is a schematic diagram of the FPGA top-level design module of the seeker signal processing method based on FPGA and DSP provided in one embodiment of this application; Figure 4 yes Figure 1 A flowchart illustrating another sub-step of step S200; Figure 5 This is a schematic diagram of the structure of a seeker signal processing system based on FPGA and DSP provided in one embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in one embodiment of this application. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0020] In the description of the embodiments of this application, the words "for example" or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design that is described as "for example" or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Rather, the use of the words "for example" or "for instance" is intended to present the relevant concepts in a specific manner.

[0021] In the description of the embodiments of this application, the term "multiple" means two or more. For example, multiple systems means two or more systems, and multiple screen terminals means two or more screen terminals. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0022] This application provides a seeker signal processing method, system, electronic device, and readable storage medium based on FPGA and DSP. The FPGA and DSP-based seeker signal processing method first receives the image data stream acquired by the seeker, providing a foundation for subsequent efficient and real-time data processing. Hard synchronization is performed on the FPGA, master DSP, and slave DSP to eliminate errors and improve processing accuracy and system stability. The FPGA performs first data processing on the image data stream to obtain first data to be displayed, enabling timely response to data processing needs and meeting real-time processing requirements. The FPGA extracts data from the image data stream and its corresponding data packets to obtain extracted data. The extracted image and instructions from the extracted data are sent to the master DSP through a preset first multiplexer, and the extracted image from the extracted data is sent to the slave DSP through a preset second multiplexer. When the data packets meet a preset number of packets, a doorbell packet is sent to both the master DSP and the slave DSP. The packet indicates the completion of a frame of data transmission, enabling efficient data transmission. Data is distributed via a multiplexer to the main DSP and slave DSP, achieving parallel data processing, improving computing power, and realizing efficient data processing. The main DSP performs a second data processing on the extracted data to obtain the second data to be displayed, and the slave DSP performs a third data processing on the extracted data to obtain the third data to be displayed. The second data processing includes loading the extracted image, overlaying character information from the extracted image, and forwarding instructions. The third data processing includes scaling the extracted image and quantizing the extracted image data. Image processing at different levels meets the requirements for improved computing power and real-time processing. The main DSP sends the second data to be displayed to the FPGA via a first multiplexer, and the slave DSP sends the third data to the FPGA via a second multiplexer. The FPGA then transmits the first, second, and third data to the storage and display modules. This achieves efficient and real-time data transmission and image processing.

[0023] It should be noted that this FPGA and DSP-based seeker signal processing method can be used for target tracking in UAVs, as well as image processing in the military field. By employing an FPGA and dual DSP (Digital Signal Processor) architecture for image acquisition, high-speed image transmission, and image processing, efficient and real-time data transmission can be achieved.

[0024] The technical solutions provided in the embodiments of this application will be further described below with reference to the accompanying drawings.

[0025] Reference Figure 1 , Figure 1This is a flowchart illustrating the FPGA and DSP-based seeker signal processing method provided in this application embodiment. The FPGA and DSP-based seeker signal processing method is applied to an FPGA and DSP-based seeker signal processing device, and is executed by a processor in an electronic device or a readable storage medium. The FPGA and DSP-based seeker signal processing method includes steps S100, S200, S300, S400, and S500.

[0026] Step S100: Receive the image data stream acquired by the seeker head and perform hard synchronization on the FPGA, main DSP, and slave DSP.

[0027] In one embodiment, an infrared seeker or a lidar sensor can be used to acquire image data streams. The image data stream is either the raw data stream or point cloud data stream transmitted by the sensor, providing data support for subsequent image processing.

[0028] like Figure 2 As shown, the signal processing system includes an FPGA, a main DSP, a slave DSP, a storage module, and a display module. The image data stream is transmitted to the storage module, which uses DDR memory to store the image data stream in real time. The FPGA reads data from the storage module for data processing and data transmission. The FPGA includes an image data coprocessing module and an application layer control interaction module. The image data coprocessing module is used to process the image data stream and interact with the main DSP framework, the slave DSP framework, the storage module, and the display module. The application layer control interaction module is used for network transmission. The FPGA uses the JFM7K325T-X chip, which can improve parallel processing efficiency. Data transmission between the FPGA, the main DSP, and the slave DSP is achieved through a serial interface module. The main DSP is used for image loading, image and character information overlay, and instruction forwarding. The slave DSP is used for image scaling and data quantization, etc. The main DSP and the slave DSP can also interact with the storage module. The main DSP uses the FT-M6678N(0) chip, and the slave DSP also uses the FT-M6678N(1) chip.

[0029] The DSP's underlying design includes: SRIO (Serial Communication Protocol), synchronous RS422, synchronous RS485, synchronous semaphore, FPGA version information reading, dual DSP communication, character display, DDR memory, terminal, DMA (Direct Memory Access), IPC (Inter-Process Communication), timers, and SPI FLASH (Serial Peripheral Interface). The FPGA's underlying design includes: synchronous RS422, synchronous RS485, CAN (Controller Area Network), CameraLink interface, image frame information and quantization, Gigabit Ethernet, and online software upgrades. It should be noted that the CameraLink interface is used to transmit image data streams to DDR memory for storage. This CameraLink interface has two chips with non-uniform phases, meaning there are two channels for receiving image data streams. With two channels for receiving image data streams, the FPGA and DSP-based seeker signal processing method after receiving the image data stream acquired by the seeker includes, but is not limited to, determining whether an image frame header exists in the image data stream. Specifically, this involves detecting whether the image data stream has a rising edge of FVAL. If a rising edge of FVAL exists, an image frame header exists. If an image frame header exists, a frame header synchronization flag is added to the image data stream. This frame header synchronization flag is used to distinguish the start position of the image data stream frame for positioning. It should be noted that adding a frame header synchronization flag to the image data stream involves inserting a 1 before the first data item and inserting 0s before subsequent data items. The rising edge of FVAL represents a valid frame signal; by determining whether an image frame header exists, the validity of the image data stream can be detected. Other detection signals are also included; for example, LVAL represents the row valid signal, DVAL represents the data valid signal, and CLK represents the clock signal.

[0030] In one embodiment, it is determined whether the image data stream has an image frame header. If no image frame header is found, it indicates that the image data stream may not be valid data, and the image data stream is skipped. When an FVAL rising edge is detected, a frame header synchronization flag is added to the image data stream to ensure that it is a valid image data stream, thereby ensuring data accuracy and enabling efficient data transmission.

[0031] In one embodiment, the image data stream is reassembled according to the frame header synchronization flag to obtain two sets of reassembled image data streams. Specifically, since there are two chips, i.e., two data transmission channels, the two channels transmit data according to a defined pixel order. For example, in the case of an 8-bit grayscale image data stream, the first channel transmits the high 4 bits and the second channel transmits the low 4 bits; in the case of 24-bit RGB, the first channel transmits the high 8 bits and the second channel transmits the low 8 bits. Based on the added frame header synchronization flag, the image data stream of each channel is arranged into frames according to a clock signal to obtain two sets of reassembled image data streams, so that the two sets of reassembled image data streams can be asynchronously clock-domain synchronized subsequently.

[0032] Then, one reconstructed image data stream is queued to form a first buffer queue, and the other reconstructed image data stream is queued to form a second buffer queue. The queues have a first-in, first-out (FIFO) characteristic to facilitate asynchronous clock synchronization between the two sets of reconstructed image data streams. The first and second buffer queues have corresponding clocks for subsequent asynchronous clock synchronization.

[0033] Based on the reconstructed image data streams in the first and second buffer queues, taking an 8-bit grayscale image as an example, the high 4 bits of the reconstructed image data stream in the first buffer queue and the low 4 bits of the reconstructed image data stream in the second buffer queue are read. Then, the start position of the frame is found according to the frame header synchronization flag, and the complete frames are reassembled sequentially using clock signals. That is, frames with the same clock signal are read from the first and second buffer queues and combined to obtain an image sequence. For example, frames with the same clock signal are placed in the clock domain and reconstructed into 64 bits of data. A flag bit is added before this data to obtain a 65-bit image sequence. Clock domain synchronization is achieved, and efficient data transmission is achieved by transmitting through two channels. The reconstructing of the image data streams facilitates subsequent image data processing.

[0034] To determine whether an image sequence is a complete frame, signals such as the rising edge of FVAL, the line valid signal of LVAL, the data valid signal of DVAL, and the clock signal of CLK can be used. If it is a complete frame, the image sequence stream is sent to the FPGA and used as an image data stream to enable hard synchronization of the FPGA, master DSP, and slave DSP for subsequent image processing.

[0035] In one embodiment, after determining whether the reconstructed image data stream is a complete frame based on the image sequence, the FPGA and DSP-based seeker signal processing method further includes, but is not limited to, the following steps: in the absence of a complete frame, performing broken frame padding on the image sequence, performing separate determinations on whether the image data stream has an image frame header, adding a frame header synchronization flag to the image data stream if an image frame header exists, and reconstructing the image data stream according to the frame header synchronization flag to obtain two sets of reconstructed image data streams.

[0036] Specifically, in the case of incomplete frames, indicating that the image data stream frame data does not correspond, the reconstructed image data stream is padded with broken frames. Following the example above, this involves counting each frame of 65-bit data; if 65 bits are not met, the remaining bits are padded with 0s. Then, the image sequence is reset, one flag bit is removed, and the data is divided into 32 bits for the first channel and another 32 bits for the second channel. The process involves checking whether an image frame header exists in the image data stream. If an image frame header exists, a frame header synchronization flag is added to the image data stream. Based on the frame header synchronization flag, the image data stream is reconstructed, resulting in two sets of reconstructed image data streams. Subsequent steps are similar to the above process and will not be elaborated here.

[0037] In one embodiment, hard synchronization is performed on the FPGA, master DSP, and slave DSP, including but not limited to: using the FPGA to acquire the level signal corresponding to the image data stream, performing anti-jitter processing on the level signal for a preset period to obtain a synchronization signal; when the synchronization signal is high, pulling up the flag signal corresponding to the high level to obtain a first flag signal; when the synchronization signal is low, pulling down the flag signal corresponding to the low level to obtain a second flag signal; and when the second flag signal converts to the first flag signal, signal synchronization is performed on the master DSP and slave DSP.

[0038] Specifically, the system utilizes an FPGA to acquire the corresponding level signals of the image data stream. The input signal level is monitored through FPGA pins. A high level is defined as a pin voltage greater than or equal to a preset voltage threshold, and a low level as a pin voltage less than the preset threshold. The preset voltage thresholds can be 1.8V / 3.3V, conforming to FPGA I / O standards. A filtering circuit then performs anti-jitter processing on the level signal for a preset period to obtain a synchronization signal. Anti-jitter reduces interference; the preset period is 10 cycles, etc. If no jitter occurs within 10 cycles, the acquired level signal is considered stable. When the synchronization signal is high, the corresponding flag signal is pulled high (i.e., the FPGA's internal flag signal is set to 1), obtaining the first flag signal, which provides the basis for subsequent signal rising edge detection. When the synchronization signal is low, the corresponding flag signal is pulled low (i.e., the FPGA's internal flag signal is set to 0), obtaining the second flag signal, which also provides the basis for subsequent signal rising edge detection.

[0039] When the second flag signal transitions back to the first flag signal, it indicates a low-to-high transition in the flag signal. This is specifically achieved by comparing the flag signals over two consecutive clock cycles. Upon detecting a transition from 0 to 1 (i.e., a rising edge), the FPGA synchronizes the signal by sending a hard synchronization data packet to the master and slave DSPs via the serial interface for time synchronization or event alignment. After the hard synchronization data packet is sent, the FPGA sends a doorbell signal to both the master and slave DSPs, indicating that the hard synchronization instruction processing is complete. By performing hard synchronization, parallel computation between the FPGA, master DSP, and slave DSP can be achieved, improving the timeliness of data transmission.

[0040] Reference Figure 3 , Figure 3This diagram illustrates the top-level design framework of the FPGA. The FPGA receives, processes, and forwards data through an image data co-processing module (represented as the topproject module). The image data stream enters the FPGA via the CameraLink interface and is transmitted to the topproject module. The topproject module divides the image data stream into three paths: two are sent to the master DSP and the slave DSP respectively; the third path, after internal processing within the topproject module, is sent to the display module (VAG display module) for VGA display and to the image scaling module (scaler_top module) for image scaling. The scaler_top module returns the scaled image to the topproject module, which then sends the image data to the display module (PAL display module). The topproject module can also send instructions to the master DSP via a converter, which then sends the image data stream to the slave DSP.

[0041] The following are detailed descriptions of the interconnected modules within the topproject module, as well as the data processing capabilities of the topproject module.

[0042] Step S200: The image data stream is processed by the FPGA to obtain the first data to be displayed.

[0043] like Figure 4 As shown, the image data stream is processed using an FPGA to obtain the first data to be displayed, including but not limited to the following steps: Step S210: Use the FPGA to perform pixel frequency statistics on the image data stream to obtain multiple cumulative pixel statistics and the total number of pixels.

[0044] In some possible embodiments of this application, an FPGA is used to perform pixel frequency statistics on the image data stream. This is done by traversing all pixels in the image data stream, counting the number of times each pixel appears, and accumulating these counts to obtain a cumulative pixel count for each pixel. By counting all pixels in the image data stream, the total number of pixels is obtained. This is then used for subsequent threshold calculations based on the cumulative pixel count and the total number of pixels.

[0045] Step S220: Divide each cumulative pixel statistical value by the total number of pixels to obtain the cumulative percentage corresponding to each cumulative pixel statistical value.

[0046] In some possible embodiments of this application, the cumulative percentage corresponding to each cumulative pixel statistical value is obtained by dividing each cumulative pixel statistical value by the total number of pixels. This cumulative percentage corresponds to the percentage of each pixel in the total number of pixels, providing a basis for subsequent calculation of the high threshold and low threshold.

[0047] Step S230: Find the minimum gray value from each cumulative pixel statistical value. If the cumulative percentage corresponding to the minimum gray value is greater than the preset first percentage threshold, the minimum gray value is taken as the low threshold.

[0048] In some possible embodiments of this application, the minimum grayscale value is found from the cumulative pixel statistics. These cumulative pixel statistics can be sorted, with the first value in ascending order being the minimum grayscale value. The first percentage threshold can be 5%, and pixels with a cumulative percentage less than 5% are considered dark pixels. If the cumulative percentage corresponding to the minimum grayscale value is greater than the preset first percentage threshold, the minimum grayscale value is used as the low threshold, and the top 5% of dark pixels with the fewest pixels are removed.

[0049] Step S240: Find the maximum gray value from each cumulative pixel statistical value. If the cumulative percentage corresponding to the maximum gray value is greater than the preset second percentage threshold, take the maximum gray value as the high threshold. The sum of the first percentage threshold and the second percentage threshold is equal to the cumulative percentage corresponding to pixel 255.

[0050] In some possible embodiments of this application, the maximum grayscale value is found from the cumulative pixel statistics. These cumulative pixel statistics can be sorted, with the highest grayscale value being the first in descending order. The second percentage threshold can be 95%, and the sum of the first and second percentage thresholds equals the cumulative percentage corresponding to pixel 255. If the cumulative percentage corresponding to the maximum grayscale value is greater than the preset second percentage threshold, or if the cumulative percentage corresponding to pixel 255 minus the cumulative percentage corresponding to the maximum grayscale value is less than or equal to the first percentage threshold, the maximum grayscale value is used as the high threshold, and the last 5% of bright pixels (those with the fewest pixels) are removed.

[0051] Step S250: Perform image processing based on the high threshold and the low threshold to obtain the first data to be displayed.

[0052] In one embodiment, image processing is performed based on a high threshold and a low threshold to obtain first data to be displayed, including but not limited to: stretching the image using a preset stretching algorithm based on the high threshold and the low threshold to obtain stretched pixel values; and using the stretched pixel values ​​to form the first data to be displayed. The stretching algorithm formula is: Where u_gs represents the stretched pixel value, H represents the high threshold, L represents the low threshold, and gs represents the grayscale value.

[0053] Specifically, for each grayscale value gs in the image data stream, the aforementioned stretching algorithm is used to process the grayscale value, resulting in a stretched pixel value. For each grayscale value in the image data stream, the pixel value between [L, H] is linearly stretched to [0, 255], and any excess is cropped. This improves contrast and makes details in both dark and bright areas clearer. The stretched pixel values ​​are then arranged according to their original grayscale values ​​to obtain the first data to be displayed. Compared to the image data stream, the first data to be displayed improves contrast, making details in both dark and bright areas clearer; it also quickly enhances global contrast and improves the accuracy of real-time processing.

[0054] In one embodiment, the image data stream is processed using an FPGA to obtain first data to be displayed. A combination of local adaptive and nonlinear transformation processing can also be employed. Specifically, the image data stream is divided into overlapping or non-overlapping local regions to obtain multiple local regions. For example, non-overlapping local region division can be used, utilizing a 3×3 or 5×5 window to divide the image data stream into multiple regions. The dynamic range is calculated for each local region. The dynamic range can be calculated by subtracting the minimum value from the maximum value, or by calculating the standard deviation, etc., and the dynamic range characterizes the local contrast of the image data stream. For example, using a 5×5 window, the maximum and minimum values ​​of pixels within the local region (5×5 window) are calculated, and the dynamic range is the maximum value minus the minimum value. A preset transformation function is used to map each pixel value in the image data stream to a corresponding new pixel value. The preset transformation function is an S-shaped curve, expressed by the formula: Where x0 represents the mean of the local partition, k represents the slope parameter, α represents the hyperparameter, DR represents the dynamic range, x represents the pixel value in the image data stream, and f(x) represents the new pixel value corresponding to the pixel value.

[0055] Specifically, the S-curve is dynamically adjusted using statistics from multiple locally segmented regions. x0 is set as the dynamic range, centered on the midtones. The α value ranges from 0.5 to 2. In the formula above, a larger dynamic range results in a smoother curve and stronger compression, while a smaller dynamic range results in a steeper curve and stronger stretching. The adjusted S-curve is then used to map each pixel value in the image data stream to its corresponding new pixel value. When local regions are divided into non-overlapping regions, the new pixel values ​​in each region are merged to obtain the first set of data to be displayed. This compresses high dynamic range regions and stretches low dynamic range regions, improving the accuracy of real-time processing.

[0056] It should be noted that when local regions are divided into overlapping parts, it is not possible to directly merge the various parts to obtain the first data to be displayed. To avoid the block effect in overlapping areas, a smooth transition is performed. This smooth transition can be achieved by weighted fusion of the overlapping parts, assigning each pixel a contribution weight from multiple windows, with the weight decreasing as the distance from the window center increases. Then, linear interpolation is used for smoothing to obtain the pixel values ​​of the overlapping areas. Next, an S-curve is used to map the pixels of each processed local part to obtain new pixel values ​​for each part. These new pixel values ​​are then merged to obtain the first data to be displayed. This local parallel processing of the first data to be displayed enables efficient image processing, suppresses ring noise, and improves the accuracy of real-time processing.

[0057] Step S300: The FPGA is used to extract data from the image data stream and the corresponding data packets to obtain extracted data. The extracted image and instructions in the extracted data are sent to the main DSP through a preset first multiplexer, and the extracted image in the extracted data is sent to the slave DSP through a preset second multiplexer. When the data packets meet the preset number of packets, a doorbell packet is sent to the main DSP and the slave DSP respectively. The doorbell packet is used to indicate that a frame of data transmission is completed.

[0058] In one embodiment, the data packets corresponding to the image data stream are frame data packets encapsulated for sending the image data stream. The FPGA is used to extract data from the image data stream and its corresponding data packets. Specifically, based on the encapsulation frames of the data packets, the packets are parsed, removing the frame header and trailer. The frame header synchronization flag is removed from the image data stream to extract valid image data information. This valid data is then decomposed to obtain extracted data, which includes extracted images, character information, and instructions. This extracted data is the valid image data corresponding to the image data stream. Subsequent processing of the extracted data is used for image display.

[0059] Then, the FPGA is used to send the extracted image and instructions from the extracted data to a first multiplexer. This first multiplexer can transmit image and instruction information, and then sends the extracted image and instructions to the main DSP for processing. The FPGA is also used to send the extracted image from the extracted data to a second multiplexer, which can only transmit image information. This second multiplexer then sends the image information to the slave DSP for processing. It should be noted that during transmission, to ensure data transmission accuracy, the number of transmitted data packets is used to determine whether image transmission is complete. If the number of data packets meets the preset limit, a doorbell packet is sent to both the main and slave DSPs. The doorbell packet indicates the completion of a frame of data transmission, distinguishing data transmission and ensuring data security and accuracy. The preset packet count is 10240 packets, and the first and second multiplexers are serial interfaces, enabling parallel transmission.

[0060] It should also be noted that before using the topproject module in the FPGA to split the data stream, it is first necessary to determine whether each piece of hardware connected to the FPGA is ready. For example, is the DSP ready to receive data? Is the DDR memory initialized? Is the SRIO interface successfully connected? Is the hardware synchronization successful? If all the above hardware is ready, the image data stream is split through the topproject module. One path sends the image data stream to the main DSP and the slave DSP, while the other path uses the FPGA to process the image and store it in the DDR memory. Finally, the processed data is sent to the display module for display.

[0061] Step S400: The main DSP performs second data processing on the extracted data to obtain second data to be displayed, and the slave DSP performs third data processing on the extracted data to obtain third data to be displayed. The second data processing includes loading the extracted image, overlaying the character information of the extracted image, and forwarding instructions. The third data processing includes scaling the extracted image and quantizing the data of the extracted image.

[0062] In one embodiment, the second data processing includes loading the extracted image, overlaying character information from the extracted image, and forwarding instructions. The main DSP performs these processes to obtain the second data to be displayed. It can also interact with a DDR memory to store the second data for the FPGA to read. The main DSP can also forward instructions to the slave DSP for data processing. The third data processing includes scaling and quantizing the extracted image. The slave DSP performs these processes to obtain the third data to be displayed. For example, the extracted image is 1024*1280, and the scaled size is 640*512. It should be noted that the instructions issued by the main DSP can be to scale the image to a desired size or specify how to display the image.

[0063] In another embodiment, the main DSP performs character information overlay processing as follows: The DDR memory enters a character information reading channel, reads the character information mask, and the mask format is defined by the character type and its position in the character matrix. The corresponding character library data is read from the DDR according to the character type, and then stored in the character matrix of the RAM according to the character matrix position. This achieves character replacement in the image data stream. Scaling the extracted image data involves proportionally changing the image size, and quantizing the extracted image data refers to standardizing pixel values, etc.

[0064] In step S500, the main DSP sends the second data to be displayed to the FPGA through the first multiplexer, and the slave DSP sends the third data to be displayed to the FPGA through the second multiplexer. The FPGA then transmits the first data to be displayed, the second data to be displayed, and the third data to be displayed to the storage module and the display module.

[0065] In one embodiment, a master DSP sends second data to be displayed to an FPGA via a first multiplexer, and a slave DSP sends third data to be displayed to the FPGA via a second multiplexer. This includes, but is not limited to: the master DSP sending the second data to be displayed to the first multiplexer, which parses the second data to be displayed to obtain first parsed data; the slave DSP sending the third data to be displayed to the second multiplexer, which parses the third data to be displayed to obtain second parsed data; the first multiplexer sending the first parsed data to the FPGA, and the second multiplexer sending the second parsed data to the FPGA, so that the FPGA sends the first parsed data to the corresponding address in the storage module for storage, and sends the second parsed data to the corresponding address in the storage module for storage.

[0066] In some possible embodiments of this application, after the main DSP processes the data, it can send the processed second data to be displayed to the first multiplexer. The first multiplexer parses the second data to be displayed into SRIO packets to obtain the first parsed data. Then, according to the address sent by the main DSP, the first multiplexer sends the second data to be displayed to the FPGA. The FPGA stores the first parsed data in the DDR memory according to the address sent. After the slave DSP processes the data, it can send the processed third data to be displayed to the second multiplexer. The second multiplexer parses the third data to be displayed into SRIO packets to obtain the second parsed data. Then, according to the address sent by the slave DSP, the second multiplexer sends the third data to be displayed to the FPGA. The FPGA stores the second parsed data in the DDR memory according to the address sent. It should be noted that the first and second multiplexers are SRIO multiplexers, which can parse the data into SRIO packets for convenient storage in the DDR memory.

[0067] In another embodiment, an FPGA is used to transmit the first, second, and third data to be displayed to a storage module and a display module. The storage module is a DDR memory capable of real-time storage of image data. The display module includes a VAG display module and a PAL display module. The toproject module sends the processed data to the VAG and PAL display modules respectively. The VAG display module can perform local display, and the PAL display module can display a color image, thereby realizing the acquisition, transmission, and processing of image data and achieving efficient and real-time data transmission.

[0068] It should be noted that the master DSP can also store the second data to be displayed in DDR memory, and the slave DSP can store the third data to be displayed in DDR memory. The master DSP and slave DSP can also interact; the master DSP can send processing instructions to the slave DSP, causing the slave DSP to process the data according to the instructions.

[0069] In one embodiment, the FPGA is also connected to a thermal imager RS422 communication module. The thermal imager RS422 communication module performs HDLC unpacking on the incoming instruction data packets and performs CRC verification on the data in real time. After the verification is successful, the data is put into a buffer. After buffering a data packet, it performs SRI packet assembly and sends it to the main DSP through the 422 channel of the SRI multiplexer. After receiving the SRI data packet sent by the DSP through the SRI multiplexer, the FPGA unpacks it and buffers the data content. When the data content meets the HDLC protocol of the thermal imager 422, it is retrieved for HDLC packet assembly and CRC verification, and then sent to the thermal imager through the thermal imager 422 interface. In one embodiment, the Topproject module in the FPGA also supports online upgrades. When an upgrade packet is sent to the Topproject module, the upgrade packet is first parsed. The upgrade packet contains address information and data information. The upgrade packet is stored in the corresponding DDR memory address. It is then determined whether the upgrade completion signal has arrived. The completion signal is the last data packet. When the last data packet is received, the upgrade completion signal arrives, and an erase command is sent to the flash memory. It is then determined whether the erase is complete. If the erase is complete, the upgrade data is read from the DDR memory, parsed, and then written into the flash memory, so that the FPGA can be upgraded online.

[0070] In another embodiment, if the upgrade signal has not arrived, the upgrade package continues to be stored in the DDR memory until the last data packet is received. If erasure is not complete, erasure continues to be performed to prevent the presence of older upgrade packages in the flash memory, which could affect system stability.

[0071] like Figure 5As shown, this application provides a seeker signal processing system 100 based on FPGA and DSP. This FPGA and DSP-based seeker signal processing system 100 receives image data streams acquired by the seeker through a receiving and synchronization module 110, providing a foundation for subsequent efficient and real-time data processing. Hard synchronization is performed on the FPGA, main DSP, and slave DSP to eliminate errors and improve processing accuracy and system stability. A first data processing module 120 uses the FPGA to perform first data processing on the image data stream to obtain first data to be displayed, enabling timely response to data processing needs and meeting real-time processing requirements. A first data transmission module 130 uses the FPGA to extract data from the image data stream and its corresponding data packets, obtaining extracted data. A preset first multiplexer sends the extracted image and instructions from the extracted data to the main DSP, and a preset second multiplexer sends the extracted image from the extracted data to the slave DSP. When the data packets meet a preset number of packets, doorbell packets are sent to both the main DSP and the slave DSP. The doorbell module indicates the completion of a data transmission frame, enabling efficient data transmission. Data is distributed via a multiplexer to the main DSP and slave DSP, achieving parallel data processing, improving computing power, and realizing efficient data processing. The second data processing module 140 uses the main DSP to perform second data processing on the extracted data to obtain the second data to be displayed, and the slave DSP performs third data processing on the extracted data to obtain the third data to be displayed. The second data processing includes loading the extracted image, overlaying character information from the extracted image, and forwarding instructions. The third data processing includes scaling the extracted image and quantizing the extracted image data. Image processing at different levels meets the requirements for improved computing power and real-time processing. The second data transmission module 150 uses the main DSP to send the second data to be displayed to the FPGA via the first multiplexer, and the slave DSP uses the second multiplexer to send the third data to be displayed to the FPGA. The FPGA then transmits the first, second, and third data to be displayed to the storage module and the display module. This achieves efficient and real-time data transmission and image data processing.

[0072] It should be noted that the receiving and synchronization module 110 is connected to the first data processing module 120, the first data processing module 120 is connected to the first data transmission module 130, the first data transmission module 130 is connected to the second data processing module 140, and the second data processing module 140 is connected to the second data transmission module 150. The aforementioned FPGA and DSP-based seeker signal processing method is applied to an FPGA and DSP-based seeker signal processing system 100. This system receives image data streams acquired by the seeker, providing a foundation for subsequent efficient and real-time data processing. Hard synchronization of the FPGA, main DSP, and slave DSP eliminates errors and improves processing accuracy and system stability. The FPGA performs first data processing on the image data stream to obtain first data to be displayed, enabling timely response to data processing requirements and meeting real-time processing needs. The FPGA extracts data from the image data stream and its corresponding data packets, obtaining extracted data. A preset first multiplexer sends the extracted image and instructions from the extracted data to the main DSP, and a preset second multiplexer sends the extracted image from the extracted data to the slave DSP. When the number of data packets meets a preset limit, doorbell packets are sent to both the main DSP and the slave DSP. The doorbell module indicates the completion of a data transmission frame, enabling efficient data transmission. Data is distributed via a multiplexer to the main DSP and slave DSP, achieving parallel data processing, improving computing power, and realizing efficient data processing. The main DSP performs a second data processing step on the extracted data to obtain the second data to be displayed, and the slave DSP performs a third data processing step on the extracted data to obtain the third data to be displayed. The second data processing includes loading the extracted image, overlaying character information from the extracted image, and forwarding instructions. The third data processing includes scaling the extracted image and quantizing the extracted image data. Image processing at different levels meets the requirements for improved computing power and real-time processing. The main DSP sends the second data to be displayed to the FPGA via a first multiplexer, and the slave DSP sends the third data to the FPGA via a second multiplexer. The FPGA then transmits the first, second, and third data to the storage and display modules. This achieves efficient and real-time data transmission and image processing. By hard synchronizing the FPGA and dual DSPs and using the FPGA and dual DSPs for image data stream processing and transmission, efficient and real-time data transmission can be achieved through parallel computing.

[0073] It should also be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0074] This application also discloses an electronic device. (See reference...) Figure 6 , Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. The electronic device 500 may include: at least one processor 501, at least one network interface 504, a user interface 503, a memory 505, and at least one communication bus 502.

[0075] The communication bus 502 is used to enable communication between these components.

[0076] The user interface 503 may include a display screen and a camera. Optionally, the user interface 503 may also include a standard wired interface and a wireless interface.

[0077] The network interface 504 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0078] The processor 501 may include one or more processing cores. The processor 501 connects to various parts of the server using various interfaces and lines, and performs various server functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in memory 505, and by calling data stored in memory 505. Optionally, the processor 501 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 501 may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display; and the modem handles wireless communication. It is understood that the modem may also not be integrated into the processor 501 and may be implemented as a separate chip.

[0079] The memory 505 may include random access memory (RAM) or read-only memory. Optionally, the memory 505 may include a non-transitory computer-readable storage medium. The memory 505 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 505 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 505 may also be at least one storage device located remotely from the aforementioned processor 501. (Refer to...) Figure 6 The memory 505, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and an application program for a seeker signal processing method based on FPGA and DSP.

[0080] exist Figure 6In the illustrated electronic device 500, the user interface 503 is mainly used to provide an input interface for the user and acquire user input data; while the processor 501 can be used to call an application program stored in the memory 505 for a seeker signal processing method based on FPGA and DSP. When executed by one or more processors 501, the electronic device 500 performs one or more methods as described in the above embodiments. It should be noted that, for the foregoing method embodiments, for the sake of simplicity, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0081] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0082] In the various embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some service interface; the indirect coupling or communication connection between apparatuses or units may be electrical or other forms.

[0083] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0084] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0085] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0086] The above are merely exemplary embodiments of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Other embodiments of this disclosure will readily conceive of those skilled in the art upon consideration of the specification and the disclosure of practical truths.

[0087] This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described in this disclosure. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

Claims

1. A seeker signal processing method based on FPGA and DSP, characterized in that, The method includes: It receives the image data stream acquired by the seeker and performs hard synchronization on the FPGA, main DSP, and slave DSP; The image data stream is processed using the FPGA to obtain first data to be displayed. The FPGA is used to extract data from the image data stream and the corresponding data packets to obtain extracted data. The extracted image and instructions in the extracted data are sent to the main DSP through a preset first multiplexer, and the extracted image in the extracted data is sent to the slave DSP through a preset second multiplexer. When the data packets meet the preset number of packets, a doorbell packet is sent to the main DSP and the slave DSP respectively. The doorbell packet is used to indicate that a frame of data transmission is completed. The main DSP performs a second data processing on the extracted data to obtain a second data to be displayed, and the slave DSP performs a third data processing on the extracted data to obtain a third data to be displayed. The second data processing includes loading the extracted image, overlaying the character information of the extracted image, and forwarding instructions. The third data processing includes scaling the extracted image and quantizing the data of the extracted image. The main DSP sends the second data to be displayed to the FPGA through the first multiplexer, and the slave DSP sends the third data to be displayed to the FPGA through the second multiplexer. The FPGA then transmits the first data to be displayed, the second data to be displayed, and the third data to be displayed to the storage module and the display module.

2. The method according to claim 1, characterized in that, The step of using the main DSP to send the second data to be displayed to the FPGA through the first multiplexer, and using the slave DSP to send the third data to be displayed to the FPGA through the second multiplexer, includes: The main DSP sends the second data to be displayed to the first multiplexer, and the first multiplexer parses the second data to be displayed to obtain the first parsed data; The third data to be displayed is sent from the DSP to the second multiplexer, and the second multiplexer parses the third data to be displayed to obtain the second parsed data; The first multiplexer sends the first parsed data to the FPGA, and the second multiplexer sends the second parsed data to the FPGA, so that the FPGA sends the first parsed data to the corresponding address in the storage module for storage, and sends the second parsed data to the corresponding address in the storage module for storage.

3. The method according to claim 1, characterized in that, The hard synchronization of the FPGA, master DSP, and slave DSP includes: The FPGA is used to acquire the level signal corresponding to the image data stream, and the level signal is subjected to anti-jitter processing for a preset period to obtain a synchronization signal; When the synchronization signal is high, the flag signal corresponding to the high level is pulled high to obtain the first flag signal; when the synchronization signal is low, the flag signal corresponding to the low level is pulled low to obtain the second flag signal. When the second flag signal is converted to the first flag signal, signal synchronization is performed on the master DSP and the slave DSP.

4. The method according to claim 1, characterized in that, The first data processing of the image data stream using the FPGA to obtain the first data to be displayed includes: The FPGA is used to perform pixel frequency statistics on the image data stream to obtain multiple cumulative pixel statistics and the total number of pixels. Divide each of the cumulative pixel statistics by the total number of pixels to obtain the cumulative percentage corresponding to each of the cumulative pixel statistics; Find the minimum gray value from each of the accumulated pixel statistics. If the accumulated percentage corresponding to the minimum gray value is greater than a preset first percentage threshold, the minimum gray value is taken as the low threshold. Find the maximum gray value from each of the cumulative pixel statistics. If the cumulative percentage corresponding to the maximum gray value is greater than a preset second percentage threshold, the maximum gray value is taken as a high threshold. The sum of the first percentage threshold and the second percentage threshold is equal to the cumulative percentage corresponding to pixel 255. Image processing is performed based on the high threshold and the low threshold to obtain the first data to be displayed.

5. The method according to claim 4, characterized in that, The step of performing image processing based on the high threshold and the low threshold to obtain the first data to be displayed includes: Based on the high threshold and the low threshold, the image is stretched using a preset stretching algorithm to obtain stretched pixel values; the stretched pixel values ​​are then used to form the first data to be displayed. The stretching algorithm formula is as follows: Where u_gs represents the stretched pixel value, H represents the high threshold, L represents the low threshold, and gs represents the grayscale value.

6. The method according to claim 1, characterized in that, When there are two channels for receiving the image data stream, after receiving the image data stream acquired by the seeker head, the method further includes: Determine whether the image data stream has an image frame header. If an image frame header exists, add a frame header synchronization flag to the image data stream. Reassemble the image data stream according to the frame header synchronization flag to obtain two sets of reassembled image data streams. The two sets of reconstructed image data streams are respectively queued and buffered to obtain a first buffer queue and a second buffer queue; The reconstructed image data stream in the first buffer queue and the reconstructed image data stream in the second buffer queue are synchronized in the clock domain to obtain an image sequence; Determine whether the image sequence is a complete frame. If it is a complete frame, send the image sequence to the FPGA and use the image sequence as the image data stream to perform the hard synchronization step on the FPGA, master DSP and slave DSP.

7. The method according to claim 6, characterized in that, After determining whether the reconstructed image data stream is a complete frame based on the image sequence, the method further includes: In the absence of complete frames, the image sequence is padded with broken frames. The steps of determining whether the image data stream has an image frame header, adding a frame header synchronization flag to the image data stream if an image frame header exists, and reconstructing the image data stream according to the frame header synchronization flag to obtain two sets of reconstructed image data streams are performed.

8. A seeker signal processing system based on FPGA and DSP, characterized in that, The system includes: The receiving and synchronization module (110) is used to receive the image data stream acquired by the seeker and perform hard synchronization on the FPGA, the main DSP and the slave DSP. The first data processing module (120) is used to perform first data processing on the image data stream using the FPGA to obtain first data to be displayed; The first data transmission module (130) is used to extract data from the image data stream and the data packets corresponding to the image data stream using the FPGA, to obtain extracted data, and to send the extracted image and instructions in the extracted data to the main DSP through a preset first multiplexer, and to send the extracted image in the extracted data to the slave DSP through a preset second multiplexer. In the case that the data packets meet the preset number of packets, a doorbell packet is sent to the main DSP and the slave DSP respectively. The doorbell packet is used to indicate that a frame of data transmission is completed. The second data processing module (140) is used to perform second data processing on the extracted data using the main DSP to obtain second data to be displayed, and to perform third data processing on the extracted data using the slave DSP to obtain third data to be displayed. The second data processing process includes loading the extracted image, overlaying the character information of the extracted image and forwarding the instruction, and the third data processing process includes scaling the extracted image and quantizing the data of the extracted image. The second data transmission module (150) is used to send the second data to be displayed to the FPGA through the first multiplexer using the main DSP, send the third data to be displayed to the FPGA through the second multiplexer using the slave DSP, and transmit the first data to be displayed, the second data to be displayed, and the third data to be displayed to the storage module and the display module using the FPGA.

9. An electronic device, characterized in that, The device includes a processor (501), a memory (505), a user interface (503), a communication bus (502), and a network interface (504). The processor (501), the memory (505), the user interface (503), and the network interface (504) are respectively connected to the communication bus (502). The memory (505) is used to store instructions. The user interface (503) and the network interface (504) are used to communicate with other devices. The processor (501) is used to execute the instructions stored in the memory (505) so that the electronic device (500) performs the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed, perform the method as described in any one of claims 1-7.

Images