Low-power-consumption digital domain accumulation CMOS-TDI image sensor and method

Abstract

The invention provides a low-power-consumption digital domain accumulation CMOS-TDI image sensor and method, and the image sensor comprises a pixel array which is connected with a correlated double-sampling circuit, the correlated double-sampling circuit is connected with an SAR ADC, the SAR ADC is connected with a digital domain accumulator, the digital domain accumulator is connected with a divider, the divider is connected with a shift register, and the shift register is connected with a comparator. A time sequence control circuit is arranged on the periphery of the pixel array; the pixel array comprises k preprocessing pixel rows and n main imaging pixel rows; the traditional single-stage high-bit-width high-speed SAR ADC quantization is divided into two stages of operations of coarse quantization and fine quantization. The method has the beneficial effects that the imaging quality is improved, and the signal-to-noise ratio in a weak light environment is improved; the power consumption is effectively reduced, and the TDI series expansion capability is improved; and the working flexibility and the power consumption adaptability of the sensor are enhanced.

Description

Technical Field

[0001] This invention belongs to the field of image sensors, and in particular relates to a low-power digital domain accumulation CMOS-TDI image sensor and method. Background Technology

[0002] Image sensors are core components for interaction between automated equipment and the outside world, making their research and development crucial. In recent years, linear array CMOS image sensors have been widely used in aerospace, industrial inspection, rail transportation, and high-end machine vision—scenarios with high requirements for imaging dynamic targets—due to their advantages such as high integration, low cost, and process compatibility.

[0003] In high-speed, low-light conditions, traditional single-exposure CMOS linear array image sensors often suffer from low signal-to-noise ratios (SNR) due to the limited integration time per pixel, making it difficult to acquire high-quality images. Therefore, imaging techniques based on time-delay integration have been proposed. These techniques involve multiple exposures of the same moving target across multiple rows of pixels, accumulating the signal of the same object row by row. This significantly increases the effective integration time, theoretically improving the SNR by up to [percentage missing]. The multiple, where N is the number of rows accumulated in TDI.

[0004] Traditional TDI (Transmission-Dependent Identification) is mostly implemented using charge-coupled devices (CCDs) because CCDs can efficiently achieve lossless charge transfer and accumulation. However, CCD processes are complex, consume high power, and are difficult to integrate with CMOS, and have been gradually replaced by CMOS-TDI structures in recent years. However, the core technological bottleneck of existing CMOS-TDI lies in:

[0005] 1. High power consumption: Most CMOS-TDI uses analog domain accumulation, and the analog signal output by the pixel needs to be accumulated multiple times, which makes the circuit noise easy to accumulate and consumes a lot of power.

[0006] 2. High speed requirement for analog-to-digital converter (ADC): Although digital domain accumulation can reduce analog noise, each exposure signal must first be quantized by a successive approximation register (SAR ADC). If an n-order TDI is used, the data from n exposures must be converted at high speed, which means that the ADC needs to have a high sampling rate and a high bit width.

[0007] 3. Complex large-scale row and column control: When the number of accumulated rows increases, traditional structures need to configure a separate ADC or multiplexed ADC for each row of pixels, which poses challenges to clock tree design, power management and noise isolation. Summary of the Invention

[0008] In view of this, the present invention aims to propose a low-power digital domain accumulation CMOS-TDI image sensor and method to solve the problems of high power consumption, high analog-to-digital converter rate requirements and complex large-scale row and column control in the prior art.

[0009] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0010] In a first aspect, the present invention provides a low-power digital domain accumulation CMOS-TDI image sensor, comprising a pixel array, wherein the pixel array is connected to a correlated dual sampling circuit, the correlated dual sampling circuit is connected to a SAR ADC, the SAR ADC is connected to a digital domain accumulator, the digital domain accumulator is connected to a divider, the divider is connected to a shift register, and a timing control circuit is arranged around the pixel array.

[0011] The pixel array consists of n+k rows, with the first k rows serving as preprocessing pixel rows and the last n rows serving as main imaging pixel rows.

[0012] Furthermore, the pixels of the pixel array are aligned column-wise.

[0013] Furthermore, a preset scanning interval is provided between each row of pixels in the pixel array.

[0014] Secondly, based on the same concept, the present invention also provides a low-power digital domain accumulation CMOS-TDI image sensing method, comprising the following steps:

[0015] S1, coarse quantification stage;

[0016] S2, Quantification Stage;

[0017] S3, Normalized output;

[0018] In step S1, the coarse quantization stage includes:

[0019] S11. Perform k rapid exposures on the same scene point using pre-processed pixel rows;

[0020] S12. The output signal is sequentially passed through the SAR ADC for coarse approximation to obtain k sets of coarse quantization results;

[0021] S13. Use a digital field accumulator to calculate the average value;

[0022] In step S2, the fine-tuning stage includes:

[0023] S21. Use the main imaging pixel row to perform n normal exposures on the same scene point;

[0024] S22. Based on the coarse quantization result of step S13, use the SAR ADC to perform a fine approximation of the residual quantity of the input signal.

[0025] S23. Use a digital field accumulator to perform total integration on the nth fine quantization result.

[0026] Furthermore, in step S13, the average value is calculated using a digital field accumulator, including:

[0027] The expression is as follows:

[0028]

[0029] In the formula, Q coarse This is the result of coarse quantization.

[0030] Furthermore, in step S22, a fine approximation of the residual amount of the input signal is performed, including:

[0031] The expression is as follows:

[0032] Q fine =Q coarse +Q residual ;

[0033] In the formula, Q fine To refine the results, Q coarse For coarse quantization results, Q residual This is the result for the remaining amount.

[0034] Furthermore, in step S23, the total integral of the n refinement results is accumulated, including:

[0035] The expression is as follows:

[0036]

[0037] In the formula, Q total For the total points accumulated, Q fine To refine the results.

[0038] Furthermore, in step S3, the normalized output includes:

[0039] The cumulative result of step S23 is divided by a preset phase coefficient using a divider, and then output in column order using a shift register.

[0040] Compared with existing technologies, the low-power digital domain accumulation CMOS-TDI image sensor and method described in this invention have the following advantages:

[0041] (1) Significantly improves imaging quality and enhances signal-to-noise ratio in low-light environments. By introducing multiple rows of pre-processed pixels into the CMOS-TDI pixel array, multiple coarse quantization exposures are first performed on the same target, and the coarse quantization results are accumulated and averaged in the digital domain before being superimposed with the multiple fine quantization results of the main pixel array. This effectively reduces the impact of single exposure noise and significantly improves imaging clarity under high-speed motion and low-light conditions.

[0042] (2) Effectively reduce power consumption and improve TDI level expansion capability. The traditional single-stage high-bit-width high-speed SAR ADC quantization is innovatively decomposed into a two-stage operation of "coarse quantization + fine quantization". The coarse quantization stage distributes the overall quantization burden through multi-row parallel exposure, and the fine quantization stage only needs to compensate for the remaining amount based on the coarse quantization result. Therefore, the number of ADC approximation times can be halved, reducing the conversion rate requirement and power consumption of the column-parallel ADC. At the same time, it reduces the complexity caused by clock tree design and channel mismatch, making the expansion of TDI level more feasible.

[0043] (3) Enhance the sensor’s operational flexibility and power consumption adaptability. The provided staged quantization architecture and digital domain accumulation scheme can adaptively adjust the number of coarse quantization rows k and the fine quantization order n according to the target’s moving speed, light intensity and required resolution in the imaging scene. Without changing the hardware structure, it can flexibly balance the accumulation times and power consumption level, enhancing the availability and environmental adaptability of the CMOS-TDI sensor in multiple scenarios. Attached Figure Description

[0044] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0045] Figure 1 This is a schematic diagram illustrating the working principle of the TDI image sensor described in an embodiment of the present invention;

[0046] Figure 2 This is a schematic diagram of a typical CMOS-TDI principle structure as described in an embodiment of the present invention;

[0047] Figure 3 This is a schematic diagram of the phased quantization described in an embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram of the digital domain accumulation CMOS-TDI image sensor architecture according to an embodiment of the present invention;

[0049] Figure 5 This is a schematic diagram of the SAR ADC workflow according to an embodiment of the present invention. Detailed Implementation

[0050] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0051] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0052] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0053] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0054] like Figures 1 to 5 As shown, a low-power digital domain accumulation CMOS-TDI image sensor is implemented as follows:

[0055] In a preferred embodiment of the present invention, the pixel array is connected to a correlated double sampling circuit, the correlated double sampling circuit is connected to a SAR ADC, the SAR ADC is connected to a digital domain accumulator, the digital domain accumulator is connected to a divider, the divider is connected to a shift register, and a timing control circuit is arranged around the pixel array. In this embodiment, each pixel unit is connected to a column-parallel SAR ADC, and the back end of the SAR ADC is connected to a digital domain accumulator and a divider, forming a staged "coarse quantization + fine quantization" quantization structure. Timing control circuits are arranged around the pixel array. The analog signal output by the pixel is first preprocessed by the correlated double sampling circuit, and then sequentially sent to the SAR ADC for two-stage quantization. To achieve effective accumulation of high-order TDI, the exposure time of each row of pixels in the pixel array is staggered sequentially, and the row-by-row exposure order is controlled by a row shift register to ensure that multiple exposure signals of the same object in different rows of pixels can be correctly aligned and accumulated in time.

[0056] In a preferred embodiment of the present invention, the pixel array consists of n+k rows, with the first k rows serving as preprocessing pixel rows and the last n rows serving as main imaging pixel rows. In this embodiment, the pixel array output signal first enters the coarse quantization stage, where the same scene point is subjected to k rapid exposures using the newly added k preprocessing pixel rows. The output signal is then coarsely approximated sequentially by the SAR ADC to obtain k sets of coarse quantization results. The main imaging pixel rows output the n normal exposure signals of the same scene point, entering the fine quantization stage. The SAR ADC uses the coarse quantization results as a reference to finely approximate the remaining amount of the input signal.

[0057] In a preferred embodiment of the present invention, the pixels of the pixel array are aligned column-wise. In this embodiment, column-wise pixel alignment ensures that the object continuously passes through the same pixel column during movement, thereby enabling multiple exposures and signal accumulation for the same scene point.

[0058] A low-power digital domain accumulation CMOS-TDI image sensing method includes the following steps:

[0059] S1, coarse quantification stage;

[0060] S2, Quantification Stage;

[0061] S3, Normalized Output.

[0062] like Figure 1 As shown, the working principle of a CMOS-TDI image sensor is as follows: Figure 2 As shown, a typical CMOS-TDI image sensor structure requires the pixel array output to undergo multiple stages of analog preprocessing, a column-parallel ADC, and a digital accumulation module. The signal processing flow can be simplified as follows:

[0063]

[0064] To ensure high TDI order and high line frequency, traditional solutions often require increasing the ADC conversion rate, as shown in the following expression:

[0065] f ADC =n×f line ;

[0066] In the formula, f ADC Where n is the required conversion rate of the ADC, n is the cumulative number of rows, and fline is the operating frequency of the linear array.

[0067] At higher orders (larger n), the ADC power consumption will be directly increased, as shown in the following expression:

[0068] P ADC ∝f ADC ×2 b ;

[0069] In the formula, b represents the ADC bit width. Therefore, how to reduce the ADC speed and power consumption while ensuring accumulation accuracy is a prominent technical challenge faced by CMOS-TDI.

[0070] like Figure 3 As shown, the present invention employs a phased quantization process of "coarse quantization + fine quantization." The pixel array output signal first enters the coarse quantization stage, where the same scene point is subjected to k rapid exposures using k newly added preprocessed pixels. The output signal is then coarsely approximated sequentially by a SAR ADC to obtain k sets of coarse quantization results, which are then averaged in a digital accumulator. The expression is as follows:

[0071]

[0072] Subsequently, the pixel array outputs n normal exposure signals for the same scene point, entering the fine quantization stage. The SAR ADC uses the coarse quantization result as a benchmark to perform a fine approximation of the remaining quantity of the input signal, as shown in the following expression:

[0073] Q fine =Q coarse +Q residual ;

[0074] The digital domain accumulator performs a total integral accumulation after receiving n refinement results, as shown in the following expression:

[0075]

[0076] To reduce the power consumption and area overhead of the division operation in the accumulation process, a column-parallel divider is set up at the back end of the accumulator to divide the accumulation result by a preset stage coefficient, thereby realizing the normalization output of the TDI signal. Finally, the output is output in column order through a shift register.

[0077] The entire structure, under the same frame period, reduces the SAR ADC conversion rate to half that of the original scheme by splitting the traditional single-stage X-bit successive approximation operation into coarse quantization X / 2 bits + fine quantization X / 2 bits, effectively reducing power consumption. The expression is as follows:

[0078]

[0079] Example 1:

[0080] like Figure 4 As shown, the pixel array comprises a one-dimensional multi-row pixel array arranged along the direction of object movement. The pixel array contains multiple rows of preprocessing pixels for coarse quantization and multiple rows of main pixels for fine quantization. All pixels are aligned by column to ensure that the object passes through the same column of pixels in sequence during movement, realizing the time delay integration function. There is a preset scanning interval between each row of pixels in the pixel array. The row-by-row exposure is controlled by the row shift register and the timing control circuit to achieve row time difference compensation that matches the object's movement speed, ensuring that the exposure of different rows of pixels for the same scene point is aligned. The output of each row of pixels first passes through the column-parallel correlation double sampling circuit, and then enters the SAR ADC for coarse or fine quantization processing. The coarse quantization output is stored in the column-parallel digital accumulator for multi-row averaging, which serves as the reference baseline for fine quantization. The fine quantization result and the coarse quantization result are merged and normalized by the divider. Finally, the final TDI accumulation result is output through the shift register.

[0081] Example 2:

[0082] like Figure 5 As shown, the SAR ADC first performs an X / 2-bit approximation on the input signal in the coarse quantization stage. The average value of the coarse quantization result is fed back by the digital to analog converter (DAC) as the starting point for fine quantization. In the fine quantization stage, the remaining X / 2-bit approximation is completed, thereby reducing the conversion rate and power consumption of the SAR ADC, while ensuring the high line frequency and low noise performance required for high-order TDI.

[0083] The advantages and beneficial effects of this invention are as follows:

[0084] (1) Significantly improves imaging quality and enhances signal-to-noise ratio in low-light environments. By introducing multiple rows of pre-processed pixels into the CMOS-TDI pixel array, multiple coarse quantization exposures are first performed on the same target, and the coarse quantization results are accumulated and averaged in the digital domain before being superimposed with the multiple fine quantization results of the main pixel array. This effectively reduces the impact of single exposure noise and significantly improves imaging clarity under high-speed motion and low-light conditions.

[0085] (2) Effectively reduce power consumption and improve TDI level expansion capability. The traditional single-stage high-bit-width high-speed SAR ADC quantization is innovatively decomposed into a two-stage operation of "coarse quantization + fine quantization". The coarse quantization stage distributes the overall quantization burden through multi-row parallel exposure, and the fine quantization stage only needs to compensate for the remaining amount based on the coarse quantization result. Therefore, the number of ADC approximation times can be halved, reducing the conversion rate requirement and power consumption of the column-parallel ADC. At the same time, it reduces the complexity caused by clock tree design and channel mismatch, making the expansion of TDI level more feasible.

[0086] (3) Enhance the sensor’s operational flexibility and power consumption adaptability. The provided staged quantization architecture and digital domain accumulation scheme can adaptively adjust the number of coarse quantization rows k and the fine quantization order n according to the target’s moving speed, light intensity and required resolution in the imaging scene. Without changing the hardware structure, it can flexibly balance the accumulation times and power consumption level, enhancing the availability and environmental adaptability of the CMOS-TDI sensor in multiple scenarios.

[0087] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-power digital domain accumulation CMOS-TDI image sensor, characterized in that: The system includes a pixel array, which is connected to a correlated double sampling circuit, which is connected to a SAR ADC, which is connected to a digital domain accumulator, which is connected to a divider, which is connected to a shift register, and a timing control circuit is arranged around the pixel array. The pixel array consists of n+k rows, with the first k rows serving as preprocessing pixel rows and the last n rows serving as main imaging pixel rows.

2. The low-power digital domain accumulation CMOS-TDI image sensor according to claim 1, characterized in that: The pixels of the pixel array are aligned column-wise.

3. The low-power digital domain accumulation CMOS-TDI image sensor according to claim 1, characterized in that: The pixel array has a preset scanning interval between each row of pixels.

4. A low-power digital domain accumulation CMOS-TDI image sensing method, applied to a low-power digital domain accumulation CMOS-TDI image sensor as described in any one of claims 1-3, characterized in that: Includes the following steps: S1, coarse quantification stage; S2, Quantification Stage; S3, Normalized output; In step S1, the coarse quantization stage includes: S11. Perform k rapid exposures on the same scene point using pre-processed pixel rows; S12. The output signal is sequentially passed through the SAR ADC for coarse approximation to obtain k sets of coarse quantization results; S13. Use a digital field accumulator to calculate the average value; In step S2, the fine-tuning stage includes: S21. Use the main imaging pixel row to perform n normal exposures on the same scene point; S22. Based on the coarse quantization result of step S13, use the SAR ADC to perform a fine approximation of the residual quantity of the input signal. S23. Use a digital field accumulator to perform total integration on the nth fine quantization result.

5. The low-power digital domain accumulation CMOS-TDI image sensing method according to claim 4, characterized in that: In step S13, the average value is calculated using a digital field accumulator, including: The expression is as follows: In the formula, Q coarse This is the result of coarse quantization.

6. The low-power digital domain accumulation CMOS-TDI image sensing method according to claim 4, characterized in that: In step S22, a fine approximation of the residual quantity of the input signal is performed, including: The expression is as follows: Q fine =Q coarse +Q residual ; In the formula, Q fine To refine the results, Q coarse For coarse quantization results, Q residual This is the result for the remaining amount.

7. The low-power digital domain accumulation CMOS-TDI image sensing method according to claim 4, characterized in that: In step S23, the total integral of the n refinement results is accumulated, including: The expression is as follows: In the formula, Q total For the total points accumulated, Q fine To refine the results.

8. The low-power digital domain accumulation CMOS-TDI image sensing method according to claim 4, characterized in that: In step S3, the output is normalized, including: The cumulative result of step S23 is divided by a preset phase coefficient using a divider, and then output in column order using a shift register.

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