Display device

Abstract

The embodiment of the invention provides a display device, which comprises a substrate, a first electrode and a second electrode, comprising main islands arranged in a first direction and a second direction, a first connection portion connecting the main islands arranged in the first direction, a second connection portion connecting the main islands arranged in the second direction, a first sub-island disposed in a middle region of the first connection portion, and a second sub-island disposed in a middle region of the second connection portion. A second sub-island disposed in an intermediate region of the second connecting portion and a plurality of penetrating portions disposed between the main islands; a first pixel circuit, a second pixel circuit, and a third pixel circuit disposed on each of the main islands; a first light emitting element disposed on the first sub-island and connected to the first pixel circuit; a first connection line disposed on the first connection portion and connecting the first pixel circuit and the first light emitting element; and a first conductive line disposed on the first connection portion.

Description

Technical Field

[0001] One or more embodiments relate to display devices, and more specifically, to stretchable display devices. Background Technology

[0002] With the development of display devices that visually display electrical signals, various display devices with excellent characteristics such as thinness, light weight, and low power consumption have been proposed. For example, flexible display devices that can be folded or rolled up have been proposed. Research and development of stretchable display devices that can be changed into various shapes are being actively carried out. Summary of the Invention

[0003] Technical issues

[0004] One or more embodiments provide a structure for a display device, such as a structure for a stretchable display device.

[0005] Solution to the problem

[0006] According to one or more embodiments, a display device includes: a substrate including main islands arranged in a first direction and a second direction; a first connection unit configured to connect the main islands arranged in the first direction to each other; a second connection unit configured to connect the main islands arranged in the second direction to each other; a first sub-island located in an intermediate portion of the first connection unit; a second sub-island located in an intermediate portion of the second connection unit; and a plurality of through portions defined between the main islands; a first pixel circuit, a second pixel circuit, and a third pixel circuit located on each of the main islands; a first light-emitting element located on the first sub-island and connected to the first pixel circuit; a first connection wiring located on the first connection unit and configured to connect the first pixel circuit to the first light-emitting element; and a first wiring located on the first connection unit.

[0007] Beneficial effects of the present invention

[0008] As described above, according to the embodiment, because the light-emitting element is located on the sub-island and connected to the pixel circuit located on the main island, visibility can be ensured even when the display device is stretched or contracted, and the aperture ratio of the emission area can be ensured. Attached Figure Description

[0009] Figure 1 This is a schematic perspective view illustrating a stretchable display device according to an embodiment.

[0010] Figure 2a It is shown in the diagram. Figure 1 A perspective view of the display device in a first state, stretched in a first direction.

[0011] Figure 2b It is shown in the diagram. Figure 1 A perspective view of the display device in a second state, stretched in a second direction.

[0012] Figure 3a and Figure 3b This is a schematic illustration of an equivalent circuit diagram of a light-emitting element and a pixel circuit electrically connected to the light-emitting element in a display device according to an embodiment.

[0013] Figure 4 This is a schematic plan view illustrating the shape of a substrate suitable for a display device according to an embodiment.

[0014] Figure 5a This is a schematic view illustrating the shape of a connection unit on a substrate suitable for a display device according to an embodiment.

[0015] Figure 5b This is a schematic view illustrating the shape of the connection unit and sub-island of a substrate suitable for a display device according to an embodiment.

[0016] Figure 6 This is a schematic plan view illustrating the pixel arrangement or light-emitting diode arrangement structure of a display device according to an embodiment.

[0017] Figure 7 This is a schematic plan view illustrating the arrangement of pixel circuits and wiring of a display device according to an embodiment.

[0018] Figure 8 This is a plan view illustrating the connection relationship between the pixel circuit and the light-emitting element of a display device according to an embodiment.

[0019] Figure 9 This is a plan view illustrating a portion of a display device according to an embodiment.

[0020] Figure 10 It is a schematic diagram. Figure 9 The first power voltage line and the first connection wiring in the components are located on the plan layout of the layer.

[0021] Figure 11 It is a schematic diagram. Figure 9 The second power voltage line in the component is located on the planar layout of the layer above it.

[0022] Figure 12 It is along Figure 9 A schematic cross-sectional view taken from line I-I'.

[0023] Figure 13 It is along Figure 9 A schematic cross-sectional view taken from line II-II'.

[0024] Figure 14This is a schematic cross-sectional view of a display device according to another embodiment.

[0025] Figure 15 This is a plan view illustrating the connection relationship between the pixel circuitry and the light-emitting element of a display device that can be modified according to another embodiment.

[0026] Figure 16 This is a plan view illustrating the connection relationship between the pixel circuit and the light-emitting element of a modified display device according to yet another embodiment.

[0027] Figure 17 This is a schematic cross-sectional view illustrating an example of a modification to the connection wiring according to an embodiment.

[0028] Figure 18 This is a schematic cross-sectional view illustrating an example of a modification to the connection wiring according to an embodiment.

[0029] Figure 19 This is a schematic cross-sectional view illustrating an example of a modification to the connection wiring according to an embodiment.

[0030] Figure 20 This is a plan view illustrating a portion of a display device according to an embodiment.

[0031] Figure 21 This is a plan view illustrating a portion of a display device according to an embodiment.

[0032] Figure 22 This is a schematic cross-sectional view of a display device according to an embodiment. Detailed Implementation

[0033] According to one or more embodiments, a display device includes: a substrate including main islands arranged in a first direction and a second direction; a first connection unit configured to connect the main islands arranged in the first direction to each other; a second connection unit configured to connect the main islands arranged in the second direction to each other; a first sub-island located in an intermediate portion of the first connection unit; a second sub-island located in an intermediate portion of the second connection unit; and a plurality of through portions defined between the main islands; a first pixel circuit, a second pixel circuit, and a third pixel circuit located on each of the main islands; a first light-emitting element located on the first sub-island and connected to the first pixel circuit; a first connection wiring located on the first connection unit and configured to connect the first pixel circuit to the first light-emitting element; and a first wiring located on the first connection unit.

[0034] The display device may further include: a second light-emitting element located on a second sub-island and connected to a second pixel circuit; and a third light-emitting element located on each of the main islands and connected to a third pixel circuit, wherein the first light-emitting element, the second light-emitting element, and the third light-emitting element emit light of different colors from each other.

[0035] In a planar diagram, the size of the third sub-pixel implemented by the third light-emitting element can be larger than the size of the first sub-pixel implemented by the first light-emitting element.

[0036] In a planar view, the third light-emitting element may at least partially overlap with the first pixel circuit.

[0037] The first connecting unit may include: a first part protruding upward in a third direction in a plan view and a second part protruding in a fourth direction opposite to the third direction, wherein the first sub-island may be located between the first part and the second part.

[0038] The display device may further include: a second wiring located on the second connection unit, wherein the first wiring and the second wiring may be located on the same layer.

[0039] At least one of the first wirings may be a scan line through which a scan signal is transmitted, and at least one of the second wirings may be a data line through which a data signal is transmitted.

[0040] The display device may further include: a first power voltage line located on each of the main island, the first connection unit, and the second connection unit, wherein the first connection wiring and the first power voltage line are located on the same layer.

[0041] The display device may further include: a second light-emitting element located on a second sub-island and connected to a second pixel circuit; a second wiring configured to provide data signals to a first pixel circuit, a second pixel circuit, and a third pixel circuit; and a second connection wiring located on a second connection unit and configured to connect the second pixel circuit to the second light-emitting element, wherein the second connection wiring and the second wiring may be located on the same layer.

[0042] The display device may further include: a second power voltage line located on each of the main island, the first connection unit, and the second connection unit, wherein the contact area where the second power voltage line and the second electrode of the first light-emitting element are connected to each other may be located on the first connection unit.

[0043] The first light-emitting element can be an organic light-emitting element.

[0044] The first light-emitting element can be a miniature light-emitting element.

[0045] The display device may further include: a first sub-light-emitting element connected to the first pixel circuit and configured to emit light of the same color as the first light-emitting element, wherein the first sub-light-emitting element may be located on each of the main islands.

[0046] The first connection wiring may include 1-1 connection wiring and 1-2 connection wiring located on different layers in the first connection unit.

[0047] The display device may further include: a second power voltage line located on each of the main island, the first connection unit, and the second connection unit, wherein the first connection wiring and the second power voltage line may be located on the same layer.

[0048] The first connecting wiring and the first electrode of the first light-emitting element can be located on the same layer.

[0049] Multiple third light-emitting elements configured to emit light of the same color can be provided on each of the main islands.

[0050] The first light-emitting element can be provided in multiple forms, and the multiple first light-emitting elements can be configured to emit light of the same color.

[0051] The display device may further include: an optical functional layer located on the first light-emitting element, wherein the optical functional layer may include a color conversion layer overlapping the first light-emitting element in a plan view and a light-shielding unit overlapping the first connection unit.

[0052] Color conversion layers can include quantum dots.

[0053] According to one or more embodiments, a display device includes: a substrate including a main island, a sub-island spaced apart from the main island, a connection unit configured to connect the main island to the sub-island, and a plurality of through portions defined between the main island and the sub-island; a first pixel circuit and a second pixel circuit located on the main island; a first light-emitting element located on the main island and at least partially overlapping the first pixel circuit and the second pixel circuit in a plan view; and a second light-emitting element located on the sub-island and connected to the second pixel circuit.

[0054] The color of the first sub-pixel implemented by the first light-emitting element and the color of the second sub-pixel implemented by the second light-emitting element can be different from each other, and in the planar diagram, the size of the first sub-pixel can be larger than the size of the second sub-pixel.

[0055] The connecting unit may include a curved portion.

[0056] The display device may further include: a second light-emitting element located on the main island and connected to the second pixel circuit.

[0057] In a plan view, the area of ​​a secondary island can be smaller than that of the main island.

[0058] The method of the present invention

[0059] Because this disclosure allows for various modifications and numerous embodiments, certain embodiments will be illustrated in the accompanying drawings and described in the detailed description. The effects and features of this disclosure, as well as methods of implementing them, will be elucidated with reference to the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below and can be embodied in various forms.

[0060] In the following description, embodiments will be described in detail with reference to the accompanying drawings, wherein the same or corresponding elements are indicated by the same reference numerals throughout, and repeated descriptions of the same or corresponding elements are omitted.

[0061] Although terms such as "first," "second," etc., can be used to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

[0062] As used herein, the singular forms “a” and “the (said)” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0063] It will be understood that the terms “comprising” and “having” are intended to indicate the presence of a feature or element described in the specification, and not to exclude the possibility that one or more other features or elements may be present or may be added.

[0064] It will be further understood that when a layer, area, or component is referred to as being "on" another layer, area, or component, that layer, area, or component may be directly on that other layer, area, or component, or may be indirectly on that other layer, area, or component, with an intermediary layer, area, or component between that layer, area, or component and that other layer, area, or component.

[0065] For ease of explanation, the dimensions of the components in the accompanying drawings may be exaggerated or reduced. For example, this disclosure is not limited thereto because the dimensions and thicknesses of the elements in the drawings are arbitrarily illustrated for ease of explanation.

[0066] When an embodiment can be implemented differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0067] In this document, "A and / or B" is used to select only A, only B, or both A and B. "At least one of A or B" is used to select only A, only B, or both A and B.

[0068] It will be understood that when a layer, area, or component is referred to as being "connected" to another layer, area, or component, that layer, area, or component may be "directly connected" to that other layer, area, or component, and / or may be "indirectly connected" to that other layer, area, or component, with other layers, areas, or components between that layer, area, or component and the other layer, area, or component. For example, when a layer, area, or component is referred to as being "electrically connected," these layers, areas, or components may be directly electrically connected, or may be indirectly electrically connected with intermediate layers, areas, or components between them.

[0069] The x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0070] Figure 1 This is a schematic perspective view of the display device 1 according to an embodiment. Figure 2a It is shown in the diagram. Figure 1 A perspective view of the first state in which the display device 1 is stretched in a first direction. Figure 2b It is shown in the diagram. Figure 1 A perspective view of the second state in which the display device 1 is stretched in the second direction.

[0071] refer to Figure 1 The display device 1 may include a display area DA and a peripheral area PA. The display area DA may include a plurality of sub-pixels. The display device 1 can provide a specific image by using light emitted from the plurality of sub-pixels. The peripheral area PA may be adjacent to the display area DA. In an embodiment, the peripheral area PA may surround the entire display area DA.

[0072] The display device 1 may include a first side L1 extending in a first direction and a second side L2 extending in a second direction. The first side L1 and the second side L2 may be edges of the display device 1. The first direction and the second direction may intersect each other. For example, an acute angle may be formed between the first direction and the second direction. Alternatively, an obtuse angle or a right angle may be formed between the first direction and the second direction. The following description will assume that the "first direction" is the x-direction or -x-direction and the "second direction" is the y-direction or -y-direction.

[0073] like Figure 2a As shown, when a pulling force is applied to the display device 1 in a first direction (e.g., the x-direction or the -x-direction), the display device 1, being a stretchable display device, can be stretched in the first direction (e.g., the x-direction or the -x-direction). In this case, Figure 2a The first side L1-1 can be greater than Figure 1The first side L1. Each of the display area DA and the peripheral area PA can be stretched in a first direction (e.g., the x-direction or the -x-direction). In another embodiment, when a contraction force is applied to the display device 1 in the first direction (e.g., the x-direction or the -x-direction), the display device 1 can be contracted in the first direction (e.g., the x-direction or the -x-direction). In this case, Figure 2a The first side L1-1 can be less than Figure 1 The first side L1. Each of the display region DA and the outer region PA can be shrunk in a first direction (e.g., the x-direction or the -x-direction).

[0074] refer to Figure 2b When a pulling force is applied to the display device 1 in a second direction (e.g., the y-direction or the -y-direction), the display device 1 can be stretched in the second direction (e.g., the y-direction or the -y-direction). In this case, Figure 2b The second side L2-1 can be greater than Figure 1 The second side L2. Each of the display area DA and the peripheral area PA can be stretched in a second direction (e.g., the y-direction or the -y-direction). In another embodiment, when a contraction force is applied to the display device 1 in the second direction (e.g., the y-direction or the -y-direction), the display device 1 can be contracted in the second direction (e.g., the y-direction or the -y-direction). In this case, Figure 2b The second side L2-1 can be less than Figure 1 The second side L2. Each of the display area DA and the peripheral area PA can be contracted in a second direction (e.g., the y-direction or the -y-direction). Therefore, when a tensile or contractile force is applied to the display device 1, the display device 1 can be changed into various shapes.

[0075] Despite Figure 2a and Figure 2b The display device is stretched or contracted in the xy plane, but this disclosure is not limited thereto. In another embodiment, the display device according to the embodiment can even be stretched or contracted in the z direction, and the display device can be changed into various shapes in three-dimensional (“3D”) space.

[0076] Figure 3a and Figure 3b This is a schematic illustration of an equivalent circuit diagram of a light-emitting element ED and a pixel circuit PC electrically connected to the light-emitting element ED in a display device 1 according to an embodiment.

[0077] refer to Figure 3aThe pixel circuit PC can be connected to the light-emitting element ED, causing the sub-pixels to emit light. The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 is connected to the scan line SL and the data line DL, and transmits the data signal Dm input through the data line DL to the driving thin-film transistor T1 according to the scan signal Sn input through the scan line SL.

[0078] A storage capacitor Cst is connected to the switching thin-film transistor T2 and the first power voltage line PL1, and stores a voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the drive voltage ELVDD supplied to the first power voltage line PL1. The first power voltage line PL1 may be a drive voltage line.

[0079] The driving thin-film transistor T1 can be connected to the first power voltage line PL1 and the storage capacitor Cst, and can control the driving current flowing from the first power voltage line PL1 to the light-emitting element ED in response to the value of the voltage stored in the storage capacitor Cst.

[0080] The second electrode (e.g., cathode) of the light-emitting element ED receives a common voltage ELVSS via a second power line PL2. The light-emitting element ED receives a drive current from the driving thin-film transistor T1 to emit light. The second power line PL2 can be a common voltage line.

[0081] Despite Figure 3a The middle pixel circuit PC includes two thin-film transistors and a storage capacitor, but this disclosure is not limited thereto.

[0082] refer to Figure 3b The pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0083] Despite Figure 3b Each pixel circuit PC includes signal lines (e.g., SL, SL-1, SL+1, EL, and DL), an initialization voltage line VL, and a first power voltage line PL1, but this disclosure is not limited thereto. In another example, at least one of the signal lines (e.g., SL, SL-1, SL+1, EL, and DL) and / or the initialization voltage line VL may be shared by adjacent pixel circuits.

[0084] The drain electrode of the driving thin-film transistor T1 can be electrically connected to the light-emitting element ED via the emitter control thin-film transistor T6. The driving thin-film transistor T1 receives the data signal Dm and supplies driving current to the light-emitting element ED according to the switching operation of the switching thin-film transistor T2.

[0085] The gate electrode of the switching thin-film transistor T2 is connected to the scan line SL, and the source electrode of the switching thin-film transistor T2 is connected to the data line DL. The drain electrode of the switching thin-film transistor T2 can be connected to the source electrode of the driving thin-film transistor T1, and can be connected to the first power voltage line PL1 via the operation control thin-film transistor T5.

[0086] The switching thin-film transistor T2 can be turned on according to the scan signal Sn received through the scan line SL, and can perform a switching operation to transmit the data signal Dm transmitted through the data line DL to the source electrode of the driving thin-film transistor T1.

[0087] The gate electrode of the compensation thin-film transistor T3 can be connected to the scan line SL. The source electrode of the compensation thin-film transistor T3 can be connected to the drain electrode of the driving thin-film transistor T1, and can be connected to the first electrode of the light-emitting element ED via the emission control thin-film transistor T6. The drain electrode of the compensation thin-film transistor T3 can be connected to one electrode of the storage capacitor Cst, the source electrode of the first initialization thin-film transistor T4, and the gate electrode of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on according to the scan signal Sn received through the scan line SL, and the driving thin-film transistor T1 is connected as a diode by connecting the gate electrode and the drain electrode of the driving thin-film transistor T1.

[0088] The gate electrode of the first initialization thin-film transistor T4 can be connected to the previous scan line SL-1. The drain electrode of the first initialization thin-film transistor T4 can be connected to the initialization voltage line VL. The source electrode of the first initialization thin-film transistor T4 can be connected to one electrode of the storage capacitor Cst, the drain electrode of the compensation thin-film transistor T3, and the gate electrode of the driving thin-film transistor T1. The first initialization thin-film transistor T4 can be turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1, and the initialization operation of the gate electrode voltage of the driving thin-film transistor T1 can be performed by supplying the initialization voltage Vint to the gate electrode of the driving thin-film transistor T1.

[0089] The gate electrode of the operating control thin-film transistor T5 can be connected to the emitter control line EL. The source electrode of the operating control thin-film transistor T5 can be connected to the first power voltage line PL1. The drain electrode of the operating control thin-film transistor T5 is connected to the source electrode of the driving thin-film transistor T1 and the drain electrode of the switching thin-film transistor T2.

[0090] The gate electrode of the emitter control thin-film transistor T6 can be connected to the emitter control line EL. The source electrode of the emitter control thin-film transistor T6 can be connected to the drain electrode of the driving thin-film transistor T1 and the source electrode of the compensation thin-film transistor T3. The drain electrode of the emitter control thin-film transistor T6 can be electrically connected to the first electrode of the light-emitting element ED. The operation control thin-film transistor T5 and the emitter control thin-film transistor T6 are simultaneously turned on according to the emitter control signal En received through the emitter control line EL, so that the driving voltage ELVDD is applied to the light-emitting element ED, and the driving current flows through the light-emitting element ED.

[0091] The gate electrode of the second initialization thin-film transistor T7 can be connected to the next scan line SL+1. The source electrode of the second initialization thin-film transistor T7 can be connected to the first electrode of the light-emitting element ED. The drain electrode of the second initialization thin-film transistor T7 can be connected to the initialization voltage line VL. The second initialization thin-film transistor T7 can be turned on according to the next scan signal Sn+1 received through the next scan line SL+1 to initialize the first electrode of the light-emitting element ED.

[0092] Despite Figure 3b The first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 are respectively connected to the previous scan line SL-1 and the next scan line SL+1, but this disclosure is not limited thereto. In another embodiment, both the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 can be connected to the previous scan line SL-1 and can be driven according to the previous scan signal Sn-1.

[0093] The other electrode of the storage capacitor Cst can be connected to the first power voltage line PL1. Any electrode of the storage capacitor Cst can be connected to the gate electrode of the driving thin-film transistor T1, the drain electrode of the compensation thin-film transistor T3, and the source electrode of the first initialization thin-film transistor T4.

[0094] The second electrode (e.g., cathode) of the light-emitting element ED receives a common voltage ELVSS through a second power voltage line PL2. The light-emitting element ED receives a drive current from the driving thin-film transistor T1 to emit light.

[0095] Pixel circuit PC is not limited to reference Figure 3a and Figure 3b The number of thin-film transistors and storage capacitors and the circuit design are described, and the number and circuit design can be modified in various ways.

[0096] Figure 4 This is a schematic plan view illustrating the shape of a substrate suitable for a display device according to an embodiment. Figure 5a This is a schematic view illustrating the shape of a connection unit on a substrate suitable for a display device according to an embodiment. Figure 5bThis is a schematic view illustrating the shape of the connection units and sub-islands of a substrate suitable for a display device according to an embodiment. As used herein, "plan view" is a view observed in the thickness direction (i.e., the z-direction) of the substrate of the display device.

[0097] Substrate 100 may comprise any of a variety of materials. Specifically, substrate 100 may be formed of glass, metal, or organic materials, etc. In another embodiment, substrate 100 may be formed of a flexible material. In embodiments, for example, substrate 100 may be formed of a material that can be bent, folded, rolled, or rolled. The flexible material used to form substrate 100 may include ultrathin glass, metal, or plastic. When substrate 100 comprises plastic, substrate 100 may comprise polyimide (“PI”). In another example, substrate 100 may comprise any of other types of plastic materials.

[0098] refer to Figures 4 to 5b The substrate 100 of the display device according to this embodiment may include a main island 101, a connecting unit 103, a sub-island 105, and a through portion V. The main island 101, the connecting unit 103, and the sub-island 105 may be integrally formed with each other (i.e., they may be a single piece).

[0099] The main island 101 can be spaced apart from each other in the first direction (x direction) and the second direction (y direction) and can have a flat top surface.

[0100] The main islands 101 can be connected to each other via connecting units 103. The connecting unit 103 may include a first connecting unit 103a connecting the main islands 101 arranged in a first direction and a second connecting unit 103b connecting the main islands 101 arranged in a second direction.

[0101] refer to Figure 5a The connecting unit 103 may include a first portion SS1 that is bent protrudingly in a third direction DR3 parallel to the xy plane, and a second portion SS2 that is connected to the first portion SS1 and bent protrudingly in a fourth direction DR4 parallel to the same plane and opposite to the third direction DR3. In the plan view, the first portion SS1 and the second portion SS2 may be bent portions. The third direction DR3 and the fourth direction DR4 may be directions intersecting the x and y directions. However, this disclosure is not limited thereto. In another embodiment, the third direction DR3 and the fourth direction DR4 may be directions parallel to the x or y direction.

[0102] Despite Figure 5aIn this embodiment, the connecting unit 103 includes a first portion SS1 and a second portion SS2. However, this disclosure is not limited thereto, and in another embodiment, the number of at least one of the first portion SS1 and the second portion SS2 of the connecting unit 103 may be two or more. In this case, the first portion SS1 and the second portion SS2 may be arranged alternately.

[0103] The third part SS3, connecting the first portion SS1 of the connecting unit 103 to the second portion SS2, can be located between the first portion SS1 and the second portion SS2 of the connecting unit 103, and the third part SS3 can correspond to the inflection point of the connecting unit 103. The third part SS3 can be a straight section without bending in a plan view. The third part SS3 can have a smaller strain than the first portion SS1 and the second portion SS2. The first portion SS1, the second portion SS2, and the third part SS3 can be provided continuously.

[0104] When viewed as a whole, the connecting unit 103 may include at least two curved portions. When viewed as a whole, the connecting unit 103 may have an S-shape or a wave shape.

[0105] The shapes of the multiple connecting units 103 can be changed by external forces, and the lengths of the multiple connecting units 103 can be increased or decreased, and when the external forces are removed, the multiple connecting units 103 can return to their original shapes. Specifically, the length of the connecting unit 103 can be increased when the first part SS1 and the second part SS2 are unfolded, or the length of the connecting unit 103 can be decreased when the first part SS1 and the second part SS2 are contracted. Accordingly, the spacing between the multiple main islands 101 can be changed by the multiple connecting units 103, and therefore, the shape of the substrate 100 can be changed two-dimensionally or three-dimensionally.

[0106] Furthermore, since the through portion V, which defines a blank space between the multiple connecting units 103, the substrate 100 can have a grid pattern, and therefore the substrate 100 can be highly flexible.

[0107] refer to Figure 5b Sub-island 105 can be located in the third part SS3, which is the middle part of connecting unit 103. Because the third part SS3 has a smaller strain than the first part SS1 and the second part SS2, the deformation of sub-island 105 can be minimized even when sub-island 105 is located in the third part SS3, and the change in elongation of connecting unit 103 can be minimized.

[0108] The first part SS1 of the connecting unit 103 can connect the main island 101 located on the left side of the sub-island 105 to the sub-island 105, and the second part SS2 of the connecting unit 103 can connect the main island 101 located on the right side of the sub-island 105 to the sub-island 105.

[0109] Return to reference Figure 4 The sub-island 105 may include a first sub-island 105a located between the main islands 101 arranged in a first direction and a second sub-island 105b located between the main islands 101 arranged in a second direction. The first sub-island 105a may be located in the middle portion of the first connecting unit 103a, and the second sub-island 105b may be located in the middle portion of the second connecting unit 103b.

[0110] In the plan view, the area of ​​the secondary island 105 may be smaller than the area of ​​the main island 101. The main island 101 may be connected to four connecting units 103. The secondary island 105 may be connected to two connecting units 103. Although each of the main island 101 and the secondary island 105 is provided in a quadrilateral shape, this disclosure is not limited thereto. Each of the main island 101 and the secondary island 105 may be provided in any of a variety of shapes, such as circular, elliptical, or polygonal.

[0111] The through portion V can be defined between the main island 101, the secondary island 105, and the connecting unit 103. The through portion V can be surrounded by the main island 101, the secondary island 105, and the connecting unit 103.

[0112] The through-portion V is defined to pass through the top and bottom surfaces of the substrate 100. The through-portion V can provide separation areas between the multiple main islands 101, reducing the weight of the substrate 100 and improving its flexibility. Furthermore, because the shape of the through-portion V changes when the substrate 100 is bent, folded, or rolled, stress generation during substrate 100 deformation can be easily reduced, thereby preventing abnormal deformation of the substrate 100 and improving durability. Accordingly, user convenience is improved when the display device 10 is used, and in particular, the display device 10 can be easily applied to wearable devices.

[0113] The through portion V can be formed by removing a portion of the substrate 100 using etching or the like. Various examples of processes for forming the through portion V in the substrate 100 are possible, and the manufacturing method is not limited.

[0114] Figure 6 This is a schematic plan view illustrating the pixel arrangement or light-emitting diode arrangement structure of a display device according to an embodiment.

[0115] refer to Figure 6In a display device, multiple unit pixels UP can be arranged repeatedly in the x and y directions. Each unit pixel UP can include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3 that emit light of different colors from each other. The first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 can be a red pixel, a green pixel, and a blue pixel, respectively.

[0116] The first sub-pixel PX1 can be located on the first sub-island 105a. The first sub-pixel PX1 can be implemented by the first light-emitting element ED1. The first light-emitting element ED1 can be located on the first sub-island 105a.

[0117] The second sub-pixel PX2 can be located on the second sub-island 105b. The second sub-pixel PX2 can be implemented by the second light-emitting element ED2. The second light-emitting element ED2 can be located on the second sub-island 105b.

[0118] The third sub-pixel PX3 can be located on the main island 101. The third sub-pixel PX3 can be implemented by the third light-emitting element ED3. The third light-emitting element ED3 can be located on the main island 101.

[0119] The first sub-pixel PX1 and the third sub-pixel PX3 can be arranged alternately in the x-direction. The second sub-pixel PX2 and the third sub-pixel PX3 can be arranged alternately in the y-direction. The third sub-pixel PX3 can be larger than the first sub-pixel PX1 and the second sub-pixel PX2.

[0120] The first sub-pixel PX1 may be spaced apart from the third sub-pixel PX3 in the x-direction. The second sub-pixel PX2 may be spaced apart from the third sub-pixel PX3 in the y-direction. In some embodiments, the spacing between the center of the first sub-pixel PX1 and the center of the third sub-pixel PX3 may be equal to the spacing between the center of the second sub-pixel PX2 and the center of the third sub-pixel PX3. The first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may be combined to form a single unit pixel UP.

[0121] In this embodiment, because the first sub-pixel PX1 and the second sub-pixel PX2 are not located on the main island 101, but on the first sub-island 105a and the second sub-island 105b spaced apart from the main island 101, the relative distance between the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 can increase or decrease when the display device is stretched or contracted. Accordingly, the size of the unit pixel can be increased or decreased as a whole, thereby effectively improving the visibility of the display device.

[0122] Assuming that all of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 are located on the main island 101, then when the display device is stretched or contracted, the relative positions of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 are maintained and only the non-display area around the first to third sub-pixels PX1, PX2, and PX3 increases, thereby reducing visibility.

[0123] However, in the embodiment, since at least some of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 are located on the sub-island 105, the reduction in visibility can be minimized even when the display device is deformed.

[0124] Furthermore, according to the embodiment, since the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 are distributed, the aperture ratio of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 can be effectively improved.

[0125] Furthermore, since the sub-island 105 is located on the portion of the connecting unit 103 where strain is minimized, the elongation of the display device can be largely unaffected even if the first sub-pixel PX1 and the second sub-pixel PX2 are located on the sub-island 105.

[0126] Figure 7 This is a schematic plan view illustrating the arrangement of pixel circuits and wiring of a display device according to an embodiment. Figure 8 This is a plan view illustrating the connection relationship between the pixel circuitry and the light-emitting element of a display device according to an embodiment. Figure 7 and Figure 8 For ease of explanation, only some components are shown in the diagram.

[0127] refer to Figure 7 and Figure 8 The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 are located on the main island 101.

[0128] The first wiring WL1 may be located on the first connection unit 103a, and the first wiring WL1 may be electrically connected to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3. The first wiring WL1, which is a signal line such as a scan line or a transmit control line, can provide scan signals or transmit control signals to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3.

[0129] The first wiring WL1 may extend in a first direction and may be bent along the shape of the first connecting unit 103a. The first wiring WL1 may include at least two bent portions on the first connecting unit 103a. The first wiring WL1 may be continuously located on the first connecting unit 103a. The first wiring WL1 may be continuously located on the first sub-island 105a.

[0130] The second wiring WL2 can be located on the second connection unit 103b, and the second wiring WL2 can be electrically connected to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3. The second wiring WL2, which is a data line, can provide data signals to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3.

[0131] The second wiring WL2 may extend in the second direction and may be bent along the shape of the second connecting unit 103b. The second wiring WL2 may include at least two bent portions on the second connecting unit 103b. The second wiring WL2 may be continuously located on the second connecting unit 103b. The second wiring WL2 may be continuously located on the second sub-island 105b.

[0132] The first pixel circuit PC1 can be a pixel circuit used to drive the first light-emitting element ED1. Because the first light-emitting element ED1 is located on the first sub-island 105a, the first pixel circuit PC1 can be connected to the first light-emitting element ED1 through the first connection wiring CWL1. The first connection wiring CWL1 can be located on the first connection unit 103a.

[0133] The second pixel circuit PC2 can be a pixel circuit used to drive the second light-emitting element ED2. Since the second light-emitting element ED2 is located on the second sub-island 105b, the second pixel circuit PC2 can be connected to the second light-emitting element ED2 via the second connection wiring CWL2. The second connection wiring CWL2 can be located on the second connection unit 103b.

[0134] The third pixel circuit PC3 can be a pixel circuit used to drive the third light-emitting element ED3. Because the third light-emitting element ED3 is located on the main island 101, the third pixel circuit PC3 can be connected to the third light-emitting element ED3 through the contact hole CNT or the connecting electrode.

[0135] Figure 9 This is a plan view illustrating a portion of a display device according to an embodiment. Figure 10 It is a schematic diagram. Figure 9 The first power voltage line and the first connection wiring in the components are located on the plan layout of the layer. Figure 11 It is a schematic diagram. Figure 9The second power voltage line in the component is located on the planar layout of the layer above it.

[0136] refer to Figure 9 The display device according to the embodiment includes a substrate 100, which includes a main island 101, a first sub-island 105a, a second sub-island 105b, a first connecting unit 103a, a second connecting unit 103b, and a through portion V.

[0137] The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 can be located on the main island 101, and the first light-emitting element ED1 connected to the first pixel circuit PC1 can be located on the first sub-island 105a. The second light-emitting element ED2 connected to the second pixel circuit PC2 can be located on the second sub-island 105b. The third light-emitting element ED3 connected to the third pixel circuit PC3 can be located on the main island 101.

[0138] The contact area CTA can be located around the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3. The contact area CTA can be the region where the second electrode and the second power voltage line PL2 of the corresponding light-emitting element are connected. Because each contact area CTA is placed for each light-emitting element, the common voltage applied to the light-emitting elements can be consistent.

[0139] In an embodiment, the emitting area of ​​the third light-emitting element ED3 can be greater than the emitting area of ​​the first light-emitting element ED1 and the emitting area of ​​the second light-emitting element ED2. Alternatively, in a planar view, the size of the third sub-pixel implemented by the third light-emitting element ED3 can be greater than each of the size of the first sub-pixel implemented by the first light-emitting element ED1 and the size of the second sub-pixel implemented by the second light-emitting element ED2.

[0140] In an embodiment, in a plan view, the third light-emitting element ED3 may overlap with the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3. In an embodiment, the first light-emitting element ED1 may overlap with the first wiring WL1. In an embodiment, in a plan view, the second light-emitting element ED2 may overlap with the second wiring WL2.

[0141] The first wiring WL1 can be located on the first connection unit 103a, and the second wiring WL2 can be located on the second connection unit 103b.

[0142] Multiple first wirings WL1 can be provided, and each of the first wirings WL1 can be a wiring that transmits signals to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3. The first wirings WL1 can transmit scan signals or transmit control signals to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3.

[0143] Multiple second wirings WL2 can be provided, and each of the second wirings WL2 can be a wiring that transmits signals to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3. The second wirings WL2 can transmit data signals to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3. A second connection wiring CWL2 can be located on one side of the second wirings WL2. The second connection wiring CWL2 can connect one electrode of the second light-emitting element ED2 to the second pixel circuit PC2. The second connection wiring CWL2 can be located on the same layer as the second wirings WL2. The first wiring WL1 and the second wiring WL2 can be located on the same layer.

[0144] refer to Figure 10 and Figure 11 The first power voltage line PL1 and the second power voltage line PL2 can be located on most of the substrate 100.

[0145] The first power voltage line PL1 can be located on the main island 101, the first sub-island 105a, the second sub-island 105b, the first connection unit 103a, and the second connection unit 103b. The first power voltage line PL1 can be positioned to correspond to the shape of the main island 101 and the connection unit 103 of the substrate 100.

[0146] The first connection wiring CWL1 may be located on the same layer as the first power voltage line PL1. The first connection wiring CWL1 may extend along one side of the first power voltage line PL1. One end of the first connection wiring CWL1 may be connected to the first pixel circuit PC1, and the other end may be connected to an electrode of the first light-emitting element ED1 through the first connection electrode CM1.

[0147] The connecting electrode CM' can be located on the same layer as the first power voltage line PL1. The connecting electrode CM' can be located on the main island 101 and can be surrounded by the first power voltage line PL1. The connecting electrode CM' can be connected to one electrode of the third pixel circuit PC3 and the third light-emitting element ED.

[0148] The second power voltage line PL2 can be located on the main island 101, the first sub-island 105a, the second sub-island 105b, the first connection unit 103a, and the second connection unit 103b. The second power voltage line PL2 can be positioned to correspond to the shape of the main island 101 and the connection unit 103 of the substrate 100.

[0149] The first connecting electrode CM1, the second connecting electrode CM2, and the third connecting electrode CM3 can be located on the same layer as the second power voltage line PL2. The first connecting electrode CM1 can be located on the first sub-island 105a. The first connecting electrode CM1 can connect the first connecting wiring CWL1 to one electrode of the first light-emitting element ED1. The second connecting electrode CM2 can be located on the second sub-island 105b. The first connecting electrode CM1 can connect the first connecting wiring CWL1 to one electrode of the first light-emitting element ED1. The third connecting electrode CM3 can be located on the main island 101 and can be surrounded by the second power voltage line PL2. The third connecting electrode CM3 can connect the third pixel circuit PC3 to one electrode of the third light-emitting element.

[0150] Figure 12 It is along Figure 9 A schematic cross-sectional view taken from line I-I'. Figure 13 It is along Figure 9 A schematic cross-sectional view taken from line II-II'.

[0151] refer to Figure 12 and Figure 13 The display device according to the embodiment may include a substrate 100, which includes a main island 101, a sub-island 105, and a connection unit 103. Pixel circuitry PC, a third light-emitting element ED3, and an encapsulation layer 300 may be located on the main island 101. A first wiring WL1, a first light-emitting element ED1, and an encapsulation layer 300 may be located on a first sub-island 105a, and the first wiring WL1 and a contact area CTA may be located on a first connection unit 103a. In the embodiment, the first light-emitting element ED1 and the third light-emitting element ED3 may be organic light-emitting elements (OLEDs).

[0152] First, the pixel circuit PC, the third light-emitting element ED3, and the encapsulation layer 300 located on the main island 101 will be described in stacking order.

[0153] A buffer layer 201 may be formed on the main island 101 to prevent impurities from penetrating into the semiconductor layer Act of the thin-film transistor (TFT). The buffer layer 201 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer or multi-layer structure including the above inorganic insulating materials.

[0154] The pixel circuit PC can be located on the buffer layer 201. The pixel circuit PC includes a thin-film transistor (TFT) and a storage capacitor Cst. The TFT can include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. In this embodiment, although the TFT is a top-gate transistor in which the gate electrode GE is located above the semiconductor layer Act and the gate insulating layer 203 is between the gate electrode GE and the semiconductor layer Act, in another embodiment, the TFT can be a bottom-gate transistor.

[0155] The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include amorphous silicon, oxide semiconductor, or organic semiconductor. The gate electrode GE may include a low-resistance metallic material. The gate electrode GE may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer or multi-layer structure comprising the above materials.

[0156] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide. The gate insulating layer 203 may have a single-layer or multi-layer structure comprising the above materials.

[0157] Each of the source electrode SE or the drain electrode DE may include a material with excellent conductivity. Each of the source electrode SE and the drain electrode DE may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer or multi-layer structure comprising the above materials. In an embodiment, each of the source electrode SE and the drain electrode DE may have a multi-layer structure comprising Ti / Al / Ti.

[0158] In the plan view, the storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 that overlap each other with a first interlayer insulating layer 205 between them. The storage capacitor Cst may overlap with a thin-film transistor (TFT). In this respect, in Figure 12 In this embodiment, the gate electrode GE of the thin-film transistor TFT is the lower electrode CE1 of the storage capacitor Cst. In another embodiment, in a plan view, the storage capacitor Cst may not overlap with the thin-film transistor TFT. The storage capacitor Cst may be covered by a second interlayer insulating layer 207.

[0159] Each of the first interlayer insulation layer 205 and the second interlayer insulation layer 207 may comprise an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide. Each of the first interlayer insulation layer 205 and the second interlayer insulation layer 207 may have a single-layer or multi-layer structure comprising the above materials.

[0160] The lower first power voltage line PL can be located on the second interlayer insulating layer 207. The lower first power voltage line PL can be connected to the pixel circuit PC to transmit the driving voltage to the pixel circuit PC. The lower first power voltage line PL can be connected to the first power voltage line PL1 located above the lower first power voltage line PL through a contact hole defined in the first organic insulating layer 209.

[0161] The pixel circuit PC, including the thin-film transistor TFT and the storage capacitor Cst, and the lower first power voltage line PL can be covered by the first organic insulating layer 209.

[0162] The first power voltage line PL1 and the connecting electrode CM' can be located on the first organic insulating layer 209. This is for transmitting the drive voltage ELVDD (see...). Figure 3a The first power voltage line PL1 of the wiring can be positioned to correspond to most of the main island 101. Accordingly, the voltage drop phenomenon of the driving voltage can be minimized. The connecting electrode CM' can be located on the same layer as the first power voltage line PL1, but spaced apart from it. The connecting electrode CM' can be connected to the third connecting electrode CM3 located above the connecting electrode CM' to connect the pixel circuit PC to the first electrode 221 of the third light-emitting element ED3.

[0163] Each of the first power voltage line PL1 and the connecting electrode CM' may include a material with excellent conductivity. Each of the first power voltage line PL1 and the connecting electrode CM' may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer or multi-layer structure comprising the above materials.

[0164] The second power voltage line PL2 and the third connecting electrode CM3 can be located on the second organic insulating layer 211. This is for transmitting the common voltage ELVSS (see [link to ELVSS]). Figure 3a The second power voltage line PL2 of the wiring can be positioned to correspond to most of the main island 101. Accordingly, the voltage drop phenomenon of the common voltage can be minimized. The third connecting electrode CM3 can be located on the same layer as the second power voltage line PL2, spaced apart from the second power voltage line PL2. The third connecting electrode CM3 can be connected to the connecting electrode CM' through the contact hole through the first organic insulating layer 209.

[0165] The third connecting electrode CM3 can be connected to the first electrode 221 of the third light-emitting element ED3.

[0166] Each of the second power voltage line PL2 and the third connecting electrode CM3 may include a material with excellent conductivity. Each of the second power voltage line PL2 and the third connecting electrode CM3 may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer or multi-layer structure comprising the above materials.

[0167] The second electrical voltage line PL2 and the third connecting electrode CM may be covered by a third organic insulating layer 213. Each of the first organic insulating layer 209, the second organic insulating layer 211, and the third organic insulating layer 213 may comprise an organic insulating material such as a general-purpose polymer (e.g., polymethyl methacrylate (“PMMA” or polystyrene (“PS”)), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, a vinyl alcohol polymer, or a blend thereof. In an embodiment, each of the first organic insulating layer 209, the second organic insulating layer 211, and the third organic insulating layer 213 may comprise a polyimide. Various modifications may be made. For example, the first organic insulating layer 209, the second organic insulating layer 211, and the third organic insulating layer 213 may comprise the same material or different materials.

[0168] To form the first organic insulating layer 209, the second organic insulating layer 211, and the third organic insulating layer 213, a liquid organic material can be applied, and then a masking process and a developing process can be performed to form contact holes. Therefore, because the first organic insulating layer 209, the second organic insulating layer 211, and the third organic insulating layer 213 are formed by curing the liquid organic material, the top surfaces of the first organic insulating layer 209, the second organic insulating layer 211, and the third organic insulating layer 213 can be substantially flat.

[0169] The third light-emitting element ED3 can be located on the main island 101 and on the third organic insulating layer 213. The third light-emitting element ED3 may include a first electrode 221, an intermediate layer 222, and a second electrode 223.

[0170] The first electrode 221 may be located on the third organic insulating layer 213. The first electrode 221 may be a pixel electrode or an anode electrode. The first electrode 221 may include a conductive oxide, such as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (“IGO”), or aluminum zinc oxide (“AZO”). In another embodiment, the first electrode 221 may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or mixtures thereof. In another embodiment, the first electrode 221 may further include a film formed of ITO, IZO, ZnO, or In2O3 above / below the reflective film.

[0171] A pixel defining film 215 may be formed on the first electrode 221. The pixel defining film 215 may define the top surface of the first electrode 221 through its exposed opening and may cover the edge of the first electrode 221. Accordingly, the pixel defining film 215 may define the emission region of a pixel. The pixel defining film 215 may include an organic insulating material. Alternatively, the pixel defining film 215 may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxynitride (SiON), or silicon oxide (SiOx). Alternatively, the pixel defining film 215 may include both organic and inorganic insulating materials.

[0172] Intermediate layer 222 may comprise low-molecular-weight or high-molecular-weight materials. When intermediate layer 222 comprises low-molecular-weight materials, it may have a single structure or a stacked structure in which a hole injection layer (“HIL”), a hole transport layer (“HTL”), an emitter layer (“EML”), an electron transport layer (“ETL”), and an electron injection layer (“EIL”) are stacked, and may comprise any of various organic materials such as copper phthalocyanine (“CuPc”), N,N'-bis(naphthyl-1-yl)-N,N'-diphenyl-benzidine (“NPB”), or aluminum tri-8-hydroxyquinoline (Alq3). These layers may be formed using vacuum deposition.

[0173] When the interlayer 222 comprises a high molecular weight material, it may have a structure including an HTL and an EML. In this case, the HTL may comprise poly(3,4-ethylenedioxythiophene) (“PEDOT”), and the EML may comprise a polymeric material such as polyphenylacetylene (“PPV”) or polyfluorene. The interlayer 222 may be formed using methods such as screen printing, inkjet printing, or laser-induced thermal imaging (“LITI”).

[0174] The intermediate layer 222 is not necessarily limited to this and may have any of a variety of structures. The intermediate layer 222 may include a layer integrally formed over the plurality of first electrodes 221 or may include a layer patterned to correspond to each of the plurality of first electrodes 221.

[0175] The second electrode 223 may be formed of a conductive material with a low work function. The second electrode 223 may be a counter electrode or a cathode electrode. In embodiments, for example, the second electrode 223 may include a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or any alloy thereof. Alternatively, the second electrode 223 may further include a layer formed of ITO, IZO, ZnO, or In2O3 on top of the (semi-)transparent layer comprising the above materials. The intermediate layer 222 and the second electrode 223 may be formed using thermal deposition. A capping layer (not shown) for protecting the second electrode 223 and improving light extraction efficiency may further be located on the second electrode 223. The capping layer may include LiF, inorganic materials, and / or organic materials.

[0176] The third light-emitting element ED3 can be provided by stacking the first electrode 221, the intermediate layer 222, and the second electrode 223, and in a plan view, the third light-emitting element ED3 can overlap with the third pixel circuit PC3.

[0177] An encapsulation layer 300 is formed on the second electrode 223. The encapsulation layer 300 can be a component for sealing the third light-emitting element ED3. The encapsulation layer 300 can block external oxygen and moisture, and can have a single-layer or multi-layer structure. The encapsulation layer 300 can include at least one of organic encapsulation layers and inorganic encapsulation layers.

[0178] Despite Figure 12 The intermediate encapsulation layer 300 includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 located between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330; however, this disclosure is not limited thereto. In another embodiment, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and their stacking order can be changed.

[0179] Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic insulating material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, or silicon oxynitride, and may be formed by using chemical vapor deposition (“CVD”) or the like.

[0180] Because the first inorganic encapsulation layer 310 is formed along the structure of the underlying layer, its top surface is not flat. The organic encapsulation layer 320 can cover the first inorganic encapsulation layer 310 to have a substantially flat top surface (different from the first inorganic encapsulation layer 310). Specifically, the portion of the organic encapsulation layer 320 corresponding to the third light-emitting element ED3, which is a display element, can have a substantially flat top surface. Furthermore, the organic encapsulation layer 320 can reduce the stress generated in the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0181] The organic encapsulation layer 320 may include polymethyl methacrylate (“PMMA”), polycarbonate (“PC”), polystyrene (“PS”), acrylic resin, epoxy resin, polyimide, polyethylene, polyethylene sulfonate, polyoxymethylene, polyarylate, or hexamethyldisilane (“HMDSO”).

[0182] In this embodiment, the organic encapsulation layer 320 may include unit organic encapsulation layers 320u, each corresponding to the main island 101. That is, the unit organic encapsulation layer 320u may be located on the main island 101 of the substrate 100 and may not be located on the connecting unit 103. Accordingly, because the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 are in contact with each other outside the unit organic encapsulation layer 320u, the components located on the main island 101 can be individually encapsulated.

[0183] Therefore, since the encapsulation layer 300 includes a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330, even if a crack occurs in the encapsulation layer 300, due to the multilayer structure, the crack will not connect between the first inorganic encapsulation layer 310 and the organic encapsulation layer 320, or between the organic encapsulation layer 320 and the second inorganic encapsulation layer 330. Accordingly, the formation of external moisture or oxygen through which it permeates into the unit display unit 200 can be prevented or minimized. Furthermore, since the second inorganic encapsulation layer 330 contacts the first inorganic encapsulation layer 310 at the edge of the main island 101, the unit organic encapsulation layer 320u can be prevented from being exposed to the outside.

[0184] Since the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can be formed on the entire surface of the substrate 100 using chemical vapor deposition (“CVD”), the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can be formed to cover the side surface of the through portion V.

[0185] When forming the unit organic encapsulation layer 320u, a certain amount of liquid organic material is applied and then cured. In this case, due to the properties of the liquid organic material, the liquid organic material may flow to the edge of the main island 101. To prevent this, a dam structure (not shown) and / or a recessed structure (not shown) may be further provided at the edge of the main island 101.

[0186] The first wiring WL1 for applying various signals to the pixel circuit PC is provided on the first sub-island 105a and the first connection unit 103a. Since the first sub-island 105a is located in the middle part of the first connection unit 103a, the first sub-island 105a can be a part of the first connection unit 103a.

[0187] Furthermore, the first power voltage line PL1 and the second power voltage line PL2 are located on the first sub-island 105a and the first connection unit 103a. The first light-emitting element ED1 is located on the first sub-island 105a.

[0188] The organic material layer 202 can be located on the first sub-island 105a and the first connection unit 103a. The first wiring WL1 can be located on the organic material layer 202. When the buffer layer 201, gate insulating layer 203, first interlayer insulating layer 205 and second interlayer insulating layer 207 located on the main island 101 are referred to as the inorganic insulating layer IL, the inorganic insulating layer IL can be removed from the first sub-island 105a and the first connection unit 103a, and the organic material layer 202 can be formed.

[0189] Because the organic material layer 202 has lower hardness than the inorganic material, it can absorb the tensile stress caused by the deformation of the first connecting unit 103a, thereby minimizing stress concentration on the first wiring WL1. Furthermore, since the organic material layer 202 is located below the first wiring WL1, the neutral surface can be located at the position of the first wiring WL1. Additionally, the organic material layer 202 can prevent height differences when the first wiring WL1 extends to the main island 101.

[0190] The organic material layer 202 can be formed of an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisilane (“HMDSO”), or phenolic resin. The organic material layer 202 can have a single-layer or multi-layer structure including organic insulating material.

[0191] The first wiring WL1 can be formed simultaneously using the same material as the source electrode SE, drain electrode DE, or lower first power voltage line PL located on the main island 101. The first wiring WL1 may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer or multi-layer structure comprising the above materials. The first wiring WL1 may be a scan line and / or an emission control line. The first wiring WL1 may extend to the main island 101 to connect to wiring located on different layers, and may transmit signals to the pixel circuit PC.

[0192] The first organic insulating layer 209 can be positioned to cover the first wiring WL1 on the first sub-island 105a and the first connection unit 103a. A first power voltage line PL1 and a first connection wiring CWL1 can be located on the first organic insulating layer 209. The first connection wiring CWL1 can be connected to the first electrode 221 of the first light-emitting element ED1 on the first sub-island 105a via a first connection electrode CM1. In a plan view, the first power voltage line PL1 can overlap with multiple first wirings WL1.

[0193] A second organic insulating layer 211 can be positioned to cover the first power voltage line PL1 and the first connection wiring CWL1. A second power voltage line PL2 and the first connection electrode CM1 can be located on the second organic insulating layer 211. In a plan view, the second power voltage line PL2 can overlap with the first power voltage line PL1. A third organic insulating layer 213 can be located on the second power voltage line PL2 and the first connection electrode CM1.

[0194] The first light-emitting element ED1 can be located on the first sub-island 105a and the third organic insulating layer 213. Because the structure of the first light-emitting element ED1 is similar to that of the third light-emitting element ED3, the description of the first light-emitting element ED1 can be applied to the third light-emitting element ED3. The first electrode 221 of the first light-emitting element ED1 can be connected to the first connecting electrode CM1 to connect to the first connecting wiring CWL1. In the plan view, the first light-emitting element ED1 can overlap with the first wiring WL1. The first light-emitting element ED1 can be sealed by the encapsulation layer 300.

[0195] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be connected to each other at the edge of the sub-island 105 and may be formed to cover the side surface of the sub-island 105. Dam structures and / or recessed structures for controlling the flow of the organic encapsulation layer 320 may be further provided at the edge of the sub-island 105.

[0196] The contact area CTA can be located on the first connection unit 103a. The contact area CTA can be the area where the second electrode 223 and the second power voltage line PL2 are connected. The third organic insulating layer 213 can define the second power voltage line PL2 through its exposed contact holes in the contact area CTA. The connecting electrode CM” can be located on the third organic insulating layer 213, and the connecting electrode CM” can be connected to the second power voltage line PL2 through the contact holes formed in the third organic insulating layer 213. The second electrode 223 can be located on the third organic insulating layer 213, and can be connected to the second power voltage line PL2 through the connecting electrode CM”. The connecting electrode CM” can be formed of the same material as the first electrode 221. The connecting electrode CM” can be omitted.

[0197] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be located on the first connection unit 103a and the second electrode 223. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may surround the side surface of the through portion V. Although not shown, the pixel defining film 215 may be further located between the third organic insulating layer 213 and the second electrode 223, and the capping layer may be further disposed between the second electrode 223 and the first inorganic encapsulation layer 310.

[0198] Figure 14 This is a schematic cross-sectional view of a display device according to another embodiment. Figure 14 In, with Figure 12 and Figure 13 In the accompanying drawings, the same reference numerals denote the same components. In this embodiment, the first light-emitting element ED1 and the third light-emitting element ED3 can be miniature light-emitting elements mLED. The miniature light-emitting element mLED can be a miniature light-emitting diode.

[0199] The miniature light-emitting element mLED may include a first electrode pad 241, a first semiconductor layer 242, an active layer 243, a second semiconductor layer 244, and a second electrode pad 245. The first electrode pad 241 and the second electrode pad 245 may be electrically connected to the first electrode 221 and the connecting electrode CM, respectively, via conductive components (not shown).

[0200] The first semiconductor layer 242 may be, for example, a p-type semiconductor layer. The first semiconductor layer 242 may be made of, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, or AlInN, having an In... x Al y Ga 1-x-y Semiconductor materials with the composition N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) are formed and can be doped with p-type dopants such as Mg, Zn, Ca, Sr or Ba.

[0201] The second semiconductor layer 244 may be an n-type semiconductor layer. The second semiconductor layer 244 may be made of, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, or AlInN, having an In... x Al y Ga 1-x-y Semiconductor materials with the composition N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) are formed and can be doped with n-type dopants such as Si, Ge or Sn.

[0202] The doping types of the first semiconductor layer 242 and the second semiconductor layer 244 are examples and are not limited thereto. For example, the first semiconductor layer 242 may be an n-type semiconductor layer and the second semiconductor layer 244 may be a p-type semiconductor layer.

[0203] The active layer 243 can be a region where electrons and holes recombine to change to a lower energy level and generate light with a corresponding wavelength. x Al y Ga 1-x-y The semiconductor material is composed of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) and can have a single quantum well or multiple quantum well (“MQW”) structure. Furthermore, the active layer 243 can have a quantum wire structure or a quantum dot structure.

[0204] The mLED (micro-LED) can be a flip-type mLED. The first electrode pad 241 and the second electrode pad 245 of the mLED can face the same surface. Each of the first electrode pad 241 and the second electrode pad 245 can include metal. In embodiments, each of the first electrode pad 241 and the second electrode pad 245 can include tin (Sn), silver (Ag), copper (Cu), and / or alloys thereof. The first electrode pad 241 and the second electrode pad 245 can include the same material or different materials. In some embodiments, each of the first electrode pad 241 and the second electrode pad 245 can include an alloy having a highest content of tin (Sn) and a decreasing content of silver (Ag) and copper (Cu).

[0205] The first electrode pad 241 can be electrically connected to the first electrode 221 to connect to the pixel circuit PC. The second electrode pad 245 can be electrically connected to the connection electrode CM” to connect to the second power voltage line PL2.

[0206] Figure 15 and Figure 16 This is a plan view illustrating the connection relationship between the pixel circuit and the light-emitting element of a display device that can be modified according to an embodiment.

[0207] refer to Figure 15 and Figure 16 The display device may further include a secondary light-emitting element connected to the same pixel circuit as at least one of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3.

[0208] refer to Figure 15 The first auxiliary light-emitting element ED1s can be connected to the same first pixel circuit PC1 as the first light-emitting element ED1. The first auxiliary light-emitting element ED1s can realize a copy pixel of the first light-emitting element ED1. The first auxiliary light-emitting element ED1s can realize a sub-pixel of the same color as the first light-emitting element ED1. The first auxiliary light-emitting element ED1s can be located on the main island 101, and the first auxiliary light-emitting element ED1s and the first light-emitting element ED1 can be connected to each other through the first connection wiring CWL1.

[0209] The second sub-light-emitting element ED2s can be connected to the same second pixel circuit PC2 as the second light-emitting element ED2. The second sub-light-emitting element ED2s can realize a copy pixel of the second light-emitting element ED2. The second sub-light-emitting element ED2s can realize a sub-pixel of the same color as the second light-emitting element ED2. The second sub-light-emitting element ED2s can be located on the main island 101, and the second sub-light-emitting element ED2s and the second light-emitting element ED2 can be connected to each other through the second connection wiring CWL2.

[0210] Accordingly, the first sub-light-emitting element ED1s, the second sub-light-emitting element ED2s, and the third light-emitting element ED3, which realize sub-pixels of different colors, can be located on the main island 101. Furthermore, the first light-emitting element ED1 can be located on the first sub-island 105a, and the second light-emitting element ED2 can be located on the second sub-island 105b. In this structure, five sub-pixels can be implemented using three pixel circuits.

[0211] In some embodiments, the first light-emitting element ED1 and the first auxiliary light-emitting element ED1s can realize red pixels, the second light-emitting element ED2 and the second auxiliary light-emitting element ED2s can realize green pixels, and the third light-emitting element ED3 can realize blue pixels.

[0212] refer to Figure 16The second light-emitting element ED2 can be located on the main island 101, and the third light-emitting element ED3 can be located on the second sub-island 105b. Furthermore, the display device may further include a third sub-light-emitting element ED3s. The third sub-light-emitting element ED3s can be connected to the same third pixel circuit PC3 as the third light-emitting element ED3. The third sub-light-emitting element ED3s can realize a copy pixel of the third light-emitting element ED3. The third sub-light-emitting element ED3s can realize a sub-pixel of the same color as the third light-emitting element ED3. The third sub-light-emitting element ED3s can be located on the main island 101, and the third sub-light-emitting element ED3s and the third light-emitting element ED3 can be connected to each other via a second connection wiring CWL2. In this structure, four sub-pixels can be implemented using three pixel circuits.

[0213] Figures 17 to 19 This is a schematic cross-sectional view illustrating an example of a modification to the connection wiring according to an embodiment.

[0214] refer to Figures 17 to 19 The first pixel circuit PC1, the third pixel circuit PC3, the first sub-light-emitting element ED1s connected to the first pixel circuit PC1, and the third light-emitting element ED3 connected to the third pixel circuit PC3 can be located on the main island 101. The first light-emitting element ED1 connected to the first pixel circuit PC1 can be located on the first sub-island 105a.

[0215] The first sub-light-emitting element ED1s and the first light-emitting element ED1 can be connected to each other through the first connection wiring CWL1. The first connection wiring CWL1 can be located on the first connection unit 103a.

[0216] refer to Figure 17 The first connection wiring CWL1 can be provided by connecting conductive layers located on different layers. In an embodiment, for example, the first connection wiring CWL1 may include a 1-1 connection wiring CWL1a located on the first organic insulating layer 209 and a 1-2 connection wiring CWL1b located on the second organic insulating layer 211. The 1-1 connection wiring CWL1a and the 1-2 connection wiring CWL1b can be connected to each other through contact holes in the first connection unit 103a. In this structure, interference with other wiring can be avoided.

[0217] refer to Figure 18 In another embodiment, the first connection wiring CWL1 of the conductive layer located on the second organic insulating layer 211 can extend continuously on the first connection unit 103a.

[0218] refer to Figure 19 The first connection wiring CWL1 can be provided as a conductive layer located on the third organic insulating layer 213. The first connection wiring CWL1 can be provided by extending the first electrode 221 of the first sub-light-emitting element ED1s.

[0219] Figure 20 This is a plan view illustrating a portion of a display device according to an embodiment. In detail, Figure 20 The illustration shows the light-emitting element located on the main island of the substrate.

[0220] refer to Figure 20 Multiple light-emitting elements (EDs) for emitting light of the same color can be located on the main island 101. When the EDs are miniature EDs, they can have very small dimensions, and therefore, multiple EDs can be provided on the main island 101. Multiple EDs can be connected to a single pixel circuit. The number of EDs can be determined by considering light efficiency.

[0221] Figure 21 This is a plan view illustrating a portion of a display device according to an embodiment. In detail, Figure 21 The illustration shows a light-emitting element located on a sub-island of the substrate.

[0222] refer to Figure 21 Multiple light-emitting elements (EDs) for emitting light of the same color can be located on the sub-island 105. When the EDs are miniature EDs, they can have very small dimensions, and therefore, multiple EDs can be provided on the sub-island 105. Multiple EDs can be connected to a pixel circuit. The number of EDs can be determined by considering their luminous efficiency. Accordingly, the number of red, green, and blue EDs located on a single sub-island 105 can be different.

[0223] Figure 22 This is a schematic cross-sectional view of a display device according to an embodiment.

[0224] refer to Figure 22 The display device according to this disclosure includes a substrate 100 comprising a main island 101, a sub-island 105 and a connection unit 103, a pixel circuit PC located on the main island 101, light-emitting elements ED located on the main island 101 and the sub-island 105, and wiring WL located on the connection unit 103. The light-emitting elements ED may be sealed by an encapsulation layer 300.

[0225] In this embodiment, the display device may further include an optical functional layer 400. The optical functional layer 400 may include a color conversion layer 402 and a light-shielding unit BM. In some embodiments, the color conversion layer 402 may be a color filter. The color conversion layer 402 may include a red color filter, a green color filter, and a blue color filter corresponding to the red sub-pixel, green sub-pixel, and blue sub-pixel, respectively. In a planar view, the color conversion layer 402 may overlap with the main island and the sub-island.

[0226] The light-shielding unit BM can be positioned to correspond to the portion where no sub-pixels are placed. In a plan view, the light-shielding unit BM can overlap with at least a portion of the connecting unit 103. The light-shielding unit BM can include at least one of black pigment, black dye, and black particles. In some embodiments, the light-shielding unit BM can include Cr or CrO. X Cr / CrO X Cr / CrO X / CrN Y Materials, resins (carbon pigments, RGB mixed pigments), graphite or non-chromium materials.

[0227] The color conversion layer 402 may include quantum dots. Quantum dots can exhibit unique excitation and emission properties depending on the material and size, and therefore can convert incident light into light of a specific color.

[0228] Quantum dots can be selected from group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof. Furthermore, quantum dots have sizes and shapes commonly used in the art and are not particularly limited. More specifically, quantum dots can have spherical shapes, pyramidal shapes, multi-armed shapes, cubic nanoparticle shapes, nanotube shapes, nanowire shapes, nanofiber shapes, or nanoplate particle shapes.

[0229] According to this embodiment, when the optical functional layer 400 is applied to a display device, the light-emitting element ED can be provided as a light-emitting element that emits light of one color. In an embodiment, for example, all of the light-emitting elements ED can emit blue light. However, this disclosure is not limited thereto. Even when the optical functional layer 400 is applied, the light-emitting element ED can emit red, green, and blue light for each position of each sub-pixel.

[0230] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail can be made without departing from the spirit and scope defined by the following claims.

Claims

1. A display device, comprising: The substrate includes a main island arranged in a first direction and a second direction, a first connecting unit configured to connect the main islands arranged in the first direction to each other, a second connecting unit configured to connect the main islands arranged in the second direction to each other, a first sub-island located in the middle portion of the first connecting unit, a second sub-island located in the middle portion of the second connecting unit, and a plurality of through portions defined between the main islands. The first pixel circuit, the second pixel circuit, and the third pixel circuit are located on each of the main islands; A first light-emitting element is located on the first sub-island and connected to the first pixel circuit; A first connection wiring is located on the first connection unit and is configured to connect the first pixel circuit to the first light-emitting element; as well as The first wiring is located on the first connection unit.

2. The display device according to claim 1, further comprising: The second light-emitting element is located on the second sub-island and connected to the second pixel circuit; as well as A third light-emitting element is located on each of the main islands and connected to the third pixel circuit. The first light-emitting element, the second light-emitting element, and the third light-emitting element emit light of different colors from each other.

3. The display device according to claim 2, wherein, In the planar view, the size of the third sub-pixel implemented by the third light-emitting element is larger than the size of the first sub-pixel implemented by the first light-emitting element.

4. The display device according to claim 2, wherein, In the plan view, the third light-emitting element at least partially overlaps with the first pixel circuit.

5. The display device according to claim 1, wherein, The first connecting unit includes a first portion protruding upward in a third direction in a plan view and a second portion protruding in a fourth direction opposite to the third direction, wherein the first sub-island is located between the first portion and the second portion.

6. The display device according to claim 1, further comprising: The second wiring is located on the second connection unit. The first wiring and the second wiring are located on the same layer.

7. The display device according to claim 6, wherein, At least one of the first wirings is a scan line through which the scan signal is transmitted, and At least one of the second wirings is a data line through which data signals are transmitted.

8. The display device according to claim 1, further comprising: A first power voltage line is located on each of the main island, the first connection unit, and the second connection unit. The first connection wiring and the first power voltage line are located on the same layer.

9. The display device according to claim 1, further comprising: The second light-emitting element is located on the second sub-island and connected to the second pixel circuit; The second wiring is configured to provide data signals to the first pixel circuit, the second pixel circuit and the third pixel circuit; as well as A second connection wiring is located on the second connection unit and is configured to connect the second pixel circuit to the second light-emitting element. The second connection wiring and the second wiring are located on the same layer.

10. The display device according to claim 1, further comprising: The second power voltage line is located on each of the main island, the first connection unit, and the second connection unit. The contact area where the second power voltage line and the second electrode of the first light-emitting element are connected to each other is located on the first connection unit.

11. The display device according to claim 1, wherein, The first light-emitting element is an organic light-emitting element.

12. The display device according to claim 1, wherein, The first light-emitting element is a miniature light-emitting element.

13. The display device according to claim 1, further comprising: A first light-emitting element is connected to the first pixel circuit and is configured to emit light of the same color as the first light-emitting element. The first auxiliary light-emitting element is located on each of the main islands.

14. The display device according to claim 13, wherein, The first connection wiring includes 1-1 connection wiring and 1-2 connection wiring located in different layers in the first connection unit.

15. The display device according to claim 13, further comprising: The second power voltage line is located on each of the main island, the first connection unit, and the second connection unit. The first connecting wiring and the second power voltage line are located on the same layer.

16. The display device according to claim 13, wherein, The first connecting wire and the first electrode of the first light-emitting element are located on the same layer.

17. The display device according to claim 1, wherein, Each of the main islands is provided with a plurality of third light-emitting elements configured to emit light of the same color.

18. The display device according to claim 1, wherein, The first light-emitting element is provided in multiple forms, and the multiple first light-emitting elements are configured to emit light of the same color.

19. The display device according to claim 1, further comprising: An optical functional layer is located on the first light-emitting element. The optical functional layer includes a color conversion layer that overlaps with the first light-emitting element in the planar view and a light-shielding unit that overlaps with the first connection unit.

20. The display device according to claim 19, wherein, The color conversion layer comprises quantum dots.

21. A display device, comprising: The substrate includes a main island, a sub-island spaced apart from the main island, a connection unit configured to connect the main island to the sub-island, and a plurality of through portions defined between the main island and the sub-island; The first pixel circuit and the second pixel circuit are located on the main island; A first light-emitting element is located on the main island and at least partially overlaps with the first pixel circuit and the second pixel circuit in a plan view; as well as The second light-emitting element is located on the sub-island and connected to the second pixel circuit.

22. The display device according to claim 21, wherein, The color of the first sub-pixel implemented by the first light-emitting element and the color of the second sub-pixel implemented by the second light-emitting element are different from each other, and in the planar diagram, the size of the first sub-pixel is larger than the size of the second sub-pixel.

23. The display device according to claim 21, wherein, The connecting unit includes a curved portion.

24. The display device according to claim 21, further comprising: The second light-emitting element is located on the main island and connected to the second pixel circuit.

25. The display device according to claim 21, wherein, In the plan view, the area of ​​the secondary island is smaller than the area of ​​the main island.

Images