A unified programming method based on multi-element arithmetic

Abstract

The application relates to a unified programming method based on multi-element computing power, and belongs to the technical field of unified programming. The method comprises the following steps: obtaining source computing power data, target computing power data and source computing power code, and performing preprocessing to obtain a source computing power data set and a target computing power data set; the source computing power data set, the target computing power data set and the source computing power code are processed by a computing power feature encoder model to obtain a source computing power feature vector, a target computing power feature vector and a source computing power code feature representation; then the source computing power feature vector, the target computing power feature vector and the source computing power code feature representation are input into a unified programming model to obtain a preliminary target computing power code feature representation; the target computing power feature vector, the target computing power code feature representation and the preliminary target computing power code feature representation are processed by a computing power guiding model to generate an adjusted feature representation, and efficient code meeting target platform characteristics is generated through a pre-defined target platform code template library. The application can improve the multi-platform adaptation capability of code.

Description

Technical Field

[0001] This invention belongs to the field of unified programming, specifically relating to a unified programming method based on multi-dimensional computing power. Background Technology

[0002] With the development of artificial intelligence technology, computing power demands are becoming increasingly diverse. Different types of chips, such as CPUs, GPUs, and FPGAs, play crucial roles in high-performance computing. This hardware diversification leads to several problems with existing programming methods: poor compatibility: Different hardware manufacturers develop independent programming models and compilers (e.g., CUDA, OpenCL, HLS) to optimize their products. The lack of a unified standard among these models makes it difficult to port applications across different hardware platforms. High porting difficulty: Existing cross-platform porting often relies on human experience or manual code rewriting. For example, migrating the same algorithm between CPU and FPGA requires readjusting parallelism based on the hardware architecture and inserting pipelined and memory partitioning instructions, resulting in high development costs, long development cycles, and severely limiting product iteration efficiency. Limitations of middleware technology: Some solutions attempt to provide a unified interface between different hardware through middleware, but this increases system complexity and overhead, easily leading to performance degradation and instability. Furthermore, due to a lack of deep modeling of hardware characteristics and code structure, the generated ported code often fails to fully leverage the computing power advantages of the target platform.

[0003] In summary, existing technologies generally suffer from problems such as inconsistent cross-platform programming standards, reliance on manual code migration, and insufficient hardware adaptation, making it difficult to meet the demands for efficient development and performance optimization in diverse computing power environments. To address this, this invention proposes a unified programming method based on diverse computing power. This method introduces a computing power feature encoder to standardize the modeling of hardware parameters and code structure, constructing a unified programming model to automatically map the semantics of the source platform to the semantics of the target platform. Furthermore, it combines a computing power guidance model and a platform characteristic matrix to perform hardware-aware optimization of the generated features. Finally, relying on a target platform code template library, it automatically generates efficient code that conforms to the characteristics of the target platform, thereby achieving one-time development and efficient adaptation across multiple platforms. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides a unified programming method based on multi-dimensional computing power.

[0005] To achieve the above objectives, the present invention employs the following technical solution:

[0006] This invention provides a unified programming method based on multi-dimensional computing power, comprising the following steps:

[0007] S1. Obtain source computing power data, target computing power data, and source computing power code, and preprocess the data to obtain source computing power dataset Ds and target computing power dataset Dt;

[0008] S2. To address the problem that existing methods, relying solely on manual rules or simple networks, struggle to fully exploit the complex nonlinear relationships between computing power parameters and code structure, this step designs a computing power feature encoder model composed of a multilayer perceptron, a self-attention mechanism, and a convolutional fusion layer. This enhances the expressive power of computing power features, enabling parallel modeling of code features and hardware features, laying the foundation for subsequent cross-platform inference. Data from the source and target computing power datasets are processed by the computing power feature encoder model to obtain the source computing power feature vector Fs and the target computing power feature vector Ft; the source computing power code is also processed by the computing power feature encoder model to obtain the source computing power code feature representation.

[0009] S3. Construct a unified programming model, which includes a first encoder, a first decoder, and an inference network; the source computing power feature vector Fs, the target computing power feature vector Ft, and the source computing power code feature representation are input into the unified programming model to obtain a preliminary target computing power code feature representation;

[0010] S4. Construct a computing power guidance model, which includes an input layer, a third multilayer perceptron, a fourth self-attention mechanism layer, and an output adjustment layer; the target computing power feature vector Ft, the target computing power code feature representation, and the preliminary target computing power code feature representation are processed by the computing power guidance model to generate an adjusted feature representation;

[0011] By designing a computational power guidance model that includes a multilayer perceptron, a fourth self-attention mechanism layer, and an output adjustment layer, and especially by introducing a platform characteristic matrix P in the output adjustment layer to explicitly map target computational power characteristics and code structure attributes, the generated features can be adjusted in a targeted manner. The advantage of this design is that the model can dynamically optimize the generated features according to platform characteristics, ensuring that the final code better meets the computational power, bandwidth, and parallelism requirements of the target platform.

[0012] S5. The adjusted feature representation is input into a predefined target platform code template library to generate efficient code that conforms to the characteristics of the target platform.

[0013] Furthermore, step S1 specifically includes:

[0014] The device type, computing power, memory capacity, memory bandwidth, communication bandwidth, power consumption, and latency of the source and target computing power devices are collected; the ratio of computing power to power consumption is used to obtain the computing density; the ratio of sequential access to random access to memory for each device is used to obtain the memory access pattern; and the ratio of communication bandwidth to computing power is used to obtain the communication efficiency.

[0015] The collected data on device type, computing power, memory capacity, memory bandwidth, communication bandwidth, power consumption, latency, computing density, memory access mode, and communication efficiency are merged to obtain data for each device; thus, the source computing power dataset Ds and the target computing power dataset Dt are obtained; the data in the source computing power dataset Ds and the target computing power dataset Dt are converted into PyTorch tensors.

[0016] Furthermore, step S2 specifically includes:

[0017] The hidden layer comprises a first hidden layer, a second hidden layer, a third hidden layer, and a Dropout layer connected in series; the feature extraction layer comprises a first self-attention mechanism layer and a feature fusion layer; the first self-attention mechanism layer adopts a multi-head attention mechanism; all hidden layers are fully connected layers.

[0018] The input layer receives the PyTorch tensor transformed from the source computing power dataset Ds and inputs it into the hidden layer to obtain the outputs of the first hidden layer, the second hidden layer, and the third hidden layer. The output of the third hidden layer passes through the first self-attention mechanism layer to obtain the output of the self-attention mechanism layer. In the feature fusion layer, the outputs of the first hidden layer, the second hidden layer, and the first self-attention mechanism layer are concatenated along the channel dimension to obtain the concatenated features. The concatenated features are then convolved to obtain the source computing power feature vector Fs.

[0019] Similarly, after the target computing power dataset Dt is converted into a PyTorch tensor, it passes through the input layer, hidden layer, and feature extraction layer to obtain the target computing power feature vector Ft;

[0020] The source computing power code is processed by the computing power feature encoder model to obtain the source computing power code feature representation.

[0021] Further, in step S3, the first encoder includes a first convolutional layer, a second convolutional layer, a third convolutional layer, and a pooling layer; all three convolutional layers are two-dimensional convolutions, and the pooling layer is a max pooling layer; the first decoder includes a first upsampling layer, a second upsampling layer, and a third upsampling layer; the processing procedures in the first encoder and the first decoder are as follows:

[0022] The source computing power feature vector Fs is augmented with dimension using the unsqueeze method to obtain the source computing power feature extension vector. The source computing power feature extension vector is then input into the first convolutional layer to obtain the output of the first convolutional layer. The output of the first convolutional layer is then input into the second convolutional layer to obtain the output of the second convolutional layer. The output of the second convolutional layer is then input into the third convolutional layer to obtain the output of the third convolutional layer. The output of the third convolutional layer is then input into the pooling layer to obtain the output of the pooling layer.

[0023] The output of the pooling layer is input to the first upsampling layer, and the spatial dimension is expanded by a factor of 2 through bilinear interpolation to obtain the first upsampling feature map. The output of the third convolutional layer of the first encoder is concatenated with the first upsampling feature map through channels to obtain the first feature map. The first feature map is compressed through a convolution operation to obtain the first compressed feature map. The first compressed feature map is input to the second upsampling layer, and the spatial dimension is expanded by a factor of 2 through bilinear interpolation to obtain the second upsampling feature map. The output of the second convolutional layer of the first encoder is concatenated with the second upsampling feature map through channels to obtain the second feature map. The second feature map is compressed through convolution to obtain a second compressed feature map. This compressed feature map is then input to the third upsampling layer, where bilinear interpolation expands the spatial dimension by a factor of two, resulting in a third upsampling feature map. The output of the first convolutional layer of the first encoder is convolved with the third upsampling feature map after adjusting the number of channels through convolution, yielding the third feature map. This third feature map is then compressed through convolution to obtain an intermediate representation of the target computing power features. The intermediate representation of the target computing power features is then flattened through convolution to obtain the intermediate representation vector of the target computing power features. Through the first encoder-decoder, the source and target computing power features are refined into an intermediate representation vector of the target computing power features and a structured vector of the target platform's full-scale features. This is then combined with the source computing power code features through an inference network to map the semantics of the source platform to the semantics of the target platform, resulting in a target computing power code feature representation and a preliminary target computing power code feature representation. By introducing intermediate representations and dual-path inference, the problem of extensive code rewriting across different platforms, as in traditional methods, is avoided, significantly reducing portability and development costs. This also improves the stability and accuracy of feature transfer.

[0024] Similarly, the target computing power feature vector Ft is processed by the first encoder and the first decoder to obtain the full-scale feature structured vector of the target platform.

[0025] Through the first encoder-decoder, the source computing power features and target computing power features are refined into an intermediate representation vector of the target computing power features and a structured vector of the target platform's full-scale features. Then, through an inference network combined with the source computing power code features, the semantics of the source platform are mapped to the semantics of the target platform, resulting in a target computing power code feature representation and a preliminary target computing power code feature representation. This design, by introducing intermediate representations and dual-path inference, avoids the problem of extensive code rewriting required across different platforms in traditional methods, significantly reducing portability difficulty and development costs. It also improves the stability and accuracy of feature transfer.

[0026] Further, in step S3, the inference network includes a second encoder and a second decoder; the second encoder includes a feature concatenation layer, a first multilayer perceptron, and a second self-attention mechanism layer; the first multilayer perceptron includes a first fully connected layer, a second fully connected layer, and a ReLU activation function; the second decoder includes a second multilayer perceptron and a third self-attention mechanism layer, the second multilayer perceptron including a third fully connected layer and a fourth fully connected layer; the processing procedure in the inference network is as follows:

[0027] The source computing power feature vector Fs, the source computing power code feature representation, and the target computing power feature intermediate representation vector are concatenated in the feature concatenation layer along the feature dimension to obtain the first concatenated feature. The first concatenated feature is processed by the first multilayer perceptron and the second self-attention mechanism layer to obtain the second encoder output feature.

[0028] The output features of the second encoder are processed by the second decoder to obtain the target computing power code feature representation.

[0029] Similarly, the target platform full-scale feature structured vector, the source computing power code feature representation, and the target computing power feature intermediate representation vector are passed through the inference network to obtain the preliminary target computing power code feature representation.

[0030] Further, step S4 specifically includes: the third multilayer perceptron includes a fifth fully connected layer, a sixth fully connected layer, and a seventh fully connected layer; all fully connected layers use the ReLU activation function to introduce nonlinearity; the fourth self-attention mechanism layer introduces a learnable bias term to enhance feature processing capability; the processing procedure in the computational power-guided model is as follows:

[0031] The target computing power feature vector Ft, the target computing power code feature representation, and the preliminary target computing power code feature representation are concatenated in the feature dimension through the input layer to obtain the second concatenated feature; the second concatenated feature is processed through the third multilayer perceptron and the fourth self-attention mechanism layer to obtain the self-attention output feature;

[0032] The output adjustment layer introduces an adjustment formula based on platform characteristics. ,in, This represents the adjusted feature representation. Let P represent the self-attention output feature, and let P represent the platform characteristic matrix.

[0033] By designing a computational power guidance model that includes a multilayer perceptron, a self-attention mechanism layer, and an output adjustment layer, and especially by introducing a platform characteristic matrix P in the output adjustment layer to explicitly map target computational power features and code structure attributes, the generated features can be adjusted in a targeted manner. The advantage of this design is that the model can dynamically optimize the generated features according to platform characteristics, ensuring that the final code better meets the computational power, bandwidth, and parallelism requirements of the target platform.

[0034] Furthermore, the predefined target platform code template library includes pre-configured optimization frameworks and dynamically populated interfaces for different hardware architectures, including: CUDA kernel function structures and thread parameter interfaces in the GPU template; HLS pipeline and memory block instruction interfaces in the FPGA template; and OpenMP multithreading and vectorization switch interfaces in the CPU template.

[0035] Furthermore, during model training, computational cost loss, resource utilization loss, and performance loss are used to train the model:

[0036] The formula for the computing power loss is as follows:

[0037] ,

[0038] in, Indicates computing power loss; Indicates resource consumption; Indicates maximum efficiency; i represents the index of the resource type being calculated; the formula for the resource usage loss is as follows:

[0039] ,

[0040] in, R represents the resource usage loss; R represents the number of resource types; r represents the resource type index; This represents the actual memory usage of the r-th type of resource; This represents the maximum memory capacity of the r-th type of resource; This represents the actual amount of computational resources allocated to the r-th type of resource; Let r represent the maximum computing power of the r-th type of resource; the formula for the performance loss is as follows:

[0041] ,

[0042] in, Indicates performance loss; Indicates the expected throughput; This represents the actual throughput.

[0043] The advantages of this invention are:

[0044] This invention achieves efficient and automatic code migration and performance optimization across heterogeneous computing platforms through multi-level model collaborative optimization and dynamic hardware feature adaptation mechanisms. It employs a computing power feature encoder to abstract heterogeneous hardware parameters into standardized feature vectors, combining this with a unified programming model to generate platform-independent intermediate representations, supporting one-time development and multi-platform adaptation. Hardware-aware code optimization is achieved through dynamic optimization of the platform feature matrix and dynamic filling of template parameters. A multi-objective loss function is designed to simultaneously optimize resource utilization, allocation rationality, and execution efficiency, and a self-attention mechanism and a multilayer perceptron (MLP) are used to fine-tune code features to maximize the utilization of target platform characteristics. A modular template library reduces learning complexity. In summary, this invention, through hardware feature encoding, dynamic matrix optimization, and multi-loss collaborative training, unifies the programming interface of heterogeneous computing platforms, solving the pain points of high manual adaptation costs, fragmented optimization strategies, and difficulty in guaranteeing performance in traditional cross-platform development. It has significant application value in multi-hardware collaborative scenarios. Attached Figure Description

[0045] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0046] Figure 1 This is a flowchart of the steps of the method of the present invention;

[0047] Figure 2 This is a comparative analysis of the performance of the multi-source computing platform of the present invention;

[0048] Figure 3 This is a feature migration heatmap of the method of the present invention. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] Example 1

[0051] In this embodiment, as Figure 1 As shown, this invention provides a unified programming method based on multi-dimensional computing power, the specific steps of which include:

[0052] S1. Obtain source computing power data, target computing power data, and source computing power code, and preprocess the data to obtain source computing power dataset Ds and target computing power dataset Dt;

[0053] To address the issues of inconsistent definitions, redundant dimensions, and difficulty in alignment of metrics across different computing power platforms in existing technologies, this step collects data on the device type, computing power, memory capacity, memory bandwidth, communication bandwidth, power consumption, and latency of both the source and target computing power devices. It then calculates the ratio of computing power to power consumption to obtain computing density; calculates the ratio of sequential to random memory accesses for each device to obtain memory access patterns; and calculates the ratio of communication bandwidth to computing power to obtain communication efficiency.

[0054] The collected data on device type, computing power, memory capacity, memory bandwidth, communication bandwidth, power consumption, latency, computing density, memory access mode, and communication efficiency are merged to obtain data for each device; thus, a source computing power dataset Ds and a target computing power dataset Dt are obtained; the data in the source computing power dataset Ds and the target computing power dataset Dt are converted into PyTorch tensors; the PyTorch tensors have a dimension of 10;

[0055] By collecting 10 core parameters, a unified indicator system for different hardware is established; the data is converted into PyTorch tensors to provide an adapted input format for subsequent computing power feature encoders, solving the problem of data silos; derived parameters, such as computational density and communication efficiency, are directly related to code execution performance, helping the model capture the implicit relationship between hardware characteristics and code efficiency.

[0056] S2 addresses the shortcomings of existing methods that rely solely on manual rules or simple networks, making it difficult to fully explore the complex nonlinear relationships between computing power parameters and code structure. It also addresses the issue of hardware parameters and code structure being processed separately, failing to model them as a holistic feature set, leading to a mismatch between hardware requirements and code capabilities during subsequent cross-platform mapping. This step designs a computing power feature encoder model composed of a multilayer perceptron, a self-attention mechanism, and a convolutional fusion layer. This model can map the source computing power dataset and the target computing power dataset into source computing power feature vectors Fs and target computing power feature vectors Ft, respectively, while simultaneously extracting the structured feature representation of the source computing power code. The advantage of this design is that it enhances the expressive power of computing power features and enables parallel modeling of code features and hardware features, laying the foundation for subsequent cross-platform inference.

[0057] Specifically, a computing power feature encoder model is constructed, which includes an input layer, a hidden layer, and a feature extraction layer. Data from the source computing power dataset and the target computing power dataset are processed by the computing power feature encoder model to obtain the source computing power feature vector Fs and the target computing power feature vector Ft. The source computing power code is processed by the computing power feature encoder model to obtain the source computing power code feature representation. The hidden layer includes a first hidden layer, a second hidden layer, a third hidden layer, and a Dropout layer connected in series. The number of neurons in the first hidden layer, the second hidden layer, and the third hidden layer are 128, 64, and 32, respectively. The feature extraction layer includes a first self-attention mechanism layer and a feature fusion layer. The first self-attention mechanism layer adopts a multi-head attention mechanism. All hidden layers are fully connected layers.

[0058] The input layer receives the PyTorch tensor transformed from the source computing power dataset Ds and inputs it into the hidden layer to obtain the outputs of the first hidden layer, the second hidden layer, and the third hidden layer. The output of the third hidden layer passes through the first self-attention mechanism layer to obtain the output of the self-attention mechanism layer. In the feature fusion layer, the outputs of the first hidden layer, the second hidden layer, and the first self-attention mechanism layer are concatenated along the channel dimension to obtain the concatenated features. The concatenated features are then convolved to obtain the source computing power feature vector Fs.

[0059] Similarly, after the target computing power dataset Dt is converted into a PyTorch tensor, it passes through the input layer, hidden layer, and feature extraction layer to obtain the target computing power feature vector Ft with dimension (batchsize, 32).

[0060] In one embodiment, the input layer receives a PyTorch tensor transformed from the source computing power dataset Ds, passes it through a first hidden layer, and obtains an output with a dimension of (batchsize, 128); the output of the first hidden layer is input into a second hidden layer to obtain an output with a dimension of (batchsize, 64); the output of the second hidden layer passes through a third hidden layer and a Dropout layer to obtain the output of the third hidden layer with a dimension of (batchsize, 32); the Dropout layer can prevent the model from overfitting during training, effectively reduce the interdependence between neurons, reduce the risk of model overfitting, enhance the model's generalization ability, and enable the model to perform well in different datasets and scenarios. The output of the third hidden layer with dimension (batchsize, 32) is input to the first self-attention mechanism layer to obtain the output of the first self-attention mechanism layer with dimension (batchsize, 32). In the feature fusion layer, the outputs of the first hidden layer, the second hidden layer, and the first self-attention mechanism layer are concatenated along the channel dimension to obtain a concatenated tensor with dimension (batchsize, 224). The concatenated tensor is then fused through a convolutional layer to obtain the source computational feature vector Fs with dimension (batchsize, 32).

[0061] The source computing power code is processed by the computing power feature encoder model to obtain a source computing power code feature representation with dimension (batchsize, 20).

[0062] This invention employs a structure consisting of three fully connected hidden layers, multi-head self-attention, and convolutional fusion. This structure can both uncover the linear relationships of basic parameters through fully connected layers and focus on key features through self-attention mechanisms. Finally, convolutional fusion achieves deep coupling between hardware and code features. A Dropout layer is then connected after the hidden layers to reduce dependencies between neurons, enabling the model to adapt to hardware from different manufacturers and with different architectures, eliminating the need for repeated training for a single hardware device.

[0063] S3. To address the problems of traditional code porting relying on human experience and lacking intermediate representations and automated reasoning mechanisms, this invention constructs a unified programming model. This unified programming model includes a first encoder, a first decoder, and an inference network. The source computing power feature vector Fs, the target computing power feature vector Ft, and the source computing power code feature representation are input into the unified programming model to obtain a preliminary target computing power code feature representation. Through the first encoder and decoder, the source computing power features and target computing power features are refined into an intermediate representation vector of the target computing power features and a full-scale feature structured vector of the target platform. Then, through the inference network combined with the source computing power code features, the semantics of the source platform are mapped to the semantics of the target platform, resulting in the target computing power code feature representation and the preliminary target computing power code feature representation. This design, by introducing intermediate representations and dual-path inference, avoids the problem of extensive code rewriting between different platforms in traditional methods, significantly reducing porting difficulty and development costs. It also improves the stability and accuracy of feature transfer.

[0064] Specifically, the source computing power feature vector Fs and the target computing power feature vector Ft are processed by the first encoder and the first decoder to obtain the target computing power feature intermediate representation vector and the target platform full-scale feature structured vector, respectively. The source computing power feature vector Fs, the source computing power code feature representation, and the target computing power feature intermediate representation vector are processed by the inference network to obtain the target computing power code feature representation. The target platform full-scale feature structured vector, the source computing power code feature representation, and the target computing power feature intermediate representation vector are processed by the inference network to obtain the preliminary target computing power code feature representation.

[0065] In one embodiment, the first encoder includes a first convolutional layer, a second convolutional layer, a third convolutional layer, and a pooling layer; all three convolutional layers are two-dimensional convolutions with a kernel size of 3×3, a stride of 1, and a padding value of 1; the first, second, and third convolutional layers have 1, 10, and 32 input channels, respectively, and 10, 32, and 64 output channels, respectively; the pooling layer is a max pooling layer with a kernel size of 2×2 and a stride of 2.

[0066] The source computing power feature vector Fs with dimension (batchsize, 32) is augmented using the unsqueeze method to obtain an extended source computing power feature vector with dimension (batchsize, 1, 1, 52). This extended vector is then input into the first convolutional layer to obtain the output of the first convolutional layer with dimension (batchsize, 10, 1, 52). The output of the first convolutional layer is then input into the second convolutional layer to obtain the output of the second convolutional layer with dimension (batchsize, 32, 1, 52). The output of the second convolutional layer is then input into the third convolutional layer to obtain the output of the third convolutional layer with dimension (batchsize, 64, 1, 52). Finally, the output of the third convolutional layer is input into a pooling layer to obtain the output of the pooling layer with dimension (batchsize, 64, 1, 26).

[0067] In one embodiment, the first decoder includes a first upsampling layer, a second upsampling layer, and a third upsampling layer; all three upsampling layers use bilinear interpolation and the scaling factor is set to 2.

[0068] The output of the pooling layer with dimensions (batchsize, 64, 1, 26) is input into the first upsampling layer, and the spatial dimension is expanded by 2 times through bilinear interpolation to obtain the first upsampled feature map with dimensions (batchsize, 64, 1, 52). The output of the third convolutional layer of the first encoder is concatenated with the first upsampled feature map with dimensions (batchsize, 64, 1, 52) to obtain the first feature map with dimensions (batchsize, 128, 1, 52). The first feature map with dimensions (batchsize, 128, 1, 52) is compressed through convolution to obtain the first compressed feature map with dimensions (batchsize, 64, 1, 26).

[0069] The first compressed feature map with dimensions (batchsize, 64, 1, 26) is input into the second upsampling layer. It is then expanded by a factor of 2 using bilinear interpolation to obtain a second upsampling feature map with dimensions (batchsize, 64, 1, 52). The output of the second convolutional layer of the first encoder is concatenated with the second upsampling feature map with dimensions (batchsize, 64, 1, 52) to obtain a second feature map with dimensions (batchsize, 128, 1, 52). This second feature map with dimensions (batchsize, 128, 1, 52) is then compressed through a convolution operation to obtain a second compressed feature map with dimensions (batchsize, 32, 1, 26).

[0070] The second compressed feature map with dimensions (batchsize, 32, 1, 26) is input to the third upsampling layer. It undergoes bilinear interpolation to double the spatial dimension, resulting in a third upsampling feature map with dimensions (batchsize, 32, 1, 52). The output of the first convolutional layer of the first encoder is then subjected to a 1×1 convolution operation to adjust the number of channels to 32, and concatenated with the third upsampling feature map with dimensions (batchsize, 32, 1, 52) to obtain the third upsampling feature map with dimensions (batchsize, 64, 1, 52). The third feature map, with dimensions (batchsize, 64, 1, 52), is compressed through convolution to obtain an intermediate representation of the target computing power feature with dimensions (batchsize, 32, 1, 26). The intermediate representation of the target computing power feature with dimensions (batchsize, 32, 1, 26) is then compressed from 32 channels to 1 through a 1×1 convolution, retaining a spatial dimension of 1×52. Finally, a flattening operation is performed to obtain the intermediate representation vector of the target computing power feature with dimensions (batchsize, 52).

[0071] Similarly, the target computing power feature vector Ft with dimension (batchsize, 32) is processed by the first encoder and the first decoder to obtain the target platform full-scale feature structured vector with dimension (batchsize, 52).

[0072] The inference network includes a second encoder and a second decoder;

[0073] In one embodiment, the second encoder includes a feature concatenation layer, a first multilayer perceptron, and a second self-attention mechanism layer; the first multilayer perceptron includes a first fully connected layer, a second fully connected layer, and a ReLU activation function; the first fully connected layer has an input dimension of 104 and an output dimension of 32; the second fully connected layer has an input dimension of 32 and an output dimension of 16.

[0074] The source computing power feature vector Fs, the source computing power code feature representation, and the target computing power feature intermediate representation vector are input to the feature concatenation layer and concatenated in the feature dimension to obtain the first concatenated feature with dimension (batchsize, 104). The first concatenated feature is processed by the first multilayer perceptron and the second self-attention mechanism layer to obtain the second encoder output feature with dimension (batchsize, 16).

[0075] In one embodiment, the second decoder includes a second multilayer perceptron and a third self-attention mechanism layer. The second multilayer perceptron includes a third fully connected layer and a fourth fully connected layer. The third fully connected layer has an input dimension of 16 and an output dimension of 32, and the fourth fully connected layer has an input dimension of 32 and an output dimension of 52.

[0076] The output features of the second encoder with dimension (batchsize, 16) are processed by the second decoder to obtain the target computing power code feature representation with dimension (batchsize, 20).

[0077] Similarly, the target platform full-scale feature structured vector, the source computing power code feature representation, and the target computing power feature intermediate representation vector are passed through the inference network to obtain the preliminary target computing power code feature representation with dimension (batchsize, 20).

[0078] This invention extracts intermediate representations through a first encoder-decoder and performs dual-path mapping in the inference network, enabling the conversion of source computing power features and source code features into target code features without manual intervention. The first encoder extracts multi-scale information of hardware features through three layers of two-dimensional convolution and max pooling, while the decoder restores detailed features through bilinear interpolation upsampling and channel concatenation. Finally, it generates an intermediate representation vector of target computing power features and a structured vector of full-scale features of the target platform, ensuring that key information is not lost during feature transfer.

[0079] S4. To address the shortcomings of existing technologies, such as the lack of hardware-aware constraints and the possibility that generated features may not align with the characteristics of the target platform, this step constructs a computing power guidance model. This model includes an input layer, a third multilayer perceptron, a fourth self-attention mechanism layer, and an output adjustment layer. The target computing power feature vector Ft, the target computing power code feature representation, and the preliminary target computing power code feature representation are processed by the computing power guidance model to generate adjusted feature representations. By designing a computing power guidance model that includes a multilayer perceptron, a fourth self-attention mechanism layer, and an output adjustment layer, and especially by introducing a platform characteristic matrix P in the output adjustment layer, the model explicitly maps the target computing power features to the code structure attributes, thereby enabling targeted adjustments to the generated features. The advantage of this design is that the model can dynamically optimize the generated features based on platform characteristics, ensuring that the final code better meets the computing power, bandwidth, and parallelism requirements of the target platform.

[0080] In one embodiment, the third multilayer perceptron includes a fifth fully connected layer, a sixth fully connected layer, and a seventh fully connected layer; the fifth fully connected layer has an input dimension of 72 and an output dimension of 40; the sixth fully connected layer has an input dimension of 40 and an output dimension of 30; the seventh fully connected layer has an input dimension of 30 and an output dimension of 20; all fully connected layers use the ReLU activation function to introduce nonlinearity; the fourth self-attention mechanism layer introduces a learnable bias term to enhance feature processing capabilities;

[0081] The target computing power feature vector Ft with dimension (batchsize, 32), the target computing power code feature representation with dimension (batchsize, 20), and the preliminary target computing power code feature representation with dimension (batchsize, 20) are concatenated in the input layer to obtain the second concatenated feature with dimension (batchsize, 72). The second concatenated feature is processed by the third multilayer perceptron and the fourth self-attention mechanism layer to obtain the self-attention output feature with dimension (batchsize, 20).

[0082] The output adjustment layer introduces an adjustment formula based on platform characteristics. ,in, This represents the adjusted feature representation. Let P represent the self-attention output features, and let P represent the platform characteristic matrix of dimension (20, 20). The row dimensions of the platform characteristic matrix correspond to the key hardware characteristic parameters of the target platform (such as computational density, memory bandwidth, thread parallelism, etc.), and the column dimensions correspond to the key attributes of the code structure (such as loop nesting depth, memory access pattern, vectorization operation frequency, etc.). The expression for the platform characteristic matrix is: Each element This represents the contribution weight of the j-th self-attention output feature to the i-th adjusted feature representation. The process of obtaining the contribution weight is as follows: Based on the hardware parameters of the target computing platform and experimental experience, an initial value of P is manually preset to make the feature weights related to the key characteristics of the platform higher. In the unified programming model, the key characteristics of the platform refer to the target hardware parameters that directly affect the code execution efficiency, including computing density, memory bandwidth, cache hierarchy, number of parallel units, instruction set characteristics, thread scheduling overhead, branch prediction efficiency, memory access energy consumption ratio, etc. These characteristics are explicitly modeled through the platform characteristic matrix P. Initially, the weights are preset based on hardware parameters and experience. Based on the hardware parameters and experience, the initial weights of the platform characteristic matrix P are preset. Combined with the core hardware characteristics of the target computing platform and code optimization experience, the weights are allocated in a targeted manner. The initial weight allocation process of the platform characteristic matrix P includes the following three steps:

[0083] The first step is to assign weights based on the importance of hardware characteristics. Based on the core hardware parameters of the target computing platform (such as GPU's computational density, memory bandwidth, and communication efficiency; FPGA's pipeline depth, memory access mode, and logic unit utilization; CPU's cache hierarchy, number of parallel units, and instruction set characteristics), assign relatively high initial weights to relevant features. For example, on a GPU platform, the computational density weight can be preset to 0.4, memory bandwidth to 0.3, communication efficiency to 0.2, and other features to 0.1; on an FPGA platform, the pipeline depth weight can be preset to 0.4, memory access mode to 0.3, logic unit utilization to 0.2, and other features to 0.1. This ensures that the platform's key characteristics dominate the matrix.

[0084] The second step is to adjust the weights based on the correlation between code features and hardware. Building upon the initial allocation, the weights are adjusted specifically based on the strength of the correlation between code features (such as data partitioning strategies, loop unrolling methods, and instruction pipelining design) and hardware characteristics. If the performance bottleneck of the target platform is the GPU's global memory bandwidth, the corresponding weights of the data partitioning strategy code features and memory bandwidth hardware characteristics are increased; if the performance bottleneck is the FPGA's pipeline latency, the corresponding weights of the instruction pipelining design code features and pipeline depth hardware characteristics are increased, thereby strengthening key mapping relationships and achieving efficient matching between code and hardware.

[0085] The third step is to determine the initial form of the matrix. Organize the above allocation and adjustment results into a diagonal or sparse matrix to highlight the weights of core features, while setting the weights of irrelevant features to 0 or a very small value (such as 0.01) to avoid them interfering with model training. This ensures both the simplicity of the matrix structure and the importance of the core features.

[0086] S5. Addressing the issues of uncontrollable end-to-end code generation and low efficiency based on manual templates in existing cross-platform solutions, this step generates efficient code that conforms to the characteristics of the target platform based on adjusted feature representations and a predefined target platform code template library. By dynamically binding feature vectors to template parameters, efficient and controllable code generation is achieved. This design not only ensures the structural stability and readability of the generated code but also fully utilizes the aforementioned feature alignment and guidance mechanisms to improve the execution performance of the generated code on the target platform.

[0087] In this step, the adjusted feature representation output in step S4 is not directly converted into source code, but rather acts as a parameter driver on a predefined target platform code template library. This predefined target platform code template library includes pre-defined optimization frameworks and dynamically populated interfaces for different hardware architectures, including: CUDA kernel function structures and thread parameter interfaces in the GPU template for adjusting thread parallelism and memory sharing; HLS pipeline and memory block instruction interfaces in the FPGA template for optimizing data locality and pipeline depth; and OpenMP multithreading and vectorization switch interfaces in the CPU template for adapting to multi-core architectures.

[0088] The adjusted feature representation carries hardware adaptation parameters (such as computational density, memory access mode, and thread parallelism) and code structure features (such as loop nesting depth and data partitioning strategy), and is mapped to template parameters through feature-code mapping dictionary and parameter binding mechanism: continuous value features are directly scaled to template parameter values.

[0089] In one embodiment, continuous-value hardware adaptation parameters in the adjusted feature representation are converted into specific parameter values ​​in the target platform code template library according to a preset scaling rule. For example, a normalized computation density value of 0.8 corresponds to a thread block size of (64, 64) on a GPU platform, and a normalized computation density value of 0.6 corresponds to pipeline II=2 on an FPGA platform. If the feature contains discrete-value features such as memory access patterns and takes the value of "order priority", the corresponding conditional branch of the target platform template will be triggered, and the FPGA platform will automatically insert #pragma HLS. The ARRAY_PARTITION instruction automatically inserts CUDA shared memory related statements into the GPU platform. If a combination of high computational density and high bandwidth exists simultaneously, the complex parameter setting logic of the template will be activated. For example, if the GPU platform detects a normalized value of 0.9 for computational density and 0.8 for bandwidth, the thread block size will be increased from (32,32) to (128,128) and the shared memory buffer will be enabled. During this process, the platform characteristic matrix P, which is jointly optimized by computational power loss, resource utilization loss, and performance loss, will strengthen the weights of key features. The FPGA platform strengthens "pipeline depth" (weight 0.4) and "memory access mode" (weight 0.3), while the GPU platform strengthens "thread parallelism" and "memory bandwidth" (both weights 0.35) to ensure that the parameters are adapted to the hardware advantages. Finally, the adjusted feature representation is precisely bound to the template parameter interface, and the template framework generates adaptation code by combining the mapping parameters. If adaptation to a new platform is required, the target computational power dataset Dt in step S1 is replaced, and the process of S1-S5 is repeated to automatically generate the new platform optimization code.

[0090] During training, the platform feature matrix P is optimized through a loss function, gradually strengthening features that highly match the key characteristics of the target platform, making the template filling parameters more aligned with hardware advantages. For example, in an FPGA platform, matrix P enhances the weights of "pipeline depth" and "memory access mode," and the generated code automatically inserts #pragma HLS PIPELINE II=1 and #pragma HLS ARRAY_PARTITION instructions; in a GPU platform, it strengthens thread parallelism and memory bandwidth features, corresponding to the generation of dim3 blockDim(32,32) and shared memory buffer instructions.

[0091] Through the above mechanism, the adjusted feature representation is precisely bound to the template library parameter interface, realizing a controllable transformation from features to code. Its advantages are: the framework for generating code is guaranteed by the template, avoiding the generation of unreadable code through an end-to-end black box; parameters are dynamically driven by the feature representation, ensuring that the hardware advantages of different platforms, such as computing power, bandwidth, and parallelism, are fully utilized; and by simply replacing the target platform dataset Dt and repeating the S1–S5 process, optimized code for the new platform can be automatically generated, achieving "one-time modeling, efficient adaptation to multiple platforms."

[0092] During model training, computational cost loss, resource utilization loss, and performance loss are used for training optimization:

[0093] The formula for the computing power loss is as follows:

[0094] ,

[0095] in, Indicates computing power loss; Indicates resource consumption; Indicates maximum efficiency; i represents the index of the resource type being calculated; the formula for the resource usage loss is as follows:

[0096] ,

[0097] in, R represents the resource usage loss; R represents the number of resource types; r represents the resource type index; This represents the actual memory usage of the r-th type of resource; This represents the maximum memory capacity of the r-th type of resource; This represents the actual amount of computational resources allocated to the r-th type of resource; Let r represent the maximum computing power of the r-th type of resource; the formula for the performance loss is as follows:

[0098] ,

[0099] in, Indicates performance loss; Indicates the expected throughput; Indicates actual throughput;

[0100] Example 2

[0101] In this embodiment, as Figure 2 As shown, the horizontal axis represents the hardware platform type, covering three mainstream multi-functional computing devices: CPU, GPU, and FPGA, corresponding to the multi-functional computing scenarios targeted by this invention. The left vertical axis represents code execution throughput, and the right vertical axis represents execution latency. The figure contains three sets of key comparative data, corresponding to the method of this invention, manual code porting, and traditional middleware solutions, respectively. It can be seen that on the GPU platform, the throughput of the code generated by this invention can reach 42GB / s, an improvement of 31.25% compared to manual porting and 40% compared to the middleware solution. This invention deeply mines the nonlinear correlation between core hardware parameters and code structure through a computing power feature encoder, and dynamically optimizes the feature representation by combining the platform characteristic matrix P in the computing power guidance model. Finally, it calls the GPU template library to generate adapted CUDA kernel functions and thread / block parameters, fully releasing the parallel computing capabilities of the GPU. In contrast, manual porting is limited by the engineer's mastery of hardware details, making it difficult to fully optimize parallelism and memory strategies. Middleware solutions suffer performance losses due to data conversion and instruction forwarding overhead caused by additional interface layers. This invention can improve the code execution efficiency of the target platform.

[0102] Example 3

[0103] In this embodiment, a heatmap is used to illustrate the migration process from source computing power features to target computing power features, such as... Figure 3 As shown, color depth represents feature similarity. The horizontal axis represents the source feature dimension, and the vertical axis represents the target feature dimension. The figure demonstrates the effectiveness of this invention in semantic preservation and feature alignment. The first encoder-decoder of this invention's unified programming model extracts intermediate representations through a U-Net structure, ensuring lossless semantic mapping from the source platform to the target platform. This invention achieves a similarity of over 0.8 in key dimensions, proving that the feature concatenation layer and multilayer perceptron in the inference network of this invention can fuse source computing power code features, achieving effective feature transfer. This invention achieves cross-platform transfer through deep feature modeling and dynamic adjustment, ensuring that the generated code retains the source semantics while adapting to the target hardware.

[0104] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A unified programming method based on multi-dimensional computing power, characterized in that, Includes the following steps: Step 1: Obtain source computing power data, target computing power data, and source computing power code, and preprocess the data to obtain the source computing power dataset Ds and the target computing power dataset Dt; Step 2: Construct a computing power feature encoder model; The data in the source computing power dataset and the target computing power dataset are processed by the computing power feature encoder model to obtain the source computing power feature vector Fs and the target computing power feature vector Ft; the source computing power code is processed by the computing power feature encoder model to obtain the source computing power code feature representation. Step 3: Construct a unified programming model, which includes a first encoder, a first decoder, and an inference network; the source computing power feature vector Fs, the target computing power feature vector Ft, and the source computing power code feature representation are input into the unified programming model to obtain a preliminary target computing power code feature representation; Step 4: Construct a computing power guidance model; The target computing power feature vector Ft, the target computing power code feature representation, and the preliminary target computing power code feature representation are processed by the computing power guidance model to generate an adjusted feature representation; Step 5: Input the adjusted feature representation into the predefined target platform code template library to generate efficient code that conforms to the characteristics of the target platform.

2. The unified programming method based on multi-dimensional computing power according to claim 1, characterized in that, The specific process of obtaining the source computing power dataset Ds and the target computing power dataset Dt is as follows: The device type, computing power, memory capacity, memory bandwidth, communication bandwidth, power consumption, and latency of the source and target computing power devices are collected; the ratio of computing power to power consumption is used to obtain the computing density. Calculate the ratio of sequential accesses to random accesses to the memory accesses of each device to obtain the memory access pattern; The communication efficiency is obtained by calculating the ratio of communication bandwidth to computing power. The collected data on device type, computing power, memory capacity, memory bandwidth, communication bandwidth, power consumption, latency, computing density, memory access mode, and communication efficiency are merged to obtain data for each device; thus, the source computing power dataset Ds and the target computing power dataset Dt are obtained; the data in the source computing power dataset Ds and the target computing power dataset Dt are converted into PyTorch tensors.

3. The unified programming method based on multi-dimensional computing power according to claim 2, characterized in that, The computing power feature encoder model includes an input layer, a hidden layer, and a feature extraction layer; specifically, it includes: The hidden layer comprises a first hidden layer, a second hidden layer, a third hidden layer, and a Dropout layer connected in series; the feature extraction layer comprises a first self-attention mechanism layer and a feature fusion layer; the first self-attention mechanism layer adopts a multi-head attention mechanism; all hidden layers are fully connected layers; The input layer receives the PyTorch tensor transformed from the source computing power dataset Ds and inputs it into the hidden layer to obtain the outputs of the first hidden layer, the second hidden layer, and the third hidden layer. The output of the third hidden layer passes through the first self-attention mechanism layer to obtain the output of the self-attention mechanism layer. In the feature fusion layer, the outputs of the first hidden layer, the second hidden layer, and the first self-attention mechanism layer are concatenated along the channel dimension to obtain the concatenated features. The concatenated features are then convolved to obtain the source computing power feature vector Fs. Similarly, after the target computing power dataset Dt is converted into a PyTorch tensor, it passes through the input layer, hidden layer, and feature extraction layer to obtain the target computing power feature vector Ft; The source computing power code is processed by the computing power feature encoder model to obtain the source computing power code feature representation.

4. The unified programming method based on multi-dimensional computing power according to claim 3, characterized in that, The first encoder includes a first convolutional layer, a second convolutional layer, a third convolutional layer, and a pooling layer; all three convolutional layers are two-dimensional convolutions, and the pooling layer is a max pooling layer; the first decoder includes a first upsampling layer, a second upsampling layer, and a third upsampling layer; the processing procedures of the first encoder and the first decoder are as follows: The source computing power feature vector Fs is augmented with dimension using the unsqueeze method to obtain the source computing power feature extension vector. The source computing power feature extension vector is then input into the first convolutional layer to obtain the output of the first convolutional layer. The output of the first convolutional layer is then input into the second convolutional layer to obtain the output of the second convolutional layer. The output of the second convolutional layer is then input into the third convolutional layer to obtain the output of the third convolutional layer. The output of the third convolutional layer is then input into the pooling layer to obtain the output of the pooling layer. The output of the pooling layer is input to the first upsampling layer, and the spatial dimension is expanded by a factor of 2 through bilinear interpolation to obtain the first upsampling feature map. The output of the third convolutional layer of the first encoder is concatenated with the first upsampling feature map through channels to obtain the first feature map. The first feature map is compressed through a convolution operation to obtain the first compressed feature map. The first compressed feature map is input to the second upsampling layer, and the spatial dimension is expanded by a factor of 2 through bilinear interpolation to obtain the second upsampling feature map. The output of the second convolutional layer of the first encoder is concatenated with the second upsampling feature map through channels to obtain the second feature map. The second feature map is compressed through convolution to obtain a second compressed feature map. The second compressed feature map is input into the third upsampling layer and expanded by a factor of 2 through bilinear interpolation to obtain a third upsampling feature map. The output of the first convolutional layer of the first encoder is convolved with the third upsampling feature map after adjusting the number of channels through convolution to obtain a third feature map. The third feature map is compressed through convolution to obtain an intermediate representation of the target computing power feature. The intermediate representation of the target computing power feature is then flattened through convolution to obtain the intermediate representation vector of the target computing power feature. Similarly, the target computing power feature vector Ft is processed by the first encoder and the first decoder to obtain the full-scale feature structured vector of the target platform.

5. The unified programming method based on multi-dimensional computing power according to claim 4, characterized in that, The inference network includes a second encoder and a second decoder; the second encoder includes a feature concatenation layer, a first multilayer perceptron, and a second self-attention mechanism layer; the first multilayer perceptron includes a first fully connected layer, a second fully connected layer, and a ReLU activation function; the second decoder includes a second multilayer perceptron and a third self-attention mechanism layer, the second multilayer perceptron including a third fully connected layer and a fourth fully connected layer; the processing procedure in the inference network is as follows: The source computing power feature vector Fs, the source computing power code feature representation, and the target computing power feature intermediate representation vector are concatenated in the feature concatenation layer along the feature dimension to obtain the first concatenated feature. The first concatenated feature is processed by the first multilayer perceptron and the second self-attention mechanism layer to obtain the second encoder output feature. The output features of the second encoder are processed by the second decoder to obtain the target computing power code feature representation; Similarly, the target platform full-scale feature structured vector, the source computing power code feature representation, and the target computing power feature intermediate representation vector are passed through the inference network to obtain the preliminary target computing power code feature representation.

6. The unified programming method based on multi-dimensional computing power according to claim 5, characterized in that, The computational power-guided model includes an input layer, a third multilayer perceptron, a fourth self-attention mechanism layer, and an output adjustment layer; the third multilayer perceptron includes a fifth fully connected layer, a sixth fully connected layer, and a seventh fully connected layer; all fully connected layers use the ReLU activation function to introduce nonlinearity; the fourth self-attention mechanism layer introduces a learnable bias term to enhance feature processing capabilities; the processing procedure in the computational power-guided model is as follows: The target computing power feature vector Ft, the target computing power code feature representation, and the preliminary target computing power code feature representation are concatenated along the feature dimension by the input layer to obtain the second concatenated feature; The spliced ​​features are processed through the third multilayer perceptron and the fourth self-attention mechanism layer to obtain the self-attention output features; The output adjustment layer introduces an adjustment formula based on platform characteristics. ,in, This represents the adjusted feature representation. Let P represent the self-attention output feature, and let P represent the platform characteristic matrix.

7. The unified programming method based on multi-dimensional computing power according to claim 6, characterized in that, The predefined target platform code template library provides pre-optimized frameworks and dynamically populated interfaces for different hardware architectures, including: CUDA kernel function structures and thread parameter interfaces in the GPU template; HLS pipeline and memory partitioning instruction interfaces in the FPGA template; and OpenMP multithreading and vectorization switch interfaces in the CPU template.

8. The unified programming method based on multi-dimensional computing power according to claim 7, characterized in that, During model training, computational cost loss, resource utilization loss, and performance loss are used to train the model: The formula for the computing power loss is as follows: ， in, Indicates computing power loss; Indicates resource consumption; Indicates maximum efficiency; i represents the index of the resource type being calculated; the formula for the resource usage loss is as follows: ， in, R represents the resource usage loss; R represents the number of resource types; r represents the resource type index; This represents the actual memory usage of the r-th type of resource; This represents the maximum memory capacity of the r-th type of resource; This represents the actual amount of computational resources allocated to the r-th type of resource; Let r represent the maximum computing power of the r-th type of resource; the formula for the performance loss is as follows: ， in, Indicates performance loss; Indicates the expected throughput; This represents the actual throughput.

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