Data transmission method, receiving unit, chip, readable medium and program product

Abstract

The invention provides a data transmission method, a receiving unit, a chip, a computer readable medium and a computer program product, belongs to the technical field of cross-die data transmission, and can solve the problem of large time delay of existing cross-die data transmission. The data transmission method is used for a receiving unit, the receiving unit and a sending unit are packaged in the same chip and connected through a bare chip connection, the receiving unit receives a data signal from the sending unit through RX FIFO, and a local clock of the sending unit and a local clock of the receiving unit are generated according to the same reference clock. A read clock of the RX FIFO is a local clock of the receiving unit, a write clock of the RX FIFO is a feed-forward clock generated according to the local clock of the sending unit, and a read cycle of the RX FIFO is greater than a write cycle; the method comprises the steps of determining an adjusted write pointer at least according to a read clock and a write clock of the RX FIFO, and determining read enable of the RX FIFO according to the adjusted write pointer.

Description

Technical Field

[0001] This disclosure relates to the field of cross-die data transmission technology, and in particular to a data transmission method, receiving unit, transmitting unit, chip, computer-readable medium, and computer program product. Background Technology

[0002] The data transmission method between different dies within a chip has a relatively large delay. Summary of the Invention

[0003] This disclosure provides a data transmission method, a receiving unit, a transmitting unit, a chip, a computer-readable medium, and a computer program product.

[0004] In a first aspect, embodiments of this disclosure provide a data transmission method for a receiving unit. The receiving unit and a transmitting unit are packaged in the same chip and connected via a bare die interconnect. The receiving unit receives data signals from the transmitting unit through a receiver-side first-in-first-out (FIFO) buffer (RX FIFO). The local clock of the transmitting unit and the local clock of the receiving unit are generated based on the same reference clock. The read clock of the RX FIFO is the local clock of the receiving unit, and the write clock is a feedforward clock generated based on the local clock of the transmitting unit. The read cycle of the RX FIFO is greater than the write cycle. The method includes:

[0005] The adjusted write pointer is determined based at least on the read clock and write clock of the RX FIFO, and the read enable of the RX FIFO is determined based on the adjusted write pointer.

[0006] In some embodiments, determining the adjusted write pointer based at least on the read clock and write clock of the RX FIFO, and determining the read enable of the RX FIFO based on the adjusted write pointer, includes:

[0007] Detect the offset between the write clock and read clock of the RX FIFO;

[0008] A sampling write pointer signal is generated based on the offset and the write clock of the RX FIFO;

[0009] At the sampling edge of the read clock of the RX FIFO, the sampling write pointer signal is sampled, and the read enable of the RX FIFO is determined based on the sampling result.

[0010] In some embodiments, the sampling edge of the read clock of the RX FIFO is located in a preset central interval of the write pointer range of the sampled write pointer signal.

[0011] In some embodiments, generating a sampling write pointer signal based on the offset and the write clock of the RX FIFO includes:

[0012] Based on the offset, a sampled write pointer signal is generated that is delayed relative to the write pointer of the RX FIFO; wherein the delay of the sampled write pointer signal relative to the write pointer of the RX FIFO is nt / 2, t is the write cycle of the RX FIFO, and n is an integer greater than or equal to 0 and less than a multiple of 2 cycles, wherein the multiple of cycles is the ratio of the read cycle to the write cycle of the RX FIFO.

[0013] In some embodiments, the method of this disclosure further includes:

[0014] In response to the RX FIFO reset, the write pointer of the RX FIFO is set to the maximum position, and the read pointer of the RX FIFO is set to the minimum position;

[0015] The step of determining the adjusted write pointer based at least on the read clock and write clock of the RX FIFO, and determining the read enable of the RX FIFO based on the adjusted write pointer, includes: generating a local high-frequency clock; synchronizing the write pointer of the RX FIFO to the read clock domain of the RX FIFO by timing the local high-frequency clock; sampling the synchronized write pointer of the RX FIFO on the sampling edge of the read clock of the RX FIFO, and determining the read enable of the RX FIFO based on the sampling result; wherein, the period of the local high-frequency clock is equal to the write period of the RX FIFO, the total period of the timing high-frequency clock is less than twice the read period of the RX FIFO, and the write pointer of the RX FIFO is in Gray code form.

[0016] In some embodiments, the cycle multiple is 4, where the cycle multiple is the ratio of the read cycle to the write cycle of the RX FIFO;

[0017] The total cycle of the high-frequency clock that beats the clock is 4 to 6 cycles.

[0018] In some embodiments, the method of this disclosure further includes:

[0019] In response to the RX FIFO reset, the write pointer of the RX FIFO is set to the maximum position, and the read pointer of the RX FIFO is set to the minimum position.

[0020] In some embodiments, the method of this disclosure further includes:

[0021] When there is no data signal to be received, the feedforward clock cannot be received from the transmitting unit;

[0022] When the time during which the feedforward clock is not received reaches a preset time threshold, the feedforward clock is received from the transmitting unit, and the write pointer of the RX FIFO is adjusted at least according to the read clock of the RX FIFO.

[0023] In some embodiments, the method of this disclosure further includes:

[0024] In response to the data volume stored in the RX FIFO reaching a preset data volume threshold, a near-full signal is sent to the transmitting unit; the data volume threshold is less than the maximum capacity of the RX FIFO, and the near-full signal is used to control the transmitting unit to pause the transmission of the data signal.

[0025] In some embodiments, the method of this disclosure further includes:

[0026] In response to the number of write cycles of the RX FIFO continuously receiving the data signal reaching a predetermined number of cycles threshold, a near-full signal is sent to the transmitting unit; the near-full signal is used to control the transmitting unit to pause the transmission of the data signal.

[0027] In some embodiments, the receiving unit receives multiple data signals from the transmitting unit through multiple RX FIFOs, wherein one of the RX FIFOs is a target RX FIFO;

[0028] The step of determining the adjusted write pointer based at least on the read clock and write clock of the RX FIFO, and determining the read enable of the RX FIFO based on the adjusted write pointer, includes: determining the adjusted write pointer based at least on the read clock and write clock of the target RX FIFO, and determining the read enable of all the RX FIFOs based on the adjusted write pointer.

[0029] Secondly, embodiments of this disclosure provide a receiving unit, including an RX FIFO, a memory, and a processor; the memory stores a computer program executable by the processor, and when the computer program is executed by the processor, it implements any of the data transmission methods of embodiments of this disclosure.

[0030] Thirdly, embodiments of this disclosure provide a chip, comprising:

[0031] Reference clock;

[0032] Transmitting unit;

[0033] Any receiving unit that implements the embodiments of this disclosure.

[0034] Fourthly, embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the data transmission methods of embodiments of this disclosure.

[0035] Fifthly, embodiments of this disclosure provide a computer program product, including a computer program, which, when executed by a processor, implements any of the data transmission methods of embodiments of this disclosure.

[0036] In this embodiment of the present disclosure, the receiving unit can generate an adjusted write pointer based on the read clock of the locally generated RX FIFO and the write clock of the RX FIFO generated by the transmitting unit, and determine the read enable of the RX FIFO based on the adjusted write pointer, thereby shortening the read and write distance and greatly reducing the latency of cross-die data transmission. Attached Figure Description

[0037] In the accompanying drawings of the embodiments disclosed herein:

[0038] Figure 1 This is a block diagram of a chip in related technologies;

[0039] Figure 2 A flowchart illustrating a data transmission method provided in an embodiment of this disclosure;

[0040] Figure 3 A flowchart illustrating another data transmission method provided in this embodiment of the disclosure;

[0041] Figure 4 A flowchart illustrating another data transmission method provided in this embodiment of the disclosure;

[0042] Figure 5 A block diagram of a receiving unit provided in an embodiment of this disclosure;

[0043] Figure 6 A block diagram of a chip provided in an embodiment of this disclosure;

[0044] Figure 7 A block diagram illustrating the composition of a computer-readable medium provided in accordance with embodiments of this disclosure;

[0045] Figure 8 A schematic diagram illustrating the sampling of the write pointer signal under different conditions in another data transmission method provided in this embodiment of the present disclosure;

[0046] Figure 9 Timing diagram for case 2 of another data transmission method provided in this embodiment of the disclosure;

[0047] Figure 10A timing diagram of another data transmission method provided in an embodiment of this disclosure;

[0048] Figure 11 This is a timing diagram of a data transmission method in related technologies;

[0049] Figure 12 Timing diagram of reading clock fast in another data transmission method provided in this disclosure embodiment;

[0050] Figure 13 Timing diagram for a slow read clock in another data transmission method provided in this embodiment of the present disclosure;

[0051] Figure 14 A system architecture diagram of the data transmission method of Example 1 provided in this disclosure embodiment;

[0052] Figure 15 This is a schematic diagram of the structure of the DES in Example 1 provided in the embodiments of this disclosure;

[0053] Figure 16 A partial detailed structural diagram of the receiving unit in Example 1 provided in this embodiment of the present disclosure;

[0054] Figure 17 for Figure 16 A schematic diagram of the structure of a phase detector;

[0055] Figure 18 A system architecture diagram of the data transmission method provided in Example 2 of this disclosure;

[0056] Figure 19 A partial detailed structural diagram of the receiving unit in Example 2 provided in this embodiment of the present disclosure. Detailed Implementation

[0057] To enable those skilled in the art to better understand the technical solutions of this disclosure, the data transmission method, receiving unit, sending unit, chip, computer-readable medium, and computer program product provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0058] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0059] The accompanying drawings are provided to further illustrate this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. These and other features and advantages will become more apparent to those skilled in the art from the description of detailed embodiments with reference to the accompanying drawings.

[0060] Unless otherwise specified, each embodiment and feature of this disclosure may be used individually or in combination with other embodiments and features thereof.

[0061] Those skilled in the art will understand that various changes in form and detail may be made to the embodiments of this disclosure without departing from the scope of this disclosure as set forth by the appended claims.

[0062] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0063] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0064] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0065] A chip is an independent computing device that includes packaged integrated circuits, such as a central processing unit (CPU) or a general-purpose graphics processing unit (GP-GPU).

[0066] As the size of circuit structures in chips continues to shrink, approaching the quantum tunneling limit, further miniaturization becomes extremely difficult from both a technological and cost perspective. Therefore, building large systems from interconnected smaller systems becomes more economical. For this purpose, chiplet technology can be employed, i.e., referring to... Figure 1 Partial integrated circuits are formed on multiple unpackaged dies. Each die can perform some computational functions relatively independently, and die-to-die connections are set between the dies to achieve cross-die data transmission. The multiple dies and their inter-die connections are then packaged into a chip.

[0067] In some related technologies, refer to Figure 1 To enable cross-die data transmission, a first-in-first-out (FIFO) buffer can be set in both the transmitting (TX) die and the receiving (RX) die. The data to be transmitted is first written to the TX FIFO by the TX die, then read from the TX FIFO, and written to the RX FIFO via the die-to-die connection. Finally, it is read from the RX FIFO and processed by the RX die.

[0068] In some related technologies, multiple bare dies can use a "same-source clock," that is, referenced to... Figure 1 Multiple bare dies generate their own local clocks (LCLK) based on the same reference clock (ref) to control various local operations. However, due to uneven circuit layout, process technology, temperature, aging, etc., there is still a certain difference between the local clocks of different bare dies, i.e., drift, and this drift may fluctuate within a certain range as the chip is used.

[0069] Based on the above-mentioned technologies, the data writing of the RX FIFO is essentially controlled by the local clock of the TX die, and the data reading is controlled by the local clock of the RX die. Therefore, there is a drift between the local clocks of the TX die and the RX die, which is equivalent to the read clock and write clock of the RX FIFO being out of sync. Hence, the RX FIFO is an "asynchronous FIFO".

[0070] In some related technologies, to ensure that the local clock of each bare die will not cause data errors regardless of left or right drift throughout the entire life cycle of the chip, the drift buffer technology can be used. That is, after the read enable of the RX FIFO is enabled, it will pause for 2-3 clock cycles to synchronize with the read clock domain, and then pause for another 1-2 clock cycles to convert to Gray code before reading begins; the specific number of clock cycles is determined according to the maximum possible drift range of the clock.

[0071] Therefore, the RX FIFO has a relatively large "read / write distance," which necessitates a large RX FIFO depth to store data during synchronization. Its depth is typically at least 4. Furthermore, the large read / write distance significantly increases the latency of cross-die data transmission. For example, when the local clock is 2GHz, or 500ps per clock cycle, the latency of data transmission within the die is typically 2 clock cycles and 1ns. The RX FIFO's read / write distance is usually 2-4 clock cycles. Adding transmission latency, the latency of cross-die data transmission typically exceeds 10ns, failing to meet the 2ns latency requirement of the Universal Chipplet Interconnect Express (UCIe) protocol.

[0072] Firstly, referring to Figures 2 to 13 This disclosure provides a data transmission method for a receiving unit. The receiving unit and the transmitting unit are packaged in the same chip and connected by a bare die interconnect. The receiving unit receives data signals from the transmitting unit through a receiving-side first-in-first-out buffer (RX FIFO). The local clock of the transmitting unit and the local clock of the receiving unit are generated based on the same reference clock. The read clock of the RX FIFO is the local clock of the receiving unit, and the write clock is a feedforward clock generated based on the local clock of the transmitting unit. The read cycle of the RX FIFO is greater than the write cycle.

[0073] Reference Figure 6 The method of this disclosure is used for a receiving unit, which is packaged together with a transmitting unit within a chip. The receiving unit includes an RX FIFO, which is connected to the transmitting unit via a die-to-die connection, so that the transmitting unit can transmit data signals to the receiving unit via the die-to-die connection and the RX FIFO.

[0074] Reference Figure 6 The receiving unit and the transmitting unit are also connected to the same reference clock (ref), and generate their respective local clocks according to the reference clock.

[0075] For the receiving unit, it generates the read clock of the RX FIFO based on the local clock, while the write clock of the RX FIFO is the feedforward clock (FWD CLK) from the transmitting unit, which is essentially generated based on the local clock of the transmitting unit.

[0076] The local clocks of the transmitting unit and the receiving unit are both generated based on the same reference clock, and their frequencies can be the same, such as 2GHz. The write clock of the RX FIFO, which is the feedforward clock, can be higher than the local clock frequency, such as 8GHz, so that the read cycle of the RX FIFO is longer than the write cycle.

[0077] For example, as one embodiment of this disclosure, refer to Figure 6 The transmitting unit may also be equipped with a receiver-side first-in-first-out buffer TX FIFO, and the data signal is transmitted to the RX FIFO through the TX FIFO. Therefore, the write clock and feedforward clock of the RX FIFO are specifically generated based on the read clock of the RX FIFO, and the read clock of the RX FIFO is generated based on the local clock of the transmitting circle.

[0078] It should be understood that the transmitting unit may not have a TX FIFO. If the data signal is sent to the RX FIFO through a register (reg) or other means, it is sufficient as long as the transmitting unit can both send the data signal and provide the write clock for the RX FIFO.

[0079] The receiving unit can be an RX bare crystal or a module within an RX bare crystal used for cross-die data transmission; the transmitting unit can be a TX bare crystal or a module within a TX bare crystal used for cross-die data transmission.

[0080] It should be understood that the TX and RX bare crystals mentioned above are determined by the direction of data transmission; however, the same bare crystal may both send data to other bare crystals and receive data from other bare crystals. Therefore, the bare crystal can be both a TX bare crystal and an RX bare crystal, and it can include both a transmitting unit and a receiving unit.

[0081] Reference Figure 2 The data transmission method of this disclosure includes:

[0082] S101. Determine the adjusted write pointer based at least on the read clock and write clock of the RX FIFO, and determine the read enable of the RX FIFO based on the adjusted write pointer.

[0083] In this embodiment of the present disclosure, the receiving unit can generate an adjusted write pointer based on the read clock of the locally generated RX FIFO and the write clock of the RX FIFO generated by the transmitting unit, and determine the read enable of the RX FIFO based on the adjusted write pointer, thereby shortening the read and write distance and greatly reducing the latency of cross-die data transmission.

[0084] It should be understood that in this embodiment of the disclosure, it is only required that the read enable of the RX FIFO be generated according to the adjusted write pointer, but it is not required that the write operation of the RX FIFO be performed according to the adjusted write pointer. That is, the RX FIFO can still write data according to its original write clock and write pointer.

[0085] It should be understood that, since the adjusted write pointer is sampled according to the read clock of the RX FIFO, the period of the adjusted write pointer should be the same as the read clock period of the RX FIFO, but larger than the actual write clock or write pointer period of the RX FIFO.

[0086] Furthermore, the number of cycles for the adjusted write pointer should also be the same as the number of cycles for the read clock, which is equal to the depth of the RX FIFO.

[0087] It should be understood that, in order to distinguish different write pointers over a wider range, the label of the adjusted write pointer can be greater than its cycle number. For example, when the depth of the RX FIFO is 4, the adjusted write pointer should be between 0 and 3, but its label can be between 0 and 7. Here, labels 0 and 4 correspond to writing to the first row of the RX FIFO, labels 1 and 5 correspond to writing to the second row of the RX FIFO, labels 2 and 6 correspond to writing to the third row of the RX FIFO, and labels 3 and 7 correspond to writing to the fourth row of the RX FIFO.

[0088] In some embodiments, refer to Figure 3 Based at least on the read clock and write clock of the RX FIFO, the adjusted write pointer is determined, and the read enable of the RX FIFO is determined based on the adjusted write pointer (S101), including:

[0089] S101A1, detects the offset between the write clock and read clock of the RX FIFO.

[0090] S101A2 generates a sampling write pointer signal based on the offset and the write clock of the RX FIFO.

[0091] S101A3: At the sampling edge of the read clock of the RX FIFO, the sampling write pointer signal is sampled, and the read enable of the RX FIFO is determined based on the sampling result.

[0092] Reading and writing operations on a row of the RX FIFO too close together, or reading a row before writing it, will lead to data errors.

[0093] Therefore, refer to Figure 3As one embodiment of this disclosure, the receiving unit may first use a phase detector (PD) or similar device to compare the write clock and read clock of the RX FIFO to obtain the actual difference between the two, which is the "offset".

[0094] For example, since the write clock of the RX FIFO, which is also the feedforward clock, has a higher frequency than the read clock, the feedforward clock can be divided to be converted to the same frequency as the read clock of the RX FIFO, and then compared with the read clock of the RX FIFO in the phase detector to obtain the offset.

[0095] Furthermore, the receiving unit can also generate a "sampling write pointer signal" based on the above offset and the original write clock of the RX FIFO. This sampling write pointer signal is equivalent to the "push write pointer" obtained by adjusting the original write pointer of the RX FIFO according to the offset.

[0096] Furthermore, while the RX FIFO is writing data according to the original write clock, the receiving unit can sample the write pointer signal at the sampling edge of the RX FIFO's read clock, such as the rising edge or the falling edge, and determine the read enable of the RX FIFO based on the sampling result, that is, determine the read operation of the RX FIFO based on the write pointer signal.

[0097] As can be seen, according to the embodiments of this disclosure, the read operation of the RX FIFO is performed based on the sampled write pointer signal, which is generated based on the offset. That is, the read operation of the RX FIFO is performed based on the difference between the write clock and the read clock of the RX FIFO. Therefore, it can be ensured that the RX FIFO actually works in the manner of a "synchronous FIFO", and can cross the clock domains of the TX die and the RX die without separate synchronization, thus greatly reducing the latency. At the same time, the sampled write pointer signal is generated based on the "real-time" offset. Therefore, based on the read enable generated by it, it can ensure that there is a necessary read-write distance between the read operation and the write operation, so as not to generate data errors. Moreover, the read-write distance is much smaller than the maximum possible offset in the entire life cycle of the chip, so as to further reduce the latency.

[0098] In some embodiments, the sampling edge of the read clock of the RX FIFO is located in a preset central interval of the write pointer range of the sampled write pointer signal.

[0099] As one embodiment of this disclosure, the sampling write pointer signal generated above can be such that the sampling edge of the read clock of the RX FIFO is located within the central interval of its write pointer range, thereby ensuring that no data errors will occur within a sufficient offset range.

[0100] In some embodiments, a sampling write pointer signal (S101A2) is generated based on the offset and the write clock of the RX FIFO, including:

[0101] S101A21. Based on the offset, generate a sampled write pointer signal with a write pointer delay relative to the RX FIFO.

[0102] The delay of the sampling write pointer signal relative to the write pointer of the RX FIFO is nt / 2, where t is the write cycle of the RX FIFO, n is an integer greater than or equal to 0 and less than a multiple of 2 cycles, and the cycle multiple is the ratio of the read cycle to the write cycle of the RX FIFO.

[0103] As one embodiment of this disclosure, the newly generated sampling write pointer signal may have a certain delay relative to the original write pointer of the RX FIFO, and can ensure that the sampling edge of the read clock of the RX FIFO is located in the center area of ​​the pointer range of the sampling write pointer signal.

[0104] For example, the original write clock of the RX FIFO can be divided to obtain a write pointer with the same read clock period as the RX FIFO. Then, the write pointer can be delayed to obtain a sampled write pointer signal.

[0105] It should be understood that the embodiments of this disclosure only require that the generated sampling write pointer signal and the original write pointer of the RX FIFO conform to the above delay relationship, and do not require that the original write clock be delayed to generate the sampling write pointer signal. For example, the sampling write pointer signal can also be generated by adjusting the local clock according to the original write clock.

[0106] It should be understood that even when the original write clock of the RX FIFO is delayed to generate the sampling write pointer signal, the write operation of the RX FIFO is still performed according to its original write clock.

[0107] For example, when the write cycle of the RX FIFO is t, the delay amount of the original write clock of the RX FIFO can be t / 2 or an integer multiple of the unit interval (UI). That is, the original write clock of the RX FIFO can be divided and delayed by n times t / 2 to obtain the sampled write pointer signal. Moreover, n is less than twice the ratio of the read cycle T of the RX FIFO to the write cycle t, or less than twice the "cycle multiple". In other words, the total delay amount of the write pointer nt / 2 must be less than the read cycle T to avoid excessive delay.

[0108] For example, refer to Figure 8The read clock frequency of the RX FIFO can be 2GHz, corresponding to a read cycle T=500ps, and the write clock frequency can be 8GHz, corresponding to a write cycle t=125ps, and a UI=62.5ps. Therefore, the read cycle T is 4 times the write cycle t, which means the cycle multiple is 4. Thus, n can be an integer between 0 and 7, and the maximum delay is 7t / 2.

[0109] Among them, reference Figure 8 Since the cycle multiple is 4, the write pointer used as the delay object here can be obtained by dividing the write clock of RXFIFO by 4, that is, the write pointer is the same as the read clock of RXFIFO, which is 2GHz.

[0110] Correspondingly, the central interval of the write pointer range can be set to 1 t. That is, if the write pointer range is defined as [0, 4t], then the interval [3t / 2, 5t / 2] is the "central interval".

[0111] Therefore, referring to Figure 8 The following are some cases where the sampling write pointer signal is generated based on the write clock of the RX FIFO:

[0112] (1) Case 1: When the sampling edge of the read clock is located in the shaded area of ​​case 1 according to the offset, that is, the difference between the leading edge of the write pointer range and the sampling edge is [-t / 2, t / 2), the write clock should be delayed by 2t to generate the sampling write pointer signal, i.e., n=4, so that the sampling edge is located in the central interval of the write pointer range of the sampling write pointer signal.

[0113] (2) Case 2: When the sampling edge of the read clock is located in the shaded area of ​​case 2 according to the offset, that is, the difference between the leading edge of the write pointer range and the sampling edge is [-3t / 2, -t / 2), the write clock should be delayed by 3t to generate the sampling write pointer signal, i.e., n=6, so that the sampling edge is located in the central interval of the write pointer range of the sampling write pointer signal.

[0114] (3) Case 3: When the sampling edge of the read clock is located in the shaded area of ​​case 3 according to the offset, that is, when the difference between the leading edge of the write pointer range and the sampling edge is [-5t / 2, -3t / 2), it is originally located directly in the central interval of the write pointer range. Therefore, the write clock does not need to be delayed to directly generate the sampled write pointer signal, or it can be regarded as delaying the write clock by 0t to sample and generate the sampled write pointer signal, i.e., n=0.

[0115] (4) Case 4: When the sampling edge of the read clock is located in the shaded area of ​​case 4 according to the offset, that is, when the difference between the leading edge of the write pointer range and the sampling edge is [-7t / 2, -5t / 2), it is equivalent to delaying the write clock by 5t. However, the total delay of 5t exceeds T. Therefore, the write clock should actually be delayed by t to generate the sampled write pointer signal, i.e., n=2, so that the sampling edge is located in the central interval of the write pointer range of the sampled write pointer signal.

[0116] It should be understood that the operation of generating a sampling write pointer signal based on the offset can be performed in the initial state, such as when the chip is powered on. For example, after the chip is powered on, before actually starting to transmit data signals, the transmitting unit can first send a test data signal to the receiving unit so that the receiving unit can initially acquire the offset and generate a sampling write pointer signal accordingly.

[0117] Meanwhile, after the chip enters the working state, that is, during the actual transmission of data signals, the receiving unit can also continuously detect the offset in real time and generate a sampling write pointer signal accordingly, that is, it can continuously "track" the offset.

[0118] In some embodiments, the method of this disclosure further includes:

[0119] S100: In response to RX FIFO reset, set the write pointer of RX FIFO to the maximum position and the read pointer of RX FIFO to the minimum position.

[0120] As another embodiment of this disclosure, when the RX FIFO is reset, such as during a power-on reset, only the read pointer can be set to the minimum position, i.e., "read pointer = 0"; for the write pointer, it is not set to zero, but is set to the maximum position, i.e., "write pointer = max"; thus, the RX FIFO can directly read the data at position 0, instead of having to wait for the write pointer to be 1 to read the data at position 0, as is the case with asynchronous FIFOs in related technologies, which can reduce the delay by one clock cycle.

[0121] For example, refer to Figure 9 In case 1 above, the original write pointer of the RX FIFO is delayed by 2t to generate a sampling write pointer signal, which is used to sample the read clock of the RX FIFO and generate a read enable accordingly.

[0122] Since the write pointer is equal to max during reset, when the RX FIFO is empty, we have:

[0123] Empty = (rdptr == sample_wrptr + 1'b1);

[0124] rd_en=~empty;

[0125] Here, rdptr represents the read pointer, sample_wrptr represents the sample write pointer, and rd_en represents the read enable, which is 1 to enable read and 0 to disable read.

[0126] When both the read and write pointers are reset values, (7+1)%8=0, rd_en=0; when the write pointer is sampled as 0, 0! = 0+1, indicating that it is not empty, so rd_en=1; when rd_en=1, the data in the RX FIFO can be read according to the read clock, and the read pointer is incremented by 1 each time it is read.

[0127] Therefore, referring to Figure 9 It can be seen that, regarding the above Figure 8 In case 1, the delay between reading and writing in the RX FIFO, that is, the time between the end of the write pointer 0 and the start of reading data D0, is 1T.

[0128] Accordingly, for the above method, the maximum delay for the write pointer is 3.5t, so it can be known that the maximum read / write delay of this embodiment is 1T + 1.5t = 1.375T.

[0129] Therefore, based on the above method, the maximum latency of the RX FIFO is only 1.375T, which is much smaller than that of the methods in related technologies.

[0130] In some embodiments, refer to Figure 4 The method in this disclosure embodiment further includes:

[0131] S100: In response to RX FIFO reset, set the write pointer of RX FIFO to the maximum position and the read pointer of RX FIFO to the minimum position.

[0132] In some embodiments, refer to Figure 4 Based at least on the read clock and write clock of the RX FIFO, the adjusted write pointer is determined, and the read enable of the RX FIFO is determined based on the adjusted write pointer (S101), including:

[0133] S101B1 generates a local high-frequency clock.

[0134] S101B2: Synchronize the write pointer of the RX FIFO to the read clock domain according to the local high-frequency clock.

[0135] S101B3. At the sampling edge of the read clock of the RX FIFO, the write pointer of the synchronized RX FIFO is sampled, and the read enable of the RX FIFO is determined based on the sampling result.

[0136] Among them, the period of the local high-frequency clock is equal to the write period of the RX FIFO, the total period of the high-frequency clock for pacing is less than twice the read period of the RX FIFO, and the write pointer of the RX FIFO is in Gray code form.

[0137] Reference Figure 4 As another embodiment of this disclosure, when the RX FIFO is reset, the read pointer can be set to 0 and the write pointer to max.

[0138] Reference Figure 4 In this case, the way to adjust the write pointer of the RX FIFO according to the read clock of the RX FIFO is as follows: the receiving unit first generates a "local high-frequency clock" with the same frequency as the write clock of the RX FIFO, such as a frequency of 8GHz, based on the local clock. Since both are derived from the local clock of the RX FIFO, the local high-frequency clock is synchronized with the read clock of the RX FIFO.

[0139] Furthermore, the receiving unit operates the RX FIFO in a manner similar to an "asynchronous FIFO". Based on the local high-frequency clock, it synchronizes the write pointer of the RX FIFO to its read clock domain by syncing the clocks. In other words, it uses the clock period t of the local high-frequency clock as the "beat" for syncing.

[0140] For example, the original write clock of the RX FIFO can be divided to obtain a write pointer with the same read clock cycle as the RX FIFO. Then, the write pointer signal can be synchronized to the read clock domain of the RX FIFO using the local high-frequency clock to obtain the synchronized write pointer of the RX FIFO.

[0141] Then, at the sampling edge of the read clock of the RX FIFO, the write pointer of the synchronized RX FIFO is sampled, and a read enable is generated based on the sampling result.

[0142] The total time for the above-mentioned slapping is less than twice the read cycle of the RX FIFO.

[0143] In the above-mentioned clock synchronization process, the write pointer of the RX FIFO needs to be converted into Gray code form. Gray code is a binary data (0 and 1) encoding method that ensures that within the encoding range, any two adjacent Gray codes differ by exactly one bit. Therefore, compared with conventional binary encoding, Gray code can achieve cross-clock domains through a single bit change under any circumstances, making it easy to implement and less prone to metastability, data errors, etc. It will not be described in detail here.

[0144] In some embodiments, the cycle multiple is 4, which is the ratio of the read cycle to the write cycle of the RX FIFO; the total cycle of the high-frequency clock for pacing is 4 to 6 cycles.

[0145] As one embodiment of this disclosure, when the above cycle multiple is 4, such as when the write cycle t=125ps and the read cycle T=500ps, 4~6 beats (4~6t) can be performed simultaneously. The beat range within this range is the smallest feasible beat range under the normal performance of the devices in the current chip.

[0146] As can be seen, referring to Figure 10 Using the timing synchronization method of this embodiment, the delay between reading and writing of the RX FIFO is 2.5T when timing is 6t.

[0147] In contrast, refer to Figure 11 In related technologies, the synchronization method is based directly on the read clock of the RX FIFO. If the synchronization is 3 clock cycles (3T), the delay between reading and writing of the RX FIFO is 3.5T.

[0148] Therefore, according to the above method, the latency of the RX FIFO can be reduced from at least 3.5T to 2.5T, which also achieves the effect of reducing latency; moreover, the above method does not require setting up a phase detector (PD) to detect the offset, and can also simplify the structure and operation of the receiving unit.

[0149] In some embodiments, the method of this disclosure further includes:

[0150] S103A1: In response to the data volume stored in the RX FIFO reaching a preset data volume threshold, a full signal is sent to the transmitting unit.

[0151] Where the data volume threshold is less than the maximum capacity of the RX FIFO, the full signal is used to control the transmitting unit to pause transmitting data signals.

[0152] As one embodiment of this disclosure, since the receiving unit determines the read enable of the RX FIFO based on the write pointer it generates (the pushed write pointer or the synchronized write pointer), the RX FIFO does not have the function of blocking writes, which may result in the situation where data continues to be written after the RX FIFO is full.

[0153] For example, refer to Figure 12 Based on the above method of pushing the write pointer, if the read clock is faster, the above loop of "case 3-case 2-case 1-case 4" will occur. When the read pointer exceeds the write pointer, the read enable will be turned off naturally, so no problem will occur.

[0154] However, refer to Figure 13 Based on the above method of pushing the write pointer, if the read clock is slow, the above loop of "case 4-case 1-case 2-case 3" will occur. In the case where the write pointer is larger than the read pointer, that is, when the write is full, the read enable will still be enabled, thus causing an error.

[0155] Therefore, when the amount of data stored in the RX FIFO reaches the data volume threshold, that is, when it is "about to be full (Half_Full)," a "full signal" is sent to the transmitting unit through sideband messages of the UCIe protocol, etc., to notify the transmitting unit to suspend the transmission of data signals for a period of time, such as 2~4t, in order to avoid the RX FIFO being full.

[0156] For example, the amount of data stored in the RX FIFO can be determined based on the positions of the read and write pointers. For instance, the Half_Full condition above can be set as follows:

[0157] Half_Full=(sample_wrptr = rdptr+1).

[0158] In some embodiments, the method of this disclosure further includes:

[0159] S103B1: In response to the number of write cycles of the RX FIFO that continuously receives data signals reaching a predetermined number of cycles threshold, a full signal is sent to the transmitting unit.

[0160] As another embodiment of this disclosure, when the number of write cycles in which the receiving unit continuously receives data signals in the RX FIFO reaches a preset cycle number threshold, the receiving unit sends a "full signal" to the transmitting unit to notify the transmitting unit to suspend the transmission of data signals for a period of time, such as 2 to 4 t, so as to avoid the RX FIFO being fully written.

[0161] It should be understood that the transmitting unit may also actively pause the transmission of data signals when it discovers that the number of cycles in which it has continuously transmitted data signals has reached the above-mentioned cycle number threshold.

[0162] In some embodiments, the method of this disclosure further includes:

[0163] S1021. When there is no data signal to be received, the feedforward clock cannot be received from the transmitting unit.

[0164] S1022. When the time during which the feedforward clock is not received reaches a preset time threshold, the feedforward clock is received from the transmitting unit, and the write pointer of the RX FIFO is adjusted at least according to the read clock of the RX FIFO.

[0165] In some related technologies, the RX FIFO adopts a constant read and write mode, that is, the read clock and write clock of the RX FIFO are always on regardless of whether there is data to be transmitted, which results in high power consumption and cannot meet the power saving requirements of the UCIe protocol's dynamic acquisition (gating).

[0166] As one embodiment of this disclosure, when there is no data signal to be sent to the receiving unit, the transmitting unit can turn off the read clock of the TX FIFO, that is, turn off the feedforward clock of the receiving unit and the write clock of the RX FIFO; and when there is a data signal to be sent again, the transmitting unit turns on the read clock of the TX FIFO, that is, turns on the feedforward clock of the receiving unit and the write clock of the RX FIFO.

[0167] Therefore, the present invention can disable the read clock of the TX FIFO at certain times, thereby reducing power consumption and meeting the requirements of the UCIe protocol.

[0168] However, during the period when the read clock of the TX FIFO is turned off, the local clocks of the transmitting and receiving units may still drift. If the actual offset caused by the drift during this period is too large, it may directly cause data errors after the read clock of the TX FIFO is turned on again.

[0169] For example, for the above 2GHz read clock, its read cycle is 500ps, and the maximum absolute value of the drift is 250ps. The minimum unit of delay for the write clock is UI=62.5ps of the 8GHz clock. Therefore, if the absolute value of the drift accumulated during the TX FIFO read clock period exceeds 250ps-62.5ps=187.5ps, the sampling edge of the read clock may directly coincide with the boundary of the write pointer. Once the TX FIFO read clock is restarted, it will cause data errors.

[0170] Therefore, a "time threshold" can be preset. The setting of this time threshold should ensure that the drift generated by the local clock within its range will not cause an excessive offset, such as not reaching the above 187.5ps. Therefore, the time threshold can be set according to the chip's performance, such as 1ms, 100μs, 10μs, 1μs, etc.

[0171] Furthermore, when the duration for which no data signal needs to be transmitted reaches the above time threshold, that is, when the duration for which the read clock of the TX FIFO is continuously turned off reaches the time threshold, the transmitting unit can start the read clock of the TX FIFO and send an analog data signal for detecting the offset. Thus, the receiving unit can adjust the write pointer of the RX FIFO according to the restarted write clock of the RX FIFO to avoid excessive accumulated drift.

[0172] In some embodiments, the receiving unit receives multiple data signals from the transmitting unit through multiple RX FIFOs, one of which is the target RX FIFO.

[0173] Based at least on the read clock and write clock of the RX FIFO, determine the adjusted write pointer, and determine the read enable of the RX FIFO based on the adjusted write pointer (S101), including:

[0174] S101C determines the adjusted write pointer based at least on the read clock and write clock of the target RX FIFO, and determines the read enable of all RX FIFOs based on the adjusted write pointer.

[0175] As one embodiment of this disclosure, the receiving unit may have multiple RXFIFOs for receiving data signals. Theoretically, the read clocks and write clocks of these RXFIFOs should be synchronized, but in practice, there may still be some drift, resulting in a certain deviation in the time when the data signals are read from them. Therefore, before actually processing the data signals from these RXFIFOs, it is usually necessary to store the signals read from each RXFIFO into a buffer to ensure that the data signals from different RXFIFOs are accurately aligned.

[0176] As one embodiment of this disclosure, one of the multiple RX FIFOs can be pre-defined as a target RX FIFO. A read enable can then be generated according to the write clock and read clock of this RX FIFO, as described above. This read enable is used to control the read operations of all RX FIFOs, ensuring that the read operations of all RX FIFOs are performed simultaneously. This guarantees precise alignment of multiple data signals, eliminating the need for a buffer and further reducing latency. Furthermore, this method only requires setting up a circuit for generating the read enable for the target RX FIFO, while other RX FIFOs can directly utilize the read enable generated by this circuit, thus simplifying the product structure.

[0177] Secondly, referring to Figure 5 This disclosure provides a receiving unit, including an RX FIFO, a memory, and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements any of the data transmission methods of this disclosure.

[0178] Thirdly, referring to Figure 6 This disclosure provides a chip, including:

[0179] Reference clock;

[0180] Transmitting unit;

[0181] Any receiving unit that implements the embodiments of this disclosure.

[0182] Fourthly, refer to Figure 7 This disclosure provides a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements any of the data transmission methods of this disclosure.

[0183] Fifthly, embodiments of this disclosure provide a computer program product, including a computer program, which, when executed by a processor, implements any of the data transmission methods of embodiments of this disclosure.

[0184] Among them, the processor is a device with data processing capabilities, including but not limited to the central processing unit (CPU); the memory is a device with data storage capabilities, including but not limited to random access memory (RAM), more specifically such as SDRAM, DDR, etc., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); I / O interface, or read-write interface, is connected between the processor and the memory, enabling information exchange between the memory and the processor, including but not limited to the data bus (Bus).

[0185] Example 1:

[0186] Reference Figures 14 to 17 Example 1 provides an exemplary description of a specific data transmission method according to an embodiment of this disclosure.

[0187] Reference Figure 14 Example 1 is used for the transmitting unit to transmit data signals to the receiving unit, wherein the transmitting unit may be a TX bare crystal, the receiving unit may be an RX bare crystal, and there is a bare crystal connection between the transmitting unit and the receiving unit.

[0188] Reference Figure 14 The transmitting and receiving units use the same 100MHz reference clock (ref).

[0189] In the transmitting unit, the reference clock is converted into an 8GHz clock via a phase-locked loop (PLL). This 8GHz clock serves as the read clock for the TX FIFO and is used to process sequence data (01010101) and transmit it to the receiving unit, where it acts as the feedforward clock (FWD CLK) and the write clock for the RX FIFO. Simultaneously, the 8GHz clock from the transmitting unit is further divided by a 4-divider (DIV4) to generate a 2GHz local clock (LCLK), which serves as the write clock for the TX FIFO.

[0190] In the receiving unit, the reference clock is generated into an 8GHz clock by a PLL, and then into a 2GHz LCLK by a 4-divider (DIV4), which serves as the read clock for the RX FIFO.

[0191] The transmitting unit includes multiple 8-to-1 data serializers (SERs), each SER containing a TX FIFO, which is connected to the receiving unit via bare crystal interconnection.

[0192] For example, refer to Figure 14 The sending unit may include:

[0193] SER1 is used to transmit 8-bit data signals (TX data), which includes TX FIFO1, corresponding to the data channel;

[0194] SER2 is used to transmit the feedforward clock (FWD CLK), which includes TX FIFO2.

[0195] Correspondingly, the receiving unit includes a 1-to-8 data deserializer (DES). The DES has an RXFIFO, which is connected to the TXFIFO of the receiving unit's SER via a bare crystal connection.

[0196] For example, refer to Figure 14 The receiving unit may include:

[0197] DES1 is used to receive data signals, and it includes RX FIFO1.

[0198] Since the FWD CLK signal is a clock signal, the receiving unit can directly receive the signal from SER2 without setting the corresponding DES.

[0199] Reference Figure 15 In the DES of the receiving unit, the serial data input via RX drv can be written using an 8GHz FWD CLK. Even-numbered bits and odd-numbered bits are sampled on the rising and falling edges respectively, and converted from serial to parallel (1 to 2). On the next rising edge, the converted 2-bit data is written to positions 0 and 1 of the first row of the RX FIFO. Then, on the next rising edge, positions 2 and 3 of the first row of the RX FIFO are written, and this process is repeated until the first row of the RX FIFO is filled in four cycles of the 8GHz clock, and then the next row is written. For example, the depth of the RX FIFO can be 4, and the data read from it can first enter a register (reg).

[0200] Reference Figure 14In the transmitting unit, a small delay line (Deskew) can also be provided for SER1, which is used to make small delay adjustments, such as a delay of about 0.04 UI, which corresponds to about 5 ps for an 8 GHz clock.

[0201] Reference Figure 14 In the receiving unit, a delay matching unit can also be provided for DES1 to compensate for the delay of the RX path.

[0202] Reference Figure 14 In the transmitting unit, a delay loop (DLL) can also be provided, which is used to delay the elapsed clock, that is, to delay FWD CLK to set the eye diagram of the sampled data. Its step can be 1ps, and the total delay can be greater than 1UI (62.5ps).

[0203] Reference Figure 16 The receiving unit also includes a phase detector (PD), which compares its own LCLK with the FWD CLK from the transmitting unit, that is, compares the read clock and write clock of the RX FIFO to determine the offset between them.

[0204] Since the FWD CLK is 8GHz and the receiver unit's LCLK is 2GHz, therefore, refer to... Figure 16 The FWD CLK can be converted into a 2GHz signal by a 4-divider (DIV4) and then compared with the LCLK of the receiving unit in the PD.

[0205] The specific form of PD can be determined according to the required offset accuracy. For example, for a 2GHz clock, a reference can be used. Figure 17 The 64-level phase detector corresponds to an offset accuracy of T / 64, which is 500ps / 64.

[0206] Alternatively, as another embodiment of this disclosure, PD may not be set, but rather 2GHz LCLK may be sampled at the rising or falling edge of 8GHz FWD CLK, and the offset may be determined based on the sampled level; it should be understood that the offset determined in this way has low accuracy, which is T / 4.

[0207] Furthermore, the 2GHz LCLK can be sampled on both the rising and falling edges of the 8GHz FWD CLK to achieve an offset accuracy of T / 8.

[0208] Reference Figure 16The receiving unit has two RX FIFOs, which are used to receive two data signals (datalane1 and data lane2) respectively, and the upper RX FIFO is the target RX FIFO; while FWD CLK serves as the write pointer for all RX FIFOs, controlling the write operations of all RX FIFOs.

[0209] Reference Figure 16 In the target RX FIFO, the FWD CLK is further divided by 4 (DIV4) to generate a 2GHz signal, which is then sent to the gen wrptr module to generate a 2GHz write pointer for delay. The gen wrptr module increments the write pointer by 1 after writing each line of 8 bits of data, and sets the initial value of the write pointer to 4, which is max. The delay module, based on the offset detected by the PD, delays the write pointer of the gen wrptr module by 0 to 7 UI (62.5ps), generating a sampled write pointer signal, which is then input to the wrptr sample module. The wrptr sample module, based on the 2GHz local clock, samples the sampled write pointer signal on the sampling edge of the read clock to generate a read enable (rd_en). In other words, the read enable is determined based on the pushed write pointer, and this read enable is used to control all read operations of the RX FIFO.

[0210] Here, rd_en=1 indicates that read enable is enabled, and rd_en=0 indicates that read enable is disabled. That is, rd_en can control the read pointer (rdptr) to read data from the RX FIFO. Specifically, when rd_en=1, data is read from the RX FIFO in each read cycle and rdptr is incremented by 1.

[0211] Therefore, the receiving module of Example 1 can implement the following process: detect the offset between the write clock and the read clock of the RX FIFO; generate a sampling write pointer signal based on the offset and the write clock of the RX FIFO; sample the sampling write pointer signal on the sampling edge of the read clock of the RX FIFO, and determine the read enable of the RX FIFO based on the sampling result.

[0212] It should be understood that in the above target RX FIFO, the wrptr sample module can compare the read pointer and the write pointer, and thus send a "full signal" to the sending unit through sideband messages of the UCIe protocol when it is about to be full (Half_Full).

[0213] Reference Figure 16The target RX FIFO may also include a counting (CNT) module, which is used to perform a cyclic count of 0 to 3 on the written 8GHz FWDCLK, which corresponds to a 2GHz cycle count. The counting of this CNT module can be used to ensure that operations such as reset and clock shutdown are performed at the edge of the corresponding 2GHz local clock, and can also be used to control when the delay module starts to delay.

[0214] Example 2:

[0215] Reference Figure 18 , Figure 19 Example 2 provides an exemplary description of another specific data transmission method according to an embodiment of this disclosure.

[0216] Reference Figure 18 The system architecture of Example 2 is the same as that of Example 1. Figure 14 similar.

[0217] The difference lies in the reference. Figure 18 In Example 2, the receiving unit also directly inputs the 8GHz clock generated by the PLL as a local high-frequency clock into the DES.

[0218] Furthermore, refer to Figure 19 The structure of the receiving unit in Example 2 is also the same as that in Example 1. Figure 16 similar.

[0219] The difference lies in the reference. Figure 19 In Example 2, the target RX FIFO does not have the PD and delay modules mentioned above, and may also not have the CNT module. Instead, it has an additional synchronization module for timing synchronization. The 8GHz local high-frequency clock directly enters the synchronization module, which is used to synchronize the write pointer generated by FWD CLK through the DIV4 and gen wrptr modules to the read clock domain of the RX FIFO. The synchronized signal is then sent to the wrptr sample module to generate read enable for all RX FIFOs.

[0220] Therefore, the receiving module of Example 2 can implement the following process: generate a local high-frequency clock; synchronize the write pointer of the RX FIFO to the read clock domain according to the local high-frequency clock; sample the synchronized RX FIFO write pointer on the sampling edge of the RX FIFO read clock, and determine the read enable of the RX FIFO based on the sampling result.

[0221] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0222] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0223] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media and communication media. In embodiments of this disclosure, computer storage media include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, and any other media that can be used to store desired information and can be accessed by a computer. In embodiments of this disclosure, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A method for data transmission, characterized in that, For a receiving unit, the receiving unit and the transmitting unit are packaged in the same chip and connected via a bare die interconnect. The receiving unit receives data signals from the transmitting unit through a receiver-side first-in-first-out (FIFO) buffer (RX FIFO). The local clock of the transmitting unit and the local clock of the receiving unit are generated based on the same reference clock. The read clock of the RX FIFO is the local clock of the receiving unit, and the write clock is a feedforward clock generated based on the local clock of the transmitting unit. The read cycle of the RX FIFO is greater than the write cycle. The method includes: The adjusted write pointer is determined based at least on the read clock and write clock of the RX FIFO, and the read enable of the RX FIFO is determined based on the adjusted write pointer.

2. The method according to claim 1, characterized in that, The step of determining the adjusted write pointer based at least on the read clock and write clock of the RX FIFO, and determining the read enable of the RX FIFO based on the adjusted write pointer, includes: Detect the offset between the write clock and read clock of the RX FIFO; A sampling write pointer signal is generated based on the offset and the write clock of the RX FIFO; At the sampling edge of the read clock of the RX FIFO, the sampling write pointer signal is sampled, and the read enable of the RX FIFO is determined based on the sampling result.

3. The method according to claim 2, characterized in that, The sampling edge of the read clock of the RX FIFO is located in a preset central interval of the write pointer range of the sampled write pointer signal.

4. The method according to claim 3, characterized in that, The step of generating a sampling write pointer signal based on the offset and the write clock of the RX FIFO includes: Based on the offset, a sampled write pointer signal is generated that is delayed relative to the write pointer of the RX FIFO; wherein the delay of the sampled write pointer signal relative to the write pointer of the RX FIFO is nt / 2, t is the write cycle of the RX FIFO, and n is an integer greater than or equal to 0 and less than a multiple of 2 cycles, wherein the multiple of cycles is the ratio of the read cycle to the write cycle of the RX FIFO.

5. The method according to claim 1, characterized in that, Also includes: In response to the RX FIFO reset, the write pointer of the RX FIFO is set to the maximum position, and the read pointer of the RX FIFO is set to the minimum position; The step of determining the adjusted write pointer based at least on the read clock and write clock of the RX FIFO, and determining the read enable of the RX FIFO based on the adjusted write pointer, includes: generating a local high-frequency clock; synchronizing the write pointer of the RX FIFO to the read clock domain of the RX FIFO by timing the local high-frequency clock; sampling the synchronized write pointer of the RX FIFO on the sampling edge of the read clock of the RX FIFO, and determining the read enable of the RX FIFO based on the sampling result; wherein, the period of the local high-frequency clock is equal to the write period of the RX FIFO, the total period of the timing high-frequency clock is less than twice the read period of the RX FIFO, and the write pointer of the RX FIFO is in Gray code form.

6. The method according to claim 5, characterized in that, The cycle multiple is 4, whereby the cycle multiple is the ratio of the read cycle to the write cycle of the RX FIFO; The total cycle of the high-frequency clock that beats the clock is 4 to 6 cycles.

7. The method according to claim 1, characterized in that, Also includes: In response to the RX FIFO reset, the write pointer of the RX FIFO is set to the maximum position, and the read pointer of the RX FIFO is set to the minimum position.

8. The method according to claim 1, characterized in that, Also includes: When there is no data signal to be received, the feedforward clock cannot be received from the transmitting unit; When the time during which the feedforward clock is not received reaches a preset time threshold, the feedforward clock is received from the transmitting unit, and the write pointer of the RX FIFO is adjusted at least according to the read clock of the RX FIFO.

9. The method according to claim 1, characterized in that, Also includes: In response to the data volume stored in the RX FIFO reaching a preset data volume threshold, a near-full signal is sent to the transmitting unit; the data volume threshold is less than the maximum capacity of the RX FIFO, and the near-full signal is used to control the transmitting unit to pause the transmission of the data signal.

10. The method according to claim 1, characterized in that, Also includes: In response to the number of write cycles of the RX FIFO continuously receiving the data signal reaching a predetermined number of cycles threshold, a near-full signal is sent to the transmitting unit; the near-full signal is used to control the transmitting unit to pause the transmission of the data signal.

11. The method according to any one of claims 1 to 10, characterized in that, The receiving unit receives multiple data signals from the transmitting unit through multiple RX FIFOs, one of which is the target RX FIFO; The step of determining the adjusted write pointer based at least on the read clock and write clock of the RX FIFO, and determining the read enable of the RX FIFO based on the adjusted write pointer, includes: determining the adjusted write pointer based at least on the read clock and write clock of the target RX FIFO, and determining the read enable of all the RX FIFOs based on the adjusted write pointer.

12. A receiving unit, characterized in that, It includes an RX FIFO, a memory, and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements the data transmission method according to any one of claims 1 to 11.

13. A chip, characterized in that, include: Reference clock; Transmitting unit; The receiving unit as described in claim 12.

14. A computer-readable medium, characterized in that, It stores a computer program that, when executed by a processor, implements the data transmission method according to any one of claims 1 to 11.

15. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the data transmission method according to any one of claims 1 to 11.

Images