A method and system for detecting outer layer circuits of a PCB

Abstract

The application discloses a kind of detection method and system of outer layer circuit of PCB, and the application relates to the technical field of outer layer circuit detection method, according to multiple first circuit abnormal characteristics and corresponding circuit processing procedure determine the circuit abnormality type of key detection area;Based on the circuit abnormality type of key detection area, area position and multiple first circuit abnormal characteristics determine the first circuit problem of outer layer circuit of PCB, improve the accuracy of the first circuit problem of outer layer circuit of PCB.Therefore, according to the trace of multiple implicit problems, the corresponding circuit review is carried out to the outer layer circuit of PCB, to add multiple second circuit abnormal characteristics;According to multiple second circuit abnormal characteristics and multiple first circuit abnormal characteristics determine the overall circuit problem of outer layer circuit of PCB, according to the overall circuit problem of outer layer circuit of PCB and the target use information of PCB Determine the priority of sub-circuit problem, improve the accuracy of circuit problem priority.

Description

Technical Field

[0001] This invention relates to the technical field of methods for testing outer layer circuits, and more particularly to a method and system for testing outer layer circuits of a PCB. Background Technology

[0002] With the development of technology, the outer layer circuitry of a PCB refers to the copper foil traces on the surface of the printed circuit board, used to achieve electrical interconnection between electronic components. These circuits are the core channels for signal transmission and power distribution in electronic devices, and their quality directly affects product performance. In existing technologies, the outer layer circuitry of the PCB is photographed, and the detection of the outer layer circuitry is triggered based on the image recognition of the PCB outer layer circuitry to directly output the corresponding circuit problems. However, this ignores the impact of the initial circuit problems and cannot accommodate the consideration of the abnormal characteristics of the second circuit, resulting in low accuracy in prioritizing circuit problems. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a method and system for detecting the outer layer circuitry of a PCB.

[0004] This invention provides a method for detecting the outer layer circuitry of a PCB, comprising: after the bare copper circuitry process of the PCB is completed, determining the circuit path based on the identification of the circuit image of the outer layer circuitry of the PCB, and marking multiple key detection areas based on the monitoring of the circuit path; determining multiple circuit features based on the identification of the key detection areas, and determining multiple first circuit anomaly features based on the location, feature shape, and surrounding environmental features of the multiple circuit features; determining the type of circuit anomaly in the key detection areas based on the multiple first circuit anomaly features and the corresponding circuit processing steps; determining the initial circuit problem of the outer layer circuitry of the PCB based on the type of circuit anomaly in the key detection areas, the location of the areas, and the multiple first circuit anomaly features; predicting multiple hidden problems of the outer layer circuitry of the PCB based on the target usage information of the PCB, the initial circuit problem, and the circuit shape of the outer layer circuitry of the PCB, and performing corresponding circuit re-inspection on the outer layer circuitry of the PCB based on the tracing of the multiple hidden problems to add multiple second circuit anomaly features; determining the overall circuit problem of the outer layer circuitry of the PCB based on the multiple second circuit anomaly features and the multiple first circuit anomaly features, and determining the priority of sub-circuit problems based on the overall circuit problem of the outer layer circuitry of the PCB and the target usage information of the PCB.

[0005] This invention provides a detection system for the outer layer circuitry of a PCB, which is applied to the aforementioned detection method for the outer layer circuitry of a PCB. The detection system for the outer layer circuitry of a PCB includes:

[0006] The critical inspection area module is used to determine the circuit path based on the recognition of the circuit image of the outer layer circuit of the PCB after the bare copper circuit process is completed, and to mark multiple critical inspection areas based on the monitoring of the circuit path.

[0007] The first line anomaly feature module is used to determine multiple line features based on the identification of key detection areas, and to determine multiple first line anomaly features based on the location, feature shape and surrounding environmental features of the multiple line features.

[0008] The initial circuit problem module is used to determine the type of circuit abnormality in the key inspection area based on multiple first circuit abnormality characteristics and corresponding circuit processing procedures; and to determine the initial circuit problem of the outer layer circuit of the PCB based on the type of circuit abnormality, the location of the area, and multiple first circuit abnormality characteristics of the key inspection area.

[0009] The second line anomaly feature module is used to predict multiple hidden problems of the outer layer circuit of the PCB based on the target usage information of the PCB, the initial line problem, and the line shape of the outer layer circuit of the PCB. Based on the tracing of multiple hidden problems, the corresponding line review of the outer layer circuit of the PCB is carried out to add multiple second line anomaly features.

[0010] The circuit problem priority module is used to determine the overall circuit problem of the outer layer circuit of the PCB based on multiple second circuit anomaly characteristics and multiple first circuit anomaly characteristics, and to determine the priority of sub-circuit problems based on the overall circuit problem of the outer layer circuit of the PCB and the target usage information of the PCB.

[0011] Compared with the prior art, the beneficial effects of the present invention are:

[0012] In this embodiment of the invention, the method is used to determine multiple first line anomaly features based on the location, feature shape, and surrounding environmental features of multiple line features; to determine the type of line anomaly in the key detection area based on the multiple first line anomaly features and the corresponding line processing steps; and to determine the first line problem of the outer layer of the PCB based on the type of line anomaly, the location of the area, and the multiple first line anomaly features of the key detection area. The introduction of first line anomaly features, which takes into account the overall consideration of the type of line anomaly, the location of the area, and the multiple first line anomaly features of the key detection area, improves the accuracy of the first line problem of the outer layer of the PCB.

[0013] Therefore, based on the target usage information of the PCB, initial circuit problems, and the circuit configuration of the PCB's outer layer circuits, multiple hidden problems of the PCB's outer layer circuits are predicted. By tracing these hidden problems, the corresponding circuits of the PCB's outer layer circuits are re-examined to add multiple second-level circuit anomaly features. Based on these second-level and first-level circuit anomaly features, the overall circuit problems of the PCB's outer layer circuits are determined. The priority of sub-circuit problems is determined based on the overall circuit problems of the PCB's outer layer circuits and the PCB's target usage information. The introduction of second-level circuit anomaly features and further control over hidden problems in the PCB's outer layer circuits achieves a holistic consideration of the overall circuit problems of the PCB's outer layer circuits and the PCB's target usage information, improving the accuracy of circuit problem prioritization. Attached Figure Description

[0014] Figure 1 This is a flowchart illustrating the detection method for the outer layer circuitry of a PCB in an embodiment of the present invention.

[0015] Figure 2 This is a flowchart illustrating step S11 of the PCB outer layer circuit detection method in an embodiment of the present invention.

[0016] Figure 3 This is a flowchart illustrating step S12 in the PCB outer layer circuit detection method of the present invention.

[0017] Figure 4 This is a flowchart illustrating step S13 of the PCB outer layer circuit detection method in an embodiment of the present invention.

[0018] Figure 5 This is a flowchart illustrating step S14 of the PCB outer layer circuit detection method in an embodiment of the present invention.

[0019] Figure 6 This is a flowchart illustrating step S15 of the PCB outer layer circuit detection method in an embodiment of the present invention.

[0020] Figure 7 This is a schematic diagram of the structural composition of the PCB outer layer circuit detection system in an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0022] Please see Figures 1 to 7 A method for inspecting the outer layer circuitry of a PCB, applicable to the inspection of the outer layer circuitry of a PCB; the method for inspecting the outer layer circuitry of a PCB includes:

[0023] Step S11: After the bare copper circuit process is completed on the PCB, the circuit path is determined based on the recognition of the circuit image of the outer layer circuit of the PCB, and multiple key detection areas are marked based on the monitoring of the circuit path.

[0024] Step S12: Based on the identification of key detection areas, determine multiple line features, and based on the location, feature shape and surrounding environmental features of the multiple line features, determine multiple first line anomaly features;

[0025] Step S13: Determine the type of circuit abnormality in the key detection area based on multiple first circuit abnormality characteristics and corresponding circuit processing procedures; determine the initial circuit problem of the outer layer circuit of the PCB based on the type of circuit abnormality, location of the area, and multiple first circuit abnormality characteristics in the key detection area.

[0026] Step S14: Based on the target usage information of the PCB, the initial circuit problem, and the circuit shape of the outer layer circuit of the PCB, predict multiple hidden problems of the outer layer circuit of the PCB. Based on the tracing of multiple hidden problems, perform corresponding circuit review on the outer layer circuit of the PCB to add multiple second circuit anomaly features.

[0027] Step S15: Determine the overall circuit problem of the outer layer of the PCB based on multiple second circuit abnormality features and multiple first circuit abnormality features; determine the priority of sub-circuit problems based on the overall circuit problem of the outer layer of the PCB and the target usage information of the PCB.

[0028] refer to Figure 2 In step S11, the specific steps are as follows:

[0029] S111: Real-time monitoring of PCB processing steps and marking of bare copper circuit steps. Based on the bare copper circuit steps, PCB positioning and shooting are triggered to capture circuit images of the outer layer circuits of the PCB. At this time, the outer layer circuits of the PCB are on the front of the circuit board and are captured by the camera.

[0030] S112: Perform image recognition on the circuit image of the outer layer of the PCB, determine multiple bare copper segments based on the image recognition of the circuit image of the outer layer of the PCB, construct the corresponding circuit path based on the multiple bare copper segments, and then gradually improve the circuit path according to the regularity of the multiple bare copper segments.

[0031] S113: Real-time monitoring of the circuit path and collection of changes in the circuit path at different times. Based on the changes in the circuit path at different times, the completion status of each circuit path is determined. Based on the completion status of each circuit path, the target usage information of the PCB, and the shape, multiple key detection areas are determined.

[0032] In the embodiments of this application, the position and current process status of the PCB board on the production line are tracked in real time through a sensor network (such as photoelectric sensors and proximity switches) and a PLC control system installed on the production line. The system records the serial number of each PCB, the timestamp of entering each process, and the process parameters. The monitoring content includes key processes such as inner layer etching, lamination, drilling, copper plating, pattern electroplating, and outer layer etching, with particular attention to the start and end status of the bare copper circuit process.

[0033] The machine vision system identifies changes in PCB surface features. When it detects that copper foil has been etched to form a circuit pattern but has not yet been covered by solder mask, the system automatically marks it as a "bare copper circuit process". The MES system adds a "bare copper process" label to the PCB and records the precise timestamp and equipment number. This label will trigger additional quality inspection parameters, such as line width uniformity and copper surface oxidation degree.

[0034] Once the system confirms that the PCB has entered the bare copper circuit process and has been running stably for 30 seconds (to ensure process stability), it automatically sends a shooting command to the vision inspection system. A high-precision servo control system is used to position the PCB within an error range of ±0.05mm to ensure the consistency of the shooting position. The camera parameters, such as resolution (usually ≥5μm / pixel), light intensity (multi-angle LED ring light source), and exposure time, are automatically adjusted according to the PCB size and circuit density.

[0035] Using an industrial-grade CCD or CMOS camera, coupled with a telecentric lens to eliminate perspective errors, high-resolution images (typically 5000×5000 pixels) are acquired; real-time image denoising, contrast enhancement, edge sharpening, and other processing are performed to ensure that line features are clearly visible; for high-density PCBs, multiple angle shooting at 0°, 45°, and 90° is required to capture line features in different directions.

[0036] Furthermore, deep learning-based image recognition algorithms, such as convolutional neural networks (CNN) or U-Net architecture, are used to process the acquired high-resolution PCB images. The algorithm first performs image preprocessing, including grayscale conversion, noise removal, and contrast enhancement. The system identifies elements such as copper lines, vias, and pads in the image, paying particular attention to the direction, width, and connection relationships of bare copper lines.

[0037] The system extracts line segment features from the image using edge detection algorithms (such as the Canny operator) and morphological operations. It records the start and end coordinates, length, width, and direction angle of each line segment. The extracted line segments are classified according to their features, such as straight segments, curved segments, T-shaped connections, and L-shaped connections, to provide basic data for subsequent path construction. Each line segment is scored for quality, taking into account factors such as line width uniformity, edge sharpness, and surface oxidation degree.

[0038] Starting from key connection points (such as chip pins and connector pads), the system constructs preliminary paths based on the connection relationships between line segments. It analyzes these relationships to establish a PCB network topology, identifying the main signal, power, and ground paths. Based on circuit design rules and electromagnetic compatibility requirements, the system optimizes the preliminary paths to ensure their rationality and reliability. The system identifies regularities in the PCB design, such as the parallel relationships of differential pairs, the tree-like structure of power lines, and the serpentine routing of clock signals. Through multiple iterative analyses, the system gradually supplements and improves the path information. Especially for paths in complex areas (such as under BGA chips or in high-density connector areas), the constructed paths are compared with the PCB design file (Gerber file) to verify their accuracy, and manual intervention and correction are performed when necessary.

[0039] Therefore, the circuit path is monitored in real time, and changes in the circuit path are collected at different times. The completion status of each circuit path is determined based on the changes in the circuit path at different times. Multiple key detection areas are determined based on the completion status of each circuit path, the target usage information of the PCB, and its shape. This approach takes into account the overall consideration of the completion status of each circuit path, the target usage information of the PCB, and its shape, ensuring the accuracy of multiple key detection areas.

[0040] At this point, a high-speed industrial camera and image acquisition system are used to continuously capture images of the same PCB area at fixed time intervals (e.g., every 5 seconds) to form a time-series image. The system employs sub-pixel-level image registration technology to ensure that images at different time points can be accurately aligned. The system uses frame difference or optical flow methods to analyze the changes in the circuit path at different time points, including parameters such as changes in circuit width, edge morphology, and surface oxidation. The system records the rate of change, trend, and magnitude of change for each circuit path to establish a dynamic change model of the circuit path.

[0041] Based on the change analysis results, the route path is divided into four states: "Incomplete," "In Progress," "Completed," and "Abnormal." The "Incomplete" state indicates the route is still under construction; the "In Progress" state indicates the route is basically formed but undergoing minor adjustments; the "Completed" state indicates the route is stable and meets design requirements; and the "Abnormal" state indicates unexpected changes to the route. The system updates the status of each route path in real time and records the time points and triggering conditions for status transitions, providing complete time-series data for subsequent analysis.

[0042] Based on the target usage information of the PCB (such as different application scenarios such as consumer electronics, automotive electronics, and aerospace), inspection weights are assigned to different areas. Safety-critical areas in automotive electronics and aerospace applications have higher weights. Considering the physical shape characteristics of the PCB, such as curved areas, connector areas, and high-density wiring areas, these areas are usually prioritized as critical inspection areas due to their high manufacturing difficulty. The final critical inspection areas are determined through a multi-factor decision algorithm that combines the circuit completion status, application weight, and shape characteristics. The system will assign a priority score to each critical inspection area to guide the allocation of subsequent inspection resources.

[0043] refer to Figure 3 In step S12, the specific steps are as follows:

[0044] S121: Collect each key detection area, determine multiple sub-detection areas based on the identification of key detection areas, determine the corresponding sub-line features based on the identification of multiple sub-detection areas, construct the corresponding line features based on the multiple sub-line features, and collect multiple line features;

[0045] S122: Determine the location of multiple line features based on the detection of multiple line features, determine the corresponding surrounding area based on the detection of the location of multiple line features, and determine the surrounding environmental features of multiple line features based on the identification of the surrounding area.

[0046] S123: Based on the morphological detection of multiple line features, determine the feature morphology of multiple line features, determine the first line anomaly feature distribution map based on the feature morphology and the location of multiple line features, determine the second line anomaly feature distribution map based on the location of multiple line features and the surrounding environmental features of multiple line features, and determine multiple first line anomaly features based on the first line anomaly feature distribution map and the second line anomaly feature distribution map.

[0047] In the embodiments of this application, the system obtains a list of determined key detection areas from step S113. Each area has a clear coordinate range and priority information. The key detection areas are precisely mapped to the actual PCB image using area coordinate mapping technology. Each key detection area contains the following information: area ID (e.g., R001), coordinate range (coordinates of the upper left and lower right corners), priority level (high / medium / low), detection frequency (e.g., every 5 minutes / every 15 minutes), and area type (e.g., power input area, signal transmission area, etc.).

[0048] An adaptive grid partitioning algorithm is adopted to divide the key detection region into multiple sub-detection regions based on its size and complexity. The grid size can be dynamically adjusted according to the importance of the region, with finer grids used for important regions. The partitioning principle is as follows: high priority regions use a 50m x 50m grid, medium priority regions use a 100m x 100m grid, and low priority regions use a 200m x 200m grid. For key detection regions with irregular shapes, a polygon clipping algorithm is used to ensure that the sub-detection regions are completely contained within the original region.

[0049] Multi-scale image processing algorithms are applied to each sub-detection region to identify specific sub-circuit features; a deep learning-based feature extraction network is used to identify various types of circuit features, including: line segments (straight lines, curves), corners (right angles, rounded corners, oblique angles), vias (through holes, blind holes, buried holes), solder pads (circular, square, elliptical), test points, and solder mask openings.

[0050] Graph theory algorithms and feature association techniques are used to combine scattered sub-circuit features into complete circuit features. A feature relationship graph is constructed, and the connection relationships between features are determined through graph matching and path search algorithms. If the endpoints of line segments in adjacent sub-detection areas are close and their directions are consistent, they are connected as the same circuit feature. According to PCB design rules, functionally related features (such as pads and connectors) are combined. Through topology checks and electrical rule verification, it is ensured that the constructed circuit features comply with design specifications.

[0051] Furthermore, the location of multiple line features is determined based on the detection of multiple line features, and the corresponding surrounding area is determined based on the detection of the location of multiple line features. The surrounding environmental features of multiple line features are determined based on the identification of the surrounding areas, which takes into account the overall consideration of the identification of surrounding areas and ensures the accuracy of the surrounding environmental features of multiple line features.

[0052] At this point, based on the multiple line features (such as line segments, pads, vias, etc.) extracted in step S121, the system uses image coordinate mapping technology to accurately determine the physical location (in millimeters) of each line feature on the PCB; the position of each line feature is represented by its center point coordinates (X,Y) and bounding box; the bounding box includes the minimum bounding rectangle or precise contour, used to describe the geometry of the line feature.

[0053] The system defines the surrounding area by extending a certain range (e.g., 1mm, 2mm, or 5mm) outward from each line feature as the center. The rules for dividing the surrounding area are as follows: high-density areas (e.g., signal transmission areas): the surrounding area is smaller (e.g., 1mm) to avoid interfering with other line features; low-density areas (e.g., power input areas): the surrounding area is larger (e.g., 5mm) to ensure coverage of potential environmental impacts. If other line features exist in the surrounding area, the system will automatically reduce the range to avoid overlap.

[0054] The system performs image analysis on each surrounding area to extract environmental features, including: physical environment features such as: density of adjacent lines (e.g., number of lines within 5mm), spacing between adjacent lines (minimum spacing, average spacing), and type of adjacent lines (power lines, signal lines, ground lines, etc.); electrical environment features such as: adjacent electrical networks (e.g., VCC3V3, GND, SIGNAL1), and potential crosstalk risks (e.g., high-speed signal lines adjacent to low-speed signal lines); and manufacturing environment features such as: etching uniformity (whether the etching depth of the surrounding area is consistent) and surface contamination (e.g., residual copper shavings, oxide layer).

[0055] Therefore, based on the morphological detection of multiple line features, the feature morphology of multiple line features is determined. Based on the feature morphology and location of multiple line features, a first line anomaly feature distribution map is determined. Based on the location and surrounding environmental features of multiple line features, a second line anomaly feature distribution map is determined. Based on the first and second line anomaly feature distribution maps, multiple first line anomaly features are determined. This approach takes into account both the first and second line anomaly feature distribution maps, ensuring the accuracy of multiple first line anomaly features.

[0056] At this point, the system performs high-precision morphological analysis on multiple line features (such as line segments, pads, vias, etc.) extracted in S121, using the following techniques: edge detection algorithms (such as Canny edge detection): extracting the contours of line features; geometric parameter calculation: measuring key parameters such as line width, line length, corner radius, and pad diameter; morphological operations (such as erosion and dilation): removing noise and optimizing feature shapes.

[0057] Characteristic morphology classification: Normal morphology: conforms to design specifications (e.g., line width 0.2mm ± 0.02mm); Abnormal morphology: includes line width that is too narrow / too wide, gaps, protrusions, and excessively sharp corners; At the same time, morphology detection parameters are collected, including: line width deviation (e.g., design value 0.2mm, actual measurement 0.15mm → deviation -25%); corner radius (e.g., design value 0.1mm, actual measurement 0.05mm → excessively sharp); pad roundness (e.g., design value 90%, actual measurement 70% → irregular).

[0058] The system combines the morphological detection results and location information of each line feature to generate the first line anomaly feature distribution map. At this time, the distribution of anomalies is represented by a heat map or scatter plot based on the PCB coordinate system. The degree of anomaly is coded by color (e.g., red: high anomaly; yellow: medium anomaly; green: normal). Key inputs: the location (X, Y) of the line feature; morphological anomaly score (e.g., line width deviation 25% → score 8.5 / 10).

[0059] Example of distribution map: Anomaly feature ID: AF001; Location: (30.456mm, 19.234mm); Anomaly type: Line width too narrow (design 0.2mm, actual measurement 0.15mm); Anomaly score: 8.5 / 10; Distribution map marker: highlighted in red.

[0060] The system combines the location of the line features with the surrounding environmental features extracted in S122 (such as adjacent lines, spacing, and electrical network) to generate a second line anomaly feature distribution map. The distribution map construction rules are as follows: focus on environmental risks (such as crosstalk, insufficient spacing, and pollution) and mark environmental anomalies with different colors (such as blue: crosstalk risk; purple: insufficient spacing). Key inputs are: the location (X, Y) of the line features and the surrounding environmental features (such as the number of adjacent lines, minimum spacing, and electrical network).

[0061] Example of distribution map: Anomaly ID: AF002; Location: (31.456mm, 19.334mm); Environmental anomaly type: Crosstalk risk (adjacent to 4 signal lines, minimum spacing 0.15mm); Anomaly score: 7.8 / 10; Distribution map marker: highlighted in blue.

[0062] The system integrates the distribution maps of the first line anomaly features (morphological anomalies) and the second line anomaly features (environmental anomalies), and determines the final anomaly features of the first line through weighted scoring or logical operations (such as AND / OR). Simultaneously, it prioritizes: high priority: morphological anomalies + environmental anomalies (e.g., excessively narrow line width + crosstalk risk); medium priority: morphological anomalies only or environmental anomalies only; low priority: minor anomalies (e.g., line width deviation <5%). A list of the first line anomaly features is collected, as shown in Table 1.

[0063] Table 1. List of Abnormal Characteristics of the First Line

[0064] Anomaly Feature ID Location (X,Y) Morphological abnormality types Environmental anomaly types Overall score Priority AF001 (30.456,19.234) Line width too narrow none 8.5 high AF002 (31.456,19.334) none Crosstalk risk 7.8 middle AF003 (29.456,18.234) Sharp corner Slight oxidation 6.2 middle

[0065] refer to Figure 4 In step S13, the specific steps are as follows:

[0066] S131: Collect multiple first line abnormal features and mark the positions corresponding to the multiple first line abnormal features. Determine the line processing steps corresponding to the first line abnormal features based on the positions of the multiple first line abnormal features and the multiple line features.

[0067] S132: Based on the traceability of the line processing steps corresponding to the first line abnormality features, determine the abnormal process information corresponding to the first line abnormality features, and determine the line abnormality type of the key detection area according to the abnormal process information corresponding to the first line abnormality features and the relative positions of multiple first line abnormality features.

[0068] S133: Determine the first line problem coefficient based on the type and location of line anomalies in the key detection area, determine the second line problem coefficient based on the type and location of line anomalies in the key detection area, determine the first line problem of the outer layer of the PCB based on the first line problem coefficient, the second line problem coefficient and the line problem mapping relationship.

[0069] In the embodiments of this application, multiple first line abnormality features are collected and the positions corresponding to the multiple first line abnormality features are marked. The line processing steps corresponding to the first line abnormality features are determined based on the positions of the multiple first line abnormality features and the multiple line features. This approach takes into account both the positions of the multiple first line abnormality features and the overall consideration of the multiple line features, ensuring the accuracy of the line processing steps corresponding to the first line abnormality features.

[0070] At this point, the system obtains multiple "first line abnormal features" from step S123. Each feature contains the following information: abnormal feature ID (e.g., AF001, AF002); abnormal type (e.g., "line width too narrow", "corner too sharp"); location coordinates (X, Y, unit: millimeters); using image marking technology, the location of these abnormal features is marked on the PCB image or CAD drawing in a visual manner, for example: marking the abnormal location with a red box or highlighted area; and attaching the abnormal ID and type next to the mark.

[0071] The system compares the location of abnormal features with the "process influence area" in the PCB manufacturing process to determine the processing process in which each abnormal feature most occurs. The "process-area mapping table" is used to predefine the main circuit areas affected by each process. For example: drilling process: affects vias and corner areas; etching process: affects line width and spacing; electroplating process: affects pads and vias; solder mask process: affects cover layer accuracy and alignment.

[0072] The process mapping table is shown in Table 2:

[0073] Table 2 Process Mapping Table

[0074] Process Name Area of ​​influence / feature type drilling Through holes, corners, and mechanical positioning holes plating Pads, vias, metallized hole walls Etching Line width, line spacing, line edge Solder mask Solder mask openings, solder mask coverage, exposed solder pad areas

[0075] If the abnormal feature appears in the corner area → match "drilling process"; if the abnormal feature is a line width problem → match "etching process"; if the abnormal feature is a pad problem → match "electroplating process".

[0076] Furthermore, based on the tracing of the processing steps corresponding to the first line abnormality feature, the abnormal process information corresponding to the first line abnormality feature is determined. Based on the abnormal process information corresponding to the first line abnormality feature and the relative positions of multiple first line abnormality features, the type of line abnormality in the key detection area is determined. This approach takes into account both the abnormal process information corresponding to the first line abnormality feature and the relative positions of multiple first line abnormality features, ensuring the accuracy of the type of line abnormality in the key detection area.

[0077] At this time, the system obtains the processing steps (such as etching, drilling, electroplating, etc.) corresponding to each abnormal feature of the first line from S131; through the process traceability mechanism, it retrieves the process parameters, equipment status, operation records and other data of the process, and identifies abnormal process information, including: process parameter deviation (such as excessive etching time, abnormal drilling speed), abnormal equipment status (such as nozzle blockage, drill bit wear), and human operation error (such as inaccurate alignment, incorrect parameter settings).

[0078] The system analyzes the relative positional relationships between multiple abnormal features of the first circuit (e.g., whether they are adjacent, in the same functional module, or regularly distributed). Combining abnormal process information, cluster analysis and pattern recognition are used to classify the abnormal features into different types of circuit abnormalities, such as: local process defects (e.g., uneven etching, drill hole misalignment), systemic equipment problems (e.g., narrow overall board linewidth, abnormal corner batches), and material or environmental factors (e.g., oxidation, contamination). Simultaneously, abnormal process information + relative positional relationship → abnormal type; therefore, longer etching time + multiple abnormalities in a banded distribution → uneven etching band; drill bit wear + abnormalities concentrated in the corner area → corner processing defects; low electroplating solution concentration + random distribution of abnormalities → unstable electroplating quality.

[0079] Specifically, assuming the key detection area of ​​a certain automotive control board is the power management module, AF001 corresponds to the etching process, and tracing back reveals that the etching time is 20% too long and the nozzle is partially blocked; AF002 corresponds to the drilling process, and tracing back reveals that the drill bit is worn, the hole diameter is too small, and the rotation speed is unstable; AF003 corresponds to the electroplating process, and tracing back reveals that the electroplating solution concentration is too low and the current fluctuation is too large; AF001 and AF003 are adjacent and located on the power input path, and the abnormal process information involves fluid parameters (etching solution, electroplating solution) → it is judged as a process fluid control abnormality; AF002 is located in the corner area, and the abnormal process information shows drill bit wear → it is judged as a corner processing defect; the types of circuit abnormalities in the output key detection area are: process fluid control abnormality and corner processing defect.

[0080] By tracing the process to extract abnormal process information and combining the relative positional relationship of abnormal features, abnormalities can be scientifically classified into different types of circuit abnormalities. This process can not only accurately locate the root cause of the problem (such as equipment, process, materials), but also provide a clear direction for subsequent process optimization and quality control. It is particularly suitable for the analysis and improvement of production abnormalities in high-reliability PCBs.

[0081] Therefore, a first circuit problem coefficient is determined based on the type and location of circuit anomalies in the key detection area. A second circuit problem coefficient is determined based on the type of circuit anomalies in the key detection area and multiple first circuit anomaly features. The initial circuit problem of the PCB's outer layer circuits is determined based on the first circuit problem coefficient, the second circuit problem coefficient, and the circuit problem mapping relationship. This approach considers the overall factors of the first circuit problem coefficient, the second circuit problem coefficient, and the circuit problem mapping relationship, ensuring the accuracy of the initial circuit problem of the PCB's outer layer circuits. Furthermore, the introduction of first circuit anomaly features, which considers the type and location of circuit anomalies in the key detection area and multiple first circuit anomaly features, improves the accuracy of the initial circuit problem of the PCB's outer layer circuits.

[0082] At this point, based on the type of line anomaly (such as process fluid control anomaly, corner machining defect) and location (such as power management module, signal transmission area) of the key detection area determined in S132, the system calculates the first line problem coefficient using a preset weighting coefficient table; the weighting coefficient table is shown in Table 3:

[0083] Table 3 Weighting Coefficients

[0084] Types of anomalies Regional location Weighting coefficient Process fluid control anomaly Power Management Module 0.8 Process fluid control anomaly Signal transmission area 0.6 Corner machining defects Power Management Module 0.7 Corner machining defects Signal transmission area 0.5

[0085] Calculation formula: First line problem coefficient = anomaly type weight × area location weight; The first line problem coefficient is a value determined based on the type of line anomaly and the area location of the key detection area. It is used to measure the severity of the anomaly in a specific area and is obtained by multiplying and summing the anomaly type weight and the area location coefficient.

[0086] The second line problem coefficient is determined based on the types of line anomalies in the key detection areas and multiple first line anomaly features. The system analyzes the number and severity of first line anomaly features (such as excessively narrow line width, excessively sharp corners, etc.) contained in each key detection area. The second line problem coefficient is calculated using an anomaly feature scoring table. The calculation formula is: Second line problem coefficient = Σ (severity score of anomaly feature) / total number of anomaly features. The second line problem coefficient is determined based on the distribution relationship between the types of line anomalies in the key detection areas and multiple first line anomaly features, reflecting the correlation and systematic impact of anomalies.

[0087] The system inputs the first and second line problem coefficients into the line problem mapping table to determine the final initial line problem; the line problem mapping table is collected, as shown in Table 4:

[0088] Table 4: Mapping Relationships of Line Problems

[0089] First line problem coefficient Second line problem coefficient Initial Line Issues ≥0.7 ≥0.6 A serious process abnormality requires immediate shutdown and maintenance. 0.5-0.7 0.4-0.6 Medium-level process abnormality, process parameters need to be adjusted. <0.5 <0.4 Minor process anomalies can continue production, but monitoring is required.

[0090] refer to Figure 5 In step S14, the specific steps are as follows:

[0091] S141: Collect target usage information of PCB, determine multiple sub-use information based on the division of target usage information of PCB, and determine the corresponding sub-use scenarios based on the identification of multiple sub-use information, so as to collect multiple sub-use scenarios of PCB.

[0092] S142: Determine abnormal matching factors based on multiple sub-use scenarios of the PCB and the initial circuit problem. Determine the corresponding abnormal trajectory based on each abnormal matching factor and the circuit shape of the outer layer circuit of the PCB. Predict multiple hidden problems of the outer layer circuit of the PCB based on the abnormal trajectory and the PCB problem database. At this time, perform multiple repeated queries along the multiple hidden problems.

[0093] S143: Trace multiple hidden problems and determine the corresponding review path based on the tracing of multiple hidden problems. Perform corresponding line review on the outer layer circuit of the PCB along each review path, and implement multiple controls on the outer layer circuit of the PCB in multiple dimensions to further identify multiple second line abnormal features. The multiple second line abnormal features are discovered after the first line abnormal features and are inconsistent with the first line abnormal features. The multiple second line abnormal features are added as new line abnormal features.

[0094] In the embodiments of this application, the system first collects the target usage information of the PCB. This information usually comes from product design documents, customer requirement specifications, or application scenario descriptions. The target usage information refers to the device or environment in which the PCB will ultimately be applied, such as automotive electronics, communication base stations, medical devices, industrial controllers, and consumer electronics products. The collection methods include: reading the "application field" field in the BOM or design document, receiving user input or system-preset usage scenario tags, and matching the usage information of similar products from the historical product database.

[0095] The system structurally breaks down the target usage information into multiple sub-use information. The breakdown is usually based on: functional module division (such as power module, signal processing module, control module), environmental condition differences (such as high temperature zone, normal temperature zone, high humidity zone), and electrical performance requirements (such as high frequency, high voltage, low noise). Each sub-use information contains the following attributes: sub-use information ID (such as SUI001), sub-use information name (such as "power management module"), target usage information (such as "automotive electronics"), environmental condition range (such as temperature range, humidity range), and electrical performance requirements (such as maximum current, operating frequency).

[0096] The system matches one or more sub-use scenarios for each sub-use information; a sub-use scenario is a description of the specific working environment faced by the sub-use information in actual application; the determination of sub-use scenarios includes: industry standards (such as the AEC-Q100 standard for automotive electronics), historical data (such as failure analysis reports of similar products), and expert knowledge bases (such as engineer experience rules).

[0097] Each sub-use scenario includes the following elements: scenario ID (e.g., SC001), scenario name (e.g., "high temperature environment in engine compartment"), sub-use information (e.g., "power management module"), environmental parameters (e.g., temperature range, vibration frequency), and reliability requirements (e.g., lifespan requirements, failure probability).

[0098] By systematically collecting information and dividing scenarios, the target usage information of PCBs is refined into multiple specific sub-use scenarios. This process provides an important scenario foundation for subsequent anomaly matching factor analysis (S142) and multiple repeated inspection mechanism (S143). In this way, the system can formulate differentiated detection strategies for different usage environments, which greatly improves the pertinence and effectiveness of PCB outer layer circuit detection.

[0099] Furthermore, the system first integrates multiple sub-use scenarios obtained in S141, as well as the initial line problems identified in S131 (such as excessively narrow line width, excessively sharp corners, etc.). Based on this information, the system determines the abnormal matching factors through a rule engine or machine learning model, that is, which environmental conditions or electrical characteristics are highly correlated with specific line abnormalities.

[0100] Abnormal matching factors include: environmental factors: temperature, humidity, vibration, corrosive gases, etc.; electrical factors: current density, voltage fluctuation, frequency characteristics, etc.; mechanical factors: stress concentration, bending deformation, coefficient of thermal expansion, etc.; and time factors: long-term aging, cyclic load, etc.

[0101] Specifically, if the sub-use scenario includes a high-temperature environment (such as an engine compartment) and the initial wiring problem is that the line width is too narrow, then the abnormal matching factors include: thermal expansion coefficient mismatch; excessive current density; thermal cycling fatigue; if the sub-use scenario includes a high-vibration environment (such as an ABS system) and the initial wiring problem is that the solder joint is cracked, then the abnormal matching factors include: mechanical stress concentration; vibration frequency resonance; insufficient solder joint strength.

[0102] The system analyzes the outer layer circuitry of the PCB (such as circuit routing, corner design, via locations, etc.), and combines anomaly matching factors to predict the anomaly development path, i.e., the anomaly trajectory. Anomaly trajectory analysis includes: thermal stress trajectory: analyzing the thermal expansion path of the circuitry at different temperatures, predicting thermal stress concentration areas, and determining the crack propagation direction; electrical stress trajectory: analyzing current distribution and hot spot areas, predicting electromigration paths, and determining short circuit or open circuit locations; mechanical stress trajectory: analyzing stress distribution during vibration or bending, predicting fatigue accumulation areas, and determining fracture locations.

[0103] Specifically, regarding the issue of excessively narrow line width on automotive ECU boards under high-temperature environments: Line morphology analysis: A 0.1mm wide power line was found to pass through multiple 90-degree corners, and this line is close to the heat-generating component (5mm distance); Abnormal trajectory identification: Thermal stress trajectory: Starting from the corner, it extends along the line direction; Electrical stress trajectory: Spreads from the center of the narrow line segment to both ends; Overall trajectory: Corner → Middle of the line → Connecting pad.

[0104] The system compares identified abnormal trajectories with a historical problem database to predict potential hidden problems. These problems are not yet apparent in current testing but will appear under specific usage conditions. The problem database includes: historical failure cases, manufacturing defect patterns, environmental test results, and simulation analysis data. The prediction method is causal chain analysis, which analyzes the chain reactions caused by abnormal trajectories to predict secondary problems. The predicted types of hidden problems are: potential cracks (not yet fully formed), early fatigue (not yet reaching failure), boundary failure (appearing only under extreme conditions), and cumulative damage (requiring time to accumulate).

[0105] The system develops a specific review plan for each hidden problem in the prediction and conducts multiple reviews. The review strategies include: magnified review: high-magnification microscopic examination of the predicted area; use of higher precision measuring equipment; and conditional simulation review.

[0106] Conduct tests under simulated usage conditions, such as high-temperature tests and vibration tests; review time series data: perform accelerated aging tests; regularly check the development of problems; conduct multi-dimensional cross-checks: combine electrical testing, physical inspection, and chemical analysis; verify the existence of problems from different perspectives.

[0107] Specifically, the PCB of a certain automotive ECU board is intended for automotive electronics, with sub-use scenarios including high-temperature environments in the engine compartment (SC001) and low-temperature environments during cold starts (SC002). The initial circuit problem was that the trace width was too narrow (AF001). The abnormal matching factors were identified as follows: High-temperature environment (SC001) + excessively narrow trace width → matching factors: mismatch in thermal expansion coefficients; excessive current density; thermal cycling fatigue; Low-temperature environment (SC002) + excessively narrow trace width → matching factors: low-temperature embrittlement; thermal shock damage.

[0108] Anomaly trajectory identified: Circuit morphology: 0.1mm wide power line with three 90-degree bends; Thermal stress trajectory: bends → middle of the circuit → pad connections; Low-temperature stress trajectory: uniform shrinkage throughout the circuit, but stress concentration at the bends; Predicted hidden problems: A database search revealed similar cases: Case #12345: Microcracks appeared on the same line width at high temperatures; Case #12346: 90-degree bends fractured after thermal cycling; Predicted hidden problems: IP001: Potential microcracks at the bends (appearing after high-temperature cycling); IP002: Early fatigue in the middle section of the circuit (appearing after long-term use); IP003: Boundary failure at pad connections (appearing under extreme temperatures).

[0109] Re-inspection of IP001: The corner area was examined using a 500x microscope; 100 cycles of thermal cycling from -40°C to 125°C were performed; Results: Micro-cracks (5μm) were found at two corners. Re-inspection of IP002: The internal structure of the circuit was examined using X-rays; 1000 hours of high-temperature aging test was performed; Results: Slight lattice changes were found in the middle of the circuit. Re-inspection of IP003: Shear strength test was performed; Extreme temperature shock (-55°C to 150°C) was simulated; Results: A 15% decrease in strength was found at the pad connection. Through multiple re-inspections, the system confirmed the existence of three hidden problems that are difficult to detect in conventional testing but lead to PCB failure under actual use conditions. These findings provide important basis for subsequent process improvement and design optimization.

[0110] Therefore, multiple hidden problems are traced, and corresponding review paths are determined based on the tracing of multiple hidden problems. The outer layer circuits of the PCB are reviewed along each review path, and multiple controls are implemented on the outer layer circuits of the PCB in multiple dimensions to further identify multiple second circuit anomalies. These second circuit anomalies are discovered after the first circuit anomalies and are inconsistent with the first circuit anomalies. These second circuit anomalies are introduced as new circuit anomalies.

[0111] At this point, the system conducts in-depth tracing of multiple implicit problems predicted in S142, analyzing the source, formation mechanism and influencing factors of each problem; the tracing process includes: process tracing: checking the processing steps that lead to the problem; material tracing: analyzing the correlation between material properties and the problem; design tracing: evaluating whether the design parameters are reasonable; environmental tracing: considering the impact of environmental factors on the problem.

[0112] Based on the tracing results, the system determines the optimal review path for each hidden problem. The review paths include: physical testing path: performing physical testing using specific equipment; electrical testing path: conducting electrical performance testing; environmental testing path: simulating specific environmental conditions for testing; and statistical analysis path: discovering problem patterns through data analysis.

[0113] Example of determining specific traceability and review paths:

[0114] Hidden Issue IP001: Potential microcracks at corners; Process traceability: Inappropriate etching process parameters, stress concentration during drilling; Material traceability: Insufficient copper foil ductility, mismatch between the thermal expansion coefficients of the substrate and copper foil; Design traceability: Corner design is too sharp, no rounded transition is used; Environmental traceability: Thermal cycling stress, mechanical vibration; Review path: Physical testing path: High-magnification microscope inspection + 3D contour measurement; Environmental testing path: Thermal cycling test + vibration test.

[0115] Hidden Issue IP002: Early fatigue in the middle section of the circuit; Process traceability: Insufficient electroplating uniformity, improper annealing process; Material traceability: Insufficient copper foil purity, improper additive ratio; Design traceability: Line width too narrow, current density too high; Environmental traceability: Long-term high temperature operation, current fluctuation; Review path: Electrical testing path: Current density test + temperature rise test; Statistical analysis path: Batch data comparison and analysis + failure mode analysis.

[0116] Hidden Issue IP003: Failure at the boundary of the pad connection; Process traceability: Inappropriate soldering temperature profile, unreasonable solder paste printing parameters; Material traceability: Deviation in solder composition, improper surface treatment of the pad; Design traceability: Pad size design is too small, unreasonable thermal design; Environmental traceability: Temperature shock, humidity effect; Review path: Physical testing path: Cross-section analysis + SEM inspection; Environmental testing path: Temperature shock test + Humidity test.

[0117] The system systematically reviews the outer layer circuitry of the PCB according to the established review path. The review process includes: Equipment preparation: Selecting appropriate testing equipment based on the review path; Sample preparation: Preparing PCB samples to be tested; Test execution: Executing the test according to the standard operating procedure; Data recording: Recording all data during the test in detail; Result analysis: Performing professional analysis on the test results.

[0118] The system manages the outer layer circuitry of the PCB from multiple dimensions to ensure comprehensive coverage of all anomalies. These multiple management dimensions include: spatial dimension: covering all areas of the PCB; temporal dimension: considering the entire product lifecycle; process dimension: monitoring all processing steps; material dimension: controlling all material properties; and environmental dimension: simulating various usage environments. Through the above multiple management and review processes, the system identifies several second-line anomaly features. These features are discovered after the first-line anomaly features and are inconsistent with the first-line anomaly features, thus being added as new line anomaly features.

[0119] The criteria for identifying abnormal features of the second line are: it must be discovered after the abnormal features of the first line; it must be inconsistent with the abnormal features of the first line (different in type, location, or manifestation); it must be confirmed through a formal detection process; and it must have a clear abnormal feature number and description.

[0120] First line anomaly characteristics (discovered in stage S131): AF001: Line width too narrow (design value 0.2mm, actual measurement 0.15mm); AF002: Corner too sharp (design R=0.1mm, actual measurement R=0.05mm); AF003: Pad size insufficient (design value 1.2mm, actual measurement 1.0mm).

[0121] Second line anomaly characteristics (newly discovered in stage S143): AF004: Microcracks at corners (3-5μm, appearing after thermal cycling); AF005: Lattice changes in the middle of the line (caused by uneven electroplating); AF006: Voids at pad connections (2-3μm, caused by soldering process); AF007: Oxidation on the surface of the line (discovered after environmental testing); AF008: Microbubbles in the insulation layer (discovered by cross-section analysis).

[0122] Characteristic analysis of the anomalies in the second circuit: AF004 is related to AF002 but different: AF002 is a design problem, while AF004 is a manufacturing problem; AF005 is related to AF001 but different: AF001 is a dimensional problem, while AF005 is a material structure problem; AF006 is related to AF003 but different: AF003 is a dimensional problem, while AF006 is a manufacturing defect; AF007 and AF008 are entirely new discoveries and are not directly related to the anomalies in the first circuit.

[0123] refer to Figure 6 In step S15, the specific steps are as follows:

[0124] S151: Collect multiple second line abnormal features and multiple first line abnormal features, and determine the line abnormal feature combination corresponding to each process node based on the multiple second line abnormal features, multiple first line abnormal features and the processing steps of the outer layer circuit of the PCB. The line abnormal feature combination includes the second line abnormal features and the first line abnormal features corresponding to the same process node.

[0125] S152: Based on the identification of the abnormal feature combination of the circuit corresponding to each process node, the abnormal event of the abnormal process node is determined. The first-level circuit problem is determined based on the location of the abnormal process node and the abnormal event. The second-level circuit problem is determined based on the relative distribution position between the abnormal event of the abnormal process node and the second-level circuit abnormal feature and the first-level circuit abnormal feature. The overall circuit problem of the outer layer of the PCB is determined based on the mapping relationship between the first-level circuit problem, the second-level circuit problem and the circuit problem.

[0126] S153: Based on the overall circuit problems of the outer layer of the PCB and the target usage information of the PCB, determine the circuit problems of the PCB in various application scenarios. Based on the circuit problems in each application scenario, the usage frequency of each application scenario and the overall circuit problems of the outer layer of the PCB, determine multiple sub-circuit problems and mark the priority of multiple sub-circuit problems.

[0127] In the embodiments of this application, the system collects multiple second line anomaly features (such as AF004, AF005, AF006, AF007, and AF008) from step S143. These features are newly added after multiple repeated checks and are anomalies that are inconsistent with the first line anomaly features. At the same time, the system collects multiple first line anomaly features (such as AF001, AF002, and AF003) from step S131. These features were discovered in the initial line problem detection. The system uniformly encodes and classifies these anomaly features for subsequent analysis.

[0128] The system maps each abnormal feature to a corresponding process node based on the PCB outer layer circuit processing flow. The process nodes include: inner layer pattern transfer, lamination, drilling, copper plating, outer layer pattern transfer, pattern electroplating, etching, solder mask, surface treatment, and molding. The system generates a circuit abnormal feature combination for each process node, which includes all first circuit abnormal features and second circuit abnormal features that appear in the same process node.

[0129] Assume the abnormal features collected by the system are as follows: First line abnormal features: AF001 (line width deviation), AF002 (over-etching), AF003 (short circuit); Second line abnormal features: AF004 (line width fluctuation), AF005 (copper foil blistering), AF006 (hole wall fracture), AF007 (pattern offset), AF008 (missing solder mask bridge).

[0130] Assume the PCB manufacturing process is as follows: inner layer pattern transfer, lamination, drilling, copper plating, outer layer pattern transfer, pattern electroplating, etching, solder mask, surface treatment, and forming; the system generates corresponding circuit abnormality feature combinations based on the mapping relationship between abnormal features and process nodes.

[0131] By systematically collecting abnormal features and mapping process nodes, each abnormal feature of the first and second lines can be accurately assigned to a specific processing process node, forming a combination of abnormal features. This process not only clearly displays the abnormal situation of each process node, but also provides key evidence for subsequent process traceability, abnormal location, and process optimization. In practical applications, this method is particularly suitable for the production anomaly analysis of high-reliability PCBs, effectively identifying weak links in the process, guiding process improvement, and improving product quality and production efficiency.

[0132] Furthermore, based on the combination of abnormal features corresponding to each process node determined in S151, the system identifies which process nodes have abnormal events. An abnormal event is when the first abnormal feature and the second abnormal feature appear simultaneously in the same process node, indicating that there is a systemic problem in that process node. The system evaluates the combination of abnormal features for each process node through a rule engine or machine learning model to determine the abnormal event.

[0133] The system identifies first-level circuit problems based on the location of the abnormal process node (in the PCB manufacturing process) and the severity of the abnormal event. First-level circuit problems refer to circuit problems directly caused by abnormal process nodes, which are usually related to process parameters, equipment status, or operating procedures. The system evaluates the abnormal event through preset rules or models to determine the type and severity of the first-level circuit problem.

[0134] Specifically, suppose the system identifies the following abnormal process nodes and their abnormal events: PN01 (inner layer pattern transfer): AF001 (linewidth deviation) and AF004 (linewidth fluctuation) occur simultaneously, and the abnormal event is "unstable pattern transfer process"; PN02 (lamination): AF002 (over-etching) and AF005 (copper foil blistering) occur simultaneously, and the abnormal event is "improper temperature and pressure control in lamination process"; PN03 (drilling): AF001 (linewidth deviation) and AF006 (hole wall fracture) occur simultaneously, and the abnormal event is "severe wear of drill bit in drilling process".

[0135] PN04 (Immersion Copper): AF007 (Pattern Misalignment) appears alone, with the anomaly being "insufficient alignment accuracy in the immersion copper process"; PN05 (Outer Layer Pattern Transfer): AF003 (Short Circuit) and AF008 (Missing Solder Mask Bridge) appear simultaneously, with the anomaly being "problems exist in both pattern transfer and solder mask processes"; PN07 (Etching): AF002 (Over-Etching) appears alone, with the anomaly being "improper control of etching process parameters"; PN08 (Solder Mask): AF008 (Missing Solder Mask Bridge) appears alone, with the anomaly being "improper exposure and development parameters in the solder mask process".

[0136] Assume the system identifies the following first-level circuit problems based on the location and events of the abnormal process nodes: PN01 (inner layer pattern transfer)'s "unstable pattern transfer process" results in "poor linewidth control" (severity: medium); PN02 (lamination)'s "improper temperature and pressure control during lamination process" results in "lamination defects" (severity: high); PN03 (drilling)'s "severe drill bit wear during drilling process" results in "poor drilling quality" (severity: high).

[0137] The "insufficient alignment accuracy of the copper plating process" in PN04 (immersion copper) leads to the first-level circuit problem of "poor pattern alignment" (severity: medium); the "problems in both pattern transfer and solder mask processes" in PN05 (outer layer pattern transfer) leads to the first-level circuit problem of "short circuit and poor solder mask" (severity: high); the "improper control of etching process parameters" in PN07 (etching) leads to the first-level circuit problem of "over-etching" (severity: medium); the "improper exposure and development parameters in the solder mask process" in PN08 (solder mask) leads to the first-level circuit problem of "missing solder mask bridges" (severity: medium).

[0138] The system analyzes abnormal events at abnormal process nodes, as well as the relative distribution (e.g., spatial distribution, temporal distribution, or process flow distribution) between the abnormal features of the second line and the abnormal features of the first line. The second-level line problem refers to the indirect line problem caused by the interaction between abnormal events and abnormal features, which is usually related to the synergy of the process flow or the superposition effect of abnormal features. The system determines the type and severity of the second-level line problem through spatial analysis, time series analysis, or process flow analysis.

[0139] Specifically, assuming the system determines the following second-level circuit problems based on the relative distribution of abnormal events and abnormal characteristics: The spatially adjacent issues of "unstable pattern transfer process" in PN01 (inner layer pattern transfer) and "problems in both pattern transfer and solder mask process" in PN05 (outer layer pattern transfer) result in the second-level circuit problem being "poor alignment of inner and outer layer patterns" (severity: high); the adjacent process flow issues of "improper temperature and pressure control in lamination process" in PN02 (lamination) and "improper control of etching process parameters" in PN07 (etching) result in the second-level circuit problem being "…". Lamination-etching coordination problem (Severity: High); The "severe wear of drill bit in drilling process" in PN03 (drilling) and the "insufficient alignment accuracy in copper plating process" in PN04 (copper plating) are adjacent in the process flow, resulting in a second circuit problem of "poor coordination between drilling and copper plating" (Severity: Medium); The "problems in both pattern transfer and solder mask process" in PN05 (outer layer pattern transfer) and the "improper exposure and development parameters in solder mask process" in PN08 (solder mask) are adjacent in the process flow, resulting in a second circuit problem of "poor coordination between pattern transfer and solder mask" (Severity: High).

[0140] The system integrates the first-level and second-level circuit problems and determines the overall circuit problems of the outer layer circuits of the PCB through a preset circuit problem mapping relationship (such as a rule base, machine learning model or expert system). The circuit problem mapping relationship refers to the rules or models that map the first-level and second-level circuit problems to the overall circuit problem, which usually includes the type, severity, scope of impact and solution of the problem. The system determines the type, severity and priority of the overall circuit problem through comprehensive evaluation.

[0141] Specifically, assuming the system is based on the mapping relationship between the first-level circuit problem, the second-level circuit problem, and the circuit problem, the following overall circuit problem of the outer layer of the PCB is determined: Overall circuit problem type: "Poor process coordination" (severity: high).

[0142] Main problems: Poor alignment of inner and outer layer patterns (caused by PN01 and PN05); poor lamination-etching coordination (caused by PN02 and PN07); poor drilling-copper plating coordination (caused by PN03 and PN04); poor pattern transfer-solder mask coordination (caused by PN05 and PN08); Affected area: the entire outer layer of the PCB; Solutions: Optimize pattern transfer process parameters (exposure, development); adjust the temperature and pressure of the lamination process; replace the drilling bit and optimize the drilling parameters; check the alignment system of the copper plating process; optimize the exposure and development parameters of the solder mask process.

[0143] By systematically identifying abnormal events, analyzing first-level circuit problems, analyzing second-level circuit problems, and determining overall circuit problems, this method can comprehensively assess process issues in the outer layer circuits of PCBs. It can identify not only circuit problems directly caused by abnormal process nodes (first-level circuit problems) but also indirect circuit problems caused by the interaction of abnormal events and abnormal features (second-level circuit problems). Finally, it determines the overall circuit problem through circuit problem mapping relationships. In practical applications, this method is particularly suitable for analyzing production anomalies in high-reliability PCBs, effectively identifying process coordination issues, guiding process improvements, and enhancing product quality and production efficiency.

[0144] Therefore, based on the overall circuit problems of the PCB's outer layer and the PCB's target usage information, the circuit problems of the PCB in various application scenarios are determined. Based on the circuit problems in each application scenario, the usage frequency of each application scenario, and the overall circuit problems of the PCB's outer layer, multiple sub-circuit problems are identified, and the priorities of these sub-circuit problems are marked. This approach considers the circuit problems in each application scenario, the usage frequency of each application scenario, and the overall circuit problems of the PCB's outer layer, ensuring the accuracy of the multiple sub-circuit problems. At the same time, a second circuit anomaly feature is introduced, and hidden problems in the PCB's outer layer are further controlled. This achieves a holistic consideration of the overall circuit problems of the PCB's outer layer and the PCB's target usage information, improving the accuracy of circuit problem prioritization.

[0145] At this point, based on the overall circuit problem of the PCB outer layer determined in S152 (such as "poor process coordination"), the system analyzes the specific manifestation of the overall circuit problem in different application scenarios in combination with the target usage information of the PCB (such as application scenario, environmental conditions, usage frequency, etc.); the system maps the overall circuit problem to each application scenario through the scenario analysis model and determines the specific circuit problem in each scenario.

[0146] The system integrates circuit problems from various application scenarios, combines the usage frequency of each scenario (e.g., high usage frequency in automotive electronics and low usage frequency in consumer electronics) with the overall circuit problems of the outer layer of the PCB, and identifies multiple sub-circuit problems. The system uses a problem clustering algorithm to merge similar or related circuit problems into sub-circuit problems, ensuring that each sub-circuit problem has a clear definition and scope.

[0147] The system calculates a priority score based on factors such as the severity, scope of impact, and frequency of use of each sub-line problem. The system uses a weighted scoring method, assigning weights to each factor to calculate a comprehensive score for each sub-line problem, and then ranking the scores to determine priority. Example: Assume the system uses the following weights and scoring criteria: Severity weight: 40% (High = 3 points, Medium = 2 points, Low = 1 point); Scope of impact weight: 30% (Large = 3 points, Medium = 2 points, Small = 1 point); Frequency of use weight: 30% (High = 3 points, Medium = 2 points, Low = 1 point).

[0148] Specifically, a priority score table is collected, as shown in Table 5:

[0149] Table 5 Priority Score Table

[0150] Sub-circuit problem Severity Scope of influence Frequency of use Overall score Priority SLP01 3 3 3 3.0 1 SLP04 3 2 2 2.4 2 SLP02 2 2 2 2.0 3 SLP05 2 2 1 1.7 4 SLP03 1 1 1 1.0 5

[0151] Priority marking results: Priority 1: SLP01 (Circuit stability issues under high temperature and high humidity environments); Priority 2: SLP04 (Pattern transfer process coordination issues); Priority 3: SLP02 (Circuit reliability issues under long-term operation); Priority 4: SLP05 (Lamination-etching process coordination issues); Priority 5: SLP03 (Circuit safety issues under static environments).

[0152] Please see Figure 7 , Figure 7 This is a schematic diagram of the structural composition of the PCB outer layer circuit detection system according to an embodiment of the present invention; the PCB outer layer circuit detection system includes:

[0153] The critical detection area module 21 is used to determine the circuit path based on the recognition of the circuit image of the outer layer circuit of the PCB after the bare copper circuit process is completed, and to mark multiple critical detection areas based on the monitoring of the circuit path.

[0154] The first line anomaly feature module 22 is used to determine multiple line features based on the identification of key detection areas, and to determine multiple first line anomaly features based on the location, feature shape and surrounding environmental features of the multiple line features.

[0155] The first-line problem module 23 is used to determine the type of line abnormality in the key detection area based on multiple first line abnormality characteristics and corresponding line processing procedures; and to determine the first-line problem of the outer layer line of the PCB based on the type of line abnormality, the location of the area and multiple first line abnormality characteristics of the key detection area.

[0156] The second line anomaly feature module 24 is used to predict multiple hidden problems of the outer layer circuit of the PCB based on the target usage information of the PCB, the initial line problem and the line shape of the outer layer circuit of the PCB, and to perform corresponding line review on the outer layer circuit of the PCB based on the tracing of multiple hidden problems, so as to add multiple second line anomaly features.

[0157] The circuit problem priority module 25 is used to determine the overall circuit problem of the outer layer circuit of the PCB based on multiple second circuit abnormality features and multiple first circuit abnormality features, and to determine the priority of sub-circuit problems based on the overall circuit problem of the outer layer circuit of the PCB and the target usage information of the PCB.

[0158] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method of detecting an outer layer circuit of a PCB, characterized by, include: After the bare copper circuit process is completed on the PCB, the circuit path is determined by recognizing the circuit image of the outer layer circuit of the PCB, and multiple key detection areas are marked by monitoring the circuit path. Based on the identification of key detection areas, multiple line features are determined, and multiple first line anomaly features are determined based on the location, feature morphology and surrounding environmental features of the multiple line features. Based on multiple first-line abnormality characteristics and corresponding line processing procedures, determine the types of line abnormalities in the key detection area; based on the types of line abnormalities, location of the area, and multiple first-line abnormality characteristics in the key detection area, determine the initial line problems of the outer layer lines of the PCB. Based on the target usage information of the PCB, the initial circuit problems, and the circuit configuration of the outer layer circuit of the PCB, multiple hidden problems of the outer layer circuit of the PCB are predicted. Based on the tracing of multiple hidden problems, the corresponding circuit review of the outer layer circuit of the PCB is carried out to add multiple second circuit anomaly features. The overall circuit problem of the outer layer of the PCB is determined based on multiple second-line anomaly characteristics and multiple first-line anomaly characteristics. The priority of sub-circuit problems is determined based on the overall circuit problem of the outer layer of the PCB and the target usage information of the PCB.

2. The method for detecting the outer layer circuitry of a PCB according to claim 1, characterized in that, After the bare copper circuitry process is completed on the PCB, the circuit path is determined based on the identification of the circuit image of the outer layer circuitry of the PCB, and multiple key detection areas are marked based on the monitoring of the circuit path, including: The system monitors the PCB manufacturing process in real time and marks the bare copper circuit process. Based on the bare copper circuit process, it triggers the positioning and shooting of the PCB to capture the circuit image of the outer layer circuit of the PCB. At this time, the outer layer circuit of the PCB is on the front of the circuit board and is captured by the camera. Image recognition is performed on the circuit image of the outer layer of the PCB. Multiple bare copper segments are identified based on the image recognition of the circuit image of the outer layer of the PCB. Corresponding circuit paths are constructed based on the multiple bare copper segments. At this time, the circuit paths are gradually improved according to the regularity of the multiple bare copper segments. The circuit path is monitored in real time, and changes in the circuit path at different times are collected. The completion status of each circuit path is determined based on the changes in the circuit path at different times. Multiple key detection areas are determined based on the completion status of each circuit path, the target usage information of the PCB, and its shape.

3. The method for detecting the outer layer circuitry of a PCB according to claim 1, characterized in that, The process involves identifying multiple line features based on the recognition of key detection areas, and determining multiple first line anomaly features based on the location, morphology, and surrounding environmental features of these features, including: Collect data from each key detection area, determine multiple sub-detection areas based on the identification of the key detection areas, determine the corresponding sub-line features based on the identification of the multiple sub-detection areas, and construct the corresponding line features based on the multiple sub-line features to collect multiple line features; The location of multiple line features is determined based on the detection of multiple line features, and the corresponding surrounding area is determined based on the detection of the location of multiple line features. The environmental features surrounding multiple line features are determined based on the identification of the surrounding area. Based on the morphological detection of multiple line features, the feature morphology of multiple line features is determined. Based on the feature morphology and location of multiple line features, a first line anomaly feature distribution map is determined. Based on the location and surrounding environmental features of multiple line features, a second line anomaly feature distribution map is determined. Based on the first and second line anomaly feature distribution maps, multiple first line anomaly features are determined.

4. The method for detecting the outer layer circuitry of a PCB according to claim 1, characterized in that, The type of line anomaly in the key detection area is determined based on multiple first line anomaly characteristics and corresponding line processing procedures. Based on the types and locations of line anomalies in key detection areas and multiple first line anomaly characteristics, the initial line problems of the outer layer lines of the PCB are determined, including: Collect multiple first line abnormal features and mark the locations corresponding to the multiple first line abnormal features. Determine the line processing steps corresponding to the first line abnormal features based on the locations of the multiple first line abnormal features and the multiple line features. Based on the tracing of the processing steps corresponding to the first line abnormality feature, the abnormal process information corresponding to the first line abnormality feature is determined. Based on the abnormal process information corresponding to the first line abnormality feature and the relative positions of multiple first line abnormality features, the type of line abnormality in the key detection area is determined.

5. The method for detecting the outer layer circuitry of a PCB according to claim 4, characterized in that, The type of line anomaly in the key detection area is determined based on multiple first line anomaly characteristics and corresponding line processing procedures. The determination of initial circuit problems in the outer layer of a PCB based on the types and locations of circuit anomalies in key detection areas and multiple first-order circuit anomaly characteristics also includes: The first line problem coefficient is determined based on the type and location of line anomalies in the key detection area. The second line problem coefficient is determined based on the type of line anomalies in the key detection area and multiple first line anomaly characteristics. The first line problem of the outer layer of the PCB is determined based on the first line problem coefficient, the second line problem coefficient and the line problem mapping relationship.

6. The method for detecting the outer layer circuitry of a PCB according to claim 1, characterized in that, The method predicts multiple hidden problems in the outer layer circuitry of the PCB based on the target usage information of the PCB, initial circuit problems, and the circuit configuration of the outer layer circuitry. Based on the tracing of these hidden problems, the outer layer circuitry of the PCB is re-examined accordingly to add multiple second circuit anomaly features, including: Collect target usage information of PCB, determine multiple sub-use information based on the division of target usage information of PCB, and determine the corresponding sub-use scenarios based on the identification of multiple sub-use information, so as to collect multiple sub-use scenarios of PCB; Based on multiple sub-use scenarios of the PCB and the initial circuit problem, anomaly matching factors are determined. Based on each anomaly matching factor and the circuit shape of the outer layer circuit of the PCB, the corresponding anomaly trajectory is determined. Based on the anomaly trajectory and the PCB problem database, multiple hidden problems of the outer layer circuit of the PCB are predicted. At this time, multiple repeated queries are performed along the multiple hidden problems.

7. The method for detecting the outer layer circuitry of a PCB according to claim 6, characterized in that, The method, based on the target usage information of the PCB, initial circuit problems, and the circuit configuration of the PCB's outer layer circuits, predicts multiple hidden problems in the PCB's outer layer circuits. Based on the tracing of these hidden problems, it performs corresponding circuit re-examinations of the PCB's outer layer circuits to add multiple second circuit anomaly features. This also includes: Multiple hidden issues are traced, and corresponding review paths are determined based on the tracing of multiple hidden issues. The outer layer circuits of the PCB are reviewed along each review path, and multiple controls are implemented on the outer layer circuits of the PCB in multiple dimensions to further identify multiple second circuit anomalies. The multiple second circuit anomalies are discovered after the first circuit anomalies and are inconsistent with the first circuit anomalies. The multiple second circuit anomalies are added as new circuit anomalies.

8. The method for detecting the outer layer circuitry of a PCB according to claim 1, characterized in that, The process of determining the overall circuit problem of the PCB's outer layer circuitry based on multiple second-line anomaly characteristics and multiple first-line anomaly characteristics, and determining the priority of sub-circuit problems based on the overall circuit problem of the PCB's outer layer circuitry and the target usage information of the PCB, includes: Collect multiple second-line abnormal features and multiple first-line abnormal features. Based on the multiple second-line abnormal features, multiple first-line abnormal features and the processing steps of the outer layer circuit of the PCB, determine the combination of line abnormal features corresponding to each process node. The combination of line abnormal features includes the second-line abnormal features and the first-line abnormal features corresponding to the same process node. The abnormal events of abnormal process nodes are determined by identifying the combination of abnormal features corresponding to each process node. The first level of circuit problem is determined based on the location of the abnormal process node and the abnormal event. The second level of circuit problem is determined based on the relative distribution of the abnormal events of the abnormal process node and the second level of circuit abnormal features with the first level of circuit abnormal features. The overall circuit problem of the outer layer of the PCB is determined based on the mapping relationship between the first level of circuit problem, the second level of circuit problem and the circuit problem.

9. The method for detecting the outer layer circuitry of a PCB according to claim 8, characterized in that, The process of determining the overall circuit problem of the outer layer of the PCB based on multiple second circuit anomaly features and multiple first circuit anomaly features, and determining the priority of sub-circuit problems based on the overall circuit problem of the outer layer of the PCB and the target usage information of the PCB, further includes: Based on the overall circuit problems of the outer layer of the PCB and the target usage information of the PCB, determine the circuit problems of the PCB in various application scenarios. Based on the circuit problems in each application scenario, the usage frequency of each application scenario and the overall circuit problems of the outer layer of the PCB, determine multiple sub-circuit problems and mark the priority of multiple sub-circuit problems.

10. A detection system for the outer layer circuitry of a PCB, characterized in that, The PCB outer layer circuit detection system is applied to the PCB outer layer circuit detection method as described in any one of claims 1-9, and the PCB outer layer circuit detection system includes: The critical inspection area module is used to determine the circuit path based on the recognition of the circuit image of the outer layer circuit of the PCB after the bare copper circuit process is completed, and to mark multiple critical inspection areas based on the monitoring of the circuit path. The first line anomaly feature module is used to determine multiple line features based on the identification of key detection areas, and to determine multiple first line anomaly features based on the location, feature shape and surrounding environmental features of the multiple line features. The initial circuit problem module is used to determine the type of circuit abnormality in the key inspection area based on multiple first circuit abnormality characteristics and corresponding circuit processing procedures; and to determine the initial circuit problem of the outer layer circuit of the PCB based on the type of circuit abnormality, the location of the area, and multiple first circuit abnormality characteristics of the key inspection area. The second line anomaly feature module is used to predict multiple hidden problems of the outer layer circuit of the PCB based on the target usage information of the PCB, the initial line problem, and the line shape of the outer layer circuit of the PCB. Based on the tracing of multiple hidden problems, the corresponding line review of the outer layer circuit of the PCB is carried out to add multiple second line anomaly features. The circuit problem priority module is used to determine the overall circuit problem of the outer layer circuit of the PCB based on multiple second circuit anomaly characteristics and multiple first circuit anomaly characteristics, and to determine the priority of sub-circuit problems based on the overall circuit problem of the outer layer circuit of the PCB and the target usage information of the PCB.

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