Ultrasonic rapid jet flow flame image acquisition and processing system and method based on FPGA
The FPGA-based supersonic jet flame image acquisition and processing system solves the problems of high latency and high energy consumption of traditional processing methods, realizes real-time image acquisition and processing, and is suitable for supersonic jet experiments.
Patent Information
- Application Number
- CN202511064460.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-11-14
AI Technical Summary
Traditional flame image processing methods suffer from high processing latency, slow response speed, and high energy consumption, making it difficult to meet the "simultaneous processing while sampling" requirements in supersonic jet experiments.
An FPGA-based supersonic jet flame image acquisition and processing system is adopted, including an image acquisition module, a CameraLink Decode module, a PingPong Buffer module, and an Accelerator module, to realize real-time acquisition, processing, and feature calculation of image data.
It achieves real-time acquisition and processing of high frame rate and high resolution images with a processing latency of less than 2ms, meeting experimental requirements. The system is highly stable, has low power consumption, and is suitable for experimental platforms with limited size and power sensitivity.
Smart Images
Figure CN120953676A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of digital image processing technology, specifically relating to an FPGA-based accelerated acquisition technology for flame images. Background Technology
[0002] In supersonic jet experiments, high-speed acquisition of flame images is crucial for studying combustion instability and thermal structural evolution. However, these images are characterized by high frame rates, high resolution, and extremely high data throughput, often resulting in frame drops or delays due to insufficient bandwidth in ordinary acquisition links. CameraLink, as an industrial-grade high-speed image interface, possesses high bandwidth and low latency, effectively meeting the real-time acquisition requirements of flame images.
[0003] However, after acquisition, a large amount of image data needs to be processed and analyzed in real time. Traditional CPU or GPU-based processing methods suffer from high processing latency, slow response speed, and high energy consumption, making it difficult to support the "process while acquiring" requirements in experiments. In contrast, FPGAs have advantages such as hardware-level parallel processing capabilities, low latency, and high customizability, making them very suitable for building accelerated processors in supersonic jet image acquisition systems to achieve high-speed and stable image processing functions. Summary of the Invention
[0004] This invention provides a supersonic jet flame image acquisition and processing system and method based on FPGA. Its purpose is to solve the problems of high processing latency, slow response speed and high energy consumption in traditional flame image processing methods, which make it difficult to support the "acquisition and processing at the same time" requirements in experiments.
[0005] The FPGA-based supersonic jet flame image acquisition and processing system proposed in this invention includes: Image acquisition module: used to acquire images of supersonic jet flames and convert the optical signals of supersonic jet flames into electrical signals; CameraLink Decode module: Used to receive three parallel data streams, perform bit stitching and format conversion, and output standardized image data; PingPong Buffer module: used for transmitting image data; The Accelerator module is used for feature calculation, distance measurement, and index matching of image data.
[0006] Furthermore, a preferred solution is provided: the image acquisition module converts the ultrasonic jet flame light signal into an electrical signal and then outputs an image data stream using the CameraLink protocol.
[0007] Furthermore, a preferred solution is provided: the output of the image data stream of the CameraLink protocol is implemented using the CameraLink interface.
[0008] Furthermore, a preferred solution is provided: the CameraLink Decode module includes: The system reset unit performs a reset when the level is low. The bit splicing logic unit is used to splice three parallel data streams into a unified image frame data. The data validity flag unit outputs a high-level pulse after a frame of image is stitched together, indicating that the data is available.
[0009] Furthermore, a preferred embodiment is provided: the PingPong Buffer module includes: The read / write counting unit uses dual counters for coordinated scheduling to achieve asynchronous read / write across clock domains for the dual buffer units; The dual-buffer unit, consisting of Buffer_A and Buffer_B, enables data acquisition and processing through an alternating read-write mechanism.
[0010] The first multiplexer switches the data output path based on the cache state.
[0011] Furthermore, a preferred solution is provided: the cache depth of the dual cache unit is configured to reserve 20% redundant space according to the image frame size.
[0012] Furthermore, a preferred embodiment is provided: the Accelerator module includes: Pipeline pixel accumulator is used to perform parallel accumulation and summation of pixels in a local region of the input image; The division and distance calculation unit calculates the Euclidean distance between the flame pixel and the reference feature based on the pixel accumulation result; The second multiplexer is used to select the minimum distance feature and continuously update the minimum distance in the register; Registers are used to perform register pacing on feature data to ensure timing convergence. BRAM storage units are used to store feature vectors and map them to output the final feature values.
[0013] The FPGA-based supersonic jet flame image acquisition and processing method proposed in this invention is implemented using the FPGA-based supersonic jet flame image acquisition and processing system described above in combination with any one or more of the above-mentioned schemes. The method includes: Acquire images of supersonic jet flames and convert the images into image data streams using the CameraLink protocol; The CameraLink Decode module is used to perform bit-by-bit stitching and format conversion on the image data stream, and output standardized image data. The PingPong Buffer module is used to implement double-buffered storage and transmission of image data; The Accelerator module is used to perform feature calculation, distance measurement, and index matching on the image data to obtain the output results.
[0014] Compared with the prior art, the advantages of the present invention are: 1. By integrating the CameraLink high-speed interface, the system supports real-time acquisition of high frame rate and high resolution images, effectively avoiding image frame loss and data transmission bottlenecks, and ensuring the complete recording of the jet combustion process; 2. The system proposed in this invention uses an FPGA hardware accelerator to realize on-site processing of image data after acquisition, with a processing delay of less than 2ms, which meets the real-time requirements for image analysis in supersonic combustion experiments. 3. This invention adopts a Ping-Pong caching mechanism, which solves the problem of traditional FIFO being easily blocked under high-frequency data streams, and realizes end-to-end uninterrupted operation of acquisition, processing and output, significantly improving the overall system stability; 4. The system proposed in this invention adopts a modular architecture, which facilitates integration with other image sources, analysis modules or host computer platforms, adapts to different experimental conditions and algorithm requirements, and has a wide range of application scenarios; 5. Compared with traditional GPU acceleration solutions, the FPGA in the system proposed in this invention has lower power consumption and smaller size while ensuring computing performance. It is suitable for deployment in experimental platforms with limited size and power sensitivity, and has high engineering practical value.
[0015] This invention is applicable to high-frequency data stream acquisition and processing scenarios. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the FPGA-based supersonic jet flame image acquisition and processing system according to Embodiment 2 of the present invention. In this diagram, Carrier Board represents the carrier board, Cameralink Cable represents the Cameralink cable, Hardware Connector represents the hardware connector; FPGA Core Module represents the FPGA core board, CameralinkDecode represents the Cameralink decoder, Buffer_A represents buffer A, Buffer_B represents buffer B, MUX represents a multiplexer, rdata_cnt represents a read data counter, and Accelerator represents an accelerator. Figure 2 This is a functional structure diagram of the CameraLink decoding module according to specific embodiment two of the present invention; Figure 3 This is a schematic diagram of the PingPong cache structure according to the second specific embodiment of the present invention; Figure 4 This is a block diagram of the accelerator module structure according to a second specific embodiment of the present invention. Detailed Implementation
[0017] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of this application with unnecessary detail.
[0018] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.
[0019] It should also be understood that the terminology used in this application specification is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this application specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.
[0020] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0021] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.
[0022] Implementation Method 1: An FPGA-based supersonic jet flame image acquisition and processing system, the system comprising: Image acquisition module: used to acquire images of supersonic jet flames and convert the light signals of the supersonic jet flames into electrical signals; after converting the light signals of the supersonic jet flames into electrical signals, the image acquisition module outputs an image data stream using the CameraLink protocol; specifically, the output of the image data stream using the CameraLink protocol is implemented using the CameraLink interface; CameraLink Decode module: Used to receive three parallel data streams, perform bit-by-bit concatenation and format conversion, and output standardized image data, including: The system reset unit performs a reset when the level is low. The bit splicing logic unit is used to splice three parallel data streams into a unified image frame data. The data validity flag unit outputs a high-level pulse after a frame of image is stitched together, indicating that the data is available.
[0023] PingPong Buffer module: Used for transferring image data, including: The read / write counting unit uses dual counters for coordinated scheduling to achieve asynchronous read / write across clock domains for the dual buffer units; The dual-buffer unit, comprising Buffer_A and Buffer_B, implements data acquisition and processing through an alternating read-write mechanism. The buffer depth of the dual-buffer unit is configured with a 20% redundancy space reserved according to the image frame size.
[0024] The first multiplexer switches the data output path based on the cache state.
[0025] The Accelerator module is used for feature calculation, distance measurement, and index matching of image data, including: Pipeline pixel accumulator is used to perform parallel accumulation and summation of pixels in a local region of the input image; The division and distance calculation unit calculates the Euclidean distance between the flame pixel and the reference feature based on the pixel accumulation result; The second multiplexer is used to select the minimum distance feature and continuously update the minimum distance in the register; Registers are used to perform register pacing on feature data to ensure timing convergence. BRAM storage units are used to store feature vectors and final feature values.
[0026] The system proposed in this embodiment achieves the following functions: high-speed image data acquisition and synchronous decoding, real-time image processing and feature extraction, double buffer scheduling and continuous data stream guarantee, modular design and interface compatibility, low power consumption, high stability and customizability.
[0027] Implementation Method Two: Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 This implementation method is described below.
[0028] This embodiment is a further illustrative example of the FPGA-based supersonic jet flame image acquisition and processing system described in Embodiment 1.
[0029] The FPGA-based supersonic jet flame image acquisition and processing system described in this embodiment comprises four parts: an image acquisition module, a transmission interface module, an FPGA decoding and buffering module, and an accelerator processing module, with the connections as follows: Figure 1 As shown.
[0030] The image acquisition module includes: Flame Imaging and Acquisition Unit: Through a high-speed, high-sensitivity camera (adapted to the transient and high-temperature characteristics of supersonic jet flames), the flame light signal is converted into an electrical signal, and an image data stream with CameraLink protocol is output.
[0031] CameraLink Cable: As a high-speed transmission medium, it supports the Base, Medium, or Full modes of the CameraLink protocol to meet different resolution and bandwidth requirements (up to 6.4Gbps), ensuring uncompressed and low-latency transmission of image data.
[0032] Hardware Connector: Enables physical layer connection for CameraLink, providing reliable mechanical and electrical interfaces, adaptable to industrial-grade vibration and temperature environments (-40℃~125℃), and ensures signal stability under extreme conditions.
[0033] The internal structure and signal connection method of the CameraLink Decode module described in this embodiment are as follows: Figure 2 As shown, this module, serving as a key conversion unit for image data streams from the physical layer to the processing layer, primarily performs bit-by-bit concatenation and format conversion on the three parallel data streams received from the CameraLink interface, outputting standardized image data for use by the next-level processing module.
[0034] The CameraLink Decode module includes the following signal interfaces: rst_n: System reset signal, active low; clk_85: Working clock signal; this module operates within the 85MHz clock domain. data_in_x, data_in_y, data_in_z: Three 28-bit image data inputs from the CameraLink physical layer, corresponding to the X, Y, and Z channels respectively; BitConcat: Bit concatenation logic unit, used to concatenate three 28-bit data streams into a unified 80-bit image frame data; data_out_80bit: Output stitched image data, with a data width of 80 bits; hw_vld: Data valid flag. When a frame of image is stitched together, this signal outputs a high-level pulse to indicate that the data is available.
[0035] As the front-end processing part of the image acquisition system, this module has the following technical effects: it adapts to multiple working modes of CameraLink and realizes three-channel parallel data synchronization; it provides a unified bit width output, which is convenient for subsequent buffering or acceleration modules to process; it ensures the stability of data timing and control signals, and improves the reliability of system acquisition; it realizes data decoding and stitching operations through pure hardware logic, and can complete one stitching in a single cycle with latency ≤ 1 cycle.
[0036] The internal structure and signal connection method of the PingPong Buffer module for image data transfer buffering described in this embodiment are as follows: Figure 3 As shown, this module is located between the CameraLink decoding module and the image accelerator, and is responsible for intermediate storage and flow control of image data. Its design philosophy is to achieve zero-wait, non-blocking data transmission by using a dual-buffer structure for alternating writing and reading.
[0037] The PingPong Buffer module includes the following units: Read / write counting unit: w_cnt counts the number of pixels in the input data frame when hw_vld = 1, generates w_fifo_vld, and controls the writing of data to Buffer_A / B; r_cnt counts the number of pixels read out, generates r_fifo_vld, controls the MUX switching and data output rhythm, and matches the accelerator processing rate.
[0038] Dual buffer units (Buffer_A / Buffer_B): Employ dual FIFOs to support asynchronous read / write across clock domains. During write operations, data_in_80bit is written to the currently active buffer under the control of w_fifo_vld; during read operations, data not currently written to the buffer is read out to data_out under the control of r_fifo_vld. The buffer depth is configured according to the image frame size, reserving 20% redundant space to handle sudden data bursts and prevent overflow.
[0039] The first multiplexer (MUX) is controlled by r_cnt and the buffer state to switch the data output path. When Buffer_A is writing and Buffer_B is reading, the MUX selects Buffer_B for output; when Buffer_A is reading and Buffer_B is writing, the MUX selects Buffer_A for output. The switching condition is determined by r_cnt detecting when the buffer is empty or w_cnt detecting when the buffer is full, achieving a ping-pong flow of "one slow write, one slow read".
[0040] The cross-clock domain coordination process of this module is as follows: During the write phase (clk_85 domain), when hw_vld = 1, w_cnt counts, and data_in_80 bits are written to the currently active buffer; after a frame of data is full, w_cnt is cleared, triggering the buffer switching flag, preparing to write to another buffer. During the read phase (clk_200 domain), r_cnt counts, and data from the currently inactive buffer is read and output to data_out via the MUX; after the buffer is empty, r_cnt is cleared, triggering the MUX switch, and reading the newly active buffer begins. Asynchronous FIFO and handshake signals ensure state alignment between the clk_85 and clk_200 domains, guaranteeing conflict-free ping-pong switching.
[0041] The structural block diagram of the Accelerator module described in this embodiment is as follows: Figure 4 As shown, this module mainly implements feature calculation, distance measurement, and index matching functions for flame image data. This module adopts a "pipeline pixel accumulation + parallel distance calculation + LUT mapping" architecture, which features strong parallel processing capabilities and low latency, making it suitable for real-time processing of high-speed continuous image data of supersonic jet flames.
[0042] The Accelerator module consists of the following functional components: The pipelined pixel accumulator performs parallel accumulation and summation of pixels in local regions of the input image, providing foundational data for subsequent feature calculations. It employs a deep pipeline architecture, with each pipeline stage processing a partial summation of a pixel window; it supports configurable window size to adapt to different scales of flame features.
[0043] The division (DIV) unit and distance calculation (Sub / Square / Add) unit: Based on the pixel accumulation result, calculate the Euclidean distance between the flame pixel and the "reference feature". The formula is simplified as follows: , in, This represents the calculated value of the current channel. This represents the value in the BRAM corresponding to the current channel.
[0044] DIV normalizes the accumulated pixel values and converts them into average pixel intensity; The distance calculation unit includes: The subtractor Sub calculates the difference between the current pixel and the reference feature; The Square function squares the difference. The accumulator Add calculates the sum of squared results, approximate distance calculation.
[0045] The "v channel" and "r channel" in the module are completely parallel and independently process different feature dimensions of the same frame image.
[0046] The second multiplexer (MUX) and register (Reg): The MUX is controlled by the comparison result between dist_v and dist_v_min, and continuously updates the minimum distance dist_v_min in Reg. Reg performs register pacing on the feature data to ensure pipeline timing convergence and avoid metastability.
[0047] BRAM storage unit: Stores feature vectors and final feature values, supports online updates, and adapts to different jet conditions; uses the idx corresponding to the minimum value of dist_v and dist_r calculated in a complete frame period as an index to map and output the final feature value.
[0048] Implementation Method 3: This embodiment is a further illustrative example of the FPGA-based supersonic jet flame image acquisition and processing system described in Embodiment 1 and Embodiment 2.
[0049] The system uses a CameraLink industrial camera to capture supersonic jet flames at high speed and transmits the image data to the FPGA acquisition system via a CameraLink cable. The hardware connector receives CameraLink data and sends it to the CameraLink decoding module inside the FPGA; The CameraLink decoding module receives three 28-bit data streams, data_in_x, data_in_y, and data_in_z, respectively. It performs bit concatenation using the BitConcat unit, outputs standardized image data data_out_80bit, and outputs a data validity signal hw_vld after each frame of data is concatenated. The stitched 80-bit image data is sent to the Ping-Pong buffer module. If the current write enable is valid (w_fifo_vld), the data is written to the currently active buffer unit (Buffer_A or Buffer_B). The number of writes is controlled by w_cnt. When the cache is full, the system switches the cache state through the data_cnt control signal, and at the same time sends the original cached data into the image accelerator module through the first multiplexer MUX. The image accelerator module starts computing under the control of the clk_200 clock. First, it performs pipelined accumulation processing on the image data through the PipelinedPixelAccumulator to form several image feature vectors. The feature vector is fed into the normalization processing module, and the pixel data is standardized by the divider (DIV). Then, it is subtracted, squared and summed with the preset template data in BRAM channel by channel to form the Euclidean distance metric values dist_v and dist_r. After calculating each set of distances, compare it with the minimum distances dist_v_min and dist_r_min recorded in the previous frame. If the current distance is smaller, update the corresponding index register value Idx. The index value Idx is converted by BRAM and output to the output_v and output_r interfaces for subsequent image classification, object extraction or other application processing.
[0050] Implementation Method Four: A method for image acquisition and processing of supersonic jet flames based on FPGA, wherein the method is implemented using the supersonic jet flame image acquisition and processing system based on FPGA as described in any one of embodiments one to three, and the method includes: Acquire images of supersonic jet flames and convert the images into image data streams using the CameraLink protocol; The CameraLink Decode module is used to perform bit-by-bit stitching and format conversion on the image data stream, and output standardized image data. The PingPong Buffer module is used to implement double-buffered storage and transmission of image data; The Accelerator module is used to perform feature calculation, distance measurement, and index matching on the image data to obtain the output results.
Claims
1. An FPGA-based supersonic jet flame image acquisition and processing system, characterized in that, The system includes: Image acquisition module: used to acquire images of supersonic jet flames, convert the optical signals of supersonic jet flames into electrical signals, and obtain three parallel data streams; CameraLink Decode module: Used to receive three parallel data streams, perform bit stitching and format conversion, and output standardized image data; PingPong Buffer module: used for transmitting image data; The Accelerator module is used for feature calculation, distance measurement, and index matching of image data.
2. The FPGA-based supersonic jet flame image acquisition and processing system according to claim 1, characterized in that, The image acquisition module converts the supersonic jet flame light signal into an electrical signal and outputs an image data stream using the CameraLink protocol as three parallel data streams.
3. The FPGA-based supersonic jet flame image acquisition and processing system according to claim 2, characterized in that, The output of image data streams using the CameraLink protocol is implemented through the CameraLink interface.
4. The FPGA-based supersonic jet flame image acquisition and processing system according to claim 1, characterized in that, The CameraLink Decode module includes: The system reset unit performs a reset when the level is low. The bit splicing logic unit is used to splice three parallel data streams into a unified image frame data. The data validity flag unit outputs a high-level pulse after a frame of image is stitched together, indicating that the data is available.
5. The FPGA-based supersonic jet flame image acquisition and processing system according to claim 1, characterized in that, The PingPong Buffer module includes: The read / write counting unit uses dual counters for coordinated scheduling to achieve asynchronous read / write across clock domains for the dual buffer units; The dual-buffer unit, consisting of Buffer_A and Buffer_B, enables data acquisition and processing through an alternating read-write mechanism. The first multiplexer switches the data output path based on the cache state.
6. The FPGA-based supersonic jet flame image acquisition and processing system according to claim 5, characterized in that, The cache depth of the dual-buffer unit is configured with 20% redundancy space based on the image frame size.
7. The FPGA-based supersonic jet flame image acquisition and processing system according to claim 1, characterized in that, The Accelerator module includes: Pipeline pixel accumulator is used to perform parallel accumulation and summation of pixels in a local region of the input image; The division and distance calculation unit calculates the Euclidean distance between the flame pixel and the reference feature based on the pixel accumulation result; The second multiplexer is used to select the minimum distance feature and continuously update the minimum distance in the register; Registers are used to perform register pacing on feature data to ensure timing convergence. BRAM storage units are used to store feature vectors and map them to output the final feature values.
8. A method for image acquisition and processing of supersonic jet flames based on FPGA, characterized in that, The method is implemented using the FPGA-based supersonic jet flame image acquisition and processing system as described in any one of claims 1-7, and the method includes: Acquire images of supersonic jet flames and convert the images into image data streams using the CameraLink protocol; The CameraLink Decode module is used to perform bit-by-bit stitching and format conversion on the image data stream, and output standardized image data. The PingPong Buffer module is used to implement double-buffered storage and transmission of image data; The Accelerator module is used to perform feature calculation, distance measurement, and index matching on the image data to obtain the output results.