Lightweight encryption and decryption method

Abstract

The invention relates to the technical field of information security, in particular to a lightweight encryption and decryption method, which comprises the following steps: acquiring a continuous binary data stream of a sensor and segmenting the continuous binary data stream into fixed-length groups; calling a pre-generated round key sequence and a whitening key, wherein the round key sequence is generated through master key shift operation and round constant iteration; performing XOR operation on the grouped data and the whitening key to output initial confusion data; segmenting the initial confusion data into four equal-length sub-segments to execute multiple rounds of iterative processing, wherein each round comprises 16-bit modular addition operation and fixed-bit cyclic shift; xOR is carried out on the shifted data and a current round key, a sub-segment state is updated according to a preset branch processing rule, and linear transformation is carried out on the updated state by adopting a self-inverse matrix; the last-round output sub-segments are spliced into a ciphertext to be transmitted to an execution mechanism; during decryption, reversely calling the round key sequence, and multiplexing the self-inverse matrix to execute inverse transformation and reverse operation to recover original data. The problem of high encryption delay of industrial control equipment is solved.

Description

Technical Field

[0001] This invention relates to the field of information security technology, and in particular to a lightweight encryption and decryption method. Background Technology

[0002] Lightweight cryptography is a category of symmetric encryption algorithms developed for hardware environments with limited computing power and memory. It is mainly used in IoT devices or micro sensor nodes. Existing encryption standards such as AES often require a lot of computing resources, which may lead to processing delays, excessive power consumption, and potential security vulnerabilities, and cannot be adapted to the constraints of low-power devices. Lightweight alternatives refine algorithm logic, reduce repetitive operation steps, and optimize data paths to maintain sufficient resistance to attacks with lower overhead, balancing security requirements and system resource limitations, thereby supporting trusted data protection and authentication mechanisms in edge computing and embedded applications.

[0003] Lightweight block cipher algorithms such as LBcipherB are designed for resource-constrained industrial control embedded environments. They use a generalized Feistel structure to process fixed-length block data. After the plaintext is input, the encryption process involves multiple rounds of iterative processing. Each round introduces a round key to drive a nonlinear F function to perform modular addition, cyclic shifting, and XOR operations, thus obfuscating and spreading the complete data. Existing cryptographic algorithms such as AES or RSA suffer from high computational overhead and energy consumption due to their complex operational structures (e.g., relying on multiple iterative operations and nonlinear transformations). When executed on resource-constrained industrial control embedded devices such as programmable logic controllers, the algorithm processing requires a large amount of processing unit resources and power, leading to increased latency and the risk of energy depletion. Taking real-time monitoring of a production line as an example, the embedded controller needs to continuously encrypt the data stream transmitted by the temperature sensor. Existing algorithms are too slow to respond in time to millisecond-level time windows, causing delays in the execution of control commands, which may trigger equipment shutdowns or safety incidents. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a lightweight encryption and decryption method. This invention solves the technical problems of real-time data processing delays and security risks caused by the high computational overhead and energy consumption of existing cryptographic algorithms for industrial control embedded devices, spaceborne resource-constrained devices, and portable or micro-terminal devices for satellite communication.

[0005] To solve the above-mentioned technical problems, the specific contents of the present invention are as follows: This invention provides a lightweight encryption / decryption method, comprising: Step 1: Acquire the continuous binary data stream collected by the sensor and divide the continuous binary data stream into fixed-length data groups; Step 2: Input the fixed-length data group obtained in Step 1 into the encryption processing unit, call the pre-generated round key sequence and whitening key, wherein the round key sequence is generated by shifting the master key and iterating the round constant. In the encryption processing unit, the fixed-length data group and the whitening key are XORed to output the initial obfuscated data. Step 3: Divide the initial obfuscated data output in Step 2 into four equal-length segments as input for iterative processing. Perform multiple rounds of iterative processing on the four equal-length segments. Each round of processing includes: processing the current segment data using 16-bit modulo addition, performing fixed-bit cyclic shift on the result of the modulo addition, and outputting the cyclically shifted segment data. Step 4: XOR the cyclically shifted sub-segment data output in Step 3 with the current round key in the round key sequence, update the sub-segment state according to the preset branch processing rules, perform a linear transformation on the updated sub-segment state using an inverse matrix, and output the transformed sub-segment of this round. Step 5: Concatenate the four transformation segments output from the last iteration of Step 4 to generate ciphertext data, and transmit the ciphertext data to the execution mechanism; during decryption, receive the ciphertext data and reverse call the round key sequence, reuse the autoinverse matrix to perform inverse linear transformation, and sequentially reverse execute the state restoration steps corresponding to the branch processing rules, XOR with the current round key, cyclic shift operation and modular addition operation to restore the fixed-length data group.

[0006] Furthermore, in the lightweight encryption / decryption method of the present invention, the generation of the round key sequence in step 2 includes: Read the 256-bit master key from the secure storage area and divide the master key into a first 128-bit segment and a last 128-bit segment; The first 128-bit segment obtained from the segmentation is circularly shifted left by 8 bits, and the last 128-bit segment is circularly shifted right by 4 bits. The first 128 bits after shifting and the last 128 bits after shifting are input into the modulo addition unit, and a 16-bit modulo addition operation is performed to generate intermediate variables; Perform an XOR operation between the intermediate variable and the preset round constant, and output the current round key; Write the current round key to the specified address in the round key storage area; Extract the left 64 bits of the current round key as the input front-end data for the next round iteration; Repeat the shift, modulo addition, XOR, and storage steps until a complete round key sequence is generated.

[0007] Furthermore, in the lightweight encryption / decryption method of the present invention, the generation of the whitening key in step 2 includes: During the generation of round key sequences, the left 64-bit segment and the right 64-bit segment of each round's output are captured; The captured current left 64-bit segment is temporarily stored in the first register; The captured right 64-bit segment of the current round is temporarily stored in the second register; Read the data temporarily stored in the first and second registers; The left 64-bit segment data and the right 64-bit segment data are input into the XOR operation unit to perform XOR operation, generate the whitening key, and write the generated whitening key into the key buffer area.

[0008] Furthermore, in the lightweight encryption / decryption method of the present invention, the preset branch processing rule update of the sub-segment state in step 4 includes: The system receives four equal-length sub-segments from the current iteration input, copies the fourth sub-segment data to the first sub-segment storage area, overwrites the original first sub-segment, reads the original first sub-segment value and the original second sub-segment value, inputs the original first sub-segment value and the original second sub-segment value into the XOR unit, outputs the mixed value, writes the mixed value into the second sub-segment storage area, swaps the storage addresses of the third sub-segment and the fourth sub-segment, and outputs the updated four sub-segments. The sub-segment update process defined in step 4 is a branch processing rule.

[0009] Furthermore, in the lightweight encryption / decryption method of the present invention, step 4 further includes: The machine code corresponding to the branch processing rules is fixed in the ARM Cortex-M4 instruction set; Load the current round counter value at the start of the iteration; Compare the current round counter value with the pre-stored total number of rounds; If the comparison result shows that the current round is less than the total number of rounds, the hard-coded instructions are invoked to execute the branch processing rules; If the comparison result shows that the current round is equal to the total rounds, skip the branch processing rule steps.

[0010] Furthermore, in the lightweight encryption / decryption method of the present invention, step 4 further includes: During the encryption phase, the processor calls the sparse matrix coefficient library, writes the preset 16x16 binary matrix in the coefficient library into the FPGA configuration register, and activates the sparse matrix operation circuit through the register latch control signal; During the decryption phase, the matrix coefficients stored in the FPGA configuration register are reused, and an inverse enable signal is input to the sparse matrix operation circuit to trigger the internal self-reversible logic gate array to perform an inverse transformation.

[0011] Furthermore, in the lightweight encryption and decryption method of the present invention, step 4 further includes: the sparse matrix operation circuit integrates a barrel shifter component, the linear transformation input data is connected to the barrel shifter data bus, the barrel shifter is configured to perform a fixed 4-bit cyclic right shift, the shifted data is output to the modular adder, the bit width of the modular adder is constrained to 16 bits, and the carry chain truncation mechanism is enabled to prevent overflow.

[0012] Furthermore, in the lightweight encryption / decryption method of the present invention, step 5 includes: During encryption, initialize the address counter and set its value to the starting address 0x0000; The round key storage area access address is calculated in ascending order of encryption rounds using the formula: Target Address = Base Address + Round Number × 8 bytes; The round key data is read from the calculated target address using memory-mapped I / O. During decryption, the address counter is reset, and the counter value is set to the end address 0x00FF; The round key storage area access address is calculated in descending order of decryption rounds using the formula: Target address = End address - Round number × 8 bytes; The round key data is read from the calculated target address using memory-mapped I / O.

[0013] Furthermore, in the lightweight encryption / decryption method of the present invention, step 2 further includes: On the rising edge of the encryption start signal, the whitening key is loaded into the R0-R3 general-purpose registers; Set the register write-protect latch to lock the whitening key data in registers R0-R3; Continuously monitor the value of the system clock cycle counter; When the system clock cycle counter value is less than the predefined total number of encryption cycles, maintain the power supply voltage of registers R0-R3; After the encryption completion signal is triggered, clear the register write-protect latch and release the storage space of registers R0-R3.

[0014] Furthermore, in the lightweight encryption / decryption method of the present invention, step 5 further includes: After receiving the continuous binary data stream collected by the sensor, the DMA controller is activated to divide the data stream into fixed-length data packets; The segmented data is grouped and input into the encryption processing unit, and the pre-generated whitening key residing in the register is called to perform an XOR operation to generate initial obfuscated data; In the encryption processing unit, cyclic shifting is performed by an integrated barrel shifter component; The round key storage area access address is generated using an address pre-computation mechanism, and the round key is read through memory-mapped I / O. The total time consumption for modular addition, branch update, and matrix transformation in the constrained single-round iterative processing is 187.5 microseconds; Sixteen iterative processing units are scheduled in parallel to execute multiple rounds of computation simultaneously. The transformed segments output from multiple rounds of computation are concatenated to generate ciphertext data; Activate the hardware AES acceleration channel to transmit the generated ciphertext data to the actuator.

[0015] Beneficial effects of this invention; This invention utilizes a self-reversible matrix multiplexing mechanism to share the same set of sparse matrix operation circuits during encryption and decryption. Combined with a barrel shifter component, it achieves zero-cycle-latency cyclic shift operations. Hard-coded branch processing rules and a final-round skip mechanism effectively compress the critical path of iterative processing. Round key sequence pre-generation and whitening key register residency strategies avoid real-time computation overhead, while address pre-computation mechanisms enable single-cycle access to the round key storage area. A DMA controller performs data splitting operations and parallel scheduling of multiple iterative processing units for synchronous computation, maximizing hardware throughput efficiency. The synergistic effect of these technologies significantly reduces end-to-end processing latency in industrial control embedded devices, solving the real-time performance issues caused by high computational overhead in existing encryption algorithms. Attached Figure Description

[0016] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on the drawings without creative effort.

[0017] Figure 1 This is a flowchart of a lightweight encryption / decryption method provided in an embodiment of the present invention. Detailed Implementation

[0018] To make the technical solution of the present invention clearer, the present invention will be clearly and completely described below with reference to specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The present invention provided by various embodiments will be described in detail below with reference to the accompanying drawings. To better understand the purpose of the present invention, the present invention will be described in further detail below.

[0019] Please see Figure 1 The present invention provides a lightweight encryption / decryption method, comprising: Step 1: Acquire the continuous binary data stream collected by the sensor and divide the continuous binary data stream into fixed-length data groups; Step 2: Input the fixed-length data group obtained in Step 1 into the encryption processing unit, call the pre-generated round key sequence and whitening key, wherein the round key sequence is generated by shifting the master key and iterating the round constant. In the encryption processing unit, the fixed-length data group and the whitening key are XORed to output the initial obfuscated data. Step 3: Divide the initial obfuscated data output in Step 2 into four equal-length segments as input for iterative processing. Perform multiple rounds of iterative processing on the four equal-length segments. Each round of processing includes: processing the current segment data using 16-bit modulo addition, performing fixed-bit cyclic shift on the result of the modulo addition, and outputting the cyclically shifted segment data. Step 4: XOR the cyclically shifted sub-segment data output in Step 3 with the current round key in the round key sequence, update the sub-segment state according to the preset branch processing rules, perform a linear transformation on the updated sub-segment state using an inverse matrix, and output the transformed sub-segment of this round. Step 5: Concatenate the four transformation segments output from the last iteration of Step 4 to generate ciphertext data, and transmit the ciphertext data to the execution mechanism; during decryption, receive the ciphertext data and reverse call the round key sequence, reuse the autoinverse matrix to perform inverse linear transformation, and sequentially reverse execute the state restoration steps corresponding to the branch processing rules, XOR with the current round key, cyclic shift operation and modular addition operation to restore the fixed-length data group.

[0020] This invention provides a lightweight encryption / decryption method, specifically implemented through the following technical solution. First, a continuous binary data stream acquired by a sensor is obtained. The data stream is then segmented into fixed-length data packets using a DMA controller to meet the bit width requirements of subsequent processing units. The grouped data is input into an encryption processing unit, which calls a pre-generated round key sequence and a whitening key. The round key sequence is generated iteratively through shift operations of the master key and round constants, while the whitening key is synthesized from intermediate data generated during the round key generation process. In the encryption processing unit, the data packets and the whitening key undergo a bitwise XOR operation to generate initial obfuscated data to eliminate the statistical characteristics of the plaintext.

[0021] The initial scrambled data is then divided into four equal-length segments, which serve as input for multi-round iterative processing. Each segment is independently loaded into the arithmetic unit register. In each iteration, the current segment data is processed using a 16-bit modulo addition operation. The result of the modulo addition operation is then subjected to a fixed-bit cyclic shift operation via a barrel shifter. The shifted segment data is XORed with the current round key in the round key sequence, and then the segment state is updated according to a preset branching rule. The branching rule includes copying the fourth segment data to overwrite the first segment's storage area, mixing the original first segment value with the original second segment value and writing it into the second segment's storage area, and swapping the storage addresses of the third and fourth segments. The updated segment state undergoes a linear transformation using an inverse matrix, which is implemented by a sparse matrix operation circuit that integrates a barrel shifter component to handle the shifting requirements in the linear transformation.

[0022] The four transformed segments output from the final iteration are concatenated to generate ciphertext data, which is then transmitted to the execution mechanism via a hardware AES acceleration channel. During decryption, the system receives the ciphertext data and reverses the round key sequence, performs an inverse linear transformation using a sparse matrix operation circuit, and sequentially reverses the state restoration steps corresponding to the branch processing rules, performs an XOR operation with the current round key, a cyclic shift operation, and a modular addition operation, ultimately recovering the original data block. This encryption and decryption process achieves low-latency, high-throughput data processing through the collaborative work of a round key pre-generation mechanism, a register-resident strategy, and hardware acceleration components.

[0023] Specifically, in the lightweight encryption / decryption method of the present invention, the generation of the round key sequence in step 2 includes: Read the 256-bit master key from the secure storage area and divide the master key into a first 128-bit segment and a last 128-bit segment; The first 128-bit segment obtained from the segmentation is circularly shifted left by 8 bits, and the last 128-bit segment is circularly shifted right by 4 bits. The first 128 bits after shifting and the last 128 bits after shifting are input into the modulo addition unit, and a 16-bit modulo addition operation is performed to generate intermediate variables; Perform an XOR operation between the intermediate variable and the preset round constant, and output the current round key; Write the current round key to the specified address in the round key storage area; Extract the left 64 bits of the current round key as the input front-end data for the next round iteration; Repeat the shift, modulo addition, XOR, and storage steps until a complete round key sequence is generated.

[0024] This invention provides a lightweight encryption and decryption method. During the generation of the round key sequence, a 256-bit master key is read from the secure storage area. The master key is divided into a first 128-bit segment and a last 128-bit segment. The first 128-bit segment is circularly shifted left by 8 bits, and the last 128-bit segment is circularly shifted right by 4 bits. The shifted first 128-bit segment and the shifted last 128-bit segment are input into the modulo addition unit to perform a 16-bit modulo addition operation to generate an intermediate variable. The intermediate variable is XORed with a preset round constant to output the current round key. The current round key is written to a specified address in the round key storage area. The left 64 bits of the current round key are extracted as the input front-end data for the next round iteration. The complete round key sequence is generated by repeatedly executing the shift, modulo addition, XOR, and storage steps.

[0025] Specifically, in the lightweight encryption / decryption method of the present invention, the generation of the whitening key in step 2 includes: During the generation of round key sequences, the left 64-bit segment and the right 64-bit segment of each round's output are captured; The captured current left 64-bit segment is temporarily stored in the first register; The captured right 64-bit segment of the current round is temporarily stored in the second register; Read the data temporarily stored in the first and second registers; The left 64-bit segment data and the right 64-bit segment data are input into the XOR operation unit to perform XOR operation, generate the whitening key, and write the generated whitening key into the key buffer area.

[0026] This invention generates a whitening key synchronously during the generation of the round key sequence. By capturing the left 64-bit segment and the right 64-bit segment output in each round, the left 64-bit segment of the current round is temporarily stored in the first register, and the right 64-bit segment of the current round is temporarily stored in the second register. The data temporarily stored in the first register and the second register are read, and the read left 64-bit segment data and the right 64-bit segment data are input into the XOR operation unit to perform an XOR operation, thereby generating a whitening key and writing it into the key buffer area.

[0027] Specifically, in the lightweight encryption / decryption method of the present invention, step 4 of updating the sub-segment state using the preset branch processing rules includes: The system receives four equal-length sub-segments from the current iteration input, copies the fourth sub-segment data to the first sub-segment storage area, overwrites the original first sub-segment, reads the original first sub-segment value and the original second sub-segment value, inputs the original first sub-segment value and the original second sub-segment value into the XOR unit, outputs the mixed value, writes the mixed value into the second sub-segment storage area, swaps the storage addresses of the third sub-segment and the fourth sub-segment, and outputs the updated four sub-segments. The sub-segment update process defined in step 4 is a branch processing rule.

[0028] This invention updates the sub-segment state by pre-defined branch processing rules. It receives four equal-length sub-segments from the current iteration input, copies the fourth sub-segment data to the first sub-segment storage area to overwrite the original first sub-segment, reads the original first sub-segment value and the original second sub-segment value, inputs the original first sub-segment value and the original second sub-segment value into an XOR unit to output a mixed value, writes the mixed value into the second sub-segment storage area, swaps the storage addresses of the third sub-segment and the fourth sub-segment, and outputs the updated four sub-segments.

[0029] Specifically, in the lightweight encryption and decryption method of the present invention, step 4 further includes: The machine code corresponding to the branch processing rules is fixed in the ARM Cortex-M4 instruction set; Load the current round counter value at the start of the iteration; Compare the current round counter value with the pre-stored total number of rounds; If the comparison result shows that the current round is less than the total number of rounds, the hard-coded instructions are invoked to execute the branch processing rules; If the comparison result shows that the current round is equal to the total rounds, skip the branch processing rule steps.

[0030] This invention embeds the machine code corresponding to the branch processing rules in the ARM Cortex-M4 instruction set. At the start of the iteration, the current round counter value is loaded, and the loaded current round counter value is compared with the pre-stored total number of rounds value. Based on the comparison result, it is determined whether to call the hard-coded instruction to execute the branch processing rule or skip the branch processing rule steps.

[0031] Specifically, in the lightweight encryption / decryption method of the present invention, step 4 further includes: During the encryption phase, the processor calls the sparse matrix coefficient library, writes the preset 16x16 binary matrix in the coefficient library into the FPGA configuration register, and activates the sparse matrix operation circuit through the register latch control signal; During the decryption phase, the matrix coefficients stored in the FPGA configuration register are reused, and an inverse enable signal is input to the sparse matrix operation circuit to trigger the internal self-reversible logic gate array to perform an inverse transformation.

[0032] This invention implements linear transformation of inverse matrices through sparse matrix operation circuits. During the encryption stage, the processor calls the sparse matrix coefficient library, writes the preset 16x16 binary matrix in the coefficient library into the FPGA configuration register, and activates the sparse matrix operation circuit through the register latch control signal. During the decryption stage, the matrix coefficients stored in the FPGA configuration register are reused, and an inverse enable signal is input to the sparse matrix operation circuit to trigger the internal inverse logic gate array to perform the inverse transformation.

[0033] Specifically, in the lightweight encryption and decryption method of the present invention, step 4 further includes: the sparse matrix operation circuit integrates a barrel shifter component, the linear transformation input data is connected to the barrel shifter data bus, the barrel shifter is configured to perform a fixed 4-bit cyclic right shift, the shifted data is output to the modular adder, the bit width of the modular adder is constrained to 16 bits, and the carry chain truncation mechanism is enabled to prevent overflow.

[0034] This invention integrates a barrel shifter component into a sparse matrix operation circuit, connects the linear transformation input data to the barrel shifter data bus, configures the barrel shifter to perform a fixed 4-bit cyclic right shift, outputs the shifted data to the modular arithmetic unit, constrains the bit width of the modular arithmetic unit to 16 bits, and enables the carry chain truncation mechanism to prevent operation overflow.

[0035] Specifically, in the lightweight encryption / decryption method of the present invention, step 5 includes: During encryption, initialize the address counter and set its value to the starting address 0x0000; The round key storage area access address is calculated in ascending order of encryption rounds using the formula: Target Address = Base Address + Round Number × 8 bytes; The round key data is read from the calculated target address using memory-mapped I / O. During decryption, the address counter is reset, and the counter value is set to the end address 0x00FF; The round key storage area access address is calculated in descending order of decryption rounds using the formula: Target address = End address - Round number × 8 bytes; The round key data is read from the calculated target address using memory-mapped I / O.

[0036] This invention employs an address pre-calculation mechanism to call the round key. During encryption, the address counter is initialized to the starting address, and the access address of the round key storage area is calculated in ascending order of the encryption rounds. The round key data stored in the target address is read through memory-mapped I / O. During decryption, the address counter is reset to the ending address, and the access address of the round key storage area is calculated in descending order of the decryption rounds. The round key data stored in the target address is read through memory-mapped I / O.

[0037] Specifically, in the lightweight encryption / decryption method of the present invention, step 2 further includes: On the rising edge of the encryption start signal, the whitening key is loaded into the R0-R3 general-purpose registers; Set the register write-protect latch to lock the whitening key data in registers R0-R3; Continuously monitor the value of the system clock cycle counter; When the system clock cycle counter value is less than the predefined total number of encryption cycles, maintain the power supply voltage of registers R0-R3; After the encryption completion signal is triggered, clear the register write-protect latch and release the storage space of registers R0-R3.

[0038] This invention maintains the whitening key through a register management mechanism. The whitening key is loaded into a general-purpose register on the rising edge of the encryption start signal. The register write-protect latch is set to lock the whitening key data in the register. The value of the system clock cycle counter is continuously monitored. When the counter value is less than the total number of encryption cycles, the register power supply voltage is maintained. After the encryption completion signal is triggered, the register write-protect latch is cleared to release the register storage space.

[0039] Specifically, in the lightweight encryption / decryption method of the present invention, step 5 further includes: After receiving the continuous binary data stream collected by the sensor, the DMA controller is activated to divide the data stream into fixed-length data packets; The segmented data is grouped and input into the encryption processing unit, and the pre-generated whitening key residing in the register is called to perform an XOR operation to generate initial obfuscated data; In the encryption processing unit, cyclic shifting is performed by an integrated barrel shifter component; The round key storage area access address is generated using an address pre-computation mechanism, and the round key is read through memory-mapped I / O. The total time consumption for modular addition, branch update, and matrix transformation in the constrained single-round iterative processing is 187.5 microseconds; Sixteen iterative processing units are scheduled in parallel to execute multiple rounds of computation simultaneously. The transformed segments output from multiple rounds of computation are concatenated to generate ciphertext data; Activate the hardware AES acceleration channel to transmit the generated ciphertext data to the actuator.

[0040] This invention processes sensor data streams through a DMA controller. After receiving the continuous binary data stream acquired by the sensor, the DMA controller is activated to divide the data stream into fixed-length data packets. The divided data packets are input into an encryption processing unit. A pre-generated whitening key residing in a register is called to perform an XOR operation to generate initial obfuscated data. In the encryption processing unit, a cyclic shift is performed through an integrated barrel shifter component. An address pre-computation mechanism is used to generate the access address of the round key storage area. The round key is read through memory-mapped I / O. The processing time of a single round of iteration is constrained. Multiple iteration processing units are scheduled in parallel to execute multiple rounds of operations synchronously. The transformed segments output from the multiple rounds of operations are concatenated to generate ciphertext data. The hardware AES acceleration channel is activated to transmit the ciphertext data to the execution mechanism.

[0041] This invention addresses the high latency issue in encryption of industrial control equipment through multi-layered collaborative optimization. At the hardware architecture level, a self-reversible matrix multiplexing mechanism is employed, allowing the encryption and decryption stages to share the same set of sparse matrix operation circuits. Matrix coefficients are stored in FPGA configuration registers, and the transformation direction is controlled by a reverse enable signal, significantly reducing hardware resource consumption. At the data processing level, a branch processing rule hard-coding technique is introduced, embedding the sub-segment state update logic into machine code of the ARM Cortex-M4 instruction set. A round counter comparison mechanism intelligently skips redundant operations in the final round, compressing the critical path of iterative processing.

[0042] At the key management level, a round key sequence pre-generation strategy is implemented. A complete key sequence is generated through differentiated shift operations of the master key and round constant iteration. Combined with a whitening key register resident mechanism, key data is kept resident in a general-purpose register and powered through a write-protected latch, eliminating real-time key computation and loading latency. At the data flow level, a DMA controller is used to perform sensor data stream segmentation. Multiple iterative processing units are scheduled in parallel to synchronously perform modular addition, branch updates, and matrix transformation operations. A barrel shifter component is used to achieve zero-cycle-latency cyclic shifting.

[0043] The address pre-computation mechanism uses a forward incrementing and reverse decrementing address generation strategy to achieve single-cycle access to the round key storage area during the encryption and decryption phases. A hardware AES acceleration channel ensures efficient ciphertext data transmission. This technical measure forms a closed-loop optimization, significantly reducing end-to-end processing latency by minimizing circuit redundancy, avoiding real-time computation, compressing processing paths, and increasing parallelism, thus meeting the dual requirements of real-time performance and security in industrial control scenarios.

[0044] This invention addresses the real-time encryption requirements of embedded industrial control environments by optimizing low-latency encryption and decryption through multi-level technology. The continuous binary data stream acquired by sensors is segmented into fixed-length data packets by a DMA controller. This design avoids direct processor involvement in data transfer, reducing interrupt handling overhead. The encryption processing unit calls a pre-generated round key sequence and a whitening key. The round key sequence employs a master key segmented shift strategy: the first 128 bits are cyclically shifted left by 8 bits, and the last 128 bits are cyclically shifted right by 4 bits. This differentiated shifting enhances key randomness.

[0045] During round key generation, a whitening key is generated synchronously. An XOR operation is performed on the left and right 64-bit segments of each round's output. This method synchronously completes whitening key derivation during key expansion, avoiding additional computational overhead. The whitening key is maintained through a register-resident mechanism, loaded into a general-purpose register and latched with write protection during the encryption startup phase, maintaining power supply stability throughout the encryption cycle.

[0046] The initial obfuscated data is divided into four equal-length segments and processed through multiple rounds of iteration. Each round uses a 16-bit modulo addition operation combined with a fixed-bit cyclic shift. After shifting, the data is XORed with the round key, and then the branching rules are executed to update the segment state. The branching rules copy the fourth segment to overwrite the first segment, mix the original first and second segment values ​​to update the second segment, and swap the storage addresses of the third and fourth segments. This operation enhances the data obfuscation effect.

[0047] The inverse matrix linear transformation is implemented through a sparse matrix operation circuit. This circuit integrates a barrel shifter component, directly connecting the linear transformation input data to the barrel shifter data bus to perform a fixed 4-bit cyclic right shift. The sparse matrix coefficients are pre-stored in the FPGA configuration register, and the direction of operation is controlled by a reverse enable signal during the encryption / decryption stage, achieving hardware resource reuse.

[0048] The round key retrieval uses an address pre-computation mechanism. During encryption, access addresses are generated in ascending order of round number, and during decryption, they are accessed in descending order. Single-cycle key reading is achieved through memory-mapped I / O. Multiple iterative processing units are scheduled to execute operations in parallel, combined with a hardware AES acceleration channel for transmitting encrypted data, forming an end-to-end optimized scheme.

[0049] This implementation achieves low-latency encryption and decryption in resource-constrained environments through algorithm optimization and hardware co-design, meeting the dual requirements of real-time performance and security for industrial control systems.

[0050] The technical features of this invention are explained below: The round key generation model in this invention is based on master key segment shifting and round constant iteration. It divides the 256-bit master key into two 128-bit segments and performs differentiated shift operations: the first segment is cyclically shifted left by 8 bits, and the second segment is cyclically shifted right by 4 bits. The shifted result is then XORed with the round constant using a 16-bit modulo addition operation to generate the round key. This model pre-generates the complete round key sequence before encryption, avoiding the latency caused by real-time key computation.

[0051] The whitening key generation model is built upon intermediate data from the round key generation process. It captures the left and right 64-bit segments of each round's output, temporarily stores them in a register, and then performs an XOR operation to synthesize the whitening key. This model utilizes intermediate data from the key expansion process to derive the whitening key, achieving initial obfuscation without additional computational overhead.

[0052] The branch processing rule model is built upon sub-segment state update logic. It achieves data obfuscation by copying the fourth sub-segment data to overwrite the first sub-segment's storage area, mixing the original first sub-segment value with the second sub-segment value, and swapping the storage addresses of the third and fourth sub-segments. This model is hard-coded using the ARM Cortex-M4 instruction set and intelligently skips the final round operation based on round count, thus compressing the processing path.

[0053] The inverse matrix operation model is built upon sparse matrices and inverse linear transformations. It configures FPGA registers using a pre-set 16x16 binary matrix and utilizes an inverse logic gate array to implement linear and inverse transformations during the encryption and decryption stages. This model integrates a barrel shifter component to handle cyclic shift requirements, controlling the transformation direction through forward and reverse enable signals to achieve hardware resource reuse.

[0054] The generalized Feistel structure employed in this invention is a block cipher design framework that achieves encryption by dividing the input data into multiple segments and performing multiple rounds of iterative processing. During encryption, each segment is processed by a round function and then mixed with other segments. The round function includes modular addition, cyclic shift, and XOR operations. This structure uses the same algorithm in reverse for decryption, eliminating the need to design an inverse round function and significantly reducing hardware implementation complexity.

[0055] Modular addition, as the core of nonlinear transformation, performs addition followed by modulo operation with a 16-bit width, effectively preventing linear analysis attacks. Modular addition processes the master key segment data during the round key generation phase and operates on the current sub-segment data during the iterative processing phase, enhancing the algorithm's resistance to differential analysis through finite field operations.

[0056] The cyclic shift operation is implemented using a barrel shifter hardware component, which performs a fixed-bit cyclic shift on the result of a modulo addition operation. The cyclic shift operation alters the positional relationship of data bits, enhancing the algorithm's diffusion characteristics. Combined with the XOR operation, it achieves a redistribution of data bits, eliminating the statistical characteristics of plaintext.

[0057] The XOR operation, as a fundamental linear transformation, is widely used in key expansion, whitening, and round key mixing stages. XOR enables fast bit flipping, combining intermediate variables with round constants in the round key generation stage, combining data blocks with the whitening key in the whitening stage, and combining shifted data with the round key in the iterative processing stage.

[0058] Sparse matrix operations use a pre-set 16x16 binary matrix as the linear transformation layer, and the matrix coefficients are optimized to include a large number of zero elements. Sparse matrix operations load the matrix coefficients through the FPGA configuration register, perform the forward linear transformation during the encryption phase, and trigger the inverse transformation through the reverse enable signal during the decryption phase, thus reducing the number of logic gates used by leveraging the sparse characteristics of the matrix.

[0059] The round key sequence is a key expansion mechanism generated by segmenting and shifting the master key and iterating the round constant. The 256-bit master key is divided into two 128-bit segments. The first segment is shifted left by 8 bits, and the second segment is shifted right by 4 bits. The shifted data is XORed with the round constant after a 16-bit modulo addition operation to generate the round key. The complete key sequence is generated iteratively for multiple rounds of encryption operations.

[0060] The whitening key is an auxiliary key derived from the intermediate data generated during the round key generation process. It is generated by capturing the left 64-bit segment and the right 64-bit segment of each round's output, temporarily storing the segmented data in a register, and then performing an XOR operation. It is used to perform an XOR operation on the data groups in the initial stage of encryption to eliminate the statistical characteristics of the plaintext.

[0061] The branch processing rule is a sub-segment state update algorithm. It overwrites the first sub-segment storage area by copying the fourth sub-segment data, updates the second sub-segment storage area by mixing the original first sub-segment value with the second sub-segment value, and swaps the storage addresses of the third and fourth sub-segments to achieve data obfuscation. This rule is hard-coded into the ARM Cortex-M4 instruction set.

[0062] The inverse matrix is ​​a linear transformation component implemented through a sparse matrix operation circuit. It uses a preset 16x16 binary matrix to configure the FPGA registers, performs a forward linear transformation during the encryption phase, and triggers an inverse transformation through a reverse enable signal during the decryption phase. It utilizes the inverse properties of the matrix to achieve hardware multiplexing for encryption and decryption.

[0063] A barrel shifter is a hardware component integrated into a sparse matrix operation circuit. Linear transformation input data is connected to the barrel shifter data bus to perform a fixed 4-bit cyclic right shift operation, achieving zero clock cycle delay in displacement processing. The shift result is directly output to the modular arithmetic unit.

[0064] The address pre-computation mechanism is a round-key scheduling strategy. During encryption, access addresses are generated in ascending order of rounds, and during decryption, they are accessed in descending order. Single-cycle key reading is achieved through memory-mapped I / O, and efficient key retrieval is achieved in conjunction with the sequential storage structure of the round-key storage area.

[0065] Register-resident strategy is a whitening key maintenance method. It loads the whitening key into a general-purpose register and enables write-protected latching when encryption starts. It maintains the stability of register power supply during the encryption cycle and avoids the time overhead caused by repeated key loading.

[0066] The DMA controller is a data preprocessing component that directly processes the continuous binary data stream acquired by the sensor, dividing the data stream into fixed-length packets to reduce the data handling burden on the processor and enable direct transmission between the data packets and the encryption processing unit.

[0067] The sparse matrix coefficient library is a pre-set set of linear transformation parameters that stores optimized 16x16 binary matrix coefficients. The matrix design includes a large number of zero elements to reduce the number of logic gates used. The coefficient library is loaded into the arithmetic circuit via the FPGA configuration register.

[0068] The hardware AES acceleration channel is a dedicated channel for encrypted transmission. It transmits the concatenated encrypted data directly to the actuator through the hardware acceleration module, bypassing the existing data transmission path and reducing transmission latency.

Claims

1. A lightweight encryption / decryption method, characterized in that, include: Step 1: Acquire the continuous binary data stream collected by the sensor and divide the continuous binary data stream into fixed-length data groups; Step 2: Input the fixed-length data group obtained in Step 1 into the encryption processing unit, call the pre-generated round key sequence and whitening key, wherein the round key sequence is generated by shifting the master key and iterating the round constant. In the encryption processing unit, the fixed-length data group and the whitening key are XORed to output the initial obfuscated data. Step 3: Divide the initial obfuscated data output in Step 2 into four equal-length segments as input for iterative processing. Perform multiple rounds of iterative processing on the four equal-length segments. Each round of processing includes: processing the current segment data using 16-bit modulo addition, performing fixed-bit cyclic shift on the result of the modulo addition, and outputting the cyclically shifted segment data. Step 4: XOR the cyclically shifted sub-segment data output in Step 3 with the current round key in the round key sequence, update the sub-segment state according to the preset branch processing rules, perform a linear transformation on the updated sub-segment state using an inverse matrix, and output the transformed sub-segment of this round. Step 5: Concatenate the four transformation segments output from the last iteration of Step 4 to generate ciphertext data, and transmit the ciphertext data to the execution mechanism; during decryption, receive the ciphertext data and reverse call the round key sequence, reuse the autoinverse matrix to perform inverse linear transformation, and sequentially reverse execute the state restoration steps corresponding to the branch processing rules, XOR with the current round key, cyclic shift operation and modular addition operation to restore the fixed-length data group.

2. The lightweight encryption / decryption method according to claim 1, characterized in that, The generation of the round key sequence in step 2 includes: Read the 256-bit master key from the secure storage area and divide the master key into a first 128-bit segment and a last 128-bit segment; The first 128-bit segment obtained from the segmentation is circularly shifted left by 8 bits, and the last 128-bit segment is circularly shifted right by 4 bits. The first 128 bits after shifting and the last 128 bits after shifting are input into the modulo addition unit, and a 16-bit modulo addition operation is performed to generate intermediate variables; Perform an XOR operation between the intermediate variable and the preset round constant, and output the current round key; Write the current round key to the specified address in the round key storage area; Extract the left 64 bits of the current round key as the input front-end data for the next round iteration; Repeat the shift, modulo addition, XOR, and storage steps until a complete round key sequence is generated.

3. The lightweight encryption / decryption method according to claim 2, characterized in that, The generation of the whitening key in step 2 includes: During the generation of round key sequences, the left 64-bit segment and the right 64-bit segment of each round's output are captured; The captured current left 64-bit segment is temporarily stored in the first register; The captured right 64-bit segment of the current round is temporarily stored in the second register; Read the data temporarily stored in the first and second registers; The left 64-bit segment data and the right 64-bit segment data are input into the XOR operation unit to perform XOR operation, generate the whitening key, and write the generated whitening key into the key buffer.

4. The lightweight encryption / decryption method according to claim 3, characterized in that, The preset branch processing rules for updating the sub-segment status in step 4 include: The system receives four equal-length sub-segments from the current iteration input, copies the fourth sub-segment data to the first sub-segment storage area, overwrites the original first sub-segment, reads the original first sub-segment value and the original second sub-segment value, inputs the original first sub-segment value and the original second sub-segment value into the XOR unit, outputs the mixed value, writes the mixed value into the second sub-segment storage area, swaps the storage addresses of the third sub-segment and the fourth sub-segment, and outputs the updated four sub-segments. The sub-segment update process defined in step 4 is a branch processing rule.

5. The lightweight encryption / decryption method according to claim 4, characterized in that, Step 4 further includes: The machine code corresponding to the branch processing rules is fixed in the ARM Cortex-M4 instruction set; Load the current round counter value at the start of the iteration; Compare the current round counter value with the pre-stored total number of rounds; If the comparison result shows that the current round is less than the total number of rounds, the hard-coded instructions are invoked to execute the branch processing rules; If the comparison result shows that the current round is equal to the total rounds, skip the branch processing rule steps.

6. The lightweight encryption / decryption method according to claim 5, characterized in that, Step 4 also includes: During the encryption phase, the processor calls the sparse matrix coefficient library, writes the preset 16x16 binary matrix in the coefficient library into the FPGA configuration register, and activates the sparse matrix operation circuit through the register latch control signal; During the decryption phase, the matrix coefficients stored in the FPGA configuration register are reused, and an inverse enable signal is input to the sparse matrix operation circuit to trigger the internal self-reversible logic gate array to perform an inverse transformation.

7. The lightweight encryption / decryption method according to claim 6, characterized in that, Step 4 also includes: The sparse matrix operation circuit integrates a barrel shifter component, which connects the linear transformation input data to the barrel shifter data bus, configures the barrel shifter to perform a fixed 4-bit cyclic right shift, and outputs the shifted data to the modular adder. The modular adder is constrained to a bit width of 16 bits, and a carry chain truncation mechanism is enabled to prevent overflow.

8. The lightweight encryption / decryption method according to claim 7, characterized in that, Step 5 includes: During encryption, initialize the address counter and set its value to the starting address 0x0000; The round key storage area access address is calculated in ascending order of encryption rounds using the formula: Target Address = Base Address + Round Number × 8 bytes; The round key data is read from the calculated target address using memory-mapped I / O. During decryption, the address counter is reset, and the counter value is set to the end address 0x00FF; The round key storage area access address is calculated in descending order of decryption rounds using the formula: Target address = End address - Round number × 8 bytes; The round key data is read from the calculated target address using memory-mapped I / O.

9. The lightweight encryption / decryption method according to claim 8, characterized in that, Step 2 also includes: On the rising edge of the encryption start signal, the whitening key is loaded into the R0-R3 general-purpose registers; Set the register write-protect latch to lock the whitening key data in registers R0-R3; Continuously monitor the value of the system clock cycle counter; When the system clock cycle counter value is less than the predefined total number of encryption cycles, maintain the power supply voltage of registers R0-R3; After the encryption completion signal is triggered, clear the register write-protect latch and release the storage space of registers R0-R3.

10. The lightweight encryption / decryption method according to claim 9, characterized in that, Step 5 also includes: After receiving the continuous binary data stream collected by the sensor, the DMA controller is activated to divide the data stream into fixed-length data packets; The segmented data is grouped and input into the encryption processing unit, and the pre-generated whitening key residing in the register is called to perform an XOR operation to generate initial obfuscated data; In the encryption processing unit, cyclic shifting is performed by an integrated barrel shifter component; The round key storage area access address is generated using an address pre-computation mechanism, and the round key is read through memory-mapped I / O. The total time consumption for modular addition, branch update, and matrix transformation in the constrained single-round iterative processing is 187.5 microseconds; Sixteen iterative processing units are scheduled in parallel to execute multiple rounds of computation simultaneously. The transformed segments output from multiple rounds of computation are concatenated to generate ciphertext data; Activate the hardware AES acceleration channel to transmit the generated ciphertext data to the actuator.

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