Ethernet phy bridging method and system, electronic device

Abstract

The application belongs to the technical field of Ethernet communication, and particularly relates to an Ethernet PHY bridging method and system and electronic equipment, wherein the Ethernet PHY bridging method comprises the following steps: configuring at least two bridging Ethernet subsystems, and deploying a data queue intellectual property core module between the bridging Ethernet subsystems; configuring one of the bridging Ethernet subsystems as a first bridging Ethernet subsystem, the first bridging Ethernet subsystem is adapted to receive external network data, and transmit the data stream to the data queue intellectual property core module in real time; and configuring another bridging Ethernet subsystem as a second bridging Ethernet subsystem, when the data queue intellectual property core module reaches a preset programmable full threshold, triggering the second bridging Ethernet subsystem to read network data from the data queue intellectual property core module and transmit the network data to a target network.

Description

Ethernet PHY bridging methods and systems, electronic equipment Technical Field

[0001] This invention belongs to the field of Ethernet communication technology, specifically relating to an Ethernet PHY bridging method and system, and electronic equipment. Background Technology

[0002] During Ethernet transmission, bridging technology is needed to connect different network segments, isolate network traffic, and improve network performance. However, if the above functions are implemented in the software layer, there are problems such as: receiving and sending require two memory copies, memory space needs to be freed up to store Ethernet packets, and CPU needs to be used to process Ethernet packets, which causes the speed of Ethernet network card transmission to be limited by the CPU and memory copy.

[0003] Therefore, there is a technical problem in the related technologies where the transmission speed of Ethernet network cards is limited by the CPU and memory copying.

[0004] It should be noted that the information disclosed in this background section is only for understanding the background technology of this application concept, and therefore, the above description is not considered to constitute information related to the technology. Summary of the Invention

[0005] The purpose of this invention is to provide an Ethernet PHY bridging method, system, and electronic device.

[0006] To address the aforementioned technical problems, this invention provides an Ethernet PHY bridging method, comprising:

[0007] Configure at least two bridged Ethernet modules and deploy a data queue intellectual property core module between each bridged Ethernet module;

[0008] Configure one of the bridging Ethernet modules as a first bridging Ethernet module, the first bridging Ethernet module being adapted to receive external network data and send the data stream to the data queue intellectual property core module in real time; and

[0009] Configure another bridging Ethernet module as a second bridging Ethernet module. When the data queue intellectual property core module reaches a preset programmable full threshold, the second bridging Ethernet module is triggered to read network data from the data queue intellectual property core module and send it to the target network.

[0010] In another aspect, the present invention also provides an Ethernet PHY bridging system, comprising:

[0011] First bridging Ethernet module;

[0012] Second bridging Ethernet module;

[0013] The data queue intellectual property core module is configured to be deployed between the first and second bridged Ethernet modules; and

[0014] The first bridging Ethernet module is adapted to receive external network data and send the data stream to the data queue intellectual property core module in real time; and

[0015] When the data queue intellectual property core module reaches a preset programmable full threshold, it is suitable to trigger the second bridging Ethernet module to read network data from the data queue intellectual property core module and send it to the target network.

[0016] Thirdly, the present invention also provides a non-transitory computer-readable storage medium having a computer program / instruction stored thereon, which, when executed by a processor, implements the Ethernet PHY bridging method as described above.

[0017] Fourthly, the present invention also provides a computer program product, including a program or instructions, wherein when the program or instructions are executed on a computer, the Ethernet PHY bridging method as described above is executed.

[0018] Fifthly, the present invention also provides an electronic device, comprising: at least one memory and at least one processor, wherein the memory stores executable instructions that, when executed by the processor, cause the processor to perform the Ethernet PHY bridging method as described above.

[0019] The beneficial effects of this invention are that the Ethernet PHY bridging method of this invention, by configuring multiple bridging Ethernet modules and a data queue intellectual property core module, and by receiving data from one of the bridging Ethernet modules through the data queue intellectual property core module, and triggering the remaining bridging Ethernet modules to read data from the data queue intellectual property core module and send it to the target network when the data queue intellectual property core module reaches a preset programmable full threshold, avoids the problem of the transmission speed of Ethernet network cards being limited by CPU and memory copying in the prior art, effectively improves the transmission efficiency of Ethernet network cards, and improves the performance of Ethernet networks.

[0020] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained through the structures particularly pointed out in the description and the drawings.

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0022] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 illustrates the steps of an Ethernet PHY bridging method according to some embodiments;

[0024] Figure 2 shows a schematic diagram of the wiring between some modules in an Ethernet PHY bridging method involving two bridged Ethernet modules in some embodiments;

[0025] Figure 3 illustrates a schematic diagram of the network data transmission path in some embodiments of the Ethernet PHY bridging method.

[0026] Figure 4 shows a flowchart of state synchronization in network data transmission under bridging mode in some embodiments of the Ethernet PHY bridging method.

[0027] Figure 5 shows a schematic diagram of the connections between some modules in the Ethernet PHY bridging method involving three bridged Ethernet modules in some embodiments;

[0028] Figure 6 shows a schematic block diagram of an Ethernet PHY bridging system involved in some embodiments;

[0029] Figure 7 shows a schematic block diagram of an electronic device involved in some embodiments. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] The following is an explanation of some of the technical terms used in this embodiment:

[0032] PHY (Physical Layer): Physical layer;

[0033] IP (Intellectual Property Core): Intellectual property core refers to a pre-designed, reusable hardware functional module;

[0034] Data Queue IP Module: Data Queue Intellectual Property Core Module;

[0035] Mode switching IP module: Mode switching intellectual property core module;

[0036] bit: Bit;

[0037] Bit-level bridging mode: Bit-level bridging mode;

[0038] Packet mode: Frame mode;

[0039] Disable packet mode: Disable frame mode;

[0040] Enable packet mode: Enable frame mode;

[0041] DMA (Direct Memory Access): Direct Memory Access;

[0042] Vivado: Xilinx hardware design platform;

[0043] It has been found that during the Ethernet transmission process, bridging technology needs to be used to connect different network segments, isolate network traffic, improve network performance, etc. However, the problems that occur when implementing the above functions at the software layer include:

[0044] 1) When receiving network card data, it is necessary to copy the network card data into memory; when sending network card data, it is necessary to copy the data in memory back to the network card again, resulting in each network data packet being copied twice;

[0045] 2) It is necessary to vacate some space in memory to store the data content arriving from the network;

[0046] 3) It is necessary to occupy the CPU to process the packets and the transmission and reception delay of the packets is greatly increased.

[0047] Regarding the defects and their causes of the above solutions, they are all the results obtained by the inventors through practice and careful research. Therefore, the process of discovering the above problems and the solutions proposed in this disclosure for the above problems should all be the contributions made by the inventors during the process of this disclosure.

[0048] Next, in conjunction with the accompanying drawings, some embodiments of the present invention will be described in detail. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0049] Therefore, at least one embodiment provides an Ethernet PHY bridging method, including:

[0050] Configure at least two bridged Ethernet modules and deploy a data queue IP module between each bridged Ethernet module; configure one of the bridged Ethernet modules as a first bridged Ethernet module, which is adapted to receive external network data and send the data stream to the data queue IP module in real time; and configure the other bridged Ethernet module as a second bridged Ethernet module, which is triggered to read network data from the data queue IP module and send it to the target network when the data queue IP module reaches a preset programmable full threshold.

[0051] The Ethernet PHY bridging method in this embodiment configures multiple bridging Ethernet modules and a data queue IP module. The data queue IP module receives data from one of the bridging Ethernet modules, and when the data queue IP module reaches a preset programmable full threshold, it triggers the remaining bridging Ethernet modules to read data from the data queue IP module and send it to the target network. This avoids the problem of the transmission speed of Ethernet network cards being limited by CPU and memory copying in the prior art, effectively improving the transmission efficiency of Ethernet network cards and improving the performance of Ethernet networks.

[0052] The various non-limiting embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0053] As shown in Figure 1, this embodiment provides an Ethernet PHY bridging method, including:

[0054] Step S101: Configure at least two bridged Ethernet modules and deploy data queue IP modules between each bridged Ethernet module;

[0055] Step S102: Configure one of the bridging Ethernet modules as a first bridging Ethernet module, the first bridging Ethernet module being adapted to receive external network data and send the data stream to the data queue IP module in real time; and

[0056] Step S103: Configure another bridging Ethernet module as a second bridging Ethernet module. When the data queue IP module reaches a preset programmable full threshold, trigger the second bridging Ethernet module to read network data from the data queue IP module and send it to the target network.

[0057] In some embodiments, the data queue IP module is configured in bit-level bridging mode and frame bridging latency is eliminated by disabling packetmode.

[0058] In some embodiments, the programmable full threshold is 8 bits.

[0059] In some embodiments, when the data queue IP module reaches a preset programmable full threshold, the second bridged Ethernet module is activated through the prog_full signal and the data flow control module to trigger the second bridged Ethernet module to read network data from the data queue IP module.

[0060] In some embodiments, the first bridging Ethernet module dynamically switches the data transmission path through a mode switching IP module. In bridging mode, the first bridging Ethernet module routes the received external network data to the data queue IP module; in non-bridging mode, the first bridging Ethernet module transfers the received external network data to memory for software processing via direct memory access (DMA).

[0061] Specifically, the data queue IP module uses the AXI4-Stream Data FIFO IP core to forward the data configuration content. The configuration attribute "enable packet mode" is set to no to perform bit bridging and reduce network latency caused by frame bridging.

[0062] The following example illustrates the process of forwarding received packets to the bridged network card using the Ethernet PHY bridging method described in this embodiment:

[0063] When the bridging mode is configured to start, external network data will be sent to the first bridging Ethernet module for data processing, and the AXI4-Stream Data FIFO IP core will be enabled. The input port of the AXI4-Stream Data FIFO IP core is connected to the receiving end of the first bridging Ethernet module, and the output port is connected to the sending end of the second bridging Ethernet module. When the first bridging Ethernet module receives external network data, it will put the data into the AXI4-Stream Data FIFO IP core. At the same time, the second bridging Ethernet module will read the data content of the AXI4-Stream Data FIFO IP core and send it out.

[0064] In Vivado, the initialization of the AXI4-Stream Data FIFO IP core and the bridged Ethernet module is as follows:

[0065]

[0066]

[0067]

[0068] As shown in Figures 2 to 4, the bridging transmission process of network packets is as follows: When the first bridging Ethernet module receives network data from the outside, it simultaneously pulls high its receive data valid m_axis_rx_tvalid_ext pin, enabling the write valid s_axis_tvalid pin of the AXI4-Stream Data FIFO IP core. This allows data to be transmitted through the data output m_axis_rx_tdata_ext pin of the first bridging Ethernet module to the write data s_axix_tdata pin of the AXI4-Stream Data FIFO IP core. When the data content in the AXI4-Stream Data FIFO IP core reaches a certain programmable full threshold... When the threshold is reached, a programmable full threshold (prog_full) signal is initiated. To reduce latency caused by queue buffering, this programmable full threshold is set to a minimum value of 8 bits. This programmable full threshold (prog_full) signal activates the transmit data valid (s_axis_tx_tvalid_cpy) pin of the second bridged Ethernet module through the data flow control (data_procssing) module. The programmable full threshold (prog_full) signal and the transmit ready (s_axis_tx_tready_cpy) pin of the second bridged Ethernet module then activate the read ready (m_axis_tready) pin of the AXI4-Stream Data FIFO IP core through the data flow control module. When the AXI4-Stream Data FIFO IP core simultaneously activates both the read valid (m_axis_tvalid) pin and the read ready (m_axis_tready) pin, the AXI4-Stream Data FIFO... Data in the IP core is transmitted via the read data m_axis_tdata pin to the data receive s_axis_tx_tdata_cpy pin of the second bridged Ethernet module, and then sent out via its data output m_axis_rx_tdata_ext pin. Partial implementation code is shown below:

[0069]

[0070]

[0071]

[0072] The Ethernet PHY bridging method in this embodiment further includes: the first bridging Ethernet module dynamically switches the data transmission path through a mode switching IP module. The mode switching IP module is a mode selection IP core, used to transmit Ethernet data to the AXI4-Stream Data FIFO IP core in bridging mode, and to transmit Ethernet data to normal Ethernet processing in non-bridging mode, transferring it to memory via direct memory access (DMA). The code for the mode selection IP core is as follows:

[0073] module mode_select(

[0074] input wire bridgen_en,

[0075] output wire s_axis_tx_aclk_cpy,

[0076] input wire s_axis_tx_tvalid_cpy,

[0077] input wire[7:0]s_axis_tx_tdata_cpy,

[0078] input wire s_axis_tx_tlast_cpy,

[0079] input wire s_axis_tx_tuser_cpy,

[0080] output wire s_axis_tx_tready_cpy,

[0081] output wire m_axis_rx_aclk_ext,

[0082] output wire m_axis_rx_tvalid_ext,

[0083] output wire[7:0]m_axis_rx_tdata_ext,

[0084] output wire m_axis_rx_tlast_ext,

[0085] output wire m_axis_rx_tuser_ext,

[0086] input wire mac_rx_mac_aclk,

[0087] input wire mac_m_axis_rx_TVALID,

[0088] input wire[7:0]mac_m_axis_rx_TDATA,

[0089] input wire mac_m_axis_rx_TLAST,

[0090] input wire mac_m_axis_rx_TUSER,

[0091] input wire mac_tx_mac_aclk,

[0092] input wire eth_buf_TX_AXIS_MAC_TREADY,output wire[7:0]eth_buf_TX_AXIS_MAC_TDATA_tmp,output wire eth_buf_TX_AXIS_MAC_TLAST_tmp,output wire eth_buf_TX_AXIS_MAC_TUSER_tmp,output wire eth_buf_TX_AXIS_MAC_TVALID_tmp,

[0093] input wire[7:0]eth_buf_TX_AXIS_MAC_TDATA,

[0094] input wire eth_buf_TX_AXIS_MAC_TLAST,

[0095] input wire eth_buf_TX_AXIS_MAC_TUSER,

[0096] input wire eth_buf_TX_AXIS_MAC_TVALID,

[0097] output wire m_axis_rx_tvalid_ext_10g,

[0098] output wire[7:0]m_axis_rx_tdata_ext_10g,

[0099] output wire m_axis_rx_tlast_ext_10g,

[0100] output wire m_axis_rx_tuser_ext_10g

[0101] );

[0102] assign m_axis_rx_aclk_ext=mac_rx_mac_aclk;

[0103] assign m_axis_rx_tvalid_ext=mac_m_axis_rx_TVALID;

[0104] assign m_axis_rx_tdata_ext=mac_m_axis_rx_TDATA;

[0105] assign m_axis_rx_tlast_ext=mac_m_axis_rx_TLAST;

[0106] assign m_axis_rx_tuser_ext=mac_m_axis_rx_TUSER;

[0107] / / Select the Ethernet receive data line connection by checking if bridging is enabled.

[0108] / / If bridging is enabled, connect the connection signal starting with s_axis to access the bridging function (where the connection signal starting with s_axis refers to the core control and data signals of the transmit path TX in the bridging Ethernet module).

[0109] / / If bridging is not enabled, normal network processing is used, copying to memory via DMA.

[0110] assign s_axis_tx_aclk_cpy=mac_tx_mac_aclk;

[0111] assign s_axis_tx_tready_cpy=eth_buf_TX_AXIS_MAC_TREADY;

[0112] assign eth_buf_TX_AXIS_MAC_TDATA_tmp=(bridgen_en==

[0113] 0)? eth_buf_TX_AXIS_MAC_TDATA:s_axis_tx_tdata_cpy;

[0114] assign eth_buf_TX_AXIS_MAC_TLAST_tmp=(bridgen_en==

[0115] 0)? eth_buf_TX_AXIS_MAC_TLAST:s_axis_tx_tlast_cpy;

[0116] assign eth_buf_TX_AXIS_MAC_TUSER_tmp=(bridgen_en==

[0117] 0)? eth_buf_TX_AXIS_MAC_TUSER:s_axis_tx_tuser_cpy;

[0118] assign eth_buf_TX_AXIS_MAC_TVALID_tmp=(bridgen_en==

[0119] 0)? eth_buf_TX_AXIS_MAC_TVALID:s_axis_tx_tvalid_cpy;

[0120] assign m_axis_rx_tvalid_ext_10g=mac_m_axis_rx_TVALID;

[0121] assign m_axis_rx_tdata_ext_10g=mac_m_axis_rx_TDATA;

[0122] assign m_axis_rx_tlast_ext_10g=mac_m_axis_rx_TLAST;

[0123] assign m_axis_rx_tuser_ext_10g=mac_m_axis_rx_TUSER;

[0124] endmodule

[0125] In some embodiments, the Ethernet PHY bridging method includes: when the number of configured bridging Ethernet modules is two or more, implementing the cascading or parallel connection of multiple bridging Ethernet modules by deploying multiple data queue IP modules.

[0126] As shown in Figure 5, for example, when three bridged Ethernet modules are configured, two data queue IP modules can be deployed to connect the three bridged Ethernet modules in pairs. Whenever one of the bridged Ethernet modules (the first bridged Ethernet module in Figure 5) receives data, it automatically fills the data into a data queue IP module (the first data queue IP module in Figure 5). The other bridged Ethernet module connected to this bridged Ethernet module (the second bridged Ethernet module in Figure 5) will automatically read the data from the data queue IP module (the first data queue IP module in Figure 5) and forward it. When bridging data from multiple network ports is required, this method can minimize the need for bridging.

[0127] CPU and DMA (Direct Memory Access) participation.

[0128] In summary, this Ethernet PHY bridging method, by configuring multiple bridging Ethernet modules and a data queue IP module, and by receiving data from one of the bridging Ethernet modules through the data queue IP module, and triggering the remaining bridging Ethernet modules to read data from the data queue IP module and send it to the target network when the data queue IP module reaches a preset programmable full threshold, avoids the problem of the transmission speed of Ethernet network cards being limited by CPU and memory copying in existing technologies, effectively improving the transmission efficiency of Ethernet network cards and improving the performance of Ethernet networks.

[0129] As shown in Figure 6, some embodiments also provide an Ethernet PHY bridging system, including: a first bridging Ethernet module; a second bridging Ethernet module; a data queue IP module configured to be deployed between the first and second bridging Ethernet modules; and the first bridging Ethernet module is adapted to receive external network data and send the data stream to the data queue IP module in real time; and when the data queue IP module reaches a preset programmable full threshold, it is adapted to trigger the second bridging Ethernet module to read network data from the data queue IP module and send it to the target network.

[0130] In some embodiments, the Ethernet PHY bridging system further includes: a mode switching IP module; the first bridging Ethernet module realizes dynamic switching of data transmission paths through the mode switching IP module, that is, in bridging mode, the first bridging Ethernet module routes the received external network data to the data queue IP module; in non-bridging mode, the first bridging Ethernet module transmits the received external network data to memory for software processing through direct memory access (DMA).

[0131] Specifically, the implementation functions of the first bridging Ethernet module, the second bridging Ethernet module, the data queue IP module, and the mode switching IP module can be found in the aforementioned Ethernet PHY bridging method, and will not be repeated here.

[0132] Some embodiments also provide a non-transitory computer-readable storage medium having a computer program / instructions stored thereon that, when executed by a processor, implements the Ethernet PHY bridging method as described above.

[0133] Please refer to the detailed description of the Ethernet PHY bridging method mentioned above; it will not be repeated here.

[0134] In some embodiments, the memory includes flash memory, hard disk, multimedia card, card-type memory (e.g., SD memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, it can be an internal storage unit of a computer device, such as the hard disk of the computer device. In other embodiments, the memory can also be an external storage device of the computer device, such as an external hard disk, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc., provided on the computer device. Furthermore, the memory can include both internal storage units and external storage devices of the computer device. The memory can be used not only to store application software and various types of data installed on the computer device, such as computer program code, but also to temporarily store data that has been output or will be output.

[0135] Some embodiments also provide a computer program product, including a program or instructions, wherein when the program or instructions are executed on a computer, the Ethernet PHY bridging method as described above is performed.

[0136] Please refer to the detailed description of the Ethernet PHY bridging method mentioned above; it will not be repeated here.

[0137] As shown in Figure 7, some embodiments also provide an electronic device including: at least one memory and at least one processor, wherein the memory stores executable instructions that, when executed by the processor, cause the processor to perform the Ethernet PHY bridging method as described above.

[0138] Please refer to the detailed description of the Ethernet PHY bridging method mentioned above; it will not be repeated here.

[0139] In some embodiments, computer devices and industrial control computers can also be used as a type of electronic device.

[0140] The structure shown in Figure 7 does not constitute a limitation on the electronic device and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0141] In some embodiments, the processor may be a central processing unit (CPU), controller, microcontroller, microprocessor, or other data processing chip, used to run program code stored in memory or process data, such as executing computer programs.

[0142] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0143] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0144] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0145] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. An Ethernet PHY bridging method, characterized in that, include: Configure at least two bridged Ethernet modules and deploy a data queue intellectual property core module between each bridged Ethernet module; Configure one of the bridging Ethernet modules as the first bridging Ethernet module. The first bridging Ethernet module is adapted to receive external network data and send the data stream to the data queue intellectual property core module in real time. And configure another bridging Ethernet module as a second bridging Ethernet module. When the data content in the data queue intellectual property core module reaches a preset programmable full threshold, the second bridging Ethernet module is activated through the programmable full threshold signal and the data flow control module, triggering the second bridging Ethernet module to read network data from the data queue intellectual property core module and send it to the target network.

2. The Ethernet PHY bridging method according to claim 1, characterized in that, The data queue intellectual property core module is configured in bit-level bridging mode and frame bridging latency is eliminated by disabling frame mode.

3. The Ethernet PHY bridging method according to claim 1, characterized in that, The programmable full threshold is 8 bits.

4. The Ethernet PHY bridging method according to claim 1, characterized in that, The first bridging Ethernet module achieves dynamic switching of data transmission paths through the mode switching intellectual property core module. That is, in bridging mode, the first bridging Ethernet module routes the received external network data to the data queue intellectual property core module. In non-bridged mode, the first bridged Ethernet module transmits the received external network data to memory for software processing via direct memory access.

5. The Ethernet PHY bridging method according to claim 1, characterized in that, When there are two or more bridged Ethernet modules configured, multiple bridged Ethernet modules can be cascaded or connected in parallel by deploying multiple data queue intellectual property core modules.

6. An Ethernet PHY bridging system, characterized in that, include: First bridging Ethernet module; Second bridging Ethernet module; The data queue intellectual property core module is configured to be deployed between the first and second bridged Ethernet modules; The first bridging Ethernet module is adapted to receive external network data and send the data stream to the data queue intellectual property core module in real time; When the data queue intellectual property core module reaches a preset programmable full threshold, it is suitable to trigger the second bridging Ethernet module to read network data from the data queue intellectual property core module and send it to the target network.

7. The Ethernet PHY bridging system according to claim 6, characterized in that, Also includes: Mode switching intellectual property core module; the first bridging Ethernet module realizes dynamic switching of data transmission path through the mode switching intellectual property core module, that is, in bridging mode, the first bridging Ethernet module routes the received external network data to the data queue intellectual property core module. In non-bridged mode, the first bridged Ethernet module transmits the received external network data to memory for software processing via direct memory access.

8. A non-transitory computer-readable storage medium having a computer program / instructions stored thereon, characterized in that, When the computer program / instruction is executed by the processor, it implements the Ethernet PHY bridging method as described in any one of claims 1-5.

9. A computer program product comprising a program or instructions, wherein when the program or instructions are executed on a computer, the Ethernet PHY bridging method as described in any one of claims 1-5 is performed.

10. An electronic device, characterized in that, The feature is that it includes: at least one memory and at least one processor, wherein the memory stores executable instructions, which, when executed by the processor, cause the processor to perform the Ethernet PHY bridging method as described in any one of claims 1-5.

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