Artificial nerve device with dual memory characteristics and preparation method thereof

Abstract

The invention relates to an artificial nerve component with dual memory characteristics and a preparation method thereof. The device comprises a substrate and at least two synapse transistors, each synapse transistor comprises a semiconductor layer, a grid electrode, a source electrode, a drain electrode and a gate dielectric layer, and the device can realize different memory characteristics by adopting an independent channel design. The device receives voltage pulse signals of different modes, and parallel processing of multi-mode sensing signals is achieved through a plurality of shared grids. The output of the device shows the double memory characteristics of short-term memory and long-term memory, and the device is suitable for complex identification and classification tasks and can be applied to the fields of intelligent sensing, bionic robots and the like.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an artificial neuron device with dual memory characteristics and its fabrication method. Background Technology

[0002] In recent years, the rapid development of artificial intelligence technology has driven the continuous improvement of performance requirements for information processing systems. Traditional von Neumann architecture computers, due to their hardware and architectural bottlenecks, have gradually revealed shortcomings such as high energy consumption and large latency, making it difficult to meet the future demands of multimodal perception and large-scale data processing. Neuromorphic devices, as innovative hardware devices that simulate the physical structure of the human brain's neural network, have become a research hotspot in the post-Moore's Law device field due to their advantages such as parallel processing and low power consumption. Unlike traditional computing architectures, neuromorphic devices achieve in-situ processing and storage fusion of perceptual information at the physical level through synaptic biomimetic design. This hardware-level innovation provides an important technical path for developing novel neuromorphic information processing devices that breaks through traditional computing paradigms. Transistor-type neuromorphic devices, as key hardware units capable of realizing synaptic and neuronal functions, are an important component of neuromorphic systems. These devices typically achieve brain-like functions by controlling the behavior of charge carriers in semiconductor channels to simulate changes in synaptic weights and the firing of neuronal impulses. Currently, related research is limited by the structural limitations and low functional levels of neuromorphic devices, which hinders their potential application in complex information processing scenarios, such as multimodal perception, real-time data processing, and edge computing. Summary of the Invention

[0003] In view of the shortcomings of traditional technologies, the present invention aims to provide an artificial neuron device with dual memory characteristics and its preparation method.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] An artificial neuron device with dual memory characteristics is disclosed. The device includes a substrate and at least two synaptic transistors exhibiting different memory characteristics. Each synaptic transistor includes a semiconductor layer, a source, a drain, a gate dielectric layer, and a gate. The gate and semiconductor layer are spaced apart on the substrate to form a side-gate structure. The source and drain are spaced apart on the semiconductor layer. The gate dielectric layer covers the gate, semiconductor layer, source, and drain. The at least two synaptic transistors include a first synaptic transistor and a second synaptic transistor. The number of gates of the first synaptic transistor and the second synaptic transistor are equal. The gates of the first and second synaptic transistors are interconnected in pairs to form a shared gate (SG). The second synaptic transistor includes a carrier trapping structure disposed between the semiconductor layer and the gate dielectric layer of the second synaptic transistor, and adsorbed onto the surface of the semiconductor layer of the second synaptic transistor, so that the memory time of the second synaptic transistor is longer than that of the first synaptic transistor.

[0006] In some implementations, the source, drain, and shared gate are metal electrodes, with the source and drain forming an interdigitated electrode pattern. The synaptic transistor includes multiple gates, with the number of shared gates being greater than or equal to two.

[0007] Each gate of the first synaptic transistor and the second synaptic transistor is used for interconnection.

[0008] In some implementations, the carrier trapping structure is made of inorganic nanomaterials.

[0009] The semiconductor layer is made of metal oxide semiconductor.

[0010] The gate dielectric layer is made of polymer electrolyte.

[0011] The substrate is a silicon wafer or a flexible polyimide film; the thickness of the substrate is greater than 0 μm and less than or equal to 2000 μm.

[0012] A method for fabricating an artificial neuron device with dual memory characteristics, the method comprising:

[0013] At least two synaptic transistors are formed, including a first synaptic transistor and a second synaptic transistor. The fabrication steps of the synaptic transistors include: forming a semiconductor layer on a substrate; forming a source and a drain spaced apart on the semiconductor layer, and forming a gate spaced apart from the semiconductor layer on the substrate, wherein the gate is interconnected with the gate of another synaptic transistor; adsorbing a carrier trapping material onto the surface of the semiconductor layer of the second synaptic transistor to form a carrier trapping structure; and forming a gate dielectric layer covering the gate, the semiconductor layer, the source, and the drain.

[0014] Furthermore, a semiconductor layer is formed: a metal oxide semiconductor precursor is spin-coated onto the surface of a flexible substrate or silicon substrate, and then annealed at high temperature to prepare a metal oxide semiconductor thin film as the semiconductor layer of the synaptic transistor.

[0015] Forming a carrier trapping material structure: The semiconductor layer of the second synaptic transistor is immersed in a solution of gold nanoparticles coated with organic ligands for surface adsorption, and the surface adsorption time is 0.5h to 5h.

[0016] Forming the gate dielectric layer: The polymer electrolyte is covered on the gate, semiconductor layer, source and drain through a flexible bonding process.

[0017] The essential features of this invention are:

[0018] This invention provides an artificial neuron device with dual memory characteristics and its fabrication method. At least two synaptic transistors with different memory characteristics are disposed on the substrate surface. Each synaptic transistor contains an independent semiconductor channel, and the two synaptic transistors share a gate and a common gate dielectric layer. A carrier trapping structure is disposed on the semiconductor layer of one synaptic transistor, which can trap carriers. This synaptic transistor achieves long-term memory characteristics through a charge storage mechanism. The semiconductor layer of the other synaptic transistor does not have a carrier trapping structure, and this synaptic transistor exhibits short-term memory characteristics.

[0019] In this invention, the two synaptic transistors share a common gate and a common gate dielectric layer, and there are multiple gates. Each shared gate can simultaneously control both synaptic transistors, and the two synaptic transistors have different output responses with different memory characteristics. Unlike traditional neuromorphic devices that can only perform simple processing of single-modal sensing signals, the artificial neuron device of this invention can achieve parallel and intelligent processing of multimodal sensing signals.

[0020] This artificial neuron device designs two synaptic transistors with different memory characteristics on the same substrate, creating a device with multiple inputs and outputs. A flexible substrate can be used to enhance the device's mechanical flexibility and wearability. The device has multiple independent channels and multiple shared gates, enabling parallel pulsed processing of multimodal sensing signals and achieving device memory characteristics and differentiated outputs at different time scales.

[0021] Compared with traditional technologies, the embodiments of the present invention have the following beneficial effects:

[0022] (1) In terms of device fabrication, the artificial neuron device of the present invention adopts low-cost fabrication technology such as solution method, which has a simple manufacturing process and a compact device structure design. It can be fabricated through high-density array to meet the requirements of large-scale hardware integration. At the same time, a flexible substrate can be used to ensure the wearable characteristics of the device, making it suitable for the needs of flexible electronics and wearable devices.

[0023] (2) Regarding the functional characteristics of the device, this invention enables the artificial neuron device to possess both short-term and long-term memory characteristics through differentiated processing of the semiconductor layer. This multi-timescale memory characteristic simulates the short-term plasticity (STP) and long-term plasticity (LTP) of biological synapses, providing hardware support for complex recognition and classification tasks. In addition, the artificial neuron device can be used to simulate synaptic plasticity regulation and memory retention behavior, providing a technical foundation for novel applications of brain-like computing and brain-like perception.

[0024] (3) In terms of multimodal sensing function, the artificial neuron device of the present invention has the characteristics of multi-end input and multi-end output, and integrates two kinds of synaptic transistors with short-term memory characteristics and long-term memory characteristics. It can process different types of sensing information at the same time, effectively realize the parallelization and pulse processing of multimodal sensing signals, and meet the intelligent sensing needs in complex environments. Attached Figure Description

[0025] Figure 1 This is a schematic exploded view of the artificial neuron device according to an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of the structure of the artificial neuron device according to an embodiment of the present invention;

[0027] Figure 3 This is a schematic circuit diagram of the artificial neuron device according to an embodiment of the present invention;

[0028] Figure 4 This is a physical diagram of an artificial neuron device based on a polyimide substrate according to an embodiment of the present invention;

[0029] Figure 5 This is a transfer curve diagram of the artificial neuron device according to an embodiment of the present invention;

[0030] Figure 6 This is a diagram illustrating the memory retention characteristics of the artificial neuron device according to an embodiment of the present invention;

[0031] Figure 7 This is a pulse number dependence characteristic diagram of the artificial neuron device according to an embodiment of the present invention;

[0032] Figure 8 This is a pulse frequency dependence characteristic diagram of the artificial neuron device according to an embodiment of the present invention;

[0033] Figure 9 This is a flowchart of the dual-modal sensing process of the artificial neuron device according to an embodiment of the present invention.

[0034] Explanation of reference numerals in the attached figures: 10, First synaptic transistor; 20, Second synaptic transistor; 30, Substrate; 40, Semiconductor layer of the second synaptic transistor; 50, Semiconductor layer of the first synaptic transistor; 60, Gate dielectric layer; 71, First gate; 72, Second gate; 73, Third gate; 74, Fourth gate; 80, Carrier trapping structure; 400, Recombinant channel structure;

[0035] S1, first source; D1, first drain; G1, first shared gate; S2, second source; D2, second drain; G2, second shared gate. Detailed Implementation

[0036] The present invention will now be described in detail with reference to the accompanying drawings and specific examples. The following examples will help those who are interested in the study and thinking of the present invention. Similar improvements can be made without departing from the spirit of the present invention. The present invention is not limited to the examples disclosed below.

[0037] like Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, in an embodiment of the present invention, the artificial neuron device includes a substrate 30 and at least two synaptic transistors. The two synaptic transistors are a first synaptic transistor 10 and a second synaptic transistor 20, which are disposed side by side on the substrate 30. The first synaptic transistor 10 and the second synaptic transistor 20 are interconnected through a first shared gate G1 and a second shared gate G2, and share a gate dielectric layer 60, thereby enabling simultaneous processing of voltage pulse signal 1 and voltage pulse signal 2.

[0038] The semiconductor layer 40 of the second synaptic transistor adsorbs carrier-trapping material, which can capture carriers and improve the memory performance of the synaptic transistor through a charge storage mechanism. The second synaptic transistor 20 has a longer memory time and can be called a long-term memory synaptic transistor. The first synaptic transistor 10 does not adsorb carrier-trapping material and has a shorter memory time, and can be called a short-term memory synaptic transistor.

[0039] Because the two synaptic transistors have semiconductor channels with different structures and output responses with different memory characteristics, artificial neuron devices that integrate the two types of synaptic transistors exhibit dual memory characteristics.

[0040] like Figure 2As shown, in this embodiment of the invention, the gate dielectric layer 60 is a polymer electrolyte layer, covering the semiconductor layer and connected to the source, drain, and gate respectively. Under the action of the gate electric field, ions in the polymer electrolyte move directionally and accumulate at the interface between the polymer electrolyte layer and the semiconductor layer. Through electrostatic interaction, these accumulated ions attract charge carriers in the semiconductor channel, forming an electric double layer, changing the concentration of charge carriers in the channel, and thus achieving channel conduction regulation. The number of gates of the synaptic transistor can be multiple, each used to form multiple shared gates. Multimodal sensing signals (such as sound, light, heat, and pressure) are converted into multiple voltage pulse signals through pulse frequency encoding and applied to multiple shared gates of the artificial neuron device, that is, to the corresponding multiple gates in each synaptic transistor, thereby realizing parallel pulsed processing of multimodal sensing signals. This processing method can significantly reduce power consumption. The working mechanism of the artificial neuron device mimics the signal integration and weighting mechanism of biological synapses, providing a hardware solution for neuromorphic computing and intelligent sensing.

[0041] In some embodiments, the number of shared gates in an artificial neuron device can be designed according to the type of information that needs to be identified, and the number of gates of the first synaptic transistor is equal to the number of gates of the second synaptic transistor.

[0042] In a preferred embodiment of the present invention, the number of gates is preferably two. The first synaptic transistor 10 includes a first gate 71 and a second gate 72, and the second synaptic transistor 20 includes a third gate 73 and a fourth gate 74. The first gate 71 and the third gate 73 constitute a first shared gate G1, and the second gate 72 and the fourth gate 74 constitute a second shared gate G2.

[0043] The first shared gate G1, the second shared gate G2, the first source S1, the first drain D1, the second source S2, and the second drain D2 are all metal electrodes, preferably gold electrodes.

[0044] refer to Figure 1 The first source S1 and the first drain D1 form an interdigitated electrode pattern, and the second source S2 and the second drain D2 form an interdigitated electrode pattern.

[0045] In a preferred embodiment of the present invention, the semiconductor layer material of the two synaptic transistors is preferably zinc oxide, zinc tin oxide, indium zinc oxide, etc. The carrier trapping material can be an inorganic low-dimensional nanomaterial, which has advantages such as high specific surface area, abundant surface / interface defects, and tunable band structure, such as nanoparticles, quantum dots, nanowires, graphene nanosheets, two-dimensional nanosheets, etc.

[0046] In a preferred embodiment of the present invention, the gate dielectric layer 60 shared by the first synaptic transistor 10 and the second synaptic transistor 20 may be a polymer electrolyte, preferably chitosan, sodium alginate, etc.

[0047] As a preferred embodiment of the present invention, such as Figure 4 As shown, the first synaptic transistor 10 and the second synaptic transistor 20 are disposed on the same substrate 30. The substrate 30 is preferably a flexible polyimide substrate to ensure the mechanical flexibility of the artificial neuron device, making the artificial neuron device suitable for the needs of flexible electronics and wearable devices.

[0048] To further illustrate the technical effects of the present invention, the following description is provided in conjunction with embodiments.

[0049] Example 1

[0050] A method for fabricating an artificial neuron device with dual memory characteristics. The fabrication method includes the following steps:

[0051] (1) Cleaning and treatment of the substrate: Polyimide film was selected as substrate 30. Substrate 30 was placed in acetone, ethanol and deionized water in sequence. Each liquid was ultrasonically cleaned for 15 minutes. The surface of substrate 30 was dried with nitrogen gas. Substrate 30 was placed in an ultraviolet ozone cleaner for surface treatment for 10 minutes.

[0052] (2) Preparation of the semiconductor layer: Acetic acid and ethanol were mixed at a volume ratio of 1:100, with a volume of 4 ml. 0.2 g of zinc acetate and 0.02 g of indium nitrate were dissolved in the mixture and stirred for 2 hours to obtain a precursor solution. The precursor solution was spin-coated onto a polyimide thin film substrate and annealed at 350 °C to obtain a metal oxide semiconductor layer. Multiple semiconductor layers can be prepared simultaneously. One semiconductor layer is used to form the composite channel structure 400 of the second synaptic transistor 20, and another semiconductor layer serves as the semiconductor layer 50 of the first synaptic transistor.

[0053] (3) Electrode fabrication: According to the pre-designed electrode pattern (refer to...) Figure 4 A first source S1, a second source S2, a first drain D1, a second drain D2, a first shared gate G1, and a second shared gate G2 are fabricated on the surface of a substrate 30 having multiple semiconductor layers. The electrode patterns are referenced from... Figure 4 Two independent semiconductor channels are formed between the first source S1 and the first drain D1, and between the second source S2 and the second drain D2, respectively. The first shared gate G1 and the second shared gate G2 are both located on the side of the semiconductor channel to form a side gate structure.

[0054] (4) Preparation of the carrier trapping structure: The semiconductor layer used to form the second synaptic transistor 20 is slowly immersed in a solution containing gold nanoparticles for 0.5 h to 5 h for surface adsorption, preferably 1 h, to achieve adsorption of gold nanoparticles coated with organic ligands on the surface of the semiconductor channel. Afterwards, the semiconductor layer that has completed surface adsorption is slowly removed from the solution, and the sample is rinsed with ethanol and deionized water, dried with nitrogen, and baked at 110°C for 30 minutes to remove residual solvent, thus completing the preparation of the carrier trapping structure 80. The gold nanoparticles in the carrier trapping structure 80 can serve as carrier trapping centers, improving the long-term memory and non-transferable storage characteristics of the device, and helping to simulate the memory and synaptic characteristics of biological neurons.

[0055] At this point, the semiconductor layer 40 of the second synaptic transistor and the semiconductor layer 50 of the first synaptic transistor can be distinguished.

[0056] Finally, the semiconductor layer 40 of the second synaptic transistor with the carrier trapping structure 80 on its surface and the semiconductor layer 50 of the first synaptic transistor without the carrier trapping structure on its surface are used as the semiconductor channels of the second synaptic transistor 20 and the first synaptic transistor 10, respectively.

[0057] (5) Preparation of gate dielectric layer: Sodium alginate colloid with good mechanical flexibility is selected as gate dielectric layer 60. Sodium alginate colloid is covered on the semiconductor layer of the first synaptic transistor 10 and the second synaptic transistor 20 by flexible bonding method. The gate dielectric layer 60 is connected to the source, drain and shared gate, thereby completing the preparation of artificial neuron device with dual memory characteristics.

[0058] The basic principles and signal processing mechanism of this artificial neuron device will be explained below.

[0059] The artificial neuron device employs a first synaptic transistor 10 and a second synaptic transistor 20 to achieve memory characteristics at two different time scales. Furthermore, by designing multiple shared gates, parallel processing and integration of multimodal input signals are achieved. The sensor module mimics biological receptors, converting different types of external information into sensing signals; the pulse coding module encodes the sensor signals into voltage pulse signals and transmits them to the shared gates of the synaptic transistors; the synaptic transistors mimic biological neurons, regulating the output current based on the amplitude, frequency, and duration of the pulse signals input to the gates.

[0060] The sensor module can be a distance sensor or a temperature sensor, and the pulse coding module is preferably a microcontroller module. The two shared gates are divided according to the input signal type: the first shared gate G1 is used to receive the pulse-coded distance signal; the second shared gate G2 is used to receive the pulse-coded temperature signal. Flexible wires and flexible circuit board connectors are used to achieve integrated design of the sensor module, pulse coding module, and artificial neuron device.

[0061] In artificial neuron devices, the transfer curves of the two synaptic transistors are as follows: Figure 5 As shown, the transfer curves of the first synaptic transistor 10 and the second synaptic transistor 20 exhibit hysteresis differences. Specifically, the second synaptic transistor 20, with a carrier trapping structure 80 on its channel surface, has a wider hysteresis window than the first synaptic transistor 10, indicating stronger memory performance. The pulse response curves obtained after the artificial neuron device receives 20 voltage pulse signals of 5V and 10Hz are shown below. Figure 6 As shown, the first synaptic transistor 10 and the second synaptic transistor 20 exhibit different memory retention characteristics. Specifically, after the pulse stops, the output current of the first synaptic transistor 10 rapidly decays to near the initial current level within a few seconds, exhibiting typical short-term memory characteristics; in contrast, the current decay of the second synaptic transistor 20 is significantly slower, maintaining a higher current level for several minutes, exhibiting long-term memory characteristics.

[0062] When the artificial neuron device sequentially receives 20, 30, and 40 voltage pulses (5V, 10Hz), the resulting pulse response curves are as follows: Figure 7 As shown, the output current of the two synaptic transistors increases with the increase of the number of pulses, indicating that the number of pulses has a regulatory effect on the output current of the two synaptic transistors, demonstrating that the artificial neuron device possesses spike number-dependent plasticity (SNDP). The pulse response curves obtained when the artificial neuron device receives voltage pulses (5V, 20 pulses) at frequencies of 5Hz and 10Hz are shown in the figure. Figure 8 As shown, the output current of the two synaptic transistors increases with the increase of the pulse frequency, indicating that the pulse frequency has a regulatory effect on the output current of the two synaptic transistors, and that the artificial neuron device has spike rate dependent plasticity (SRDP).

[0063] The transmission, encoding, and identification of sensor information in this invention are as follows: Figure 9As shown, the signal employs a pulse frequency encoding strategy, mimicking biological principles, to encode the input signal based on the neuronal firing frequency (i.e., the number of pulses per unit time). Specifically, multiple voltage thresholds are preset, and voltage pulse signals of corresponding frequencies are output according to the range of the input signal, ensuring a positive correlation between the input signal intensity and the output voltage pulse signal. The input signal includes distance signal 1 and temperature signal 2, which are encoded into two voltage pulse signals of different modes, namely voltage pulse signal 1 and voltage pulse signal 2, by the pulse encoding module. These are then applied to the first shared gate G1 and the second shared gate G2 of the artificial neuron device, respectively. Short-term memory synapses output short-term memory synaptic currents, and long-term memory synapses output long-term memory synaptic currents. Biological neurons transmit signals through the synergistic effect of resting potential and action potential. The action potential triggers the release of neurotransmitters at the presynaptic membrane, acting on the postsynaptic membrane to cause potential changes, thereby transmitting signals and altering the synaptic connection strength. This artificial neuron device mimics the working mechanism of biological neurons. It modulates the channel conductance by applying voltage pulse signals to a shared gate, thereby changing the output current. The first and second synaptic transistors possess different memory characteristics, mimicking the short-term and long-term plasticity of biological synapses. The artificial neuron device provided by this invention integrates synaptic transistors with different characteristics and employs a multiple shared-gate structure. At the device level, it simulates the memory characteristics of biological synapses at different time scales, thereby achieving parallel integration and synaptic processing of multimodal signals. It features low power consumption and high parallelism, and can serve as a basic unit for neuromorphic devices and brain-like devices to realize functions such as sensor-memory-computation integration and brain-like perception, providing hardware support for complex recognition and classification tasks.

[0064] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An artificial neuron device with dual memory characteristics, characterized in that: The artificial neuron device includes a substrate and at least two synaptic transistors, which exhibit different memory characteristics. Each synaptic transistor includes a semiconductor layer, a source, a drain, a gate dielectric layer, and a gate. The gate and the semiconductor layer are spaced apart on the substrate to form a side-gate structure. The source and the drain are spaced apart on the semiconductor layer. The gate dielectric layer covers the gate, the semiconductor layer, the source, and the drain. The at least two synaptic transistors include a first synaptic transistor and a second synaptic transistor. The number of gates of the first synaptic transistor and the second synaptic transistor are equal. The gates of the first synaptic transistor and the second synaptic transistor are interconnected in pairs to form a shared gate. The second synaptic transistor includes a carrier trapping structure disposed between the semiconductor layer and the gate dielectric layer of the second synaptic transistor and adsorbed on the surface of the semiconductor layer of the second synaptic transistor, so that the memory time of the second synaptic transistor is longer than that of the first synaptic transistor.

2. The artificial neuron device with dual memory characteristics according to claim 1, characterized in that: The synaptic transistor includes multiple gates, and the number of shared gates is greater than or equal to 2.

3. The artificial neuron device with dual memory characteristics according to claim 1, characterized in that: The carrier trapping structure is made of inorganic low-dimensional nanomaterials; the semiconductor layer is made of metal oxide semiconductors; and the gate dielectric layer is made of polymer electrolytes.

4. The artificial neuron device with dual memory characteristics according to claim 1, characterized in that: The substrate is a silicon wafer or a flexible polyimide film; the thickness of the substrate is greater than 0 μm and less than or equal to 2000 μm.

5. A method for fabricating an artificial neuron device with dual memory characteristics as described in any one of claims 1 to 4, characterized in that, The preparation method includes: At least two synaptic transistors are formed, including a first synaptic transistor and a second synaptic transistor. The fabrication steps of the synaptic transistors include: forming a semiconductor layer on a substrate; forming a source and a drain spaced apart from the semiconductor layer, and forming a gate spaced apart from the semiconductor layer on the substrate, wherein the gate is interconnected with the gate of another synaptic transistor; adsorbing a carrier trapping material onto the surface of the semiconductor layer of the second synaptic transistor to form a carrier trapping structure; and forming a gate dielectric layer covering the gate, the semiconductor layer, the source, and the drain.

6. The preparation method according to claim 5, characterized in that, Forming the semiconductor layer: A metal oxide semiconductor precursor is spin-coated onto the surface of a flexible substrate or a silicon substrate and then annealed at a high temperature to prepare a metal oxide semiconductor thin film as the semiconductor layer; To form the carrier trapping structure: the semiconductor layer of the second synaptic transistor is immersed in a solution of gold nanoparticles coated with organic ligands for surface adsorption, and the surface adsorption time is 0.5 h to 5 h; Forming the gate dielectric layer: A polymer electrolyte is applied to the gate, the semiconductor layer, the source, and the drain using a flexible bonding process.

Images