An LDMOS device and its fabrication method

Abstract

This application discloses an LDMOS device and its fabrication method. The LDMOS device includes: a semiconductor layer of a first doping type; a body region and a drift region located inside the semiconductor layer, the body region having a first doping type, and the drift region having a second doping type opposite to the first doping type, the drift region including a plurality of horizontally arranged partitions separated from each other; a source region located in the body region and a drain region located in the drift region, the source region and the drain region having a second doping type; a gate conductor located on the surface of the semiconductor layer between the source region and the drain region; and a plurality of polysilicon field plates located on the surface of the partitions between the source region and the drain region; wherein the plurality of polysilicon field plates are electrically connected to each other and are externally voltage applied.

Description

Technical Field

[0001] This invention relates to the field of LDMOS device technology, and in particular to an LDMOS device and its fabrication method. Background Technology

[0002] The BCD (Bipolar-CMOS-DMOS) process fabricates bipolar transistors, CMOS (Complementary Metal Oxide Semiconductor), and DMOS (Double-Diffused Metal-Oxide-Semiconductor) devices on the same chip, with the DMOS device being the core component of the entire chip.

[0003] DMOS devices have a similar structure to CMOS devices, but they have a higher drain breakdown voltage. There are two main types of DMOS: VDMOSFET (Vertical double-diffused MOSFET) and LDMOSFET (Lateral double-diffused MOSFET). DMOS devices operate at voltages from 12V to 90V, and even ultra-high voltages from 500V to 700V. LDMOS devices typically improve their horizontal breakdown voltage by optimizing the drain design.

[0004] In traditional technologies, a field plate structure is typically placed on the surface of the semiconductor layer between the gate conductor and the drain region. The breakdown voltage of the device is improved by increasing the length and thickness of the field plate structure, or a shallow trench isolation structure is placed at the drain end of the device, and the breakdown voltage is improved by increasing the depth and width of the shallow trench isolation structure. However, increasing the length and thickness of the field plate structure or increasing the depth and width of the shallow trench isolation structure results in an excessively large device size, and the on-resistance also increases accordingly. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide an LDMOS device and a method for fabricating the same, which reduces the doping concentration of the drift region by setting the drift region to include multiple mutually separated partitions, and sets multiple interconnected polysilicon field plates on the corresponding partitions, thereby improving the breakdown voltage of the LDMOS device.

[0006] According to one aspect of the present invention, an LDMOS device is provided, comprising: a semiconductor layer of a first doping type; a body region and a drift region located within the semiconductor layer, the body region having a first doping type, the drift region having a second doping type opposite to the first doping type, the drift region comprising a plurality of horizontally arranged partitions separated from each other; a source region located in the body region and a drain region located in the drift region, the source region and the drain region having a second doping type; a gate conductor located on the surface of the semiconductor layer between the source region and the drain region; and a plurality of polysilicon field plates located on the surfaces of the partitions between the source region and the drain region; wherein the plurality of polysilicon field plates are electrically connected to each other and are externally voltage applied.

[0007] Optionally, the spacing between adjacent partitions on the side closer to the leak region is smaller than the spacing between adjacent partitions on the side closer to the source region.

[0008] Optionally, the spacing between adjacent partitions gradually increases in the direction from the drain region to the source region.

[0009] Optionally, it further includes a shallow trench isolation structure, the shallow trench isolation structure comprising: a first shallow trench isolation structure adjacent to the drain region on the side of the drain region closer to the source region; and a second shallow trench isolation structure adjacent to the drain region on the side of the drain region farther from the source region; an electrical connection portion is provided in the first shallow trench isolation structure, and the gate conductor is electrically connected to the electrical connection portion; the drain region extends in a second direction, and the first shallow trench isolation structure adjacent to the drain region and the electrical connection portion located in the first shallow trench isolation structure extend accordingly in the second direction.

[0010] Optionally, the system further includes a shallow trench isolation structure, comprising: a first shallow trench isolation structure adjacent to the drain region on the side of the drain region closer to the source region; a second shallow trench isolation structure adjacent to the drain region on the side of the drain region farther from the source region; and a third shallow trench isolation structure adjacent to the drain region at its end; the drain region extends in a second direction, corresponding to the first and second shallow trench isolation structures, and the third shallow trench isolation structure extends in a first direction intersecting the second direction; the third shallow trench isolation structure is connected to both the first and second shallow trench isolation structures to form an annular shallow trench isolation structure; an electrical connection portion is provided in the shallow trench isolation structure, and the gate conductor is electrically connected to the electrical connection portion; the electrical connection portion is correspondingly configured as an annular structure surrounding the drain region.

[0011] Optionally, the leak region and the shallow trench isolation structure are located in the partition furthest from the source region.

[0012] Optionally, the polycrystalline silicon field plate is made of polycrystalline silicon of a first doping type.

[0013] According to another aspect of the present invention, a method for fabricating an LDMOS device is provided, comprising: forming a body region and a drift region in a semiconductor layer, the semiconductor layer and the body region having a first doping type, the drift region having a second doping type opposite to the first doping type, the drift region comprising a plurality of partitions arranged in a horizontal direction and separated from each other; forming a gate conductor and a plurality of polysilicon field plates on the surface of the semiconductor layer; forming a drain region of the second doping type in the drift region, forming a source region of the second doping type in the body region, the polysilicon field plates being located on the surface of the partitions between the source region and the drain region; wherein the plurality of polysilicon field plates are electrically connected to each other and are externally voltage applied.

[0014] Optionally, before forming the body region and the drift region, the step of forming a shallow trench isolation structure is further included; the shallow trench isolation structure includes: a first shallow trench isolation structure adjacent to the drain region on the side of the drain region closer to the source region; and a second shallow trench isolation structure adjacent to the drain region on the side of the drain region away from the source region; after forming the source region and the drain region, the step of forming an electrical connection in the first shallow trench isolation structure is further included, the gate conductor being electrically connected to the electrical connection; the drain region extends in a second direction, and the first shallow trench isolation structure adjacent to the drain region and the electrical connection located in the first shallow trench isolation structure extend accordingly in the second direction.

[0015] Optionally, before forming the body region and the drift region, the method further includes the step of forming a shallow trench isolation structure; a first shallow trench isolation structure adjacent to the drain region on the side of the drain region closer to the source region; a second shallow trench isolation structure adjacent to the drain region on the side of the drain region farther from the source region; and a third shallow trench isolation structure adjacent to the drain region at the end of the drain region; the drain region extends in a second direction, corresponding to the first shallow trench isolation structure and the second shallow trench isolation structure, and the third shallow trench isolation structure extends in a first direction intersecting the second direction, the third shallow trench isolation structure being connected to the first shallow trench isolation structure and the second shallow trench isolation structure respectively to form an annular shallow trench isolation structure; after forming the source region and the drain region, the method further includes the step of forming an electrical connection portion in the first shallow trench isolation structure, the gate conductor being electrically connected to the electrical connection portion, the electrical connection portion being correspondingly configured as an annular shape surrounding the drain region.

[0016] The unexpected technical effect of this application is:

[0017] In this embodiment, the drift region is configured to include multiple mutually separated partitions. Adjacent partitions are isolated by semiconductor layers with lower doping concentrations. Dopant ions in the partitions diffuse into the adjacent semiconductor layers, thereby reducing the overall doping concentration of the drift region and obtaining a higher breakdown voltage.

[0018] Furthermore, this application introduces a first-doped polysilicon field plate in the secondary voltage reduction region between the first shallow trench isolation structure and the drain region. The presence of the polysilicon field plate not only modulates the electric field but also assists in the depletion of the drift region, achieving a double resurf effect. Furthermore, multiple polysilicon field plates are electrically connected and externally voltaged to reduce the peak electric field at the edge of the gate conductor and avoid introducing new electric field spikes.

[0019] Furthermore, on the side closer to the drain region, there is a smaller spacing between adjacent partitions, and on the side closer to the source region, there is a larger spacing between adjacent partitions. This can modulate the electric field and reduce the surface electric field, optimize the on-resistance, and avoid channel current congestion, thus achieving a smooth transition with the channel region (body region).

[0020] In this embodiment, a first shallow trench isolation structure is provided in the main voltage drop region (the high electric field region near the drain region) near the drain region, and the gate conductor is connected to the first shallow trench isolation structure via an electrical connection to introduce an equipotential shielding layer in the main voltage drop region. This forces the high electric field in this region to be pushed from the surface of the semiconductor layer (silicon) to the interior of the first shallow trench isolation structure, thereby dispersing the lateral electric field, reducing the surface electric field, realizing the "longitudinal extension" of the electric field, and significantly increasing the breakdown voltage (BVD).

[0021] In a preferred embodiment, the shallow trench isolation structure and electrical connection are configured as a ring around the drain region. The ring-shaped electrical connection simultaneously wraps around the drain region 105 in both the first and second directions, dispersing the electric field in all directions and further reducing the local electric field peak. The ring-shaped electrical connection forms a "barrel-shaped" potential barrier, constraining the drain region electric field in all directions, which is particularly suitable for high-voltage (>200V) or multi-directional current expansion scenarios (such as RF LDMOS). Furthermore, the ring-shaped electrical connection provides more sufficient charge compensation with the drift region, optimizing the depletion layer expansion. Attached Figure Description

[0022] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0023] Figure 1a A cross-sectional view of a conventional LDMOS device is shown;

[0024] Figure 1b A cross-sectional view of another conventional LDMOS device is shown;

[0025] Figure 2 A top view of the LDMOS device according to the first embodiment of this application is shown;

[0026] Figure 3 It shows Figure 2 Cross-sectional view along the AA direction;

[0027] Figure 4 A top view of the LDMOS device according to the second embodiment of this application is shown;

[0028] Figures 5a to 5d It shows Figure 2 The diagram shows cross-sectional views of various stages in the manufacturing process of an LDMOS device; where:

[0029] Figure 5a A schematic diagram of a shallow trench isolation structure formed in a semiconductor layer is shown.

[0030] Figure 5b A schematic diagram of the structure forming the drift region and the volume region is shown;

[0031] Figure 5c A schematic diagram of the structure forming the gate conductor and the polysilicon field plate is shown;

[0032] Figure 5d A schematic diagram of the structure forming the source and drain regions is shown;

[0033] Explanation of reference numerals in the attached figures: 101-Semiconductor layer; 102-Bulk region; 103-Drift region; 103a-Partition; 104-Source region; 105-Drain region; 106-Gate dielectric layer; 107-Gate conductor; 108-Field plate structure; 109-Shallow trench isolation structure; 109a-First shallow trench isolation structure; 109b-Second shallow trench isolation structure; 109c-Third shallow trench isolation structure; 110-Electrical connection; 111-Dielectric layer; 112-Polysilicon field plate; First polysilicon field plate 112a; Second polysilicon field plate 112b; Third polysilicon field plate 112c. Detailed Implementation

[0034] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0035] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.

[0036] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on top of and adjacent to".

[0037] Unless otherwise specified below, the various parts of an LDMOS device may be made of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as gallium arsenide (GaAs) and gallium nitride (GaN), group IV-IV semiconductors such as silicon carbide (SiC), group II-VI compound semiconductors such as cadmium sulfide (CdS) and cadmium telluride (CdTe), and group IV semiconductors such as silicon (Si) and germanium (Ge). The gate conductor may be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor comprising a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, and PtSi. x The gate dielectric can be composed of Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric can be made of SiO2 or materials with a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, and titanates. Furthermore, the gate dielectric can be formed not only of materials known to those skilled in the art, but also of materials developed in the future for use as gate dielectrics.

[0038] This application may be presented in various forms, some of which will be described below.

[0039] Figure 1a A cross-sectional view of a conventional LDMOS device is shown, such as... Figure 1a As shown, the LDMOS device includes a semiconductor layer 101, a body region 102 and a drift region 103 located in the semiconductor layer 101, a source region 104 located in the body region 102, a drain region 105 located in the drift region 103, a gate dielectric layer 106 located on the surface of the semiconductor layer 101, a gate conductor 107 located on the gate dielectric layer 106, and a field plate structure 108 located between the gate conductor 107 and the drain region 105. Figure 1a In the LDMOS device shown, the horizontal breakdown voltage of the LDMOS device is improved by increasing the length and thickness of the field plate structure 108.

[0040] Figure 1b A cross-sectional view of another conventional LDMOS device is shown, such as... Figure 1b As shown, the LDMOS device includes a semiconductor layer 101, a body region 102 and a drift region 103 located in the semiconductor layer 101, a source region 104 located in the body region 102, a drain region 105 located in the drift region 103, a gate dielectric layer 106 located on the surface of the semiconductor layer 101, a gate conductor 107 located on the gate dielectric layer 106, and a shallow trench isolation (STI) structure 109 located in the drift region 103. Figure 1b In the LDMOS device shown, the horizontal breakdown voltage of the LDMOS device is improved by increasing the depth and width of the shallow trench isolation structure 109.

[0041] As the operating voltage required for LDMOS devices increases Figure 1a and Figure 1b The LDMOS device shown requires increasing the length and thickness of the field plate structure 108 or the depth and width of the shallow trench isolation structure 109 to improve the horizontal breakdown voltage of the LDMOS device. Furthermore, Figure 1a and Figure 1b The LDMOS device shown typically requires increasing the thickness of the semiconductor layer 101 to improve longitudinal breakdown voltage and reduce latch-up effect. Figure 1a and Figure 1b The LDMOS device shown increases the device size and the difficulty of fabrication.

[0042] Figure 2 A top view of the LDMOS device according to the first embodiment of this application is shown; Figure 3 It shows Figure 2 Cross-sectional view along the AA direction. (See image.) Figure 2 and Figure 3 As shown, the LDMOS device includes a semiconductor layer 101, a body region 102 and a drift region 103 located in the semiconductor layer 101, a source region 104 located in the body region 102, a drain region 105 located in the drift region 103, a gate dielectric layer 106 located on the surface of the semiconductor layer 101 between the source region 104 and the drain region 105, and a gate conductor 107 located on the gate dielectric layer 106. The semiconductor layer 101 and the body region 102 have a first doping type, and the drift region 103, the source region 104, and the drain region 105 have a second doping type. The first doping type is either N-type or P-type, and the second doping type is either N-type or P-type. In this embodiment, the first doping type is, for example, P-type doping, and the second doping type is, for example, N-type doping.

[0043] Semiconductor layer 101 can be selected from any of a semiconductor substrate, a doped epitaxial layer (EPI), or a combination thereof. Body region 102 and drift region 103 extend from the surface of semiconductor layer 101 toward its interior, respectively. Source region 104 extends from the surface of body region 102 toward its interior; drain region 105 extends from the surface of drift region 103 toward its interior. Drain region 105 and source region 104 are aligned in a first direction (e.g., ...). Figure 2 The source region 104 and the drain region 105 are arranged in the second direction (e.g., along the X-axis direction), and are arranged in the second direction (e.g., along the X-axis direction). Figure 2 (Extends along the Y-axis direction).

[0044] In this embodiment, the drift region 103 includes multiple regions in a first direction (e.g., Figure 2 The regions 103a are arranged in a manner that follows the X-axis direction. These regions 103a are separated from each other, and adjacent regions 103a are isolated by a semiconductor layer 101 with a lower doping concentration. A drain region 105 is located in one of the regions 103a. In one embodiment, the drain region 105 is located in the region 103a furthest from the source region 104.

[0045] Furthermore, on the side near the drain region 105, adjacent partitions 103a have a smaller spacing, while on the side near the source region 104, adjacent partitions 103a have a larger spacing. This embodiment, by setting the spacing between adjacent partitions 103a, ensures a higher doping concentration on the side near the drain region 105 to provide sufficient carriers and reduce the on-resistance Ron, while a lower doping concentration on the side near the source region 104 ensures complete depletion under high voltage, thereby improving the device's breakdown voltage (BV).

[0046] In one embodiment, the spacing between adjacent partitions 103a gradually increases in the direction from drain region 105 to source region 104 to ensure a smooth transition of the overall doping concentration of drift region 103 in the direction from drain region 105 to source region 104.

[0047] The LDMOS device includes a shallow trench isolation structure 109. The shallow trench isolation structure 109 is adjacent to the drain region 105 at least on the side of the drain region 105 closest to the source region 104. In this embodiment, the shallow trench isolation structure 109 is located on a first side (the side of the drain region 105 closest to the source region 104) and a second side (the side of the drain region 105 furthest from the source region 104) of the drain region 105, and the shallow trench isolation structure 109 is adjacent to the drain region 105. For example, a first shallow trench isolation structure 109a is provided on the first side of the drain region 105 (the side of the drain region 105 closest to the source region 104) adjacent to the drain region 105, and a second shallow trench isolation structure 109b is provided on the second side of the drain region 105 (the side of the drain region 105 furthest from the source region 104) adjacent to the drain region 105. Corresponding to the drain region 105 in a second direction (e.g.) Figure 2 Extending in the Y-axis direction, the first shallow trench isolation structure 109a and the second shallow trench isolation structure 109b also extend in the second direction (e.g., in the Y-axis direction). Figure 2 (Extends along the Y-axis direction).

[0048] Furthermore, the first shallow trench isolation structure 109a is located in the partition 103a farthest from the source region 104 to ensure that the first shallow trench isolation structure 109a can be adjacent to the drain region 105. The electric field distribution around the drain region 105 is relatively concentrated. In this embodiment, the first shallow trench isolation structure 109a is adjacent to the drain region 105 to minimize the electric field. In this embodiment, the first shallow trench isolation structure 109a is located in only one partition 103a, that is, the partition 103a farthest from the source region 104. In other embodiments, the first shallow trench isolation structure 109a is located in the partition 103a farthest from the source region 104 and extends into other partitions 103a.

[0049] Furthermore, an electrical connection portion 110 is provided in at least one shallow trench isolation structure 109 (i.e., the first shallow trench isolation structure 109a) on the side of the drain region 105 near the source region 104. The gate conductor 107 is electrically connected to the electrical connection portion 110 to connect the gate conductor 107 to the shallow trench isolation structure 109. Connecting the gate conductor 107 to the shallow trench isolation structure 109 is equivalent to adding a "virtual electrode" at the drain end, which is equivalent to introducing an equipotential shielding layer at the drain end. This can push the high electric field region from the surface of the semiconductor layer 101 (silicon) into the shallow trench isolation structure 109, thereby dispersing the lateral electric field, reducing the surface electric field, achieving "vertical extension" of the electric field, and significantly increasing the breakdown voltage (BVD). On the other hand, the introduction of the electrical connection portion 110 reduces the gate-drain capacitance (C). gd This improved the switching speed of the device.

[0050] The LDMOS device includes multiple polysilicon field plates 112, such as a first polysilicon field plate 112a, a second polysilicon field plate 112b, and a third polysilicon field plate 112c, but is not limited thereto. The polysilicon field plates 112 are located on the surface of partition 103a of the drift region 103 between the gate conductor 107 and the drain region 105, and a dielectric layer 111 is disposed between the polysilicon field plates 112 and partition 103a of the drift region 103. Furthermore, the multiple polysilicon field plates 112 are electrically connected and can be externally voltaged. In one embodiment, the external voltage of the multiple polysilicon field plates 112 is 1 / 3 to 1 / 2 of the operating voltage of the LDMOS device.

[0051] Furthermore, the polysilicon field plate 112 uses polysilicon of the first doping type (P-type doping). The presence of the P-type doped polysilicon field plate 112 can not only adjust the electric field but also assist in depleting the drift region 103 of the second doping type. Simultaneously, by increasing the concentration of the drift region 103, it can achieve a high voltage drop while maintaining a relatively good on-resistance Ron, achieving a double resurf effect. This significantly improves the breakdown voltage BV while maintaining a good on-resistance Ron, achieving a high quality factor FOM (Figure of Merit). Wherein, the device's quality factor FOM = BV. 2 / Ron, BV is the withstand voltage of the device.

[0052] In this embodiment, the drift region 103 is configured to include multiple mutually separated partitions 103a. Adjacent partitions 103a are isolated by a semiconductor layer 101 with a lower doping concentration. Dopant ions in partition 103a diffuse into the adjacent semiconductor layer 101, thereby reducing the overall doping concentration of the drift region 103 and obtaining a higher breakdown voltage. Furthermore, on the side near the drain region 105, adjacent partitions 103a have a smaller spacing, while on the side near the source region 104, adjacent partitions 103a have a larger spacing. This can modulate the electric field and reduce the surface electric field, optimize the on-resistance, and avoid channel current congestion, thus achieving a smooth transition with the channel region (body region 102).

[0053] In this embodiment, a first shallow trench isolation structure 109a is provided in the main voltage reduction region (the high electric field region near the drain region 105) near the drain region 105, and the gate conductor 107 is connected to the first shallow trench isolation structure 109a via the electrical connection portion 110, so as to introduce an equipotential shielding layer in the main voltage reduction region, forcibly pushing the high electric field in this region from the surface of the semiconductor layer 101 (silicon) to the interior of the first shallow trench isolation structure 109a, thereby dispersing the lateral electric field, reducing the surface electric field, realizing the "longitudinal extension" of the electric field, and significantly increasing the breakdown voltage (BVD).

[0054] Furthermore, this application introduces a first-doped polysilicon field plate 112 in the secondary step-down region between the first shallow trench isolation structure 109a and the source region 104. The presence of the first-doped polysilicon field plate 112 can not only regulate the electric field but also assist in the depletion of the drift region 103, achieving a double resurf effect. Furthermore, multiple polysilicon field plates 112 are electrically connected and externally voltaged to reduce the peak electric field at the edge of the gate conductor 107 and avoid introducing new electric field spikes.

[0055] Figure 4A top view of the LDMOS device according to the second embodiment of this application is shown. Figure 4 As shown, unlike the first embodiment, in this embodiment, the shallow trench isolation structure 109 is annular around the drain region 105. Specifically, the drain region 105 is a straight line extending in a first direction. A first shallow trench isolation structure 109a adjacent to the drain region 105 is provided on the first side of the drain region 105 (e.g., the side of the drain region 105 close to the source region 104), and a second shallow trench isolation structure 109b adjacent to the drain region 105 is provided on the second side of the drain region 105 (e.g., the side of the drain region 105 away from the source region 104). A third shallow trench isolation structure 109c adjacent to the end of the drain region 105 is provided at the end of the drain region 105. The third shallow trench isolation structure 109c is connected to the first shallow trench isolation structure 109a and the second shallow trench isolation structure 109b respectively to form an annular shallow trench isolation structure 109.

[0056] Furthermore, the electrical connection 110 is also correspondingly configured as an annular shape surrounding the drain region 105. The gate conductor 107 is electrically connected to the electrical connection 110 via a metal forming wire (not shown) to connect the gate conductor 107 to the shallow trench isolation structure 109. The annular electrical connection 110 is in a first direction (e.g.) Figure 4 (in the X-axis direction) and the second direction (e.g.) Figure 4 The annular electrical connection 110 simultaneously surrounds the drain region 105 along the Y-axis, dispersing the electric field in all directions and further reducing the local electric field peak. The annular electrical connection 110 forms a "barrel-shaped" potential barrier, comprehensively confining the drain region's electric field, making it particularly suitable for high-voltage (>200V) or multi-directional current expansion scenarios (such as RF LDMOS). Furthermore, the annular electrical connection 110 provides more adequate charge compensation with the drift region 103, optimizing depletion layer expansion.

[0057] Figures 5a to 5d It shows Figure 2 The diagrams shown below are cross-sectional views of various stages in the manufacturing process of LDMOS devices. The following will combine... Figures 5a to 5d The manufacturing process of the LDMOS device according to the embodiments of this application will be described.

[0058] like Figure 5a As shown, a shallow trench isolation structure 109 is formed in the semiconductor layer 101.

[0059] In this step, shallow trenches are formed in the semiconductor layer 101 using processes such as photolithography, etching, and deposition, and the shallow trenches are filled with an isolation medium to form a shallow trench isolation structure 109.

[0060] like Figure 5b As shown, a drift region 103 and a body region 102 are formed.

[0061] In this step, a mask layer is formed on the surface of semiconductor layer 101, and the mask layer is patterned.

[0062] The mask layer is, for example, a photoresist layer. A photomask is placed on top of the mask layer. Based on the reaction mechanism of the photoresist layer, it can be divided into positive photoresist and negative photoresist. The exposed portion of the positive photoresist is removed during development to form an opening area, while the exposed portion of the negative photoresist is retained during development to form a masking area. It can be understood that, in the case of using a negative photoresist, the etched hole pattern of the photomask is a complementary pattern to that using a positive photoresist.

[0063] In this embodiment, a positive resist is used as an example. The photomask includes a light-blocking area and a light-transmitting area. During the photolithography step, the mask layer is exposed through the photomask, and the exposed portion of the mask layer is removed during development, thereby forming an opening area in the mask layer corresponding to the light-transmitting area of ​​the photomask. The mask layer includes multiple mutually separated opening areas.

[0064] Next, using a mask layer as a mask, ion implantation is performed on the exposed portion of the semiconductor layer 101 through multiple mutually separated opening regions of the mask layer to form multiple mutually separated partitions 103a within the semiconductor layer 101. The multiple mutually separated partitions 103a constitute drift regions 103. After the drift regions 103 are formed, the mask layer is removed.

[0065] Next, a patterned mask layer is formed on the surface of semiconductor layer 101, and ion implantation is performed on semiconductor layer 101 through the patterned mask layer to form body region 102.

[0066] Among them, the spacing between adjacent partitions 103a is smaller on the side away from body region 102 compared to the side closer to body region 102.

[0067] like Figure 5c As shown, a gate conductor 107 and a polysilicon field plate 112 are formed.

[0068] In this step, an oxide layer and a polysilicon layer are formed, and the polysilicon layer and oxide layer are etched to form a gate conductor 107 and a polysilicon field plate 112 that are separated from each other. The oxide layer between the gate conductor 107 and the semiconductor layer 101 forms a gate dielectric layer 106, the polysilicon field plate 112 is located on the surface of a partition 103a of the corresponding drift region 103, and the oxide layer between the polysilicon field plate 112 and the surface of partition 103a forms a dielectric layer 111.

[0069] like Figure 5d As shown, source region 104 and drain region 105 are formed, for example, by photolithography and ion implantation processes.

[0070] The leak region 105 is located in the drift region 103, specifically in one of the multiple partitions 103a, while the source region 104 is located in the body region 102.

[0071] Next, an electrical connection 110 is formed in the shallow trench isolation structure 109.

[0072] The unexpected technical effect of this application is:

[0073] In this embodiment, the drift region is configured to include multiple mutually separated partitions. Adjacent partitions are isolated by semiconductor layers with lower doping concentrations. Dopant ions in the partitions diffuse into the adjacent semiconductor layers, thereby reducing the overall doping concentration of the drift region and obtaining a higher breakdown voltage.

[0074] Furthermore, this application introduces a first-doped polysilicon field plate in the secondary voltage reduction region between the first shallow trench isolation structure and the drain region. The presence of the polysilicon field plate not only modulates the electric field but also assists in the depletion of the drift region, achieving a double resurf effect. Furthermore, multiple polysilicon field plates are electrically connected and externally voltaged to reduce the peak electric field at the edge of the gate conductor and avoid introducing new electric field spikes.

[0075] Furthermore, on the side closer to the drain region, there is a smaller spacing between adjacent partitions, and on the side closer to the source region, there is a larger spacing between adjacent partitions. This can modulate the electric field and reduce the surface electric field, optimize the on-resistance, and avoid channel current congestion, thus achieving a smooth transition with the channel region (body region).

[0076] In this embodiment, a first shallow trench isolation structure is provided in the main voltage drop region (the high electric field region near the drain region) near the drain region, and the gate conductor is connected to the first shallow trench isolation structure via an electrical connection to introduce an equipotential shielding layer in the main voltage drop region. This forces the high electric field in this region to be pushed from the surface of the semiconductor layer (silicon) to the interior of the first shallow trench isolation structure, thereby dispersing the lateral electric field, reducing the surface electric field, realizing the "longitudinal extension" of the electric field, and significantly increasing the breakdown voltage (BVD).

[0077] In a preferred embodiment, the shallow trench isolation structure and electrical connection are configured as a ring around the drain region. The ring-shaped electrical connection simultaneously wraps around the drain region 105 in both the first and second directions, dispersing the electric field in all directions and further reducing the local electric field peak. The ring-shaped electrical connection forms a "barrel-shaped" potential barrier, constraining the drain region electric field in all directions, which is particularly suitable for high-voltage (>200V) or multi-directional current expansion scenarios (such as RF LDMOS). Furthermore, the ring-shaped electrical connection provides more sufficient charge compensation with the drift region, optimizing the depletion layer expansion.

[0078] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. An LDMOS device, characterized by, Comprise: a semiconductor layer of a first doping type; a body region and a drift region inside the semiconductor layer, the body region having the first doping type, the drift region having a second doping type opposite to the first doping type; a source region in the body region and a drain region in the drift region, the source region and the drain region having the second doping type; a gate conductor on the surface of the semiconductor layer between the source region and the drain region; and a plurality of polysilicon field plates on the surface of the partition between the source region and the drain region, the polysilicon field plates being of polysilicon of the first doping type; wherein the plurality of polysilicon field plates are electrically connected and externally connected to a voltage; the drift region comprises a plurality of partitions arranged in a horizontal direction, the plurality of partitions are separated from each other, and the spacing between adjacent partitions on the side close to the drain region is smaller than the spacing between adjacent partitions on the side close to the source region. The spacing between adjacent partitions gradually increases in the direction from the drain region to the source region.

2. The LDMOS device of claim 1, wherein, Further comprising a shallow trench isolation structure, the shallow trench isolation structure comprising:

3. The LDMOS device of claim 1, wherein, a first shallow trench isolation structure adjacent to the drain region on the side close to the source region; and a second shallow trench isolation structure adjacent to the drain region on the side away from the source region; an electrical connection part is arranged in the first shallow trench isolation structure, and the gate conductor is electrically connected to the electrical connection part; the drain region extends in a second direction, and the first shallow trench isolation structure adjacent to the drain region and the electrical connection part arranged in the first shallow trench isolation structure correspondingly extend in the second direction. Further comprising a shallow trench isolation structure, the shallow trench isolation structure comprising:

4. The LDMOS device of claim 1, wherein, a first shallow trench isolation structure adjacent to the drain region on the side close to the source region; a second shallow trench isolation structure adjacent to the drain region on the side away from the source region; and a third shallow trench isolation structure adjacent to the drain region at an end portion of the drain region; the drain region extends in a second direction, and the first shallow trench isolation structure and the second shallow trench isolation structure correspondingly extend in the second direction, the third shallow trench isolation structure extends in a first direction intersecting the second direction, and the third shallow trench isolation structure is connected to the first shallow trench isolation structure and the second shallow trench isolation structure respectively to form a ring-shaped shallow trench isolation structure; an electrical connection part is arranged in the shallow trench isolation structure, and the gate conductor is electrically connected to the electrical connection part; the electrical connection part is correspondingly arranged in a ring shape around the drain region. The drain region and the shallow trench isolation structure are located in the partition farthest from the source region.

5. The LDMOS device of claim 3 or 4, wherein, Comprise:

6. A method of fabricating an LDMOS device, characterized by, forming a body region and a drift region in a semiconductor layer, the semiconductor layer and the body region having a first doping type, and the drift region having a second doping type opposite to the first doping type; forming a gate conductor and a plurality of polysilicon field plates on the surface of the semiconductor layer, the polysilicon field plates being of polysilicon of the first doping type; and ​ ​ a drain region of a second doping type is formed in the drift region, a source region of the second doping type is formed in the body region, and the polysilicon field plate is located on a surface of a sub-region between the source region and the drain region; wherein the plurality of polysilicon field plates are electrically connected and externally connected to a voltage; the drift region comprises a plurality of sub-regions arranged in a horizontal direction, the plurality of sub-regions are separated from each other, and a distance between adjacent sub-regions on a side close to the drain region is smaller than a distance between adjacent sub-regions on a side close to the source region.

7. The method of claim 6, wherein the method further comprises: Before the body region and the drift region are formed, a step of forming a shallow trench isolation structure is further included; the shallow trench isolation structure comprises: a first shallow trench isolation structure adjacent to the drain region on a side of the drain region close to the source region; and a second shallow trench isolation structure adjacent to the drain region on a side of the drain region away from the source region. After the source region and the drain region are formed, a step of forming an electrical connection part in the first shallow trench isolation structure is further included, and the gate conductor is electrically connected to the electrical connection part. The drain region extends in a second direction, and the first shallow trench isolation structure adjacent to the drain region and the electrical connection part in the first shallow trench isolation structure correspondingly extend in the second direction. Before the body region and the drift region are formed, a step of forming a shallow trench isolation structure is further included; 8. The method of claim 6, wherein the LDMOS device is formed by: a first shallow trench isolation structure adjacent to the drain region on a side of the drain region close to the source region; a second shallow trench isolation structure adjacent to the drain region on a side of the drain region away from the source region; and a third shallow trench isolation structure adjacent to the drain region on an end of the drain region. The drain region extends in a second direction, the first shallow trench isolation structure and the second shallow trench isolation structure correspondingly extend in the second direction, the third shallow trench isolation structure extends in a first direction intersecting the second direction, and the third shallow trench isolation structure is connected to the first shallow trench isolation structure and the second shallow trench isolation structure respectively to form a ring-shaped shallow trench isolation structure. After the source region and the drain region are formed, a step of forming an electrical connection part in the first shallow trench isolation structure is further included, and the gate conductor is electrically connected to the electrical connection part, which is correspondingly arranged in a ring shape around the drain region. ​ ​

Images