LDMOS device
By setting a groove on the top surface of the substrate in the LDMOS device, the curvature effect of the drain region is eliminated, resulting in higher breakdown voltage and lower on-resistance, and solving the charge imbalance problem caused by the drain region in the prior art.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI BRIGHT POWER SEMICONDUCTOR CO LTD
- Filing Date
- 2025-07-04
- Publication Date
- 2026-06-23
AI Technical Summary
The high doping concentration in the drain region of existing LDMOS devices leads to the drain curvature effect, which makes it impossible to achieve a high breakdown voltage and a low on-resistance.
A groove is provided on one side of the top surface of the substrate, the drain region is located in the groove, the drift region is located below the bottom surface of the groove and partly below the drain region, the side surface of the drain region is located above the top surface of the drift region, the gate structure covers part of the body region and the drift region, and the source region is located on the side of the gate structure away from the drain region.
The curvature effect of the drain region on the drift region is eliminated, resulting in a better reduction of the surface electric field, higher breakdown voltage and lower on-resistance, thus improving product competitiveness.
Smart Images
Figure CN224401989U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to an LDMOS device. Background Technology
[0002] Lateral double-diffused metal oxide semiconductor (LDMOS) devices have high voltage withstand capability and high current drive characteristics, and are widely used in radio frequency power, power management, automotive electronics and other fields.
[0003] Figures 1 to 5 This is a schematic diagram illustrating the fabrication process of an existing LDMOS device. The fabrication process of this LDMOS device is as follows: Figure 1 As shown, a first mask layer 101 is formed on a P-type substrate 100. Ion implantation is performed using the first mask layer 101 as a mask to form a P-type bulk region 102 in the substrate 100. The first mask layer 101 is then removed. Figure 2 As shown, a second mask layer 103 is formed on the substrate 100, and an ion implantation process is performed using the second mask layer 103 as a mask to form an N-type drift region 104 in the substrate 100; the second mask layer 103 is then removed; as... Figure 3 As shown, a reduced surface field oxide layer is formed on the substrate 100, and a third mask layer 105 is formed on the reduced surface field oxide layer. Using the third mask layer 105 as a mask, part of the reduced surface field oxide layer is etched away to form a reduced surface field oxide (ROX) layer 106; as shown. Figure 4 As shown, a gate oxide layer 107 and a gate electrode 108 located on the gate oxide layer 107 are formed on the substrate 100. The gate electrode 108 covers a portion of the surface electric field reducing oxide layer 106; as Figure 5 As shown, a source region 109 and a body region lead-out region 110 are formed on the body region 102, and a drain region 111 is formed on the drift region 104. The source region 109 and the drain region 111 are N+ regions, and the body region lead-out region 110 is a P+ region. A metal silicide barrier layer (not shown) is formed on the substrate 100. Under the protection of the metal silicide barrier layer, metal silicides (not shown) are formed on the top surfaces of the source region 109, the body region lead-out region 110, the gate electrode 108, and the drain region 111. Corresponding contact plugs (not shown) are formed on the metal silicides of the source region 109, the body region lead-out region 110, the gate electrode 108, and the drain region 111.
[0004] In the aforementioned LDMOS device, the highly doped drain region 111 is embedded in the drift region 104, which will produce a drain curvature effect, resulting in an imbalance of charges in the drift region 104. Consequently, it is impossible to achieve a good optimization result in reducing the surface electric field (RESURF), and it is impossible to obtain a high breakdown voltage (BV) and a low on-resistance (Rsp). Utility Model Content
[0005] One of the objectives of this invention is to provide an LDMOS device that can eliminate the drain curvature effect caused by the drain region, making the charge in the drift region more balanced, achieving better RESURF optimization, and thus obtaining higher breakdown voltage and lower on-resistance.
[0006] To achieve the above objectives, the LDMOS device provided by this utility model includes: a substrate having a groove on one side of its top surface and a protrusion defined by the groove; a drain region located in the protrusion; a drift region located in the substrate below the bottom surface of the groove and partially located below the drain region, the side surface of the drain region being located above the top surface of the drift region and the top surface of the drift region being in contact with the bottom surface of the drain region; a body region located in the substrate below the bottom surface of the groove and located on the side of the drift region away from the drain region; a gate structure located in the groove and covering a portion of the body region and a portion of the drift region; and a source region located on the side of the gate structure away from the drain region, located in the substrate below the bottom surface of the groove and located above the body region.
[0007] Optionally, the bottom surface of the drain region is not lower than the top surface of the drift region, and the side surface of the drain region is not in contact with the drift region.
[0008] Optionally, the side surface of the drain region near the gate structure overlaps with a portion of the sidewall of the groove.
[0009] Optionally, the LDMOS device further includes a body region lead-out region, which is located above the body region and on the side of the source region away from the gate structure.
[0010] Optionally, the substrate, the body region, and the body region lead-out region are all of the first conductivity type, and the drift region, the source region, and the drain region are all of the second conductivity type. The first conductivity type and the second conductivity type are opposite. The doping concentration of the body region lead-out region is greater than the doping concentration of the body region, and the doping concentration of the drain region and the source region are both greater than the doping concentration of the drift region.
[0011] Optionally, the LDMOS device further includes a metal silicide barrier layer; the metal silicide barrier layer at least covers the drift region between the gate structure and the drain region.
[0012] Optionally, the LDMOS device further includes a contact hole field plate located on the metal silicide barrier layer.
[0013] Optionally, the metal silicide barrier layer covers the drift region between the gate structure and the drain region and extends to cover a portion of the surface of the gate electrode of the gate structure, and the contact hole field plate is partially located on the gate electrode and partially located on the drift region.
[0014] Optionally, the metal silicide barrier layer is a multilayer structure of stacked different material layers, and the contact hole field plate penetrates a portion of the material layer of the metal silicide barrier layer and is suspended inside the metal silicide barrier layer.
[0015] Optionally, the LDMOS device further includes a metal silicide formed on the top surface of the drain region, the gate electrode of the gate structure, the source region, and the body region lead-out region.
[0016] Optionally, the LDMOS device further includes multiple contact plugs; corresponding contact plugs are provided on the metal silicide of the drain region, the gate electrode of the gate structure, the source region, and the body region lead-out region.
[0017] Optionally, the gate structure includes a gate oxide layer, a gate electrode, and a sidewall, wherein the gate oxide layer is located on the substrate, the gate electrode is located on the gate oxide layer, and the sidewall at least covers the sidewall of the gate electrode; the source region is located below the sidewall and is self-aligned with the gate electrode.
[0018] In the LDMOS device provided by this utility model, a groove and a protrusion defined by the groove are provided on one side of the top surface of the substrate. The drain region is located in the protrusion, and the drift region is located in the substrate below the bottom surface of the groove and partially below the drain region. The side surface of the drain region is located above the drift region, and the top surface of the drift region is in contact with the bottom surface of the drain region. The body region is located in the substrate below the bottom surface of the groove and is located on the side of the drift region away from the drain region 202. The gate structure is located in the groove and covers part of the body region and part of the drift region. The source region is located on the side of the gate structure away from the drain region, in the substrate below the bottom surface of the groove, and above the body region. This application elevates the drain region by setting a groove on one side of the top surface of the substrate, so that the side surface of the drain region is above the top surface of the drift region. This can eliminate the drain curvature effect brought by the drain region to the drift region, so that the charge balance in the drift region is achieved, thereby achieving a better reduction of the surface electric field effect. This results in a higher breakdown voltage and a lower on-resistance, improving product competitiveness.
[0019] Furthermore, the LDMOS device of this application also includes a metal silicide barrier layer and a contact hole field plate. The metal silicide barrier layer at least covers the drift region between the gate structure and the drain region, and the contact hole field plate is located on the metal silicide barrier layer. Replacing the surface electric field reduction oxide layer, which is usually located under the gate electrode, with a contact hole field plate can achieve a better surface electric field reduction optimization effect, which is beneficial to further optimize device characteristics. Moreover, since the contact hole field plate can be fabricated simultaneously with the contact plug, the independent mask required for fabricating the surface electric field reduction oxide layer can be saved, which helps to save costs. Attached Figure Description
[0020] Figures 1 to 5 This is a schematic diagram of the fabrication process of an existing LDMOS device.
[0021] Figure 6 This is a schematic diagram of the structure of an LDMOS device provided in an embodiment of the present invention.
[0022] Figures 7 to 13 This is a schematic diagram of the manufacturing process of an LDMOS device provided in an embodiment of the present invention.
[0023] Explanation of reference numerals in the attached figures: 100 - substrate; 101 - first mask layer; 102 - body region; 103 - second mask layer; 104 - drift region; 105 - third mask layer; 106 - oxide layer for reducing surface electric field; 107 - gate oxide layer; 108 - gate electrode; 109 - source region; 110 - body region lead-out region; 111 - drain region;
[0024] 200 - Substrate; 201 - Drift region; 202a - Original drain region; 203 - First mask layer; 204 - Groove; 205 - Gate oxide layer; 206 - Gate electrode; 206a - Gate material layer; 207 - Second mask layer; 208 - Sidewall; 209 - Body region; 210a - Original source region; 210 - Source region; 211 - Fourth mask layer; 212 - Body region lead-out region; 213 - Metal silicide barrier layer; 213a - Silicon oxide layer; 213b - Silicon nitride layer; 214 - Metal silicide; 215 - Contact plug; 216 - Contact hole field plate. Detailed Implementation
[0025] The LDMOS device proposed in this utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.
[0026] Figure 6 This is a schematic diagram of the structure of an LDMOS device provided in an embodiment of the present invention. Figure 6 As shown, the LDMOS device provided in this embodiment includes a substrate 200, a drain region 202, a drift region 201, a body region 209, a gate structure, and a source region 210.
[0027] The substrate 200 has a groove 204 and a protrusion defined by the groove 204 on one side of its top surface; a drain region 202 is located in the protrusion; a drift region 201 is located in the substrate below the bottom surface of the groove 204 and is partially located below the drain region 202, with the side surface of the drain region 202 located above the top surface of the drift region 201 and the top surface of the drift region 201 in contact with the bottom surface of the drain region 202; a body region 209 is located in the substrate below the bottom surface of the groove 204 and is located on the side of the drift region 201 away from the drain region 202; a gate structure is located in the groove and covers part of the body region 209 and part of the drift region 201; a source region 210 is located on the side of the gate structure away from the drain region 202, in the substrate below the bottom surface of the groove 204 and above the body region 209.
[0028] In this embodiment, the substrate 200 can be a silicon substrate. In other embodiments, the substrate 200 can also be a germanium substrate, a silicon-germanium substrate, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. Furthermore, certain dopant particles can be implanted into the substrate 200 to change the electrical parameters according to design requirements.
[0029] refer to Figure 6As shown, the top surface of the base 200 has a groove 204 and a protrusion defined by the groove 204 on one side.
[0030] The drain region 202 is located within the protrusion, and the bottom of the drain region 202 is not lower than the bottom surface of the groove 204. In this embodiment, the depth of the groove 204 can be equal to the height of the drain region 202 (i.e., the injection depth of the drain region 202), and the drain region 202 extends from the top surface of the substrate 200 toward the bottom surface of the substrate 200 to the height of the bottom surface of the groove 204, but is not limited thereto. For example, the depth of the groove 204 and the height of the drain region 202 can both be greater than or equal to 0.05 μm and less than or equal to 0.5 μm, but are not limited thereto.
[0031] In other embodiments, the depth of the groove 204 can be greater than the injection depth of the drain region 202, or the depth of the groove 204 can be greater than the height of the drain region 202, so that the top of the protrusion is the drain region 202 and the bottom of the protrusion can be the drift region 201.
[0032] For example, the drain region 202 overlaps with a portion of the sidewall of the gate structure near the side surface of the gate structure and the groove 204.
[0033] The drift region 201 is located in the base below the bottom surface of the groove 204 and is partially located below the drain region 202. The side surface of the drain region 202 is located above the top surface of the drift region 201 and the top surface of the drift region 201 is in contact with the bottom surface of the drain region 202.
[0034] It should be emphasized that in this embodiment, the drain region 202 is located entirely above the drift region 201 and protrudes entirely from the top surface of the drift region 201. The bottom surface of the drain region 202 is not lower than the top surface of the drift region 201, and the side surface of the drain region 202 is not in contact with the drift region 201. This helps to eliminate the drain curvature effect brought by the drain region 202 to the drift region 201, so as to balance the charge in the drift region 201, thereby achieving a better reduction of the surface electric field, and thus obtaining a higher breakdown voltage and a lower on-resistance, improving product competitiveness.
[0035] Body region 209 is located in the substrate below the bottom surface of the groove 204 and on the side of the drift region 201 away from the drain region 202. For example... Figure 6 As shown, in this embodiment, the body region 209 and the drift region 201 are laterally connected, but this is not the only embodiment. In other embodiments, the body region 209 and the drift region 201 may have a spacing greater than zero.
[0036] The gate structure is located in the recess 204 and between the body region 209 and the drift region 201. One end of the gate structure extends to cover part of the body region 209 and the other end extends to cover part of the drift region 201.
[0037] For example, the gate structure includes a gate oxide layer 205, a gate electrode 206, and a sidewall 208. The gate oxide layer 205 is located on the substrate 200, the gate electrode 206 is located on the gate oxide layer 205, and the sidewall 208 at least covers the sidewall of the gate electrode 206. The material of the gate oxide layer 205 includes, but is not limited to, silicon oxide. The gate oxide layer 205 may also extend to cover the substrate surface on the side of the gate electrode 206, but is not limited thereto. The material of the gate electrode 206 includes, but is not limited to, polysilicon. The sidewall 208 may be formed on the gate oxide layer 205, but is not limited thereto. The material of the sidewall 208 includes silicon oxide and / or silicon nitride. The sidewall 208 may be a single-layer structure composed of a single material layer, or a multilayer structure composed of different material layers. For example, the sidewall 208 may be an ONO structure, including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer sequentially covering the sidewall of the gate electrode 206 from the inside out.
[0038] like Figure 6 As shown, in this embodiment, no surface electric field reduction oxide layer (ROX) is provided below the gate electrode 206, which requires partial coverage of the gate electrode 206. Therefore, the gate electrode 206 is planar rather than stepped.
[0039] refer to Figure 6 As shown, the source region 210 is located on the side of the gate structure away from the drain region 202, in the substrate below the bottom surface of the groove 204, and above the body region 209.
[0040] Specifically, the bottom surface and at least part of the side surface of the source region 210 are in contact with the body region 209. The source region 210 is partially located below the sidewall 208 of the gate structure and is self-aligned with the gate electrode 206 of the gate structure, that is, part of the boundary of the source region 210 is aligned with the sidewall of the gate electrode 206 away from the drain region 202.
[0041] refer to Figure 6 As shown, the LDMOS device further includes a body region lead-out region 212, which is located above the body region 209 and on the side of the source region 210 away from the gate structure. In this embodiment, the body region lead-out region 212 and the source region 210 can be laterally connected.
[0042] It should be noted that the substrate 200, the body region 209 and the body region lead-out region 212 are all of the first conductivity type, and the drift region 201, the source region 210 and the drain region 202 are all of the second conductivity type. The first conductivity type and the second conductivity type are opposite.
[0043] This embodiment uses an N-type LDMOS device as an example, where the first conductivity type is P-type and the second conductivity type is N-type. In other embodiments, the LDMOS device can also be a P-type LDMOS device, where the first conductivity type can be N-type and the second conductivity type can be P-type.
[0044] In this embodiment, the body region lead-out region 212 can be a P+ doped region, and the doping concentration of the body region lead-out region 212 is greater than the doping concentration of the body region 209, so as to reduce the resistance of the lead-out body region. The drain region 202 and the source region 210 can both be N+ doped regions, and the doping concentration of the drain region 202 and the source region 210 is greater than the doping concentration of the drift region 201.
[0045] Continue to refer to Figure 6 As shown, the LDMOS device may further include a metal silicide barrier layer 213 (SAB), which at least covers the drift region 201 between the gate structure and the drain region 202.
[0046] The metal silicide barrier layer 213 can be a multilayer structure composed of stacked layers of different materials. For example, the metal silicide barrier layer 213 may include a silicon oxide layer 213a (SiO2) and a silicon nitride layer 213b (Si3N4) located on the silicon oxide layer 213a, but is not limited thereto. The metal silicide barrier layer 213 can also be an ONO layer, or include oxide layers, nitride layers, oxide layers, and nitride layers stacked sequentially from bottom to top.
[0047] The gate oxide layer 205 may extend to cover the drift region 201 between the gate electrode 206 and the drain region 202. The metal silicide barrier layer 213 may be formed on the gate oxide layer 205, but is not limited thereto.
[0048] refer to Figure 6 As shown, the LDMOS device may further include a metal silicide 214, which can be formed on the silicon surface not covered by the metal silicide barrier layer 213. Exemplarily, in this embodiment, the metal silicide barrier layer 213 exposes the top surfaces of the drain region 202, gate electrode 206, source region 210, and body lead-out region 212, while the metal silicide 214 is formed on the top surfaces of these regions.
[0049] The LDMOS device may further include multiple contact plugs 215. Corresponding contact plugs 215 are provided on the metal silicide 214 of the drain region 202, the gate electrode 206 of the gate structure, the source region 210, and the body region 212 to lead out the drain region 202, the gate electrode 206, the source region 210, and the body region 212. For example, the metal silicide 214 on the source region 210 and the body region 212 can be interconnected, so that the source region 210 and the body region 212 can be led out together through the same contact plug 215, thus providing ample space for the arrangement of the contact plugs 215 on the source region 210 and the body region 212.
[0050] The LDMOS device may also include a contact hole field plate 216 formed on the metal silicide barrier layer 213.
[0051] In this embodiment, the metal silicide barrier layer 213 is located between the gate structure and the drain region 202, and the contact hole field plate 216 is also located between the gate structure and the drain region 202 and is suspended on the metal silicide barrier layer 213. More specifically, one end of the contact hole field plate 216 may penetrate a portion of the material layer of the metal silicide barrier layer 213 and be suspended inside the metal silicide barrier layer, for example, it may penetrate the silicon nitride layer 213b of the metal silicide barrier layer 213 and be suspended on the silicon oxide layer 213a, but is not limited thereto.
[0052] In other embodiments, the metal silicide barrier layer 213 may also extend laterally to cover part of the top surface of the gate electrode 206 and expose part of the top surface of the gate electrode 206, the top surface of the drain region 202, the top surface of the source region 210 and the top surface of the body region lead-out region 212. The contact hole field plate 216 may be partially located on the gate electrode 206 and partially located on the drift region 201 on the side of the gate electrode 206.
[0053] For example, the breakdown voltage of the LDMOS device provided in this embodiment can be greater than or equal to 6V and less than or equal to 1000V, but is not limited thereto.
[0054] The LDMOS device provided in this embodiment can be a discrete device or integrated into the BCD platform.
[0055] Figures 7 to 13 This is a schematic diagram illustrating the fabrication process of the LDMOS device provided by this utility model. The following is in conjunction with... Figures 7 to 13 The fabrication process of the LDMOS device provided in this application is described below. For example, the fabrication process of the LDMOS device provided in this application includes the following steps.
[0056] like Figure 7As shown, a substrate 200 is provided, and a drift region 201 and a primary drain region 202a located on the top of the substrate 200 are formed thereon. The top surface of the drift region 201 and the bottom surface of the primary drain region 202a are in contact.
[0057] For example, both the drift region 201 and the original drain region 202a can cover the entire top of the substrate 200. The drift region 201 and the original drain region 202a can be formed by an ion implantation process. When forming the drift region 201 and the original drain region 202a, they can be implanted as a whole on the top surface of the substrate 200 without the need to set a mask layer.
[0058] like Figure 8 As shown, a first mask layer 203 is formed on the substrate 200, the first mask layer 203 defining the formation area of the groove and the formation area of the drain region; using the first mask layer 203 as a mask, a portion of the original drain region 202a is etched away until the drift region 201 is exposed, so as to form a groove 204 and the drain region 202 defined by the groove 204 on one side of the top surface of the substrate 200; the first mask layer 203 is then removed.
[0059] For example, the thickness of the original drain region 202a can be greater than or equal to 0.05 μm and less than or equal to 0.5 μm, and the etching depth of the substrate 200 etched with the first mask layer 203 as a mask can be greater than or equal to the thickness of the original drain region 202a.
[0060] It should be noted that this application forms the drift region 201 and the original drain region 202a integrally on the top surface of the substrate 200, and then forms the drain region 202 by etching the original drain region 202a. This can ensure the alignment accuracy of the drain region 202 or the positional accuracy of the drain region 202. In addition, this can ensure that the formed drain region 202 is located above the drift region 201, avoiding the side surface of the drain region 202 from contacting the drift region 201. This helps to eliminate the drain curvature effect brought by the drain region 202 to the drift region 201, so as to balance the charge in the drift region 201 and thus achieve a better effect of reducing the surface electric field.
[0061] like Figure 9 As shown, a gate oxide layer 205 covering the substrate 200 is formed on the substrate 200, a gate material layer 206a covering the gate oxide layer 205 is formed on the gate oxide layer 205, and a second mask layer 207 is formed on the gate material layer 206a. The second mask layer 207 defines the formation region of the body region. Using the second mask layer 207 as a mask, the gate material layer 206a and the gate oxide layer 205 are etched downwards. During the etching process, a portion of the thickness of the gate oxide layer 205 can be retained to avoid the etching directly contacting the substrate surface and causing surface defects, and also to avoid subsequent ion implantation damaging the substrate surface.
[0062] like Figure 10 As shown, under the masking of the second mask layer 207 and the remaining gate material layer 206a, the substrate 200 is formed into a self-aligned ion implantation body region 209.
[0063] In this embodiment, the injection depth of the body region 209 is the same as the injection depth of the drift region 201, that is, the bottom surface of the body region 209 and the bottom surface of the drift region 201 can be flush, but this is not a limitation. In other embodiments, the injection depth of the body region 209 can be adjusted as needed.
[0064] like Figure 10 As shown, under the masking of the second mask layer 207 and the remaining gate material layer 206a, self-aligned implantation is performed to form the original source region 210a above the body region 209; then the second mask layer 207 is removed.
[0065] It should be noted that this application requires the body region 209 to be partially located below the gate electrode to form a channel region. For example, during ion implantation to form the body region 209, the dopant can be obliquely implanted into the substrate, such that the formed body region 209 is partially located below the gate electrode; alternatively, the body region 209 can be formed by implanting boron (B) and the original source region 210a can be formed by implanting phosphorus (P). Since the diffusion rate of B is greater than that of P in the same heat treatment process, after forming the original source region 210a, heat treatment can be performed to allow the body region 209 to laterally extend below the gate material layer 206a, while the original source region 210a does not extend below the gate material layer 206a, thereby allowing the body region 209 to laterally extend below the subsequently formed gate electrode 206 to form a channel region.
[0066] like Figure 11 As shown, a third mask layer (not shown) is formed on the gate material layer 206a, and the third mask layer defines the formation region of the gate electrode; using the third mask layer as a mask, the gate material layer 206a is etched to form the gate electrode 206; the third mask layer is removed; and a sidewall 208 is formed on the sidewall of the gate electrode 206.
[0067] like Figure 12As shown, a fourth mask layer 211 is formed on the substrate 200. The fourth mask layer 211 defines the formation area of the body region lead-out region. Specifically, the fourth mask layer 211 covers the drain region 202, the gate structure and the drift region 201 between the drain region 202, the gate structure, and a portion of the original source region 210a on the side of the gate structure. Using the fourth mask layer 211 as a mask, ion implantation is performed to form a body region lead-out region 212 above the body region 209. In this embodiment, the body region lead-out region 212 replaces a portion of the original source region 210a, and the original source region 210a covered by the fourth mask layer 211 serves as the final source region 210. After forming the body region lead-out region 212, the fourth mask layer 211 is removed. If there is still a gate oxide layer remaining on the source region 210 and the body region lead-out region 212, the gate oxide layer on the source region 210 and the body region lead-out region 212 can be removed.
[0068] like Figure 13 As shown, a metal silicide barrier layer 213 is formed on the substrate 200. The metal silicide barrier layer 213 at least covers the drift region 201 between the gate structure and the drain region 202 and exposes at least a portion of the top surface of the drain region 202, the gate electrode 206, the source region 210 and the body region lead-out region 212. Under the protection of the metal silicide barrier layer 213, a metal silicide 214 is formed on the substrate 200. The metal silicide 214 is formed on the top surface of the drain region 202, the gate electrode 206, the source region 210 and the body region lead-out region 212.
[0069] like Figure 6 As shown, a contact hole field plate 216 and multiple contact plugs 215 are formed on the substrate 200. The contact hole field plate 216 is formed on a metal silicide barrier layer 213. Corresponding contact plugs 215 are disposed on the metal silicides 214 of the drain region 202, the gate electrode 206, the source region 210, and the body lead-out region 212. In the LDMOS device, the metal silicide barrier layer 213 is used both to define the formation location of the metal silicides 214 and to serve as a dielectric layer between the contact hole field plate 216 and the substrate 200 and the gate electrode 206.
[0070] In the LDMOS device provided by this utility model, a groove 204 and a protrusion defined by the groove 204 are provided on one side of the top surface of the substrate 200. The drain region is located in the protrusion. The drift region 201 is located in the substrate below the bottom surface of the groove and is partially located below the drain region 202. The side surface of the drain region 202 is located above the drift region 201 and the top surface of the drift region 201 is in contact with the bottom surface of the drain region 202. The body region 209 is located in the substrate below the bottom surface of the groove 204 and is located on the side of the drift region 201 away from the drain region 202. The gate structure is located in the groove 204 and covers part of the body region 209. The source region 210, along with part of the drift region 201, is located on the side of the gate structure away from the drain region 202, in the substrate below the bottom surface of the groove 204, and above the body region 209. By setting the groove 204 on one side of the top surface of the substrate 200 to raise the drain region 202, the side surface of the drain region 202 is located above the top surface of the drift region 201. This can eliminate the drain curvature effect brought by the drain region 202 to the drift region 201, so that the charge balance in the drift region 201 is achieved, thereby achieving a better reduction of the surface electric field, and thus obtaining a higher breakdown voltage and a lower on-resistance, improving product competitiveness.
[0071] Furthermore, the LDMOS device of this application also includes a metal silicide barrier layer 213 and a contact hole field plate 216. The metal silicide barrier layer 213 at least covers the drift region 201 between the gate structure and the drain region 202, and the contact hole field plate 216 is located on the metal silicide barrier layer 213. Replacing the surface electric field reduction oxide layer usually disposed under the gate electrode with the contact hole field plate 216 can achieve a better surface electric field reduction optimization effect, which is beneficial to further optimize device characteristics. Moreover, since the contact hole field plate 216 can be fabricated simultaneously with the contact plug 215, the independent mask required for fabricating the surface electric field reduction oxide layer can be saved, which is beneficial to cost reduction.
[0072] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. Any person skilled in the art can make possible changes and modifications to the technical solution of the present utility model by using the methods and techniques disclosed above without departing from the spirit and scope of the present utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present utility model without departing from the content of the technical solution of the present utility model shall fall within the protection scope of the technical solution of the present utility model.
Claims
1. An LDMOS device, characterized in that, include: A base having a groove on one side of its top surface and a protrusion defined by the groove; The drain region is located within the protrusion; A drift region is located in the base below the bottom surface of the groove and partially below the drain region. The side surface of the drain region is located above the top surface of the drift region and the top surface of the drift region is in contact with the bottom surface of the drain region. The body region is located in the substrate below the bottom surface of the groove and on the side of the drift region away from the drain region; A gate structure located in the recess and covering a portion of the body region and a portion of the drift region; as well as The source region is located on the side of the gate structure away from the drain region, in the substrate below the bottom surface of the recess, and above the body region.
2. The LDMOS device as described in claim 1, characterized in that, The bottom surface of the drain region is not lower than the top surface of the drift region, and the side surface of the drain region is not in contact with the drift region.
3. The LDMOS device as described in claim 1, characterized in that, The side surface of the drain region near the gate structure overlaps with a portion of the sidewall of the groove.
4. The LDMOS device according to any one of claims 1 to 3, characterized in that, The LDMOS device further includes a body region lead-out region, which is located above the body region and on the side of the source region away from the gate structure.
5. The LDMOS device as described in claim 4, characterized in that, The substrate, the body region, and the body region lead-out region are all of the first conductivity type, and the drift region, the source region, and the drain region are all of the second conductivity type. The first conductivity type and the second conductivity type are opposite. The doping concentration of the body region lead-out region is greater than the doping concentration of the body region, and the doping concentration of the drain region and the source region are both greater than the doping concentration of the drift region.
6. The LDMOS device as described in claim 1, characterized in that, The LDMOS device further includes a metal silicide barrier layer; the metal silicide barrier layer at least covers the drift region between the gate structure and the drain region.
7. The LDMOS device as described in claim 6, characterized in that, The LDMOS device also includes a contact hole field plate located on the metal silicide barrier layer.
8. The LDMOS device as described in claim 7, characterized in that, The metal silicide barrier layer covers the drift region between the gate structure and the drain region and extends to cover a portion of the surface of the gate electrode of the gate structure. The contact hole field plate is partially located on the gate electrode and partially located on the drift region.
9. The LDMOS device as described in claim 7, characterized in that, The metal silicide barrier layer is a multilayer structure with different material layers stacked together. The contact hole field plate penetrates a portion of the material layer of the metal silicide barrier layer and is suspended inside the metal silicide barrier layer.
10. The LDMOS device as described in claim 4, characterized in that, The LDMOS device further includes a metal silicide formed on the top surface of the drain region, the gate electrode of the gate structure, the source region, and the body region lead-out region.
11. The LDMOS device as claimed in claim 10, characterized in that, The LDMOS device further includes multiple contact plugs; corresponding contact plugs are provided on the metal silicide of the drain region, the gate electrode of the gate structure, the source region and the body region lead-out region.
12. The LDMOS device according to any one of claims 1 to 3, characterized in that, The gate structure includes a gate oxide layer, a gate electrode, and a sidewall. The gate oxide layer is located on the substrate, the gate electrode is located on the gate oxide layer, and the sidewall at least covers the sidewall of the gate electrode. The source region is located below the sidewall and is self-aligned with the gate electrode.