Method of manufacturing a semiconductor device

Abstract

This invention provides a method for manufacturing a semiconductor device. Before the active region manufacturing process, trench etching is performed on the substrate region to be fabricated as a high-voltage transistor to form at least a first depth adjustment trench located outside the gate oxide region of the high-voltage transistor. A first drift region is then formed by ion implantation. This solves the problem of incomplete corner implantation caused by the rounded exposure of photoresist corners in existing LDD processes. Furthermore, the depth of the first depth adjustment trench increases the bottom depth of the shallow trench isolation structure used to isolate the source / drain regions and channel regions of the high-voltage transistor, increasing the charge path of the high-voltage transistor and its breakdown voltage. Further, by simultaneously forming a gate oxide trench for fabricating a thick gate oxide layer with the first depth adjustment trench, the step height between the high-voltage transistor and other components is reduced, thereby reducing the load effect and defects in subsequent processes and improving the performance of the high-voltage transistor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] High-voltage transistors (HVMOS) are devices capable of withstanding higher voltages while ensuring that the gate is not broken down under high-voltage operation. On one hand, the source / drain regions of an HVMOS are isolated from the device channel by a shallow trench isolation (STI) structure to improve the breakdown voltage. This STI structure is typically formed during the active region formation process (AA loop), along with the STI structures of other components (such as low-voltage LVMOS, medium-voltage MVMOS, or core components). The trench depth of the STI structure is limited by the process technology and its stability, making it difficult to deepen further using the AA loop. On the other hand, the gate oxide process in HVMOS involves directly growing the gate oxide layer (HV GOX) on the silicon wafer surface. However, after the HV GOX is grown, a step height (SH) inevitably exists between the HVMOS and other components because the HV GOX... The gate oxide layer (GOX) is much thicker than that formed on other device regions such as LVMOS and MVMOS (e.g., two orders of magnitude thicker). This step height will increase the process loading in subsequent processes, which may affect the performance of HVMOS. For example, this step height may cause insufficient overlap between the drift region and the gate in HVMOS, thus affecting the performance of HV devices.

[0003] Therefore, how to provide a method for manufacturing semiconductor devices that improves the performance of high-voltage transistors without degrading the performance of other components is one of the important technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a semiconductor device that can improve the performance of a high-voltage transistor without degrading the performance of other components.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0006] A substrate is provided, and a trench etching is performed on the substrate region to be fabricated as a high-voltage transistor to form at least a first depth adjustment trench located outside the gate oxide region of the high-voltage transistor.

[0007] At least the substrate of the gate oxide region sidewall is ion implanted to form a first drift region;

[0008] An active region manufacturing process is performed on the substrate having the first drift region to form corresponding shallow trenches in the substrate, wherein a portion of the shallow trenches overlaps with and communicates with the first depth adjustment trench, and the active region manufacturing process deepens the bottom depth of the portion of the shallow trenches through the first depth adjustment trench.

[0009] Dielectric material is filled into each of the shallow trenches and the first depth adjustment groove to form a shallow trench isolation structure;

[0010] Ion implantation is performed on the active region of the high-voltage transistor to form a second drift region;

[0011] A thick gate oxide layer is formed on the gate oxide region.

[0012] Optionally, a hard mask layer is formed over the substrate having the first depth adjustment groove before or after the formation of the first drift region by ion implantation and before the active region manufacturing process is performed.

[0013] Optionally, the first depth adjustment trench exposes the substrate surface of the sidewall of the gate oxide region; or, trench etching is performed on the substrate area to be fabricated as a high-voltage transistor to form a gate oxide trench while forming the first depth adjustment trench, wherein the active region at the bottom of the gate oxide trench is the gate oxide region, and the portion of the shallow trench is also connected to the gate oxide trench; wherein the gate oxide trench is spaced apart from or connected to the first depth adjustment trenches on both sides, and / or, the first depth adjustment trench on one side of the gate oxide trench is one or at least two.

[0014] Optionally, trench etching is performed on the substrate area to be fabricated for the high-voltage transistor. While forming the first depth adjustment trench, at least one second depth adjustment trench is also formed at the boundary of the active region of the high-voltage transistor. After the active region fabrication process is performed, the second depth adjustment trench overlaps with and communicates with the corresponding shallow trench to deepen the bottom depth of the shallow trench and separate the active region of the high-voltage transistor from the active regions of other components. The sidewall of the second depth adjustment trench is aligned with or forms a step with the sidewall of the shallow trench it communicates with.

[0015] Optionally, at least the substrate of the gate oxide sidewall of the high-voltage transistor is ion implanted, and the first drift region formed extends from a portion of the second depth adjustment trench to the gate oxide sidewall of the high-voltage transistor.

[0016] Optionally, the step of forming the first depth adjustment groove includes:

[0017] A first pad oxide layer, a first nitride layer, and a first photoresist layer are sequentially formed on the substrate;

[0018] The first photoresist layer is photolithographically etched using a first photomask to at least define the formation area of ​​the first depth adjustment groove;

[0019] Using the first photoresist layer after photolithography as a mask, the first nitride layer, the first pad oxide layer and the substrate are etched sequentially to form at least the first depth adjustment groove in the substrate;

[0020] Remove the first photoresist layer, the first nitride layer, and the first pad oxide layer.

[0021] Optionally, the hard mask layer also covers the inner surface of the gate oxide trench, and after the dielectric material is filled to form a shallow trench isolation structure, the shallow trench isolation structure also buries the hard mask layer in the gate oxide trench.

[0022] Optionally, the method for manufacturing the semiconductor device further includes at least one of the following (1) to (5):

[0023] (1) After the second drift region is formed and before the thick gate oxide layer is formed on the gate oxide region, the shallow trench isolation structure in the gate oxide trench is etched open, and the shallow trench isolation structure on the sidewall of the gate oxide trench is further etched to form a side trench that exposes the apex of the active region in the gate oxide trench. The hard mask layer in the gate oxide trench protects the active region in the gate oxide trench during the formation of the side trench. The thick gate oxide layer is also formed in the side trench.

[0024] (2) Before filling the shallow trenches and the first depth adjustment trench with dielectric material, the sidewalls of the hard mask layer on the substrate are first pulled back and etched.

[0025] (3) After filling each of the shallow trenches and the first depth adjustment trench with dielectric material, the top surface of the dielectric material is planarized until the top surface of the hard mask layer on the substrate region surrounding the gate oxide trench is exposed or until the hard mask layer on the substrate region surrounding the gate oxide trench is removed.

[0026] (4) Before forming the thick gate oxide layer, the remaining hard mask layer in the gate oxide trench is removed to expose the top surface of the active region of the gate oxide region;

[0027] (5) The hard mask layer includes a second pad oxide layer stacked on the substrate, or includes a second pad oxide layer and a second nitride layer stacked sequentially on the substrate.

[0028] Optionally, before forming the first drift region by ion implantation, a second pad oxide layer is first formed on the substrate, and after forming the first drift region and before performing the active region manufacturing process, a second nitride layer is formed on the second pad oxide layer to form the hard mask layer.

[0029] Optionally, the method for manufacturing the semiconductor device further includes at least one of the following (1) to (5):

[0030] (1) Ion implantation is performed using a lightly doped source-drain ion implantation process to form the first drift region;

[0031] (2) The sidewall of the first depth adjustment groove is aligned with or forms a step with the sidewall of the shallow groove it communicates with;

[0032] (3) Photolithography and trench etching are performed on the substrate area to be fabricated for high voltage transistors using the zero-layer photomask, so as to form the first depth adjustment trench and the zero-layer alignment mark in the substrate at the same time.

[0033] (4) Before filling each of the shallow trenches and the first depth adjustment groove with dielectric material, a line oxide layer is formed on the inner surface of each of the shallow trenches and the first depth adjustment groove.

[0034] (5) After forming the thick gate oxide layer, a thin gate oxide layer is also formed on the active region of the other elements, and a gate is formed together on the thick gate oxide layer and the thin gate oxide layer.

[0035] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0036] 1. Before performing the active region manufacturing process, trench etching is performed on the substrate area of ​​the high-voltage transistor to be fabricated to form at least a first depth adjustment trench located outside the gate oxide region of the high-voltage transistor. This allows the depth of the first depth adjustment trench to be used to increase the bottom depth (STI trench) of the shallow trench isolation structure used to isolate the source / drain region and the channel region of the high-voltage transistor after subsequent active region manufacturing processes, thereby increasing the charge path of the high-voltage transistor and increasing its breakdown voltage.

[0037] 2. After forming the first depth adjustment trench and before performing the active region manufacturing process (AA loop), the active region on the gate oxide sidewall is first implanted with ions using the LDD process to form the first drift region. This can effectively implant ions into the corners of the regions that should be implanted in the existing LDD (lightly doped source / drain ion implantation) process. This helps to eliminate the side effect caused by the step height SH of the high voltage transistor and avoids the problem of incomplete implantation caused by the rounded exposure of photoresist corners in the existing LDD (lightly doped source / drain ion implantation) process.

[0038] 3. At the same time as forming the first depth adjustment trench, a gate oxide trench is also formed to reduce the top height of the gate oxide region of the high voltage transistor. This gate oxide trench is used to reduce the step height between the high voltage transistor and other components, thereby reducing the load effect and defects of subsequent processes and improving the performance of the high voltage transistor.

[0039] 4. Under the same voltage withstand capability, the high voltage transistor of the present invention can have a shorter active region length compared with the existing high voltage transistor, which is beneficial to reduce the area of ​​the high voltage transistor, thereby reducing the chip area and improving the integration density. Attached Figure Description

[0040] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0041] Figure 1 This is a schematic diagram of a semiconductor device manufacturing method according to a specific embodiment of the present invention.

[0042] Figures 2A to 2C This is a schematic cross-sectional view of an example device structure in a specific embodiment of the semiconductor device manufacturing method of the present invention.

[0043] Figures 3 to 8 This is a cross-sectional schematic diagram of other example device structures in the manufacturing method of a semiconductor device according to a specific embodiment of the present invention.

[0044] Figure 9 This is a schematic diagram of the photoresist edge rounding exposure in the existing LDD (lightly doped source / drain ion implantation) process. Detailed Implementation

[0045] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0046] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0047] Please refer to Figure 1 An embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps:

[0048] S1, providing a substrate, and performing trench etching on the substrate region to be fabricated as a high-voltage transistor to form at least a first depth adjustment trench located outside the gate oxide region of the high-voltage transistor;

[0049] S2, at least the substrate of the gate oxide region sidewall is ion implanted to form a first drift region;

[0050] S3, perform an active region manufacturing process on the substrate having the first drift region to form corresponding shallow trenches in the substrate, wherein a portion of the shallow trenches overlaps with and is connected to the first depth adjustment trench, and the active region manufacturing process deepens the bottom depth of the portion of shallow trenches through the first depth adjustment trench.

[0051] S4, fill each of the shallow trenches and the first depth adjustment groove with dielectric material to form a shallow trench isolation structure;

[0052] S5, Ion implantation is performed on the active region of the high-voltage transistor to form a second drift region;

[0053] S6, a thick gate oxide layer is formed on the gate oxide region.

[0054] Please refer to Figure 2A In step S1, firstly, the provided substrate 100 can be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC), or silicon-on-insulator (SOI). The substrate 100 can be a bare silicon wafer or a wafer that has undergone appropriate processing. Next, any suitable process can be used to form the required first depth adjustment trench in region HV of the substrate 100 where the high-voltage transistor is to be fabricated.

[0055] As an example, please continue to refer to Figure 2A The steps for forming the first depth adjustment groove include:

[0056] S1.1, a first pad oxide layer 101, a first nitride layer 102 and a first photoresist layer 200 are sequentially formed on the substrate 100. The first pad oxide layer 101 can be formed by any suitable process such as thermal oxidation, the first nitride layer 102 can be formed by any suitable process such as chemical vapor deposition, and the first photoresist layer 200 can be formed by spin coating.

[0057] S1.2, a first photomask (not shown) is used to perform photolithography on the first photoresist layer 200 to define the formation area of ​​the trench 103 in the substrate region HV where the high voltage transistor is to be fabricated, that is, to define the formation area of ​​the gate oxide trench and the first depth adjustment trench on both sides thereof.

[0058] S1.3 Using the first photoresist layer 200 after photolithography as a mask, any suitable etching process, such as dry etching, can be used to sequentially etch the first nitride layer 102, the first pad oxide layer 101, and the substrate 100 to form a trench 103 in the substrate 100. The trench 103 is located between the source and drain regions of the high-voltage transistor, covering the area of ​​the gate oxide trench and the first depth adjustment trenches on both sides. In this example, the gate oxide trench and the first depth adjustment trenches on both sides are connected as one unit to form the trench 103. The bottom surface of the trench 103 is flat.

[0059] S1.4, the first photoresist layer 200 is removed by any suitable photoresist removal process such as dry photoresist removal or wet photoresist removal, and the first nitride layer 102 and the first pad oxide layer 101 are removed by any suitable process such as wet etching.

[0060] It should be understood that the depth h of trench 103 (i.e., the gate oxide trench and the first depth adjustment trenches on both sides thereon) needs to meet not only the thickness requirements of the gate oxide layer of the high-voltage transistor, but also the depth requirements of the shallow trench isolation (STI) structure surrounding the gate oxide trench of the high-voltage transistor. As an example, the depth h of trench 103 is approximately... (can be) etc).

[0061] In one example, please refer to Figure 2A In step S1.2, a first photomask (not shown) is used to perform photolithography on the first photoresist layer 200, defining not only the formation area of ​​the trench 103 but also the formation area of ​​the second depth adjustment trench 104 in the substrate region HV where the high-voltage transistor is to be fabricated. In step S1.3, using the photolithographically rendered first photoresist layer 200 as a mask, the substrate 100 is etched, forming the trench 103 (i.e., the gate oxide trench and the first depth adjustment trench) and the second depth adjustment trench 104 simultaneously in the substrate 100. The trench 103 has a relatively large linewidth, covering not only the active region HVG of the gate oxide region of the high-voltage transistor, but also the region of the shallow trench 107 that defines the area surrounding the gate oxide trench (which separates the active region HVG and the source / drain regions HVS / D of the high-voltage transistor). The second depth adjustment trench 104 is located at the boundary of the active region of the high-voltage transistor to be fabricated, and is used to achieve device isolation between the high-voltage transistor and other surrounding components together with the shallow trench subsequently connected to it. The substrate region between the second depth adjustment trench 104 and the trench 103 is used to fabricate the source / drain regions HVS / D of the high-voltage transistor. The second depth adjustment trench 104 deepens the bottom depth of the subsequently formed shallow trench isolation structure STI2, enhances the isolation performance of the shallow trench isolation structure STI2, and further improves the performance of the high-voltage transistor.

[0062] In one example, please refer to Figure 3In step S1.2, when the substrate 100 provided in step S1.1 is a bare silicon wafer, trenches (i.e., gate oxide trenches and first depth adjustment trenches on both sides thereof) 103 and second depth adjustment trenches 104 can be formed in the substrate 100 through a zero-loop fabrication process. In this example, the first pad oxide layer 101, the first nitride layer 102, and the photoresist layer 200 formed sequentially on the substrate 100 are the starting layers (also called the zero layer) formed on the surface of the substrate 100, and have not yet undergone an etching step, so the surface of the substrate 100 has no uneven terrain. Therefore, the first photomask used in step S1.2 is the zero-layer photomask, which is the photomask required in the first photolithography process of substrate processing. This zero-layer photomask is usually used to define the formation area of ​​the zero-layer alignment mark (ZM0), which is used for alignment in subsequent photolithography processes. Clearly, the zero-layer photomask in this example (i.e., the first photomask), compared to the zero-layer photomask of the prior art, not only defines the formation area of ​​the zero-layer alignment mark ZM0, but also simultaneously defines the formation area of ​​the trench 103, or simultaneously defines the formation areas of the trench 103 and the second depth adjustment groove 104. Therefore, in step S1.3, the trench 103 and the zero-layer alignment mark ZM0 are formed simultaneously, with the depth of the trench 103 being the same as the depth of the zero-layer alignment mark ZM0. The zero-layer alignment mark ZM0 can then be filled with dielectric material in the subsequent step S5.

[0063] Figures 2A to 2C and Figure 3 In the example shown, the trench 103 formed in step S1 is a single trench with a relatively large opening size. The top of the substrate in the trench 103 is flat. The trench 103 covers the gate oxide trench of the high voltage transistor and the formation area of ​​the shallow trench isolation structure around the gate oxide trench (i.e., the area between the gate oxide trench and the source / drain region). The number of first depth adjustment trenches on one side of the gate oxide trench is equivalent to one, but the technical solution of the present invention is not limited to this.

[0064] In another example of this embodiment, please refer to Figure 4In step S1, photolithography and etching are performed using the same photomask to simultaneously form the gate oxide trench 103a and the first depth adjustment trench 103b. The gate oxide trench 103a is not connected to the first depth adjustment trenches 103b on both sides. The number of first depth adjustment trenches 103b on one side of the gate oxide trench 103a can be one, two, or more. After the subsequent step S3, the shallow trenches 107 formed on both sides of the gate oxide trench 103a are connected to the gate oxide trench 103a and one, two, or more first depth adjustment trenches 103b on the same side. Each first depth adjustment trench 103b forms a deepening trench 107a corresponding to the first depth adjustment trench 103b at the bottom of the shallow trench 107a.

[0065] Please refer to Figure 5 In another example of this embodiment, in step S1.2, when photolithography is performed on the first photoresist layer 200 using a first photomask (not shown), the formation region of the second depth adjustment trench is not defined at the boundary region of the substrate region HV to be fabricated for the high-voltage transistor. In step S1.3, after etching the substrate 100 using the photolithographically rendered first photoresist layer 200 as a mask, the second depth adjustment trench is not formed simultaneously while the trench 103 (i.e., the gate oxide trench and the first depth adjustment trench) is formed in the substrate 100. Therefore, after the subsequent step S3, the bottom depth of the shallow trench 108 formed at the boundary of the substrate region HV to be fabricated for the high-voltage transistor is the same as the bottom depth of the shallow trench 109 formed in the substrate region Other used to fabricate other components.

[0066] In yet another example of this embodiment, please refer to Figure 6 In step S1, photolithography and etching are performed using the same photomask to simultaneously form the first depth adjustment trench 103b and the second depth adjustment trench 104, but the gate oxide trench is not formed simultaneously. The first depth adjustment trench 103b exposes the substrate sidewall of the gate oxide region (HVG) of the high voltage transistor. The number of first depth adjustment trenches 103b on one side of the gate oxide region (HVG) of the high voltage transistor can be one, two, or more. The number of second depth adjustment trenches 104 on one side of the gate oxide region (HVG) can be one, two, or more.

[0067] Furthermore, it should be understood that in the above examples, the critical dimension CD of the first depth adjustment groove needs to meet the requirements of subsequent processes, such as being at least greater than 80nm, to ensure the process window for forming the second pad oxide layer 105 and the second nitride layer 106 in the subsequent step S2.

[0068] Please continue to refer to this. Figure 2A The step of forming the first drift region 111 in step S2 includes:

[0069] S2.1, a second pad oxide layer 105 and a second photoresist layer 201 are sequentially formed on the surface of the substrate 100 after the trench 103 is formed. The second pad oxide layer 105 covers the inner surface of the trench 103 (i.e., the gate oxide trench and the first depth adjustment trench) and the surface of the substrate 100 surrounding the trench 103. The second pad oxide layer 105 can be formed by any suitable process such as thermal oxidation or chemical vapor deposition, and it serves as a substrate protection layer for subsequent photolithography and other processes.

[0070] S2.2, a different photomask than the first photomask is used to perform photolithography on the second photoresist layer 201 to define the injection area of ​​the first drift region.

[0071] S2.3 Using the second photoresist layer 201 after photolithography as a mask, ion implantation is performed on the top of the substrate in the exposed area of ​​the second photoresist layer 201 after photolithography using a lightly doped source-drain ion implantation (LDD) process to form a first drift region 111.

[0072] S2.4, Remove the second photoresist layer 201.

[0073] In this example, the first drift region 111 can be formed on the top sidewall of the active region HVG of the gate oxide region of the high voltage transistor, extending from the top of the second active region of the second depth adjustment trench 104 to the top of the active region HVG of the high voltage transistor, under the limiting effect of the second photoresist layer 201 after photolithography, thereby making the top of the source / drain region HVS / D of the high voltage transistor subsequently defined.

[0074] For other examples, please refer to Figure 7 The first drift region 111 can be formed only on the top sidewall of the active region HVG of the gate oxide region of the high voltage transistor under the constraint of the second photoresist after photolithography.

[0075] In step S2 of this embodiment, whether the conductivity type of the ions implanted by the LDD process is n-type or p-type depends on whether the high-voltage transistor is an nMOS or a pMOS. The LDD process used in this step is a tilted ion implantation process, and its conditions can be the same as those of the LDD process in the prior art. Therefore, its implantation depth in the vertical direction is shallow, and at the same time, its implantation depth in the lateral direction of the gate oxide region is also shallow, resulting in a low implantation concentration.

[0076] In this embodiment, since the active region sidewall of the gate oxide region of the high-voltage transistor is exposed when the first depth adjustment trench is formed in step S1, or a gate oxide trench is further formed in step S1, and ion implantation in step S2 is performed before performing the active region manufacturing process (AA Loop, i.e., performing step S3), ions can be effectively implanted into the corners of the area to be implanted in the LDD process. Compared with the prior art (i.e., first filling each shallow trench to form a shallow trench isolation structure, then defining the LDD process implantation area by photoresist PR, and then performing the LDD process), the present invention can avoid the rounding of the corner openings of the photoresist PR (e.g., Figure 9 (As shown in the dashed box in the figure) This leads to imperfect corner injection of the active region HVG of the gate oxide region of the high voltage transistor under LDD process, thus eliminating the side effect caused by the step height (SH) of the high voltage transistor in the prior art.

[0077] In addition, please refer to Figure 2A In the ion implantation process of step S2, since the top of the active region of the gate oxide region of the high voltage transistor is covered by the second pad oxide layer 105, the ions can be implanted into the implantation area required by the LDD process and have a good protection effect on the active region below, without having a bad impact on the threshold voltage regulation of the high voltage transistor.

[0078] In another example of this embodiment, please refer to Figure 6 When no gate oxide trench is formed in step S1 and the formed first depth adjustment trench 103b can expose the sidewall of the active region HVG of the gate oxide region of the high voltage transistor, the first pad oxide layer 101 and the first nitride layer 102 can be retained after the first depth adjustment trench 103b is formed in step S1, so that the remaining second photoresist layer is formed and photolithographically ...

[0079] Optionally, the second nitride layer 106 can be formed on the second pad oxide layer 105 after forming the second pad oxide layer 105 in step S2 and before ion implantation; or, the second nitride layer 106 can be formed on the second pad oxide layer 105 after removing the second photoresist layer 201; or, after removing the second photoresist layer 201, the remaining second pad oxide layer 105 can be removed first, and a new second pad oxide layer 105 can be re-covered, and the second nitride layer 106 can be formed on the new second pad oxide layer 105. Thus, the second nitride layer 106 and the second pad oxide layer 105 covering it constitute a hard mask layer, preparing for the subsequent fabrication of shallow trenches. The second pad oxide layer 105 covered by the second nitride layer 106 serves as an etching stop layer for etching the second nitride layer 106 in subsequent etching processes, and protects the surface of the substrate 100 during the etching of the second nitride layer 106. The second nitride layer 106 can be formed by any suitable process such as chemical vapor deposition, and its material can be any suitable dielectric material such as silicon nitride.

[0080] Please refer to Figure 2A and Figure 2B In step S3, an active region fabrication process (AA loop) is performed on the substrate 100 having a first depth adjustment trench and a first drift region 111 to form corresponding shallow trenches 107, 108, and 109 in the substrate 100, thereby defining the active regions for high-voltage transistors and other components. The specific process of this active region fabrication process (AA loop) includes the following steps:

[0081] S3.1, A third photoresist layer 202 is formed on the second nitride layer 106 by spin coating and other processes;

[0082] S3.2, the third photoresist layer 202 is photolithographically ...

[0083] S3.3, using the third photoresist layer 202 after photolithography as a mask, the second nitride layer 106, the second pad oxide layer 105 and the substrate 100 are etched using any suitable etching process such as dry etching to form corresponding shallow trenches 107, 108 and 109.

[0084] S3.4 Remove the third photoresist layer 202 using any suitable photoresist removal process, such as dry or wet photoresist removal.

[0085] The shallow trench 107 formed at trench 103 is located on both sides of the gate oxide trench (i.e., the active region HVG of the gate oxide region of the high-voltage transistor), and overlaps with the first depth adjustment trench and is connected to both the gate oxide trench and the first depth adjustment trench, so as to separate the active region HVG at the gate oxide trench from the source / drain region HVS / D of the high-voltage transistor. Due to the effect of trench 103, the bottom of the shallow trench 107 formed at trench 103 is deeper than the bottom of the shallow trench 109 in the region of other components. In addition, the shallow trench 108 is formed between the active region (i.e., HV region) of the high-voltage transistor and the active region (i.e., Other) of other components, on the one hand to realize the isolation between the active region of the high-voltage transistor and the active region of other components, and on the other hand to define the source / drain region HVS / D of the high-voltage transistor together with the shallow trench 107.

[0086] In one example, please refer to Figure 2A Since trenches 103 and second depth adjustment trenches 104 of essentially the same depth are simultaneously formed in the substrate region HV of the high-voltage transistor to be fabricated in step S1, in step S3, when performing the above-mentioned active region manufacturing process, a corresponding shallow trench 108 is also formed in the substrate at the second depth adjustment trench 104. The shallow trench 108 formed at the second depth adjustment trench 104 overlaps with and is connected to the second depth adjustment trench 104. At this time, the bottom depth of the shallow trench 108 formed at the second depth adjustment trench 104 is essentially the same as the bottom depth of the shallow trench 107, and is deeper than the bottom of the shallow trench 109 in the region of other components.

[0087] For other examples, please refer to Figure 5 When the second depth adjustment groove 104 is not formed synchronously in step S1, after the above-mentioned active area manufacturing process is performed in step S3, the bottom depth of the shallow trench 108 formed is the same as the bottom depth of the shallow trench 109 in the other component area Other, and is shallower than the bottom depth of the shallow trench 107 formed at the trench 103.

[0088] In addition, it should be understood that please refer to Figure 2A and Figure 2B In the process, the degree of overlap between the corresponding opening in the third photoresist layer 202 after photolithography and the trench 103 determines the degree of overlap between the shallow trench 107 formed at the trench 103 and the trench 103, and thus determines whether the sidewall of the shallow trench 107 formed at the trench 103 is aligned with the sidewall of the trench 103 or forms a step, or in other words, the degree of overlap between the shallow trench 107 and the first depth adjustment groove, and thus determines whether the sidewall of the shallow trench 107 is aligned with the sidewall of the first depth adjustment groove or has a step.

[0089] In one example, such as Figure 2A , Figure 2B and Figure 5 As shown, the corresponding opening in the third photoresist layer 202 after photolithography is aligned with the trench 103, and the sidewall of the shallow trench 107 formed at the trench 103 is aligned with the sidewall of the trench 103, that is, the sidewall of the shallow trench 107 is aligned with the sidewall of the first depth adjustment groove.

[0090] In another example, please refer to Figure 7 The corresponding opening in the third photoresist layer 202 after photolithography is relatively large and offset outward relative to the sidewall of the trench 103. Therefore, a step is formed between the outer wall of the shallow trench 107 formed at the trench 103 and the outer wall of the trench 103 (that is, a step is formed between the outer wall of the shallow trench 107 and the outer wall of the first depth adjustment groove).

[0091] In yet another example, please refer to Figure 8 The size of the corresponding opening in the third photoresist layer 202 after photolithography is relatively small and offset inward relative to the sidewall of the trench 103. Therefore, a step is also formed between the outer wall of the shallow trench 107 formed at the trench 103 and the outer wall of the trench 103 (that is, a step is formed between the outer wall of the shallow trench 107 and the outer wall of the first depth adjustment groove). In this case, the active region surface exposed above the top surface of the step is also covered with a second pad oxide layer 105 and a second nitride layer 106.

[0092] Similarly, when the second depth adjustment groove 104 is formed at the same time as the groove 103 is formed, the overlap between the shallow groove 108 and the second depth adjustment groove 104 at the second depth adjustment groove 104 is different, which can also make the sidewall of the shallow groove 108 at the second depth adjustment groove 104 aligned with the sidewall of the second depth adjustment groove 104 or form a step, which will not be described in detail here.

[0093] It should be understood that, in this embodiment, by utilizing the depth of the first depth adjustment trench (including the portion of trench 103 used as the first depth adjustment trench) and the depth of the second depth adjustment trench 104, the depth of the shallow trench (STI trench) in the substrate region of the high-voltage transistor can be increased, thereby increasing the charge path of the high-voltage transistor and increasing its breakdown voltage. Moreover, under the same breakdown voltage capability, the high-voltage transistor of the present invention can have a shorter active region length compared to existing high-voltage transistors, which is beneficial for reducing the area of ​​the high-voltage transistor, and thus the chip area, and improving integration density. In some examples, the depth of the gate oxide trench is further utilized to reduce the top height of the thick gate oxide layer subsequently formed on the active region HVG, thereby reducing the step height (SH) between the high-voltage transistor and other components.

[0094] Please refer to Figure 2BIn step S4, any suitable process can be used to fill dielectric material into each shallow trench 107, 108, 109 and trench 103 and second depth adjustment groove 104 to form the desired shallow trench isolation structures STI1, STI2 and STI3.

[0095] In one example, a gate oxide trench is formed synchronously with the first depth adjustment trench in step S1. Before or after filling the dielectric material, the hard mask layer (i.e., the second pad oxide layer 105 and the second nitride layer 106) on the active region HVG of the gate oxide region is retained. At this time, the shallow trench isolation structure STI1 buries the hard mask layer on the active region HVG of the gate oxide region of the high voltage transistor. Then the second nitride layer 106 in the hard mask layer exposed by the shallow trench isolation structure can be removed, and even the second pad oxide layer 105 in these remaining areas can be removed.

[0096] In this example, the process of forming the required shallow trench isolation structures STI1, STI2, and STI3 in step S4 includes the following steps:

[0097] S4.1, using any suitable process such as dry etching, pull back the second nitride layer 106 in the hard mask layer to make the pattern sidewall of the second nitride layer 106 retreat a certain distance.

[0098] S4.2, A linear oxide layer 110 is formed on the inner surface of shallow trenches 107, 108, 109 and trench 103 and second depth adjustment groove 104 by processes such as thermal oxidation;

[0099] S4.3, using a high aspect ratio fill process (HARP) or other suitable process, deposit dielectric material 112 (e.g., silicon oxide) in shallow trenches 107, 108, 109 and trenches 103 and second depth adjustment trenches 104 until the shallow trenches 107, 108, 109 and trenches 103 and second depth adjustment trenches 104 are filled;

[0100] S4.4, using a suitable process such as chemical mechanical polishing, the top surface of the filled dielectric material 112 is planarized until the top surface of the second nitride layer 106 is exposed. This forms a shallow trench isolation structure STI1 in the connected shallow trenches 107 and 103 to isolate the active region HVG of the gate oxide region of the high-voltage transistor from the source / drain region HVS / D of the high-voltage transistor; a shallow trench isolation structure STI2 is formed in the connected shallow trench 108 and the second depth adjustment trench 104 to define the source / drain region HVS / D of the high-voltage transistor and isolate the high-voltage transistor from other components; and a shallow trench isolation structure STI3 is formed in the shallow trench 109 to isolate other components from the high-voltage transistor. At this time, due to the trench 103, the second nitride layer 106 and the second pad oxide layer 105 on the active region HVG of the gate oxide region of the high-voltage transistor are retained and buried within the shallow trench isolation structure STI1.

[0101] S4.5, the second nitride layer 106 exposed by the shallow trench isolation structure STI1 (i.e., the hard mask layer on the area other than the gate oxide trench) is removed by any suitable process such as wet etching, and the second pad oxide layer 105 is retained. The second pad oxide layer 105 protects the surface of the substrate 100 other than the active region HVG of the gate oxide region of the high voltage transistor in subsequent steps S5 and S6.

[0102] In other examples of this embodiment, in step S4.4, a suitable process such as chemical mechanical polishing can also be used to planarize the top surface of the filled dielectric material 112 until the second nitride layer 106 on the substrate other than the active region HVG of the gate oxide region of the high voltage transistor is removed, thereby saving one etching process.

[0103] In other examples of this embodiment, when the gate oxide trench is not formed synchronously with the first depth adjustment trench in step S1, in step S4.4, a suitable process such as chemical mechanical polishing can be used to planarize the top surface of the filled dielectric material 112 until the second nitride layer 106 is removed or until the second pad oxide layer 105 is removed.

[0104] Please continue to refer to this. Figure 2BIn step S5, a patterned photoresist (not shown) is formed using photolithography to mask the active regions of other components (i.e., the substrate region Other used to form other components) and expose the active region of the high-voltage transistor (i.e., the substrate region HV used to form the high-voltage transistor). Using the patterned photoresist as a mask, a suitable process such as vertical ion implantation is employed to implant ions into the active region of the high-voltage transistor to form a second drift region 113. The implanted ions are suitable ions such as n-type or p-type ions. The patterned photoresist is then removed. The ion implantation depth for forming the second drift region 113 is greater than the ion implantation depth for forming the first drift region 111. The second drift region 113 and the first drift region 111 are connected, together forming the drift region required for the high-voltage transistor.

[0105] As an example, ion implantation to form the second drift region 113 can include two steps: the first step involves slightly deeper ion implantation at a lower energy level, serving as channel conditioning. For pMOS transistors, this step can implant lightweight n-type ions such as phosphorus (P) ions, while for nMOS transistors, it can implant lightweight p-type ions such as boron (B) ions. The second step involves very shallow ion implantation at a very low energy level, serving as threshold voltage conditioning. This step can implant the same ions as the first step or different ions. For example, for pMOS transistors, this step can implant heavy n-type ions such as arsenic (As) or antimony (Sb) ions, which are less prone to diffusion; for nMOS transistors, this step can implant heavy n-type ions such as aluminum (Al), gallium (Ga), or indium (In), which are also less prone to diffusion.

[0106] In one example, please refer to Figure 2C The process of forming the desired thick gate oxide layer 118 in step S6 includes the following steps:

[0107] S6.1, a silicon nitride layer 115 can be deposited by processes such as chemical vapor deposition. The thickness of the silicon nitride layer 115 is generally much thicker than that of the second nitride layer 106. Therefore, when the second nitride layer 106 is subsequently pulled back and etched or removed, even if the silicon nitride layer 115 and the second nitride layer 106 are consumed simultaneously, there will be no adverse effects.

[0108] S6.2 Spin-coat photoresist and perform photolithography on the photoresist layer to open the photoresist layer on the active region HVG of the gate oxide region of the high voltage transistor, forming a patterned photoresist layer (not shown).

[0109] S6.3, using a patterned photoresist layer as a mask, etch the silicon nitride layer 115 on the active region HVG of the gate oxide region of the high voltage transistor;

[0110] S6.4, Remove the patterned photoresist layer, and using the silicon nitride layer 115 as a mask, etch the shallow trench isolation structure STI1 on the active region HVG of the gate oxide region of the high voltage transistor until the second nitride layer 106 on the active region HVG of the gate oxide region of the high voltage transistor is exposed.

[0111] S6.5, using silicon nitride layer 115 as a mask and under the protection of second nitride layer 106, the top sidewalls of shallow trench isolation structure STI1 on both sides of the active region HVG of the gate oxide region of the high voltage transistor are etched to form side trench 117. In this process, the presence of second nitride layer 106 can form etching protection for the active region HVG of the gate oxide region of the high voltage transistor, so that more dielectric material 112 is consumed at side trench 117, and less consumption of second pad oxide layer 105 below second nitride layer 106 and the apex corner of the active region. This is beneficial to optimize the rounding of the apex corner of the active region HVG of the gate oxide region of the high voltage transistor, and further remove the remaining second nitride layer 106 and the second pad oxide layer 105 below it on the active region HVG of the gate oxide region. The process of removing second nitride layer 106 will thin the silicon nitride layer 115 to a certain extent.

[0112] S6.6 Using silicon nitride layer 115 as a mask, the active region HVG of the gate oxide region of the high voltage transistor is thermally oxidized to form a thick gate oxide layer 118 of the required thickness.

[0113] In one example, in step S6.5, the etching process that forms the trench 117 also slowly etches and removes the second nitride layer 106 and the second pad oxide layer 105 below it, while forming the trench 117 of the required depth, and also exposes the top surface and top corner of the active region HVG of the gate oxide region of the high voltage transistor.

[0114] In step S6, since the height of the active region HVG of the gate oxide region of the high voltage transistor is reduced by the trench 103 formed in step S1, after the formation of the thick gate oxide layer 118, the step height (SH) between the high voltage transistor and other components can be reduced compared with the prior art, thereby reducing the load effect and defects of subsequent processes, improving the performance of the high voltage transistor, and also helping to reduce the device area of ​​the high voltage transistor.

[0115] In other examples of this embodiment, the fabrication of the side trench 117 can be omitted as needed, and the top surface of the active region HVG of the exposed gate oxide region of the high voltage transistor can be directly thermally oxidized to form a thick gate oxide layer 118.

[0116] After step S6, the silicon nitride layer 115 and the second pad oxide layer 105 are removed first. Then, a thin gate oxide layer (not shown) is formed on the active region of other components and the substrate region HV of the high voltage transistor to be fabricated. The gate (not shown) is formed together on the thick gate oxide layer and the thin gate oxide layer.

[0117] In summary, the semiconductor device manufacturing method of the present invention, before performing the active region manufacturing process, first performs trench etching on the substrate region of the high-voltage transistor to be fabricated, so as to form at least a first depth adjustment trench located outside the gate oxide region of the high-voltage transistor. This allows the depth of the first depth adjustment trench to increase the bottom depth (STItrench) of the shallow trench isolation structure used to isolate the source / drain regions and the channel region of the high-voltage transistor after subsequent active region manufacturing processes, thereby increasing the charge path of the high-voltage transistor and its breakdown voltage. After forming the first depth adjustment trench and before performing the active region manufacturing process (AA loop), ion implantation is performed on the active region of the gate oxide sidewall using the LDD process to form a first drift region. This effectively implants ions to the corners of the regions that should be implanted in the existing LDD (lightly doped source / drain ion implantation) process, which helps to eliminate the side effect caused by the step height (SH) of the high-voltage transistor and avoids the problem of incomplete implantation caused by the rounded exposure of photoresist corners in the existing LDD process. While forming the first depth adjustment trench, a gate oxide trench is also formed to reduce the top height of the gate oxide region of the high-voltage transistor. This gate oxide trench reduces the step height between the high-voltage transistor and other components, thereby reducing the load effect and defects in subsequent processes and improving the performance of the high-voltage transistor. At the same voltage withstand capability, the high-voltage transistor of this invention can have a shorter active region length compared to existing high-voltage transistors, which helps to reduce the area of ​​the high-voltage transistor, and consequently the chip area, and improve integration density. The semiconductor device manufacturing method of this invention is simple, controllable, and effective.

[0118] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, and a trench etching is performed on the substrate region to be fabricated as a high-voltage transistor to form at least a first depth adjustment trench located outside the gate oxide region of the high-voltage transistor. At least the substrate of the gate oxide region sidewall is ion implanted to form a first drift region; An active region manufacturing process is performed on the substrate having the first drift region to form corresponding shallow trenches in the substrate, wherein a portion of the shallow trenches overlaps with and communicates with the first depth adjustment trench, and the active region manufacturing process deepens the bottom depth of the portion of shallow trenches through the first depth adjustment trench. Dielectric material is filled into each of the shallow trenches and the first depth adjustment groove to form a shallow trench isolation structure; Ion implantation is performed on the active region of the high-voltage transistor to form a second drift region; A thick gate oxide layer is formed on the gate oxide region.

2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, Before or after the formation of the first drift region by ion implantation and before the active region manufacturing process is performed, a hard mask layer is also formed over the substrate having the first depth adjustment groove.

3. The method for manufacturing a semiconductor device as described in claim 1 or 2, characterized in that, The first depth adjustment trench exposes the substrate surface of the sidewall of the gate oxide region; or, trench etching is performed on the substrate area to be fabricated as a high-voltage transistor to form a gate oxide trench at the same time as forming the first depth adjustment trench, wherein the active region at the bottom of the gate oxide trench is the gate oxide region, and the portion of the shallow trench is also connected to the gate oxide trench; wherein the gate oxide trench is spaced apart from or connected to the first depth adjustment trenches on both sides, and / or, the first depth adjustment trench on one side of the gate oxide trench is one or at least two.

4. The method for manufacturing a semiconductor device as described in claim 3, characterized in that, Trench etching is performed on the substrate area to be fabricated for a high-voltage transistor. While forming the first depth adjustment trench, at least one second depth adjustment trench is also formed at the boundary of the active region of the high-voltage transistor. After the active region fabrication process is performed, the second depth adjustment trench overlaps with and communicates with the corresponding shallow trench to deepen the bottom depth of the shallow trench and separate the active region of the high-voltage transistor from the active regions of other components.

5. The method for manufacturing a semiconductor device as described in claim 4, characterized in that, Ion implantation is performed on at least the substrate of the gate oxide sidewall of the high-voltage transistor, and the resulting first drift region extends from a portion of the second depth adjustment trench to the gate oxide sidewall of the high-voltage transistor.

6. The method for manufacturing a semiconductor device as described in claim 1, 2, or 5, characterized in that, The steps for forming the first depth adjustment groove include: A first pad oxide layer, a first nitride layer, and a first photoresist layer are sequentially formed on the substrate; The first photoresist layer is photolithographically etched using a first photomask to at least define the formation area of ​​the first depth adjustment groove; Using the first photoresist layer after photolithography as a mask, the first nitride layer, the first pad oxide layer and the substrate are etched sequentially to form at least the first depth adjustment groove in the substrate; Remove the first photoresist layer, the first nitride layer, and the first pad oxide layer.

7. The method for manufacturing a semiconductor device as described in claim 3, characterized in that, The hard mask layer also covers the inner surface of the gate oxide trench, and after the dielectric material is filled to form a shallow trench isolation structure, the shallow trench isolation structure also buries the hard mask layer in the gate oxide trench.

8. The method for manufacturing a semiconductor device as described in claim 7, characterized in that, It also includes at least one of the following (1) to (5): (1) After the second drift region is formed and before the thick gate oxide layer is formed on the gate oxide region, the shallow trench isolation structure in the gate oxide trench is etched open, and the shallow trench isolation structure on the sidewall of the gate oxide trench is further etched to form a side trench that exposes the apex of the active region in the gate oxide trench. The hard mask layer in the gate oxide trench protects the active region in the gate oxide trench during the formation of the side trench. The thick gate oxide layer is also formed in the side trench. (2) Before filling the shallow trenches and the first depth adjustment trench with dielectric material, the sidewalls of the hard mask layer on the substrate are first pulled back and etched. (3) After filling each of the shallow trenches and the first depth adjustment trench with dielectric material, the top surface of the dielectric material is planarized until the top surface of the hard mask layer on the substrate region surrounding the gate oxide trench is exposed or until the hard mask layer on the substrate region surrounding the gate oxide trench is removed. (4) Before forming the thick gate oxide layer, the remaining hard mask layer in the gate oxide trench is removed to expose the top surface of the active region of the gate oxide region; (5) The hard mask layer includes a second pad oxide layer stacked on the substrate, or includes a second pad oxide layer and a second nitride layer stacked sequentially on the substrate.

9. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, Before forming the first drift region by ion implantation, a second pad oxide layer is first formed on the substrate. After forming the first drift region and before performing the active region manufacturing process, a second nitride layer is formed on the second pad oxide layer to form the hard mask layer.

10. A method for manufacturing a semiconductor device as described in any one of claims 1-2, 4-5, or 7-9, characterized in that, It also includes at least one of the following (1) to (5): (1) Ion implantation is performed using a lightly doped source-drain ion implantation process to form the first drift region; (2) The sidewall of the first depth adjustment groove is aligned with or forms a step with the sidewall of the shallow groove it communicates with; (3) Photolithography and trench etching are performed on the substrate area to be fabricated for high voltage transistors using the zero-layer photomask, so as to form the first depth adjustment trench and the zero-layer alignment mark in the substrate at the same time. (4) Before filling each of the shallow trenches and the first depth adjustment groove with dielectric material, a linear oxide layer is formed on the inner surface of each of the shallow trenches and the first depth adjustment groove. (5) After forming the thick gate oxide layer, a thin gate oxide layer is also formed on the active region of the other elements, and a gate is formed together on the thick gate oxide layer and the thin gate oxide layer.

Images