High-voltage mos device and testing method thereof

Abstract

The application discloses a high-voltage MOS device, and relates to the technical field of semiconductors, comprising a substrate layer, a first epitaxial layer is stacked on the top of the substrate layer, a second epitaxial layer is stacked on the top of the first epitaxial layer, a gate metal is arranged on the second epitaxial layer, the gate metal is wrapped with a contact metal layer outside, the contact metal layer comprises a contact section in contact with the second epitaxial layer, a source metal is arranged on the top of the contact section, and a drain metal is arranged on the bottom of the substrate layer; wherein a first insulating silicon section is arranged between the first epitaxial layer and the substrate layer and located on the left side, a second insulating silicon section is arranged between the first epitaxial layer and the substrate layer and located on the right side, and a gap section is formed between the first insulating silicon section and the second insulating silicon section; a third insulating silicon section is arranged between the second epitaxial layer and the first epitaxial layer and opposite to the gap section; and a testing method of the high-voltage MOS device is also disclosed. The application has the advantages of safety and stability, high reliability and strong anti-single-particle radiation capacity.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a high-voltage MOS device and its testing method. Background Technology

[0002] MOS devices (metal-oxide-semiconductor field-effect transistors) are the main components in modern integrated circuits. Currently, during the continuous operation of MOS devices under radio frequency and other signals, the electronic system may be disturbed or even interrupted due to the radiation of a single energy particle on the semiconductor material or the sensitive area of ​​the semiconductor device. This may also cause a difference in the internal local potential. This local potential difference can trigger parasitic devices inside the semiconductor device, resulting in abnormal circuits or large currents in the semiconductor device, ultimately causing a change in the state of the semiconductor device. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a high-voltage MOS device and its testing method.

[0004] A high-voltage MOS device includes a substrate layer, a first epitaxial layer stacked on top of the substrate layer, a second epitaxial layer stacked on top of the first epitaxial layer, a gate metal disposed on the second epitaxial layer, a contact metal layer surrounding the gate metal, the contact metal layer including a contact segment contacting the second epitaxial layer, a source metal disposed on top of the contact segment, and a drain metal disposed at the bottom of the substrate layer; wherein, a first insulating silicon segment located on the left and a second insulating silicon segment located on the right are disposed between the first epitaxial layer and the substrate layer, and a gap segment is formed between the first insulating silicon segment and the second insulating silicon segment; a third insulating silicon segment is disposed between the second epitaxial layer and the first epitaxial layer, the third insulating silicon segment being directly opposite the gap segment. In the entire high-voltage MOS device, the arrangement of the first and second epitaxial layers forms the mounting positions for the first, second, and third insulating silicon segments, while also increasing the breakdown voltage and effectively reducing the current collapse effect, thus improving the device's reliability. Furthermore, by separately setting the first and second insulating silicon segments between the first epitaxial layer and the substrate layer, and then setting the third insulating silicon segment between the first and second epitaxial layers, two staggered insulating silicon segments are formed. When heavy particles are injected into the entire high-voltage MOS device from the surface, all their injection directions will pass through the two staggered insulating silicon segments. The interface formed by the first epitaxial layer-insulating silicon segment-second epitaxial layer has a significant recombination effect on the newly generated electrons and holes generated by heavy particle radiation, thereby greatly improving the device's resistance to single-event radiation.

[0005] Preferably, the first insulating silicon segment and the second insulating silicon segment are made of silicon dioxide. Between the first epitaxial layer and the substrate layer, the silicon-silicon dioxide cross-section has a recombination effect on newly generated electrons and holes near the cross-section, which reduces the number of newly generated electrons and holes in the heavy particle radiation track ionization region, thereby improving the overall device's resistance to single-event radiation.

[0006] Preferably, the third insulating silicon segment is made of silicon dioxide. Similarly, between the second epitaxial layer and the first epitaxial layer, the silicon-silicon dioxide cross-section has a recombination effect on newly generated electrons and holes near the cross-section, which reduces the number of newly generated electrons and holes in the heavy particle radiation track ionization region, thereby improving the overall device's resistance to single-event radiation.

[0007] Preferably, a passivation layer is disposed on the exterior of the source metal. The passivation layer can block incident particles to a certain extent.

[0008] Preferably, a gate oxide layer is disposed between the gate metal and the second epitaxial layer.

[0009] Preferably, the source metal is stacked on the contact metal layer.

[0010] A testing method for high-voltage MOS devices is also provided, including a device breakdown voltage test procedure, a current collapse test procedure, and a gate pulse test procedure. The device breakdown voltage test procedure measures the breakdown voltage, a crucial indicator of device performance that determines its application environment in circuits. Its off-state breakdown voltage limits the voltage swing of logic circuits and the output power density of amplifiers. The current collapse test procedure detects a significant compression of output leakage current. The gate pulse test procedure measures the gate pulse characteristics, reflecting the switching characteristics of the device.

[0011] Preferably, the device breakdown voltage test steps include: S11, applying current to the drain metal of the device; S12, measuring the breakdown voltages of the source metal and drain metal; S13, measuring the breakdown voltages of the gate metal and drain metal. The drain metal injection is preferably a preset current value, and then the gate metal voltage is gradually increased from zero, while monitoring the gate current (I) during this scan. G Drain-source metal voltage (V) DS ) and drain-gate metal voltage (V DG The change of V. GS It is in the conducting state when the voltage is greater than the threshold voltage, requiring only a very small V. DS That will enable I D It equals the preset value, so V at this time DS Approaching zero, I G Approaching zero. When V GSWhen the voltage is below the threshold voltage, it is in the off state. At this time, the leakage current I needs to be maintained. D To equal the preset value, V must be increased. DS , and V DG =V DS -V GS And it also increases accordingly, when I G equal to -I D When the value is equal to the negative preset value, a breakdown occurs between the gate metal and the drain metal.

[0012] Preferably, the current collapse test steps include: S21, simultaneously applying two pulse signals to the gate metal and drain metal of the device; S22, grounding the source metal; and S23, monitoring the effective electrical signals on the drain metal and gate metal. During the test, the voltage signals on the gate electrode and drain electrode will synchronously change alternately in the form of a first preset voltage, a second preset voltage, and a third preset voltage.

[0013] Preferably, the gate pulse test step includes: S31, electrically connecting the drain metal and applying a constant voltage of a preset value; S32, electrically connecting the gate metal and applying a voltage pulse from the off state to the on state; S33, monitoring the relationship between the drain metal current and the gate metal voltage over time. Typically, due to the presence of numerous surface traps between the gate and drain metals, the response of the drain metal current is delayed compared to the rise of the voltage on the gate metal. Obviously, the smaller this time delay, the better the switching characteristics of the device.

[0014] The beneficial effects of this invention are reflected in:

[0015] In this invention, the arrangement of the first and second epitaxial layers forms the mounting positions for the first, second, and third insulating silicon segments, while simultaneously increasing the breakdown voltage and effectively reducing the current collapse effect of the device, thereby improving its reliability. Furthermore, by separately setting the first and second insulating silicon segments between the first epitaxial layer and the substrate layer, and then setting the third insulating silicon segment between the first and second epitaxial layers, two interleaved insulating silicon segments are formed. When heavy particles are injected into the entire high-voltage MOS device from the surface, all their injection directions will pass through the two interleaved insulating silicon segments. The interface formed by the first epitaxial layer, the insulating silicon segment, and the second epitaxial layer has a significant recombination effect on the newly generated electrons and holes generated by heavy particle radiation, thereby greatly improving the device's resistance to single-event radiation. Attached Figure Description

[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0017] Figure 1 This is a schematic diagram of the high-voltage MOS device of the present invention;

[0018] Figure 2 This is a circuit diagram illustrating the device breakdown voltage test step in the high-voltage MOS device test method of the present invention.

[0019] Figure 3 This is a circuit diagram of the gate pulse test step in the test method for high-voltage MOS devices of the present invention.

[0020] Figure label:

[0021] 1-Substrate layer, 2-First epitaxial layer, 3-Second epitaxial layer, 4-Gate metal, 5-Contact metal layer, 51-Contact segment, 6-Source metal, 7-Drain metal, 8-First insulating silicon segment, 9-Second insulating silicon segment, 10-Third insulating silicon segment, 11-Gap segment, 12-Passivation layer, 13-Gate oxide layer. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0024] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] In the description of the embodiments of the present invention, it should be noted that the terms "inner", "outer", "upper", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the present invention.

[0026] like Figure 1 As shown, a high-voltage MOS device includes a substrate layer 1, a first epitaxial layer 2 stacked on top of the substrate layer 1, a second epitaxial layer 3 stacked on top of the first epitaxial layer 2, a gate metal 4 disposed on the second epitaxial layer 3, a contact metal layer 5 surrounding the gate metal 4, the contact metal layer 5 including a contact segment 51 contacting the second epitaxial layer 3, a source metal 6 disposed on top of the contact segment 51, and a drain metal 7 disposed at the bottom of the substrate layer 1; wherein, a first insulating silicon segment 8 located on the left and a second insulating silicon segment 9 located on the right are disposed between the first epitaxial layer 2 and the substrate layer 1, and a gap segment 11 is formed between the first insulating silicon segment 8 and the second insulating silicon segment 9; a third insulating silicon segment 10 is disposed between the second epitaxial layer 3 and the first epitaxial layer 2, and the third insulating silicon segment 10 is directly opposite the gap segment 11.

[0027] In this embodiment, it should be noted that, in the entire high-voltage MOS device, the arrangement of the first epitaxial layer 2 and the second epitaxial layer 3 forms, on the one hand, the mounting positions of the first insulating silicon segment 8, the second insulating silicon segment 9, and the third insulating silicon segment 10, and on the other hand, it can improve the breakdown voltage, effectively reduce the current collapse effect of the device, and improve the reliability of the device. Furthermore, by separately setting the first insulating silicon segment 8 and the second insulating silicon segment 9 between the first epitaxial layer 2 and the substrate layer 1, and then setting the third insulating silicon segment 10 between the first epitaxial layer 2 and the second epitaxial layer 3, two layers of interleaved insulating silicon segments are formed. When heavy particles are injected into the entire high-voltage MOS device from the surface, all their injection directions will pass through the two layers of interleaved insulating silicon segments. The interface formed by the first epitaxial layer 2-insulating silicon segment-second epitaxial layer 3 has a significant recombination effect on the newly generated electrons and holes generated by heavy particle radiation, thereby greatly improving the device's resistance to single-event radiation.

[0028] Specifically, the first insulating silicon segment 8 and the second insulating silicon segment 9 are made of silicon dioxide.

[0029] In this embodiment, it should be noted that between the first epitaxial layer 2 and the substrate layer 1, the silicon-silicon dioxide cross section has a recombination effect on newly generated electrons and holes near the cross section, which reduces the number of newly generated electrons and holes in the heavy particle radiation track ionization region, thereby improving the overall device's resistance to single-event radiation.

[0030] Specifically, the third insulating silicon segment 10 is made of silicon dioxide.

[0031] In this embodiment, it should be noted that, similarly, between the second epitaxial layer 3 and the first epitaxial layer 2, the silicon-silicon dioxide cross section has a recombination effect on newly generated electrons and holes near the cross section, which reduces the number of newly generated electrons and holes in the heavy particle radiation track ionization region, thereby improving the overall device's resistance to single-event radiation.

[0032] Specifically, a passivation layer 12 is disposed on the outside of the source metal 6.

[0033] In this embodiment, it should be noted that the passivation layer 12 can block incident particles to a certain extent.

[0034] Specifically, a gate oxide layer 13 is disposed between the gate metal 4 and the second epitaxial layer 3.

[0035] Specifically, the source metal 6 is stacked on the contact metal layer 5.

[0036] A test method for high-voltage MOS devices is also provided, including a device breakdown voltage test step, a current collapse test step, and a gate pulse test step.

[0037] In this embodiment, it should be noted that the device breakdown voltage test step is used to measure the breakdown voltage, which is an important indicator of device performance and determines the application environment of the device in the circuit. Its off-state breakdown voltage limits the voltage swing of the logic circuit and the output power density of the amplifier; the current collapse test step is used to test the output leakage current, which shows a significant compression; the gate pulse test step is used to test the gate pulse characteristics, which reflect the switching characteristics of the device.

[0038] Specifically, the device breakdown voltage test steps include: S11, passing current through the drain metal 7 of the device; S12, measuring the breakdown voltage of the source metal 6 and the drain metal 7; S13, measuring the breakdown voltage of the gate metal 4 and the drain metal 7.

[0039] In this embodiment, it should be noted that, as Figure 2As shown, a current of a preset value is injected into the drain metal 7, and then the voltage of the gate metal 4 is gradually increased from zero. During this scan, the changes in the gate current (), drain-source metal 6 voltage (), and drain-gate metal 4 voltage () are monitored. When the voltage is greater than the threshold voltage, the circuit is in the on state, and only a small amount is needed to make it equal to the preset value, so it is close to zero at this time. When the voltage is less than the threshold voltage, the circuit is in the off state. At this time, to maintain the drain current equal to the preset value, it must be increased, and the voltage (=-) also increases accordingly. When the voltage equals - equals the negative preset value, a breakdown occurs between the gate metal 4 and the drain metal 7.

[0040] Specifically, the current collapse test steps include: S21, applying two pulse signals simultaneously to the gate metal 4 and drain metal 7 of the device; S22, grounding the source metal 6; and S23, monitoring the effective electrical signals on the drain metal 7 and gate metal 4.

[0041] In this embodiment, it should be noted that during the test, the voltage signals on the gate electrode and the drain electrode will change synchronously in the form of a first preset voltage, a second preset voltage, and a third preset voltage.

[0042] Specifically, the gate pulse test steps include: S31, electrically connecting the drain metal 7 and applying a constant voltage of a preset value; S32, electrically connecting the gate metal 4 and applying a voltage pulse from the off state to the on state; S33, monitoring the relationship between the drain metal 7 current and the gate metal 4 voltage over time.

[0043] In this embodiment, it should be noted that, as Figure 3 As shown, due to the presence of numerous surface traps between the gate and drain metals 7, the response of the drain metal 7 current is delayed compared to the rise of the voltage on the gate metal 4. Obviously, the smaller this time delay, the better the switching characteristics of the device.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and specification of the present invention.

Claims

1. A high-voltage MOS device, characterized in that, The system includes a substrate layer, a first epitaxial layer stacked on top of the substrate layer, a second epitaxial layer stacked on top of the first epitaxial layer, a gate metal disposed on the second epitaxial layer, a contact metal layer surrounding the gate metal, the contact metal layer including a contact segment contacting the second epitaxial layer, a source metal disposed on top of the contact segment, and a drain metal disposed at the bottom of the substrate layer; wherein... A first insulating silicon segment located on the left and a second insulating silicon segment located on the right are disposed between the first epitaxial layer and the substrate layer. A gap segment is formed between the first insulating silicon segment and the second insulating silicon segment. At the gap segment, the first epitaxial layer contacts the substrate layer. The gap segment is located only directly below the gate metal. A third insulating silicon segment is disposed between the second epitaxial layer and the first epitaxial layer. The third insulating silicon segment is located directly below the gate metal and is directly opposite the gap segment.

2. The high-voltage MOS device according to claim 1, characterized in that, The first insulating silicon segment and the second insulating silicon segment are made of silicon dioxide.

3. The high-voltage MOS device according to claim 1, characterized in that, The third insulating silicon segment is made of silicon dioxide.

4. The high-voltage MOS device according to claim 1, characterized in that, The source metal is provided with a passivation layer on its exterior.

5. The high-voltage MOS device according to claim 1, characterized in that, A gate oxide layer is disposed between the gate metal and the second epitaxial layer.

6. The high-voltage MOS device according to claim 1, characterized in that, The source metal is stacked on the contact metal layer.

7. A test method for a high-voltage MOS device according to any one of claims 1-6, characterized in that, This includes device breakdown voltage testing procedures, current collapse testing procedures, and gate pulse testing procedures.

8. The test method for high-voltage MOS devices according to claim 7, characterized in that, The device breakdown voltage test steps include: S11, passing current through the drain metal of the device; S12, measuring the breakdown voltage of the source metal and drain metal; S13, measuring the breakdown voltage of the gate metal and drain metal.

9. The test method for the high-voltage MOS device according to claim 7, characterized in that, The current collapse test steps include: S21, applying two pulse signals simultaneously to the gate metal and drain metal of the device; S22, grounding the source metal; S23, monitoring the effective electrical signals on the drain metal and gate metal.

10. The test method for the high-voltage MOS device according to claim 7, characterized in that, The gate pulse test steps include: S31, electrically connecting the drain metal and applying a constant voltage of a preset value; S32, electrically connecting the gate metal and applying a voltage pulse from the off state to the on state; S33, monitoring the relationship between the drain metal current and the gate metal voltage over time.

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