Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes a display area and a non-display area formed around the display area, the display device including: a substrate; a pixel circuit layer disposed on the substrate and including a plurality of sub-pixel circuits disposed in the display area; the plurality of first conductive connectors are arranged on the pixel circuit layer; and a display element layer disposed on the first conductive connector. The display element layer may include a plurality of light-emitting elements disposed in the display area and a plurality of dummy light-emitting elements disposed in the non-display area, in which the plurality of light-emitting elements are electrically connected to the sub-pixel circuits through first conductive connectors disposed in the display area, and the plurality of dummy light-emitting elements are electrically connected to the sub-pixel circuits through second conductive connectors disposed in the non-display area. And is configured to emit light in response to a signal applied from the sub-pixel circuit. The light-emitting element and the dummy light-emitting element may include the same material.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0063191, filed on May 14, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of this disclosure relate to display devices and methods of manufacturing display devices. Background Technology

[0004] The recent increase in interest in displays has spurred ongoing research and development of display devices. Summary of the Invention

[0005] Various embodiments of this disclosure relate to display devices and methods of manufacturing display devices, which can simplify manufacturing processes, shorten the time spent performing manufacturing processes, and reduce production costs.

[0006] Various embodiments of this disclosure relate to display devices that can reduce the risk of electrical short circuits and methods of manufacturing display devices.

[0007] Various embodiments of this disclosure relate to display devices with improved light output efficiency and methods for manufacturing display devices.

[0008] However, the features of this disclosure are not limited to those described above, and various modifications are possible without departing from the spirit and scope of this disclosure.

[0009] According to embodiments of this disclosure, a display device including a display area and a non-display area formed around the display area includes: a substrate; a pixel circuit layer disposed on the substrate and including a plurality of sub-pixel circuits disposed in the display area; a plurality of first conductive connectors disposed on the pixel circuit layer. The plurality of first conductive connectors includes first conductive connectors disposed in the display area and first conductive connectors disposed in the non-display area; and a display element layer disposed on the plurality of first conductive connectors. The display element layer may include a plurality of light-emitting elements disposed in the display area and a plurality of dummy light-emitting elements disposed in the non-display area. The plurality of light-emitting elements are electrically connected to the sub-pixel circuits via the first conductive connectors disposed in the display area and are configured to emit light in response to a signal applied from the sub-pixel circuits. The light-emitting elements and the dummy light-emitting elements may include the same material.

[0010] In an embodiment, each of the light-emitting element and the dummy light-emitting element may include: a first semiconductor layer disposed on a first conductive connector; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; and a second conductive connector disposed on the second semiconductor layer. The first semiconductor layer, the active layer, the second semiconductor layer, and the second conductive connector may be stacked sequentially in the thickness direction of the substrate. The first conductive connector disposed in the display area may contact the light-emitting element and be connected to the sub-pixel circuit. The first conductive connector disposed in the non-display area may contact the dummy light-emitting element and be separate from the sub-pixel circuit.

[0011] In this embodiment, the non-display area may include a dummy area surrounding the display area, a cathode contact area surrounding the dummy area, a pad area spaced apart from the cathode contact area, and a dam area surrounding the pad area. The dummy light-emitting elements may include: a plurality of first dummy light-emitting elements disposed in the dummy area; a plurality of second dummy light-emitting elements disposed in the cathode contact area; a plurality of third dummy light-emitting elements disposed in the pad area; and a plurality of fourth dummy light-emitting elements disposed in the dam area. Along the thickness direction, the cross-section of the first, second, third, or fourth dummy light-emitting elements may be the same as the cross-section of the light-emitting elements disposed in the display area.

[0012] In the implementation, the fourth dummy light-emitting element can extend along the dam area in a closed-loop shape.

[0013] In an embodiment, the display element layer may further include: an insulating layer covering at least a portion of the top surface of the first conductive connector, the light-emitting element, and the dummy light-emitting element, and at least a portion of the side surface of the first conductive connector, the light-emitting element, and the dummy light-emitting element; a reflective layer disposed on the insulating layer and configured to guide light emitted from the light-emitting element in the thickness direction; a protective layer disposed on the reflective layer; and a metal mesh disposed on the protective layer in the spaces between adjacent light-emitting elements, between adjacent dummy light-emitting elements, and between any one of adjacent light-emitting elements and any one of the dummy light-emitting elements. A portion of the top surface of the protective layer may not be covered by the metal mesh.

[0014] In an embodiment, the insulating layer, reflective layer, and protective layer may include: a plurality of first contact holes extending to at least a portion of the top surface of the light-emitting element, and a trench extending to a portion of the top surface of the fourth dummy light-emitting element.

[0015] In one embodiment, the display element layer may further include a cathode electrode disposed on the protective layer and the metal mesh. The cathode electrode may be electrically connected to the top surface of the light-emitting element through a first contact hole. The portion of the cathode electrode formed in the cathode contact region and the portion of the cathode electrode formed in the pad region may be separated from each other by a trench disposed in the dam region.

[0016] In one embodiment, the display element layer may further include a thin-film encapsulation layer disposed on the cathode electrode. The thin-film encapsulation layer may contact the top surface of each of the fourth dummy light-emitting elements via trenches.

[0017] In an embodiment, the insulating layer, reflective layer, and protective layer may further include: a plurality of second contact holes extending to at least a portion of the top surface of the first conductive connector contacting the second dummy light-emitting element; and a plurality of third contact holes extending to at least a portion of the top surface of the first conductive connector contacting the third dummy light-emitting element. A first end of the metal mesh disposed in the cathode contact region may be electrically connected to at least a portion of the top surface of the first conductive connector contacting the second dummy light-emitting element via the second contact holes. A second end of the metal mesh disposed in the cathode contact region may be electrically connected to the cathode electrode. A first end of the metal mesh disposed in the pad region may be electrically connected to at least a portion of the top surface of the first conductive connector contacting the third dummy light-emitting element via the third contact holes. A second end of the metal mesh disposed in the pad region may be electrically connected to the cathode electrode.

[0018] In one embodiment, the thin-film encapsulation layer may include a fourth contact hole extending to the top surface of the cathode electrode disposed in the pad region. The display element layer may also include pad electrodes disposed on the thin-film encapsulation layer and electrically connected to the cathode electrode through the fourth contact hole.

[0019] According to embodiments of this disclosure, a method for manufacturing a display device including a display area and a non-display area surrounding the display area includes: forming a pixel circuit layer on a first substrate in which a plurality of sub-pixel circuits are disposed; forming a first conductive material layer on the pixel circuit layer; sequentially forming a first semiconductor material layer, an active material layer, and a second semiconductor material layer on a second substrate; bonding the first conductive material layer and the second semiconductor material layer to make them contact each other; and separating the second substrate from the first semiconductor material layer; forming a second conductive material layer on the first semiconductor material layer; and forming a plurality of light-emitting elements disposed in the display area and a plurality of dummy light-emitting elements disposed in the non-display area by removing portions of the second conductive material layer, the first semiconductor material layer, the active material layer, and the second semiconductor material layer.

[0020] In an embodiment, the method may further include forming a first insulating material layer on the first conductive material layer, the light-emitting element, and the dummy light-emitting element.

[0021] In an embodiment, the method may further include: removing portions of the first insulating material layer and the first conductive material layer, wherein portions of the top surface of the pixel circuit layer and the side surface of the first conductive material layer may be exposed; forming a second insulating material layer on the first insulating material layer, the exposed side surface of the first conductive material layer, and the exposed portion of the top surface of the pixel circuit layer; forming a reflective material layer on the second insulating material layer; and forming a protective material layer on the reflective material layer.

[0022] In one embodiment, the method may further include: forming a third conductive material layer on the protective material layer; and planarizing the third conductive material layer. A portion of the protective material layer may be exposed by planarizing the third conductive material layer.

[0023] In an embodiment, the method may further include: forming a plurality of first contact holes by removing portions of a protective material layer, a reflective material layer, a second insulating material layer, and a first insulating material layer, wherein at least a portion of the top surface of a second conductive material layer disposed in the display area can be exposed through the first contact holes; and forming a fourth conductive material layer on the protective material layer and the third conductive material layer, wherein the fourth conductive material layer can be electrically connected to the second conductive material layer disposed in the display area through the first contact holes.

[0024] In an embodiment, the method may further include: forming a thin film encapsulation material layer on a fourth conductive material layer; and disposing of a plurality of lenses on the portion of the thin film encapsulation material layer that overlaps with the light-emitting element in the thickness direction of the first substrate.

[0025] In an embodiment, the method may further include: forming a fourth conductive material layer on the exposed portion of the protective material layer and on the third conductive material layer; and forming a thin film encapsulation material layer on the fourth conductive material layer.

[0026] In an embodiment, the method may further include: forming a second insulating material layer on a first insulating material layer; forming a reflective material layer on the second insulating material layer; and forming a protective material layer on the reflective material layer.

[0027] In an embodiment, the method may further include: forming a plurality of second contact holes by removing portions of a protective material layer, a reflective material layer, a second insulating material layer, and a first insulating material layer, wherein a portion of the top surface of the first conductive material layer disposed in the non-display area can be exposed through the second contact holes; forming a third conductive material layer on the exposed portions of the top surface of the protective material layer and the first conductive material layer disposed in the non-display area, wherein the third conductive material layer is electrically connected to the first conductive material layer through the second contact holes; and forming a metal mesh by planarizing the third conductive material layer, wherein a portion of the protective material layer can be exposed by planarizing the third conductive material layer.

[0028] In an embodiment, the method may further include: forming a fourth conductive material layer on the protective material layer and the metal mesh; and forming a thin film encapsulation material layer on the fourth conductive material layer.

[0029] In an embodiment, the method may further include: forming a third contact hole by removing a portion of a thin-film encapsulation material layer, wherein a portion of the top surface of a fourth conductive material layer disposed in a non-display area can be exposed through the third contact hole; and forming a fifth conductive material layer on the exposed portion of the fourth conductive material layer disposed in the non-display area, wherein the fifth conductive material layer can be electrically connected to the fourth conductive material layer through the third contact hole.

[0030] In an embodiment, the method may further include: forming a fourth conductive material layer on the exposed portion of the protective material layer and on the third conductive material layer; forming a fourth contact hole by removing portions of the fourth conductive material layer, the protective material layer, the reflective material layer, the second insulating material layer, and the first insulating material layer, wherein the top surface of the second conductive material layer disposed in the non-display area can be exposed through the fourth contact hole; and forming a thin film encapsulation material layer on the top surface of the second conductive material layer exposed through the fourth contact hole and on the side surfaces of the first insulating material layer, the second insulating layer, the reflective material layer, the protective material layer, and the fourth conductive material layer facing the fourth contact hole.

[0031] The technical solutions disclosed herein may not be limited to the above content, and other technical solutions disclosed herein will be clearly understood by those skilled in the art from the following disclosure and accompanying drawings. Attached Figure Description

[0032] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0033] Figure 2 It is shown Figure 1 A block diagram of an implementation of any of the sub-pixels.

[0034] Figure 3 It is shown Figure 1 A cross-sectional view of an embodiment of the display panel.

[0035] Figure 4 It is shown Figure 1 A cross-sectional view of an embodiment of the display panel.

[0036] Figure 5 It is shown Figure 1 A plan view of an embodiment of the display panel.

[0037] Figure 6 It is along Figure 5 A sectional view taken from lines A-A' and B-B'.

[0038] Figure 7 It is shown Figure 5 A magnified plan view of region C.

[0039] Figure 8 This is a cross-sectional view of a display panel showing the steps of forming a pixel circuit layer on a substrate and forming a first conductive connector on the pixel circuit layer.

[0040] Figure 9 This is a cross-sectional view of a display panel during the steps of forming a first semiconductor material layer, an active material layer, and a second semiconductor material layer on a second substrate.

[0041] Figure 10 This is a cross-sectional view of a display panel during the steps of bonding a first conductive material layer and a second semiconductor material layer into contact with each other and separating a second substrate from the first semiconductor material layer.

[0042] Figure 11 This is a cross-sectional view of a display panel during the step of forming a second conductive material layer on a second semiconductor material layer.

[0043] Figure 12 This is a cross-sectional view of a display panel showing the steps of forming multiple light-emitting elements in the display area and forming multiple dummy light-emitting elements in the non-display area by removing portions of the second conductive material layer, the second semiconductor material layer, the active material layer and the first semiconductor material layer.

[0044] Figure 13 This is a cross-sectional view of a display panel showing the step of forming a first insulating material layer on a first conductive material layer, a light-emitting element, and a dummy light-emitting element.

[0045] Figure 14 This is a cross-sectional view of the display panel during the step of removing portions of the first insulating material layer and the first conductive material layer.

[0046] Figure 15 It is a cross-sectional view of a display panel showing the steps of forming a second insulating material layer on a portion of the exposed side surface of the first insulating material layer and the first conductive connector, and on a portion of the top surface of the pixel circuit layer, and forming a reflective material layer and a protective material layer on the second insulating material layer.

[0047] Figure 16 This is a cross-sectional view of a display panel during the step of forming a first contact hole by removing portions of a protective material layer, a reflective material layer, a second insulating material layer, and a first insulating material layer.

[0048] Figure 17This is a cross-sectional view of a display panel during the step of forming a third conductive material layer on the top surface of the protective material layer and the first conductive connector, exposed through the first contact hole.

[0049] Figure 18 This is a cross-sectional view of the display panel showing a portion of the steps in planarizing the third conductive material layer and exposing the protective material layer.

[0050] Figure 19 This is a cross-sectional view of a display panel in the step of forming a plurality of second contact holes by removing portions of a protective material layer, a reflective material layer, a second insulating material layer, and a first insulating material layer.

[0051] Figure 20 This is a cross-sectional view of a display panel during the step of forming a fourth conductive material layer on a second conductive connector that serves as a protective material layer and a light-emitting element.

[0052] Figure 21 This is a cross-sectional view of a display panel in the process of forming multiple third contact holes by removing portions of the fourth conductive material layer, the protective material layer, the reflective material layer, the second insulating material layer, and the first insulating material layer.

[0053] Figure 22 This is a cross-sectional view showing the steps of forming a thin film encapsulation material layer on the second conductive connector of the cathode electrode and the fourth dummy light-emitting element.

[0054] Figure 23 This is a cross-sectional view of a display panel during the step of forming a lens array on a light-emitting element.

[0055] Figure 24 This is a cross-sectional view of the display panel during the step of forming the fourth contact hole by removing a portion of the thin-film encapsulation material layer.

[0056] Figure 25 This is a cross-sectional view of a display panel showing the step of forming a pad electrode on a cathode electrode located in the pad area.

[0057] Figure 26 This is a block diagram illustrating an implementation of the display system.

[0058] Figure 27 It is shown Figure 26 A 3D diagram illustrating an application example of the display system.

[0059] Figure 28 It is shown Figure 27 The image shows a head-mounted display device worn by the user. Detailed Implementation

[0060] In the following description, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this description, only the parts necessary for understanding operation according to the present disclosure will be described, and descriptions of other parts will be omitted to avoid obscuring the essential points of the disclosure. Therefore, the present disclosure is not limited to the embodiments set forth herein, but may be implemented in other ways. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the technical spirit of the present disclosure to those skilled in the art.

[0061] It will be understood that when an element is referred to as being “connected” to or “attached” to another element, the element may be directly connected to the other element, or may be directly linked to the other element, or there may be an intervening element between them. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. For example, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, when an element is referred to as “comprising” or “including” a component, another component is not excluded, but other components may be included, unless the context clearly indicates otherwise. “At least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ). As used herein, the term “and / or” can include any and all combinations of one or more of the associated listed items.

[0062] Here, the terms “first,” “second,” etc., may be used herein to describe various types of elements and to distinguish these elements from others. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0063] Spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “high,” and “side” (e.g., as in “sidewall”) may be used herein for descriptive purposes and thereby describe the relationship of one element or feature as shown in the accompanying drawings to another element (or other) element or feature. In addition to the orientations depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped upside down, an element described as “below” or “under” other elements or features would then be oriented “above” other elements or features. Thus, the term “below” can include both above and below orientations. Furthermore, the device may be oriented in other directions (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0064] Various embodiments will be described with reference to the accompanying drawings, which illustrate idealized embodiments. Therefore, variations in the shape of the figures should be expected due to factors such as manufacturing techniques and / or tolerances. Consequently, the embodiments disclosed herein should not be construed as limited to the shape of the specifically shown areas, but should include deviations in shape, for example, due to manufacturing processes. Therefore, the shapes shown in the drawings may not represent the actual shape of areas of the device, and are therefore not intended to be limiting.

[0065] Figure 1 This is a block diagram illustrating a display device DD according to an embodiment of the present disclosure.

[0066] refer to Figure 1 The display device DD may include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0067] The display panel DP may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. In addition, sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn.

[0068] Subpixels (SPs) can produce two or more colors of light. For example, each subpixel SP can produce light in colors such as red, green, blue, cyan, magenta, or yellow.

[0069] Two or more subpixels in subpixel SP can form a pixel PXL. For example, as Figure 1 As shown, pixel PXL may include four sub-pixels SP. However, the implementation is not limited to the example mentioned above. In another example, pixel PXL may include two sub-pixels SP. Therefore, pixel PXL can emit light of various colors and brightnesses based on the combination of light emitted from the sub-pixels SP included therein.

[0070] Gate driver 120 can be connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output gate signals to first gate lines GL1 to m-th gate lines GLm in response to a gate control signal GCS received from controller 150. In an embodiment, gate control signal GCS may include a start signal indicating the start of a frame for each of the sub-pixels SP and a horizontal synchronization signal, etc.

[0071] The gate driver 120 may be disposed on one side of the display panel DP. However, the implementation is not limited to the examples mentioned above. For example, the gate driver 120 may be divided into two or more drivers that are physically and / or logically separated from each other. The drivers may be disposed on a first side of the display panel DP and a second side of the display panel DP opposite to the first side. According to the implementation, the gate driver 120 may be disposed around the display panel DP in various forms and positions.

[0072] The data driver 130 can be connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. The data driver 130 can receive image data DATA and data control signals DCS from the controller 150. The data driver 130 can operate in response to the data control signals DCS. In an embodiment, the data control signals DCS may include a source start signal, a source shift clock signal, a source output enable signal, etc.

[0073] The data driver 130 can receive voltage from the voltage generator 140. The data driver 130 can use the received voltage to apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 through the nth data line DLn. When a gate signal is applied to each of the first gate lines GL1 through the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the first data lines DL1 through the nth data line DLn. Therefore, the sub-pixel SP can generate light corresponding to the data signal, allowing the display panel DP to display the image.

[0074] In one embodiment, the gate driver 120 and the data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0075] Voltage generator 140 can operate in response to a voltage control signal VCS provided from controller 150. Voltage generator 140 is configured to generate multiple voltages and supply the generated voltages to components of display device DD, such as gate driver 120, data driver 130, and controller 150. Voltage generator 140 can receive input voltages from external devices of display device DD and generate multiple voltages by adjusting the received voltages.

[0076] Voltage generator 140 can generate a first power supply voltage and a second power supply voltage. The generated first and second power supply voltages can be supplied to the sub-pixel SP via power line PL. In another example, at least one of the first and second power supply voltages can be supplied to the display device DD from an external device.

[0077] Furthermore, voltage generator 140 can provide various voltages and / or signals. For example, voltage generator 140 can provide one or more initialization voltages to be applied to the sub-pixel SP. For example, during sensing operations for sensing the electrical characteristics of the sub-pixel SP and / or transistors electrically connected to the sub-pixel SP, a specific reference voltage can be applied to each of the first data lines DL1 to the nth data lines DLn. Voltage generator 140 can generate a reference voltage and transmit the reference voltage to data driver 130.

[0078] In another example, during display operations for displaying an image on the display panel DP, a common pixel control signal can be applied to the sub-pixel SP, and a voltage generator 140 can generate a pixel control signal. In an implementation, the voltage generator 140 can provide the pixel control signal to the sub-pixel SP via the pixel control line PXCL. Although Figure 1 The diagram shows a pixel control line PXCL connected between the voltage generator 140 and the display panel DP, but the implementation is not limited to this. For example, the pixel control line PXCL can be connected between the gate driver 120 and the display panel DP. In this case, pixel control signals can be transmitted from the gate driver 120 to the sub-pixels SP via the pixel control line PXCL.

[0079] The controller 150 can control all operations of the display device DD. The controller 150 can receive input image data IMG and control signal CTRL from an external device. In response to the control signal CTRL, the controller 150 can provide a gate control signal GCS to the gate driver 120, a data control signal DCS to the data driver 130, and a voltage control signal VCS to the voltage generator 140.

[0080] The controller 150 can convert the input image data IMG into a format suitable for a display device DD or a display panel DP and output image data DATA. In one embodiment, the controller 150 can align the input image data IMG line by line to fit the sub-pixels SP, and then output the image data DATA.

[0081] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted into a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 may be functionally separate components within a single driver integrated circuit (DIC). However, the implementation is not limited to this, and at least one of the data driver 130, voltage generator 140, and controller 150 may be configured as a component separate from the driver integrated circuit (DIC).

[0082] Figure 2 It is shown Figure 1 A block diagram of an implementation of any of the sub-pixels SP.

[0083] exist Figure 2 In, it is shown Figure 1 The sub-pixel SPij in the sub-pixel SP is set in the i-th row (where i is an integer equal to or greater than 1 and less than or equal to m) and the j-th column (where j is an integer equal to or greater than 1 and less than or equal to n).

[0084] refer to Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0085] The light-emitting element (LD) can be connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. The first power supply voltage node VDDN can be connected to... Figure 1 One of the power lines PL shown is used to receive the first power supply voltage. The second power supply voltage node VSSN can be connected to... Figure 1 Another power line PL shown is used to receive the second power supply voltage. Here, the first power supply voltage may have a higher voltage level than the second power supply voltage.

[0086] The light-emitting element (LD) can be connected between the anode electrode AE ​​and the cathode electrode CE. The anode electrode AE ​​can be connected to a first power supply voltage node VDDN via a sub-pixel circuit SPC. For example, the anode electrode AE ​​can be connected to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC. The cathode electrode CE can be connected to a second power supply voltage node VSSN. The light-emitting element LD can be configured to emit light based on the current flowing from the anode electrode AE ​​to the cathode electrode CE.

[0087] Sub-pixel circuits (SPCs) can be connected to Figure 1 The i-th gate line GL1 to the m-th gate line GLm and Figure 1 The first data line DL1 to the nth data line DLn, specifically the j-th data line DLj. In response to the gate signal received via the i-th gate line GL1, the sub-pixel circuit SPC can control the light-emitting element LD to emit light based on the data signal received via the j-th data line DLj. In an embodiment, the sub-pixel circuit SPC can also be connected to... Figure 1 The pixel control line PXCL. In this case, the sub-pixel circuit SPC can also control the light-emitting element LD in response to the pixel control signal received through the pixel control line PXCL.

[0088] For the operations mentioned above, the sub-pixel circuit SPC may include circuit elements (e.g., transistors and one or more capacitors).

[0089] The transistors in the sub-pixel circuit SPC may include P-type transistors and / or N-type transistors. In some embodiments, the transistors in the sub-pixel circuit SPC may include metal-oxide-semiconductor field-effect transistors (MOSFETs). In other embodiments, the transistors in the sub-pixel circuit SPC may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, etc.

[0090] Figure 3 It is shown Figure 1 A cross-sectional view of an embodiment of the display panel.

[0091] refer to Figure 3 According to the embodiment, the display panel DP may include a substrate SUB and a pixel circuit layer PCL, a display element layer DPL, an optical functional layer OFL, an outer coating OCL, and a cover window CW, which are sequentially stacked on the substrate SUB on a third direction DR3 intersecting the first direction DR1 and the second direction DR2.

[0092] The substrate SUB can be made of an insulating material such as glass or resin. For example, the substrate SUB may include a glass substrate or a polyimide substrate, or it may include a silicon wafer substrate formed by semiconductor processes.

[0093] In embodiments, the substrate SUB can be made of a flexible material to be bent or foldable, and has a single-layer or multi-layer structure. For example, the flexible material may include at least one of the following: polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, embodiments are not limited to the examples mentioned above.

[0094] The pixel circuit layer (PCL) can be disposed on the substrate (SUB). The PCL may include an insulating layer and semiconductor and conductive patterns disposed between the insulating layer (e.g., ...). Figure 6 (CVW, WR1, WR2, and WR3). The conductive patterns of the pixel circuit layer PCL can be used as circuit elements, lines, etc.

[0095] The circuit elements of the pixel circuit layer PCL may include those for Figure 1 The corresponding sub-pixel circuit SPC (reference) for each of the sub-pixels SP Figure 2 In other words, the circuit elements of the pixel circuit layer PCL may include transistors of the sub-pixel circuit SPC and one or more capacitors.

[0096] The lines of the pixel circuit layer (PCL) may include lines connected to each of the sub-pixels (SP). The lines of the pixel circuit layer (PCL) may also include various signal lines and / or voltage lines required to drive the display element layer (DPL).

[0097] The display element layer (DPL) can be set on the pixel circuit layer (PCL). The display element layer (DPL) may include the light-emitting elements (LDs) of the sub-pixels (SPX).

[0098] The optical functional layer (OFL) can be disposed on the display element layer (DPL). The optical functional layer (OFL) may include a color filter layer (not shown) and a lens array (see reference). Figure 6 (LA in the middle).

[0099] A color filter layer can be disposed between the display element layer (DPL) and the lens array (LA). The color filter layer can be configured to selectively output light within a wavelength range corresponding to each sub-pixel (SP) or light of a color corresponding to each sub-pixel (SP) by filtering light emitted from the light-emitting element (LD). The color filter layer may include color filters (not shown) respectively corresponding to each sub-pixel (SP). Each of the color filters allows light within the wavelength range corresponding to the associated sub-pixel (SP) to pass through.

[0100] For example, a color filter corresponding to any one sub-pixel SP allows red light to pass through, a color filter corresponding to another sub-pixel SP allows green light to pass through, and a color filter corresponding to yet another sub-pixel SP allows blue light to pass through. Depending on the light emitted from the light-emitting element LD of each sub-pixel SP, at least some of the color filters can be omitted.

[0101] The lens array LA can be disposed on the color filter layer. The lens array LA may include lenses corresponding to sub-pixels SP (see reference). Figure 6 (LS1 and LS2 in the image). Each of lenses LS1 and LS2 can output light emitted from the light-emitting element LD and guide the light emitted from the light-emitting element LD along a desired path, thus enhancing light output efficiency.

[0102] The lens array LA can have a relatively high refractive index. For example, the lens array LA can have a higher refractive index than the outer coating OCL. In embodiments, lenses LS1 and LS2 can comprise organic or acrylic materials. However, the materials constituting lenses LS1 and LS2 are not limited to the examples described above.

[0103] The outer coating layer (OCL) can be disposed on the optical functional layer (OFL). In other words, the outer coating layer (OCL) can cover the optical functional layer (OFL), the display element layer (DPL), and the pixel circuit layer (PCL). The outer coating layer (OCL) can include various materials suitable for protecting the underlying layers from foreign matter such as dust and water. For example, the outer coating layer (OCL) can include at least one of inorganic and organic insulating layers. For example, the outer coating layer (OCL) can include epoxy resin, but the implementation is not limited thereto. The outer coating layer (OCL) can have a lower refractive index than the lens array (LA).

[0104] A cover window (CW) may be disposed on the outer coating (OCL). The cover window (CW) protects the underlying layer. The cover window (CW) may have a higher refractive index than the outer coating (OCL). The cover window (CW) may include glass, but the implementation is not limited thereto. For example, the cover window (CW) may be an encapsulating glass layer configured to protect components disposed beneath it. In other embodiments, the cover window (CW) may be omitted.

[0105] Figure 4 It is shown Figure 1 A cross-sectional view of an embodiment of the display panel.

[0106] refer to Figure 4 According to the embodiment, the display panel DP' may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, an input sensing layer ISL, an optical functional layer OFL, an outer coating OCL, and a cover window CW. The substrate SUB, pixel circuit layer PCL, display element layer DPL, optical functional layer OFL, outer coating OCL, and cover window CW can each be respectively aligned with a reference... Figure 3 The substrate (SUB), pixel circuit layer (PCL), display element layer (DPL), optical functional layer (OFL), outer coating layer (OCL), and cover window (CW) are configured in the same manner. Redundant descriptions will be omitted below.

[0107] The input sensing layer (ISL) can sense user input on the top surface (or display surface) of the display panel (DP'). The input sensing layer (ISL) may include components adapted to sense external objects such as the user's hand or a pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0108] Figure 5 It is shown Figure 1 A plan view showing the detailed components of the display panel. Figure 6 It is along Figure 5 A sectional view taken from lines A-A' and B-B'. Figure 7 It is shown Figure 5 A magnified plan view of region C.

[0109] exist Figures 5 to 7In this disclosure, the display device DD according to the embodiments of the present disclosure is mainly described as a micro-light-emitting diode display device (or micro-LED display device) that includes a micro-light-emitting diode (or micro-LD) as a light-emitting element LD. However, the embodiments of the present disclosure are not limited to the above examples.

[0110] In addition, Figures 5 to 7 In this disclosure, the display device DD according to the embodiments of the present disclosure will be mainly described as a silicon-on-a-light-emitting diode (LEDoS) device, in which the light-emitting diode is disposed on a semiconductor circuit substrate formed by semiconductor processes. However, the embodiments of the present disclosure are not limited thereto.

[0111] In embodiments, the display device DD can be applied to wearable devices including watches, smart glasses, electronic devices in automotive applications, and various electronic devices such as tablet PCs, televisions, smartphones, and laptop computers, but is not limited thereto. In embodiments, the display device DD can also be applied to transparent display devices configured to allow light emission.

[0112] In the following text, Figures 5 to 7 In this diagram, the first direction DR1 refers to the horizontal direction of the display panel DP, the second direction DR2 refers to the vertical direction of the display panel DP, and the third direction DR3 refers to the thickness direction of the display panel DP. In this context, "left," "right," "up," and "down" can refer to the directions when the display panel DP is viewed in a plan view. For example, the term "right side" can refer to one side in the first direction DR1, while the term "left side" can refer to the other side in the first direction DR1. Similarly, the term "upper side" can refer to one side in the second direction DR2, while the term "lower side" can refer to the other side in the second direction DR2. Furthermore, the term "top" refers to one side in the third direction DR3, and the term "bottom" refers to the other side in the third direction DR3.

[0113] refer to Figure 5 The display device DD according to the embodiments of the present disclosure may include a display panel DP, which includes a display area AA (or effective area) and a non-display area NAA (or non-effective area).

[0114] The display panel DP can have a rectangular planar shape with sides extending in the first direction DR1 and the second direction DR2. Here, the planar shape of the display panel DP is not limited to the examples mentioned above, and can have other polygonal shapes, circular shapes, elliptical shapes or amorphous shapes other than rectangular shapes.

[0115] In this embodiment, the display panel DP may have a planar display surface or a display surface that is at least partially rounded. In this embodiment, the display panel DP may be flexible, foldable, or rollable. In this case, the display panel DP and / or the substrate SUB of the display panel DP may include a material with flexible properties.

[0116] The display area AA can be an area for displaying images, and the non-display area NAA can be an area for not displaying images. The planar shape of the display area AA can follow the planar shape of the display panel DP. In an embodiment, the display area AA can be located in the central area of ​​the display panel DP, but this disclosure is not limited thereto. For example, depending on the intended function of the display device DD, the display area AA can be located in any area of ​​the display panel DP.

[0117] In this implementation, the display area AA can have various shapes. The display area AA can have a closed-loop shape including linear edges and / or curved edges. For example, the display area AA can have shapes such as polygons, circles, semicircles, and ellipses.

[0118] The display area AA of the display panel DP includes multiple subpixels SP. Subpixels SP can be divided into a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. In the following text, when referring to at least one of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, or when referring to two or more types of subpixels SP together, the term "subpixel SP" or "multiple subpixels SP" will be used.

[0119] although Figure 5 The illustration shows each pixel PXL comprising a first sub-pixel SP1, a second sub-pixel SP2, and two third sub-pixels SP3, but embodiments of this disclosure are not limited thereto. In the following description, for ease of description, it is assumed that each pixel PXL comprises a first sub-pixel SP1, a second sub-pixel SP2, and two third sub-pixels SP3 as shown in the accompanying drawings. Furthermore, although each of the first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3 has a circular planar shape, embodiments of this disclosure are not limited thereto.

[0120] Subpixels SP can be in the form of stripes or The arrangement structure is regularly arranged in the first direction DR1 and the second direction DR2. The arrangement structure of the sub-pixels SP is not limited to this, and the sub-pixels SP can be arranged in various structures and / or schemes in the display area AA.

[0121] For example, sub-pixels SP can be arranged in a zigzag pattern in the display area AA along the first direction DR1 and the second direction DR2. Specifically, in a pixel PXL, the first sub-pixel SP1 and the second sub-pixel SP2 can be arranged parallel to each other along the first direction DR1, and two third sub-pixels SP3 can be spaced apart from each other along the second direction DR2 and arranged in the space between the first sub-pixel SP1 and the second sub-pixel SP2.

[0122] For example, in Figure 5 In this embodiment, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are arranged in a diamond shape within a single pixel PXL, but the implementation is not limited to this. The arrangement of the sub-pixels SP can vary depending on the implementation method.

[0123] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can produce light of one of various colors, such as red, green, blue, cyan, magenta, and yellow. In the following description, for clarity and brevity, it is assumed that the first sub-pixel SP1 is configured to produce red light, the second sub-pixel SP2 is configured to produce blue light, and the third sub-pixel SP3 is configured to produce green light.

[0124] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include at least one light-emitting element (LD) configured to generate light. In one embodiment, the light-emitting elements (LDs) of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of the same color. For example, the light-emitting elements (LDs) of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate blue light. In another embodiment, the light-emitting elements (LDs) of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of different colors. For example, the light-emitting elements (LDs) of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate red, green, and blue light, respectively.

[0125] The non-display area NAA can be configured to surround the outer portion of the display area AA. Components for controlling sub-pixels SP can be located within the non-display area NAA. Lines connected to the sub-pixels SP (e.g., Figure 1 The first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL can be set in the non-display area NAA.

[0126] Figure 1At least one of the gate driver 120, data driver 130, voltage generator 140, and controller 150 can be disposed in the non-display area (NAA). In an embodiment, the gate driver 120 can be disposed in the NAA. In this case, the data driver 130, voltage generator 140, and controller 150 can be implemented as follows: Figure 1 The driver integrated circuit (DIC) is separate from the display panel (DP). The driver integrated circuit (DIC) can be connected to the pad area (PAD) located in the non-display area (NAA). In an embodiment, the gate driver 120, as well as the data driver 130, voltage generator 140, and controller 150, can be implemented as a single integrated circuit (IC) separate from the display panel (DP).

[0127] Specifically, the non-display area NAA may include the dummy area DA, the cathode contact area CCA, the pad area PAD, the dam area DAM, and the peripheral area PA.

[0128] A dummy region DA can be formed outside and around the display region AA. A plurality of first dummy light-emitting elements DLD1 can be disposed within the dummy region DA. Specifically, the first dummy light-emitting elements DLD1 can be arranged in the entire area of ​​the dummy region DA in the same pattern as the sub-pixels SP arranged in the display region AA. Furthermore, the first dummy light-emitting elements DLD1 can comprise substantially the same material as the light-emitting elements LD.

[0129] Because of the structure in which the dummy region DA, including the first dummy light-emitting element DLD1, surrounds the display region AA, the process uniformity of the display region AA can be improved.

[0130] A cathode contact region (CCA) can be formed outside and around a dummy region (DA). Multiple second dummy light-emitting elements (DLD2) can be disposed within the cathode contact region (CCA). Specifically, the second dummy light-emitting elements (DLD2) can be arranged in the entire area of ​​the cathode contact region (CCA) with the same pattern as the sub-pixels (SP) disposed in the display region (AA). For example, the light-emitting element (LD) disposed in the display region (AA), the first dummy light-emitting element (DLD1) disposed in the dummy region (DA), and the second dummy light-emitting elements (DLD2) disposed in the cathode contact region (CCA) can be arranged in the same pattern on the display panel (DP). Furthermore, the second dummy light-emitting elements (DLD2) can comprise substantially the same material as the light-emitting element (LD) and the first dummy light-emitting element (DLD1).

[0131] The cathode contact area (CCA) can be connected via conductive connection components (e.g., formed in the pixel circuit layer PCL). Figure 6The second connection line WR2, the third connection line WR3, and the common voltage line CVW are electrically connected to the pad area PAD to transmit the common voltage signal applied through the pad area PAD to the dummy area DA and the display area AA. (Refer to...) Figure 6 The mechanism by which the common voltage signal is applied through the pad area PAD and transmitted to the display area AA via the cathode contact area CCA and the dummy area DA, as well as the resulting actions and effects, are described in more detail.

[0132] The pad area PAD can be spaced apart from the cathode contact area CCA by a certain distance d. The pad area PAD can be disposed on one side of the display panel DP, so as to be spaced apart from some areas defined by the display area AA, the dummy area DA, and the cathode contact area CCA on the display panel DP. A plurality of third dummy light-emitting elements DLD3 can be disposed in the pad area PAD. Specifically, the third dummy light-emitting elements DLD3 can be arranged in the entire area of ​​the pad area PAD with the same pattern as the sub-pixels SP disposed in the display area AA. For example, the light-emitting element LD disposed in the display area AA, the first dummy light-emitting element DLD1 disposed in the dummy area DA, the second dummy light-emitting element DLD2 disposed in the cathode contact area CCA, and the third dummy light-emitting element DLD3 disposed in the pad area PAD can be arranged in the same pattern on the display panel DP. In addition, the third dummy light-emitting element DLD3 can include substantially the same material as the light-emitting element LD, the first dummy light-emitting element DLD1, and the second dummy light-emitting element DLD2.

[0133] The pad area PAD can be electrically connected to a circuit board (not shown) separate from the display panel DP to receive electrical signals from the circuit board for driving the display device DD. For example, the circuit board may include the above-mentioned reference. Figure 1 The described driver integrated circuit (DIC) and its other variations. Furthermore, the electrical signals applied to the pad area (PAD) may include those referenced above. Figure 1 The described gate control signal GCS, gate signal, data signal, pixel control signal, first power supply voltage, and / or second power supply voltage will be referenced. Figure 6 The mechanism by which electrical signals applied from the circuit board to the pad area PAD are transmitted to the display area AA via the dam area DAM, the cathode contact area CCA, and the dummy area DA, as well as the resulting actions and effects, are described in more detail.

[0134] The dam region DAM can be formed outside and around the pad region PAD. One or more fourth dummy light-emitting elements DLD4 can be disposed in the dam region DAM. Specifically, the fourth dummy light-emitting element DLD4 can extend along the dam region DAM in a closed-loop shape to surround the pad region PAD. Furthermore, the fourth dummy light-emitting element DLD4 can comprise substantially the same material as the light-emitting element LD, the first dummy light-emitting element DLD1, the second dummy light-emitting element DLD2, and the third dummy light-emitting element DLD3.

[0135] The dam region (DAM) can electrically insulate the cathode contact region (CCA) and the pad region (PAD) from each other within the display element layer (DPL). Due to the aforementioned structure, electrical signals applied to the pad region (PAD) can be transmitted to the cathode contact region (CCA) through the pixel circuit layer (PCL). (Refer to...) Figure 6 The mechanism by which electrical signals applied from the circuit board to the pad area PAD are transmitted to the display area AA via the dam area DAM, the cathode contact area CCA, and the dummy area DA, as well as the resulting actions and effects, are described in more detail.

[0136] The peripheral region PA may not correspond to any of the display areas AA, dummy areas DA, cathode contact areas CCA, pad areas PAD, and dam areas DAM on the display panel DP. Multiple fifth dummy light-emitting elements DLD5 may be disposed in the peripheral region PA. Specifically, the fifth dummy light-emitting elements DLD5 may be arranged in the entire area of ​​the peripheral region PA with the same pattern as the sub-pixels SP disposed in the display area AA. For example, the light-emitting element LD disposed in the display area AA, the first dummy light-emitting element DLD1 disposed in the dummy area DA, the second dummy light-emitting element DLD2 disposed in the cathode contact area CCA, the third dummy light-emitting element DLD3 disposed in the pad area PAD, and the fifth dummy light-emitting element DLD5 disposed in the peripheral region PA may be arranged in the same pattern on the display panel DP. Furthermore, the fifth dummy light-emitting element DLD5 may comprise substantially the same material as the light-emitting element LD, the first dummy light-emitting element DLD1, the second dummy light-emitting element DLD2, and the third dummy light-emitting element DLD3.

[0137] In the following text, the terms "dummy light-emitting element DLD" or "multiple dummy light-emitting elements DLD" will be used to arbitrarily specify at least one dummy light-emitting element of a single type, such as first dummy light-emitting element DLD1, second dummy light-emitting element DLD2, third dummy light-emitting element DLD3, fourth dummy light-emitting element DLD4, and fifth dummy light-emitting element DLD5, or to jointly specify two or more types of dummy light-emitting elements.

[0138] refer to Figure 6The display panel DP may include a substrate SUB, a pixel circuit layer PCL disposed on the substrate SUB and including a plurality of sub-pixel circuits SPC disposed in the display area AA, a plurality of first conductive connectors CC1 disposed on the pixel circuit layer PCL, and a display element layer DPL disposed on the first conductive connectors CC1.

[0139] The display element layer (DPL) may include multiple light-emitting elements (LDs) and multiple dummy light-emitting elements (DLDs). The LDs are disposed in the display area (AA) and electrically connected to the sub-pixel circuit (SPC) via some of the first conductive connectors (CC1) to emit light in response to signals applied to them from the SPC. The dummy light-emitting elements (DLDs) are disposed in the non-display area (NAA). The dummy light-emitting elements (DLDs) may contain the same material as the LDs.

[0140] The substrate (SUB), sub-pixel circuit (SPC), and display element layer (DPL) can be respectively connected to a reference. Figure 2 and Figure 3 The substrate (SUB), subpixel circuitry (SPC), and display element layer (DPL) are configured in the same manner. Redundant descriptions will be omitted below.

[0141] Each of the light-emitting element LD and the dummy light-emitting element DLD may include a first semiconductor layer SEM1 disposed on a corresponding one of the first conductive connectors CC1, an active layer MQW disposed on the first semiconductor layer SEM1, a second semiconductor layer SEM2 disposed on the active layer MQW, and a second conductive connector CC2 disposed on the second semiconductor layer SEM2.

[0142] The first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the second conductive connector CC2 that form the light-emitting element LD or the dummy light-emitting element DLD can be stacked sequentially in the thickness direction of the substrate SUB (i.e., the third direction DR3).

[0143] Some of the first conductive connectors CC1 can contact the light-emitting element LD and be connected to the sub-pixel circuit SPC. Others of the first conductive connectors CC1 can contact the dummy light-emitting element DLD and be disconnected from the sub-pixel circuit SPC.

[0144] Here, the statement that "some of the other first conductive connectors CC1 can contact the dummy light-emitting element DLD and be separate from the sub-pixel circuit SPC" can mean that the first conductive connectors CC1 located in the non-display area NAA are physically located in a different space from the sub-pixel circuit SPC located in the display area AA. This can also mean that some of the first conductive connectors CC1 located in the non-display area NAA can be connected to the sub-pixel circuit SPC via intermediate media (such as the first connecting line WR1, the second connecting line WR2, and the third connecting line WR3, as well as the common voltage line CVW). Even in this case, as will be described later, unlike the light-emitting element LD, because the dummy light-emitting element DLD is also insulated from the cathode electrode CE, even if an electrical signal is applied from the sub-pixel circuit SPC to the dummy light-emitting element DLD through the first conductive connector CC1, the dummy light-emitting element DLD cannot emit light.

[0145] Specifically, for the first conductive connector CC1 located in the dummy region DA, its top surface can contact the first dummy light-emitting element DLD1, and its bottom surface can contact the first connecting line WR1. The first connecting line WR1 can transmit various electrical signals for driving the display panel DP to other components, and in some embodiments, the first connecting line WR1 can be omitted.

[0146] Furthermore, the top surface of the first conductive connector CC1, located in the cathode contact area CCA, can contact the second dummy light-emitting element DLD2 and the metal mesh MM, and its bottom surface can contact the common voltage line CVW. The first conductive connector CC1 in the cathode contact area CCA can receive a common voltage signal from the common voltage line CVW and transmit the common voltage signal to the second dummy light-emitting element DLD2 and the metal mesh MM located in the cathode contact area CCA.

[0147] Furthermore, the top surface of the first conductive connector CC1, located in the pad area PAD, can contact the third dummy light-emitting element DLD3 and the metal mesh MM, and its bottom surface can contact the second connecting line WR2. The first conductive connector CC1, located in the pad area PAD, can receive various electrical signals for driving the display panel DP from the metal mesh MM and transmit electrical signals to the second connecting line WR2.

[0148] Specifically, the second connection line WR2 can transmit various electrical signals applied to the pad electrode PE for driving the display panel DP to the sub-pixel circuit SPC and the common voltage line CVW via other conductive connection components formed in the pixel circuit layer PCL (e.g., the first connection line WR1 and the third connection line WR3). These signals, such as anode signals or cathode signals, are used to drive the display panel DP.

[0149] Furthermore, the top surface of the first conductive connector CC1 located in the dam area DAM can contact the fourth dummy light-emitting element DLD4, and its bottom surface can contact the third connecting line WR3. The third connecting line WR3 can be electrically connected to other conductive connecting components located in the pixel circuit layer PCL to transmit various electrical signals for driving the display panel DP to other components, but in some embodiments the third connecting line WR3 can be omitted.

[0150] The first conductive connector CC1, the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the second conductive connector CC2 can be patterned across the display area AA, the dummy area DA, the cathode contact area CCA, the dam area DAM, the pad area PAD, and the peripheral area PA using the same process. The cross-section of any one of the first dummy light-emitting elements DLD1, the second dummy light-emitting element DLD2, the third dummy light-emitting element DLD3, and the fourth dummy light-emitting element DLD4, taken along the thickness direction (third direction DR3) of the substrate SUB, can have the same cross-sectional shape as any one of the light-emitting elements LD taken along the thickness direction (third direction DR3) of the substrate SUB.

[0151] The fourth dummy light-emitting element DLD4 has the same cross-sectional shape as the light-emitting element LD, the first dummy light-emitting element DLD1, the second dummy light-emitting element DLD2, and the third dummy light-emitting element DLD3. However, on the display panel DP, unlike the dotted light-emitting elements LD, DLD1, DLD2, and DLD3, the fourth dummy light-emitting element DLD4 can have a rectangular shape extending along the dam region DAM in a closed-loop shape.

[0152] The first conductive connector CC1 may include a first barrier layer BRL1, a main layer MNL, and a second barrier layer BRL2. The first barrier layer BRL1, the main layer MNL, and the second barrier layer BRL2 may be stacked sequentially on the pixel circuit layer PCL in the thickness direction (third direction DR3) of the display panel DP.

[0153] The main layer MNL can be formed from an alloy of a first metallic material and a second metallic material having a melting point lower than that of the first metallic material. In other words, the main layer MNL can be formed from an IMC alloy, provided by a process of infiltrating a second metallic material with a relatively low melting point into a molten first metallic material. For example, any one of gold (Au), silver (Ag), and copper (Cu) can be selected as the first metallic material with a relatively high melting point. A metal with a melting point lower than that of the first metallic material can be selected as the second metallic material. For example, tin (Sn) can be selected as the second metallic material. In other words, the main layer MNL can be formed from an IMC alloy corresponding to any one of AuSn, AgSn, and CuSn.

[0154] Each of the first barrier layer BRL1 and the second barrier layer BRL2 can be formed of a material capable of preventing diffusion of the main layer MNL. For example, titanium (Ti) can be selected as the material for each of the first barrier layer BRL1 and the second barrier layer BRL2.

[0155] The first conductive connector CC1 can be used as a connection electrode or anode electrode configured to apply an emission signal to the light-emitting element LD. The first conductive connector CC1 can be an ohmic connection electrode, but is not limited to this, and in some examples it can be a Schottky connection electrode.

[0156] The first semiconductor layer SEM1 can be disposed on any one of the first conductive connectors CC1. The first semiconductor layer SEM1 can be a P-type semiconductor and can include a semiconductor with Al. x GayIn 1-x-y Semiconductor materials with the chemical formula N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the semiconductor material may include one or more of P-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The first semiconductor layer SEM1 may be doped with a P-type dopant. The P-type dopant may be Mg, Zn, Ca, Ba, etc. For example, the first semiconductor layer SEM1 may include P-GaN doped with P-type Mg.

[0157] The active layer MQW can be disposed on the first semiconductor layer SEM1. The active layer MQW can emit light in response to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2 via the recombination of electron-hole pairs. The active layer MQW can emit light from any of the blue, green, and red wavelength bands.

[0158] The active layer MQW can include materials having a single quantum well structure or a multiple quantum well structure. When the active layer MQW includes a material having a multiple quantum well structure, the active layer MQW can have a structure formed by alternately stacking multiple well layers and multiple barrier layers. Here, although the well layers can be formed of InGaN and the barrier layers can be formed of GaN or AlGaN, this disclosure is not limited thereto.

[0159] In another example, the active layer MQW can have a structure formed by alternately stacking semiconductor materials with large bandgap energies and semiconductor materials with small bandgap energies, and can include group III to group V semiconductor materials depending on the wavelength band of the light to be emitted. In an embodiment, when indium (In) is included in the active layer MQW, the color of the emitted light can vary depending on the indium content. For example, if the indium content is in the range of about 10% to about 15%, light in the blue wavelength band can be emitted. If the indium content is in the range of about 20% to about 25%, light in the green wavelength band can be emitted. If the indium content is in the range of about 30% to about 45%, light in the red wavelength band can be emitted.

[0160] Although not shown in the accompanying drawings, an electron blocking layer (EBL) can be interposed between the first semiconductor layer SEM1 and the active layer MQW. The EBL can be a layer configured to mitigate or prevent excessive electron inflow into the active layer MQW. For example, the EBL can comprise p-AlGaN doped with p-type magnesium (Mg). Figure 6 As shown, EBL can be omitted.

[0161] The second semiconductor layer SEM2 can be disposed on the active layer MQW. The second semiconductor layer SEM2 can be formed of an N-type semiconductor. The second semiconductor layer SEM2 may include materials with Al... x Ga y In 1-x-y Semiconductor materials with the chemical formula N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer SEM2 may include any one or more of N-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN.

[0162] The second semiconductor layer, SEM2, can be doped with an N-type dopant. The N-type dopant can be silicon (Si), germanium (Ge), tin (Sn), etc. For example, the second semiconductor layer, SEM2, can be N-GaN doped with N-type Si. The second semiconductor layer, SEM2, can transmit the common voltage signal applied through the cathode electrode, CE, to the light-emitting element, LD.

[0163] Although not shown in the accompanying drawings, a superlattice layer (SLT) can be interposed between the active layer MQW and the second semiconductor layer SEM2. The SLT can alleviate stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the SLT can include InGaN or GaN. Figure 6 As shown, SLT can also be omitted in the same way as EBL.

[0164] The second conductive connector CC2 can be disposed on the second semiconductor layer SEM2. The second conductive connector CC2 can be formed of a substantially transparent or semi-transparent conductive material to meet specific light transmittance requirements. The second conductive connector CC2 can be a common layer formed on all light-emitting elements LD. The second conductive connector CC2 can be a cathode electrode. In embodiments, the second conductive connector CC2 can be formed of various transparent conductive oxides (TCOs) such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO), or semi-transparent conductive materials such as magnesium (Mg), silver (Ag), or alloys of magnesium (Mg) and silver (Ag). When the second conductive connector CC2 is formed of a semi-transparent conductive material, the light output efficiency can be enhanced through a microcavity. Here, the material of the second conductive connector CC2 is not limited to these.

[0165] The following section will describe in more detail the arrangement of the display panel DP on the light-emitting element LD and the dummy light-emitting element DLD, and other components.

[0166] The display element layer (DPL) may also include an insulating layer (INS), a reflective layer (RFM), a protective layer (PTL), a metal mesh (MM), a cathode electrode (CE), and a thin-film encapsulation layer (TFE). As described in detail below, the insulating layer (INS), reflective layer (RFM), protective layer (PTL), metal mesh (MM), cathode electrode (CE), and thin-film encapsulation layer (TFE) may be formed across the entire surface of the display panel (DP), including the display area (AA), dummy area (DA), cathode contact area (CCA), dam area (DAM), pad area (PAD), and peripheral area (PA), and are not limited to one or more specific areas of the display panel (DP). However, it should be noted that certain components may have shapes achieved by etching and removing portions of specific areas.

[0167] The insulating layer INS can cover at least a portion of the side surfaces of the first conductive connector CC1, the light-emitting element LD, and the dummy light-emitting element DLD, as well as at least a portion of the top surfaces of the first conductive connector CC1, the light-emitting element LD, and the dummy light-emitting element DLD. The insulating layer INS can protect the components disposed under the insulating layer INS (such as the first conductive connector CC1, the light-emitting element LD, and the dummy light-emitting elements DLD1, DLD2, DLD3, and DLD4) from the influence of external water, moisture, etc. Specifically, the insulating layer INS can include a first insulating layer INS1 and a second insulating layer INS2.

[0168] The first insulating layer INS1 may cover a portion of the top surface of the first conductive connector CC1, at least a portion of the side surfaces of the light-emitting element LD and the dummy light-emitting element DLD, and at least a portion of the top surface of the light-emitting element LD and the dummy light-emitting element DLD. The first insulating layer INS1 can prevent sidewall defects of the light-emitting element LD from occurring during the etching process of manufacturing the display device DD, thereby reducing non-emission defects, which will be described later.

[0169] The first insulating layer INS1 can be formed of an inorganic insulating layer comprising an inorganic material. For example, the first insulating layer INS1 may comprise silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon nitride oxide (SiO) x N y ) and such as aluminum oxides (AlO) x At least one of the metal oxides of ). However, the material of the first insulating layer INS1 is not limited to the above. For example, the first insulating layer INS1 may include an organic insulating layer containing organic materials.

[0170] The second insulating layer INS2 can be disposed on the first insulating layer INS1, and together with the first insulating layer INS1, it can cover part of the top surface and side surface of the light-emitting element LD and part of the top surface and side surface of the dummy light-emitting element DLD, as well as part of the top surface and side surface of the first conductive connector CC1. The second insulating layer INS2 can protect the components disposed under the second insulating layer INS2 (such as the first insulating layer INS1, the second conductive connector CC2, the second semiconductor layer SEM2, the active layer MQW, the first semiconductor layer SEM1, and the first conductive connector CC1) from the influence of external water, moisture, etc.

[0171] The second insulating layer INS2 can be formed of an inorganic insulating layer comprising inorganic materials. For example, the second insulating layer INS2 may comprise silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon nitride oxide (SiO) x Ny ) and such as aluminum oxides (AlO) x At least one of the metal oxides of ). However, the material of the second insulating layer INS2 is not limited to the above. For example, the second insulating layer INS2 may include an organic insulating layer containing organic materials.

[0172] Therefore, since the insulating layer INS, including the first insulating layer INS1 and the second insulating layer INS2, covers a portion of the top surface and a portion of the side surface of the light-emitting element LD and the dummy light-emitting element DLD, as well as a portion of the top surface and a portion of the side surface of the first conductive connector CC1, adjacent light-emitting elements LD can be insulated from each other.

[0173] The reflective layer RFM can be disposed on the insulating layer INS and can include a conductive material suitable for reflecting light (such as aluminum (Al)). The reflective layer RFM can have an opening extending along the third direction DR3 on the light-emitting element LD. Due to the above structure, light emitted from the light-emitting element LD can be guided along the third direction DR3. Therefore, the light output efficiency of the light-emitting element LD can be enhanced. In embodiments, the reflective layer RFM can include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected from the aforementioned materials. However, the embodiments are not limited to this.

[0174] The protective layer PTL can be disposed on the reflective layer RFM. The protective layer PTL can protect the components disposed under the protective layer PTL (such as the reflective layer RFM, the second insulating layer INS2, the first insulating layer INS1, the second conductive connector CC2, the second semiconductor layer SEM2, the active layer MQW, the first semiconductor layer SEM1, and the first conductive connector CC1) from the influence of external water, moisture, etc.

[0175] The protective layer PTL can be formed from an inorganic insulating layer comprising inorganic materials. For example, the protective layer PTL may comprise silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon nitride oxide (SiO) x N y ) and such as aluminum oxides (AlO) x At least one of the metal oxides of ). However, the material of the protective layer PTL is not limited to the examples mentioned above. For example, the protective layer PTL may include an organic insulating layer containing organic materials.

[0176] The metal mesh MM can be disposed on the protective layer PTL in the space between adjacent light-emitting elements LD, in the space between adjacent dummy light-emitting elements DLD, and in the space between any one of the adjacent dummy light-emitting elements DLD and any one of the light-emitting elements LD, while exposing part of the top surface of the protective layer PTL.

[0177] The insulating layer INS, the reflective layer RFM, and the protective layer PTL may include a plurality of first contact holes H1 extending to at least a portion of the top surface of the light-emitting element LD and a trench TR extending to a portion of the top surface of the fourth dummy light-emitting element DLD4.

[0178] Specifically, the first contact hole H1 can extend to the top surface of the second conductive connector CC2 of the light-emitting element LD located in the display area AA. Furthermore, the trench TR can extend to the top surface of the second conductive connector CC2 of the fourth dummy light-emitting element DLD4 located in the dam area DAM.

[0179] The cathode electrode CE can be disposed on the protective layer PTL and the metal mesh MM. Furthermore, the cathode electrode CE can be electrically connected to the top surface of the second conductive connector CC2 of the light-emitting element LD through the first contact hole H1. Therefore, the top surface of the light-emitting element LD is electrically connected to the cathode electrode CE, and the bottom surface of the light-emitting element LD is electrically connected to the first conductive connector CC1. Thus, the light-emitting element LD can emit light based on the current flowing from the first conductive connector CC1 to the cathode electrode CE.

[0180] The portion of the cathode electrode CE formed in the cathode contact region CCA and the other portion formed in the pad region PAD can be separated from each other, and a trench TR is inserted between them. In other words, the dam region DAM allows the portion of the cathode electrode CE formed in the cathode contact region CCA to be insulated from the portion formed in the pad region PAD.

[0181] The thin-film encapsulation layer (TFE) can be disposed on the cathode electrode (CE). The TFE can include an inorganic insulating layer containing inorganic materials and / or an organic insulating layer containing organic materials. The inorganic insulating layer can include, for example, silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO) x N y ) and such as aluminum oxides (AlO) xThe organic insulating layer may include at least one of the following metal oxides: acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin. The thin-film encapsulation layer TFE may be configured as a single-layer structure comprising organic or inorganic materials, and may be configured as a multilayer structure formed by alternating stacking of organic and inorganic materials. The thin-film encapsulation layer TFE may include various materials capable of serving as a buffer layer to protect the underlying layer from external impacts or suitable for protecting the underlying layer from oxygen and foreign matter such as dust or water. In the following description, for ease of illustration, the case where the thin-film encapsulation layer TFE is configured as a single-layer structure will be used.

[0182] A lens array LA, including a first lens LS1 and a second lens LS2, can be formed on top of the light-emitting element LD in a trench portion of the thin-film encapsulation material layer TFE corresponding to the first contact hole H1. The lens array LA can be formed as many as the number of light-emitting elements LD, corresponding to each of all light-emitting elements LD formed in the display area AA.

[0183] The thin-film encapsulation layer TFE can contact the top surface of the second conductive connector CC2 of the fourth dummy light-emitting element DLD4 located in the dam region DAM via the trench TR. According to the above structure, the side surface of the cathode electrode CE located in the dam region DAM can be covered by the thin-film encapsulation layer TFE above the fourth dummy light-emitting element DLD4. Furthermore, the side surfaces of the protective layer PTL, reflective layer RFM, second insulating layer INS2, and first insulating layer INS1, sequentially disposed below the cathode electrode CE, can also be covered by the thin-film encapsulation layer TFE.

[0184] The insulating layer INS, the reflective layer RFM, and the protective layer PTL may include a plurality of second contact holes H2 in the cathode contact area CCA and a plurality of third contact holes H3 in the pad area PAD. The plurality of second contact holes H2 extend to at least a portion of the top surface of the first conductive connector CC1 that contacts the second dummy light-emitting element DLD2, and the plurality of third contact holes H3 extend to at least a portion of the top surface of the first conductive connector CC1 that contacts the third dummy light-emitting element DLD3.

[0185] The first end E1 of the metal mesh MM located in the cathode contact region CCA can be electrically connected via the second contact hole H2 to at least a portion of the top surface of the first conductive connector CC1 located in the cathode contact region CCA. The second end E2 of the metal mesh MM located in the cathode contact region CCA can be electrically connected to the cathode electrode CE located in the cathode contact region CCA. According to the above structure, in the cathode contact region CCA, the electrical signal applied through the common voltage line CVW can be transmitted to the cathode electrode CE through the first conductive connector CC1 and the metal mesh MM.

[0186] Therefore, the electrical signal transmitted to the cathode electrode CE can be transmitted to the dummy area DA and the display area AA. When the electrical signal reaches the dummy area DA, the first dummy light-emitting element DLD1 is insulated from the cathode electrode CE through the insulating layer INS and the protective layer PTL. Therefore, the electrical signal applied to the cathode electrode CE may not be transmitted to the first dummy light-emitting element DLD1. Therefore, the first dummy light-emitting element DLD1 may not emit light.

[0187] Since the cathode electrode CE located in the display area AA is electrically connected to the second conductive connector CC2 of the light-emitting element LD, the electrical signal applied to the cathode electrode CE in the cathode contact area CCA can be transmitted to the second conductive connector CC2 of the light-emitting element LD via the dummy area DA. Therefore, the light-emitting element LD can emit light based on a first electrical signal (e.g., an anode signal) applied to the sub-pixel circuit SPC and a second electrical signal (e.g., a cathode signal) provided from the cathode electrode CE.

[0188] The first end E3 of the metal mesh MM located in the pad area PAD can be electrically connected to at least a portion of the top surface of the first conductive connector CC1 located in the pad area PAD through the third contact hole H3. Furthermore, the second end E4 of the metal mesh MM located in the pad area PAD can be electrically connected to the cathode electrode CE located in the pad area PAD.

[0189] The thin-film encapsulation layer TFE may include a fourth contact hole H4 extending to the top surface of the cathode electrode CE located in the pad region PAD. The display element layer DPL may also include a pad electrode PE disposed on the thin-film encapsulation layer TFE and electrically connected to the cathode electrode CE through the fourth contact hole H4.

[0190] As described above, the pad electrode PE can be electrically connected to a circuit board (e.g., a driver integrated circuit DIC) separate from the display panel DP. Therefore, the pad electrode PE can receive various electrical signals from the circuit board for driving the display panel DP. The electrical signals applied to the pad electrode PE can be transmitted to the second connection line WR2 via components located below the display panel DP (such as the cathode electrode CE, metal mesh MM, and first conductive connector CC1, all electrically connected to the pad electrode PE).

[0191] In the following text, reference will be made to Figure 6 and Figure 7 A more detailed description of the dam area DAM and its surrounding components.

[0192] refer to Figure 6 and Figure 7 Based on the planes defined in the first direction DR1 and the second direction DR2, the fourth dummy light-emitting element (DLD4) can have a closed-loop shape surrounding the pad region PAD. The fourth dummy light-emitting element (DLD4) can include a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, and a second conductive connector CC2 in the same manner as other dummy light-emitting elements (DLDs). The cross-sectional shape of the fourth dummy light-emitting element (DLD4) can also be the same as the cross-sectional shape of other dummy light-emitting elements (DLDs).

[0193] As described above, the trench TR can extend to the top surface of the fourth dummy light-emitting element DLD4 (i.e., the top surface of the second conductive connector CC2 located in the dam region DAM). The thin-film encapsulation layer TFE can be connected to the top surface of the second conductive connector CC2 located in the dam region DAM via the trench TR. The thin-film encapsulation layer TFE located in the dam region DAM can fill the trench TR, thereby covering all side surfaces of the components between the second conductive connector CC2 and the thin-film encapsulation layer TFE. Furthermore, the side surfaces of the first conductive connector CC1, which respectively contacts the bottom surface of the fourth dummy light-emitting element DLD4, can be covered with an insulating layer INS and are therefore insulated from each other.

[0194] The fourth dummy light-emitting element DLD4 can be formed in a grid shape in the dam region DAM based on a plane defined on the first direction DR1 and the second direction DR2. In the dam region DAM, the space not occupied by the fourth dummy light-emitting element DLD4 can be filled with a metal grid MM. For example, the metal grid MM can be formed between adjacent fourth dummy light-emitting elements DLD4 based on the first direction DR1 or the second direction DR2. Figure 7 The diagram illustrates two spaces where a fourth dummy light-emitting element DLD4 is not formed, based on either a first direction DR1 or a second direction DR2. The metal mesh MM may include a first metal mesh MM1 and a second metal mesh MM2 respectively disposed in the two spaces. Figure 6 and Figure 5 The cross section corresponding to line B-B' can also be understood as along... Figure 7 A sectional view taken by line D-D'.

[0195] As described above, the metal mesh MM can be a component distributed throughout the entire area of ​​the display panel DP, and can be used to electrically connect the first conductive connector CC1 and the cathode electrode CE in the cathode contact area CCA and the pad area PAD to each other. On the other hand, the metal mesh MM located in the dam area DAM can be insulated by an insulating layer INS inserted between the thin film encapsulation layer TFE formed in the trench TR and the adjacent first conductive connector CC1.

[0196] For example, in order to transmit electrical signals from the pad area PAD through the cathode electrode CE to the cathode contact area CCA, all the cathode electrodes CE, which are physically separated from each other by a total of three trenches TR, must be free of manufacturing defects. In other words, if the trenches TR are not formed as designed during the manufacturing process, it results in the inability to physically separate the cathode electrodes CE in the dam area DAM, and unwanted current flow may occur in the display element layer DPL, which could potentially lead to an electrical short circuit.

[0197] In an embodiment, a total of three trenches (TRs) can be formed in the dam region (DAM). According to the above structure, even if a manufacturing defect occurs in one trench TR, the remaining two trenches (TRs) can still physically separate the cathode electrode (CE) from each other, thus preventing electrical short circuits. However, the examples mentioned above are merely illustrative, and the embodiments are not limited thereto. For the reasons mentioned above, two or more trenches (TRs) can be formed, but the structure of forming a single trench TR as a structure for preventing electrical short circuits is not entirely excluded from this disclosure.

[0198] In the following text, reference will be made to Figures 8 to 25 Describe in detail the method for manufacturing the display device DD. Figures 8 to 25 This is a cross-sectional view showing the method of manufacturing the display device DD according to the embodiment through the process steps.

[0199] Figure 8 This is a cross-sectional view of the display panel DP during the steps of forming a pixel circuit layer PCL on a first substrate SUB1 and forming a first conductive connector CC1 on the pixel circuit layer PCL.

[0200] refer to Figure 8 A first conductive material layer CCM1 can be formed on a first substrate SUB1 on which a pixel circuit layer PCL can be formed.

[0201] The first substrate SUB1 and the pixel circuit layer PCL can be respectively connected to the reference. Figure 3 The substrate SUB and pixel circuit layer PCL described are the same components. For ease of illustration, in Figure 8 In this document, the first substrate SUB1 and the pixel circuit layer PCL are represented as a single layer SUB1 / PCL. However, the first substrate SUB1 and the pixel circuit layer PCL formed as separate layers (e.g., the pixel circuit layer PCL is formed on the first substrate SUB1) may be included within the scope of this disclosure. Redundant descriptions thereof will be omitted below.

[0202] The first conductive material layer CCM1 may be configured to be formed via a manufacturing process described later. Figure 6 The first conductive connector CC1 is described as a component. In other words, the first conductive material layer CCM1 may include the same material as the first conductive connector CC1. Specifically, the first conductive material layer CCM1 may be a conductive element and includes a first barrier material layer BRLM1, a main material layer MNLM, and a second barrier material layer BRLM2. The first barrier material layer BRLM1, the main material layer MNLM, and the second barrier material layer BRLM2 may be stacked sequentially in the thickness direction (third direction DR3) of the first substrate SUB1.

[0203] The first barrier material layer BRLM1, the main material layer MNLM, and the second barrier material layer BRLM2 can also be configured to be formed by a manufacturing process described later. Figure 6 The components of the first barrier layer BRL1, the main layer MNL, and the second barrier layer BRL2 are described. In other words, the first barrier material layer BRL1, the main material layer MNL, and the second barrier material layer BRL2 may each comprise the same material as the first barrier layer BRL1, the main layer MNL, and the second barrier layer BRL2. Considering the above, redundant descriptions will be omitted below.

[0204] Figure 9 This is a cross-sectional view of the display panel DP during the steps of forming a first semiconductor material layer SEMM1, an active material layer MQWM, and a second semiconductor material layer SEMM2 on a second substrate SUB2.

[0205] refer to Figure 9 A second substrate SUB2 can be prepared (or provided), and a first semiconductor material layer SEMM1, an active material layer MQWM, and a second semiconductor material layer SEMM2 can be sequentially formed on the second substrate SUB2.

[0206] The first semiconductor material layer SEMM1, the active material layer MQWM, and the second semiconductor material layer SEMM2 can be respectively configured to be formed by a manufacturing process described later. Figure 6The components of the second semiconductor layer SEM2, the active layer MQW, and the first semiconductor layer SEM1 are described. In other words, the first semiconductor material layer SEMM1, the active material layer MQWM, and the second semiconductor material layer SEMM2 may include the same materials as the second semiconductor layer SEM2, the active layer MQW, and the first semiconductor layer SEM1, respectively. Considering the above, redundant descriptions will be omitted below.

[0207] In an embodiment, the second substrate SUB2 may be a base substrate that allows target material to be stacked thereon. The second substrate SUB2 may be a wafer for the epitaxial growth of the desired material. In an embodiment, the second substrate SUB2 may be any of a sapphire substrate, a GaAs substrate, a Ga substrate, and an InP substrate, but this disclosure is not limited thereto. For example, if a particular material satisfies the selectivity required for fabricating a light-emitting element (LD) and smoothly induces the epitaxial growth of the desired material, that particular material may be selected as the material for the second substrate SUB2.

[0208] The first semiconductor material layer SEMM1, the active material layer MQWM, and the second semiconductor material layer SEMM2 can be formed by growing seed crystals on the second substrate SUB2 according to an epitaxial method. For example, the first semiconductor material layer SEMM1, the active material layer MQWM, and the second semiconductor material layer SEMM2 can be formed by any of the following methods: molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), electron beam deposition, physical vapor deposition (PVD) (such as sputtering), chemical vapor deposition (CVD), type-two thermal evaporation, and metal-organic chemical vapor deposition (MOCVD). However, this disclosure is not limited thereto.

[0209] There are no particular limitations on the precursor materials used to form the first semiconductor material layer SEMM1 and the second semiconductor material layer SEMM2, as long as the precursor materials fall within the range that can be typically selected to form the target materials. For example, the precursor materials can be metal precursors that include alkyl groups such as methyl or ethyl groups. For example, the precursor materials can include, but are not limited to, compounds such as trimethylgallium (Ga(CH3)3), trimethylaluminum (Al(CH3)3), or triethyl phosphate ((C2H5)3PO4).

[0210] Figure 10 This is a cross-sectional view of the display panel DP during the steps of bonding the first conductive material layer SEMM1 and the second semiconductor material layer SEMM2 into contact with each other and separating the second substrate SUB2 from the first semiconductor material layer SEMM1.

[0211] refer to Figure 10The second substrate SUB2, on which the first semiconductor material layer SEMM1, the active material layer MQWM, and the second semiconductor material layer SEMM2 are stacked in sequence, can be aligned with the first substrate SUB1, such that the second semiconductor material layer SEMM2 faces the second barrier material layer BRLM2 of the first conductive material layer CCM1.

[0212] When heat and pressure are applied in a direction that brings the first substrate SUB1 and the second substrate SUB2 closer together while the second semiconductor material layer SEMM2 and the second barrier material layer BRLM2 are in contact with each other, the second semiconductor material layer SEMM2 and the second barrier material layer BRLM2 can bond together. After the second semiconductor material layer SEMM2 and the second barrier material layer BRLM2 are bonded together, the second substrate SUB2 can be separated from the first semiconductor material layer SEMM1.

[0213] Through the processes mentioned above, a structure can be obtained in which the second semiconductor material layer SEMM2, the active material layer MQWM, and the first semiconductor material layer SEMM1 are sequentially stacked on the first conductive material layer CCM1.

[0214] For reference, Figure 10 In this context, based on the order in which semiconductor material layers SEMM1 and SEMM2 are stacked on the second substrate SUB2 (i.e., in the order of the second substrate SUB2, the first semiconductor material layer SEMM1, the active material layer MQWM, and the second semiconductor material layer SEMM2), semiconductor material layers SEMM1 and SEMM2 are designated as "first" and "second". On the other hand, in... Figure 6 In this case, the semiconductor layers are designated as "first" and "second" according to the order in which they are stacked on the first substrate SUB1. In the following text, for ease of explanation, reference will be made to... Figures 11 to 25 ,exist Figures 11 to 25 China and Israel Figure 6 In the same manner as in [previous section], the first semiconductor material layer SEMM1 and the second semiconductor material layer SEMM2 are designated sequentially in order closer to the first substrate SUB1. Considering the above, redundant descriptions will be omitted below.

[0215] Figure 11 This is a cross-sectional view of the display panel DP during the step of forming a second conductive material layer CCM2 on a second semiconductor material layer SEMM2.

[0216] refer to Figure 11 The second conductive material layer CCM2 can be formed on the second semiconductor material layer SEMM2.

[0217] The second conductive material layer CCM2 may be configured to be formed via a manufacturing process described later. Figure 6The second conductive connector CC2 is described as a component. In other words, the second conductive material layer CCM2 may include the same material as the second conductive connector CC2. Given the above, redundant descriptions will be omitted below.

[0218] The second conductive material layer CCM2 can be formed of a transparent or translucent material with conductivity, and can be formed by physical vapor deposition (PVD) (such as sputtering) or chemical vapor deposition (CVD), but this disclosure is not limited thereto. For example, the material layer can be deposited on a flexible substrate using a deposition method such as roll-to-roll.

[0219] Figure 12 This is a cross-sectional view of a display panel DP showing the steps of forming multiple light-emitting elements LD in the display area AA and forming multiple dummy light-emitting elements DLD in the non-display area NAA by removing portions of the second conductive material layer CCM2, the second semiconductor material layer SEMM2, the active material layer MQWM and the first semiconductor material layer SEMM1.

[0220] refer to Figure 12 This method can remove portions of components (i.e., the second conductive material layer CCM2, the second semiconductor material layer SEMM2, the active material layer MQWM, and the first semiconductor material layer SEMM1) formed on the first conductive connector CC1. Dry etching can be used to remove portions of the second conductive material layer CCM2, the second semiconductor material layer SEMM2, the active material layer MQWM, and the first semiconductor material layer SEMM1, but this disclosure is not limited thereto.

[0221] The remaining portion not removed in this step can be formed into multiple light-emitting elements (LDs) and multiple dummy light-emitting elements (DLDs). The LDs and DLDs can comprise substantially the same material. In other words, each of the LDs and DLDs can include a first semiconductor material layer SEMM1, an active material layer MQWM, a second semiconductor material layer SEMM2, and a second conductive material layer CCM2 in the same manner.

[0222] Specifically, the remaining portions of the first semiconductor material layer SEMM1, the active material layer MQWM, the second semiconductor material layer SEMM2, and the second conductive material layer CCM2 in the display area AA can be formed as corresponding light-emitting elements LD of the sub-pixel circuit SPC electrically connected to the pixel circuit layer PCL.

[0223] Furthermore, the remaining portions of the first semiconductor material layer SEMM1, the active material layer MQWM, the second semiconductor material layer SEMM2, and the second conductive material layer CCM2 in the dummy region DA can be formed as the corresponding first dummy light-emitting element DLD1 of the first connection line WR1 of the contact pixel circuit layer PCL.

[0224] Furthermore, the remaining portions of the first semiconductor material layer SEMM1, the active material layer MQWM, the second semiconductor material layer SEMM2, and the second conductive material layer CCM2 in the cathode contact region CCA can be formed as a corresponding second dummy light-emitting element DLD2 electrically connected to the common voltage line CVW of the pixel circuit layer PCL.

[0225] Furthermore, the remaining portions of the first semiconductor material layer SEMM1, the active material layer MQWM, the second semiconductor material layer SEMM2, and the second conductive material layer CCM2 in the pad region PAD can be formed as a corresponding third dummy light-emitting element DLD3 electrically connected to the second connection line WR2 of the pixel circuit layer PCL.

[0226] Furthermore, the remaining portions of the first semiconductor material layer SEMM1, the active material layer MQWM, the second semiconductor material layer SEMM2, and the second conductive material layer CCM2 in the dam region DAM can be formed as the corresponding fourth dummy light-emitting element DLD4 of the third connection line WR3 of the contact pixel circuit layer PCL.

[0227] From a viewpoint perpendicular to the plane formed on the first direction DR1 and the second direction DR2, unlike the first to third dummy light-emitting elements DLD1 to DLD3 which have a point-like shape, the fourth dummy light-emitting element DLD4 can be formed in a grid shape in the dam region DAM and extend in a closed-loop shape around the pad region PAD. (Already referenced) Figure 6 and Figure 7 The above structure has been described in detail, and therefore a more detailed description of it will be omitted.

[0228] Semiconductor material layers can be etched using typical methods. For example, etching processes can be performed using dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), and inductively coupled plasma reactive ion etching (ICP-RIE). In the case of dry etching, anisotropic etching is possible, making it suitable for vertical etching. When using the etching methods mentioned above, the etchant can be chlorine (Cl2), oxygen (O2), etc., but is not limited to these.

[0229] Following this step, the remaining portions of the first semiconductor material layer SEMM1, the active material layer MQWM, the second semiconductor material layer SEMM2, and the second conductive material layer CCM2 will no longer be processed. Therefore, for ease of explanation, in Figures 13 to 25 In this context, the first semiconductor material layer SEMM1, the active material layer MQWM, the second semiconductor material layer SEMM2, and the second conductive material layer CCM2 will be referred to as the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the second conductive connector CC2, respectively.

[0230] Figure 13 This is a cross-sectional view of the display panel DP during the step of forming the first insulating material layer INSM1 on the first conductive material layer CCM1, the light-emitting element LD, and the dummy light-emitting element DLD.

[0231] refer to Figure 13 The first insulating material layer INSM1 can be formed across the entire surface of the display panel DP in both the display area AA and the non-display area NAA. The first insulating material layer INSM1 can cover the portions of the pixel circuit layer PCL where no light-emitting element LD and dummy light-emitting element DLD are formed, the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, the side surface of the second conductive connector CC2, and the top surface of the second conductive connector CC2.

[0232] The first insulating material layer INSM1 may be configured to be formed by a manufacturing process described later. Figure 6 The first insulating layer INS1 is described. In other words, the first insulating material layer INSM1 may include substantially the same material as the first insulating layer INS1. Given the above, redundant descriptions will be omitted below.

[0233] In embodiments, the first insulating material layer INSM1 can be formed by atomic layer deposition (ALD), sol-gel processes, chemical vapor deposition such as plasma-enhanced chemical vapor deposition (PECVD), etc. However, the above is merely illustrative and the present disclosure is not limited thereto.

[0234] Figure 14 This is a cross-sectional view of the display panel DP during the step of removing a portion of the first insulating material layer INSM1 and a portion of the first conductive material layer CCM1.

[0235] refer to Figure 14Except for the spaces IBS2 between adjacent second dummy light-emitting elements DLD2 and IBS2 between adjacent third dummy light-emitting elements DLD3, portions of the first insulating material layer INSM1 and the first conductive material layer CCM1 located in the spaces IBS1 between adjacent light-emitting elements LD and IBS3 between adjacent dummy light-emitting elements DLD, which constitute the remaining region, can be removed. Therefore, portions of the side surface of the first conductive connector CC1 and the top surface of the pixel circuit layer PCL can be exposed. Dry etching can be used as a method to remove portions of the first insulating material layer INSM1 and the first conductive material layer CCM1, but the implementation is not limited to this.

[0236] Regarding the cathode contact area CCA and the pad area PAD, portions of the space IBS2 between the first insulating material layer INSM1 and the first conductive connector CC1, located between the second dummy light-emitting element DLD2 and the third dummy light-emitting element DLD3, can be retained without removal.

[0237] After this step, the remaining portion of the first conductive material layer CCM1 can be left unprocessed. Therefore, for ease of explanation, in Figures 15 to 25 In this context, the first conductive material layer CCM1 will be referred to as the first conductive connector CC1.

[0238] Figure 15 This is a cross-sectional view of a display panel DP showing the steps of forming a second insulating material layer INSM2 on the exposed side surface of the first insulating material layer INSM1, the first conductive connector CC1, and the exposed portion of the top surface of the pixel circuit layer PCL, and forming a reflective material layer RFMM and a protective material layer PTLM on the second insulating material layer INSM2.

[0239] refer to Figure 15 The second insulating material layer INSM2 can be formed across the entire surface of the display panel DP. In other words, the second insulating material layer INSM2 can be formed across the entire display area AA, dummy area DA, cathode contact area CCA, dam area DAM, and pad area PAD.

[0240] The second insulating material layer INSM2, the reflective material layer RFMM, and the protective material layer PTLM can be respectively related to the reference. Figure 6 The second insulating layer INS2, the reflective layer RFM, and the protective layer PTL are the same components described. Redundant descriptions will be omitted below.

[0241] In embodiments, the second insulating material layer INSM2 can be formed by atomic layer deposition (ALD), sol-gel processes, chemical vapor deposition (such as plasma-enhanced chemical vapor deposition (PECVD)), etc. However, the above is merely illustrative and this disclosure is not limited thereto.

[0242] The reflective material layer RFMM can also be formed across the entire surface of the display panel DP. In other words, the reflective material layer RFMM can also be formed across the entire display area AA, dummy area DA, cathode contact area CCA, dam area DAM, and pad area PAD. In embodiments, the reflective material layer RFMM can be formed by metal deposition methods such as sputtering, but this disclosure is not limited thereto.

[0243] The protective material layer PTLM can also be formed across the entire surface of the display panel DP. In other words, the protective material layer PTLM can also be formed across the entire display area AA, dummy area DA, cathode contact area CCA, dam area DAM, and pad area PAD. The protective material layer PTLM can be formed on the reflective material layer RFMM using the same method as the first insulating material layer INSM1 or the second insulating material layer INSM2.

[0244] Figure 16 This is a cross-sectional view of the display panel DP during the step of forming the first contact hole CNT1 by removing portions of the protective material layer PTLM, the reflective material layer RFMM, the second insulating material layer INSM2, and the first insulating material layer INSM1.

[0245] refer to Figure 16 This can be achieved by removing the protective material layer PTLM, the reflective material layer RFMM, the second insulating material layer INSM2, and the first insulating material layer INSM1 from the space between the second dummy light-emitting element DLD2 (see reference). Figure 14 The space between IBS2 and the third dummy light-emitting element DLD3 (reference) Figure 14 A portion of the IBS2 in the cathode contact area (CCA) is used to form multiple first contact holes (CNT1), thereby allowing a portion of the top surface of the first conductive connector CC1 located in the cathode contact area (CCA) and the pad area (PAD) to be exposed through the first contact holes (CNT1). The first contact holes (CNT1) can be formed by a dry etching process.

[0246] When the first contact hole CNT1 is formed, a first cross section CP1 can be formed in the protective material layer PTLM, the reflective material layer RFMM, the second insulating material layer INSM2, and the first insulating material layer INSM1 located in the cathode contact region CCA and the pad region PAD. The first cross section CP1 can be aligned based on a direction substantially the same as that of the third direction DR3.

[0247] Figure 17 This is a cross-sectional view of the display panel DP during the step of forming a third conductive material layer CCM3 on the portion of the top surface of the protective material layer PTLM and the first conductive connector CC1 exposed through the first contact hole CNT1.

[0248] refer to Figure 17 The third conductive material layer CCM3 can be formed across the entire surface of the display panel DP. Specifically, the third conductive material layer CCM3 can cover the first cross-section (see reference). Figure 16 The portion of the top surface of the CP1, the entire top surface of the protective material layer PTLM, and the top surface of the first conductive connector CC1 exposed by the first contact hole CNT1 formed between adjacent second dummy light-emitting elements DLD2 and adjacent third dummy light-emitting elements DLD3.

[0249] The third conductive material layer CCM3 may be configured to be formed via a manufacturing process described later. Figure 6 The metal mesh MM is described. In other words, the third conductive material layer CCM3 may include the same material as the metal mesh MM. Given the above, redundant descriptions will be omitted below.

[0250] The third conductive material layer CCM3 can be formed of a conductive metallic material, and in some embodiments, it may include copper (Cu). However, the embodiments are not limited to the above examples, and the third conductive material layer CCM3 may include at least one selected from copper (Cu), gold (Au), tin (Sn), titanium (Ti), aluminum (Al), and silver (Ag), or may be formed of an alloy thereof. The third conductive material layer CCM3 can be patterned by an inlay process, but this disclosure is not limited thereto.

[0251] Therefore, when the conductive third conductive material layer CCM3 fills the first contact hole (reference) Figure 16 When the CNT1 in the cathode contact area CCA and the portion covering the top surface of the first conductive connector CC1 are connected, the first conductive connector CC1 located in the cathode contact area CCA and the pad area PAD can be electrically connected to the third conductive material layer CCM3.

[0252] Figure 18 This is a cross-sectional view of the display panel DP during the step of planarizing the third conductive material layer CCM3 and exposing the protective material layer PTLM.

[0253] refer to Figure 18The upper portion of the third conductive material layer CCM3 can be removed by a polishing process such as chemical mechanical polishing (CMP) and / or etching. Specifically, a polishing process and / or etching process can be performed on the third conductive material layer CCM3 to planarize it. In the preceding steps, the third conductive material layer CCM3 covers the protective material layer PTLM, and therefore the third conductive material layer CCM3 is formed in the thickness direction (third direction DR3) of the first substrate SUB1 at a position higher than the protective material layer PTLM. Furthermore, although not shown in the figures, the top surface of the third conductive material layer CCM3 can have a rough surface after being formed by the deposition process. The top surface of the third conductive material layer CCM3 can be treated by polishing and / or etching the third conductive material layer CCM3 to have a smooth surface and expose the top surface of the protective layer PTL.

[0254] As described above, the third conductive material layer CCM3 is the same component as the metal mesh MM and is electrically connected to the first conductive connector CC1 in the cathode contact area CCA and the pad area PAD, as referenced. Figure 6 As described, it is therefore used as a connection electrode for receiving and transmitting signals to drive the display panel DP.

[0255] Therefore, as described above, the third conductive material layer CCM3 can not only be used as a component for electrical connection between components, but also play a role in planarization during intermediate manufacturing processes.

[0256] Typically, in the manufacturing process of a display panel (DP), a planarization process is performed by depositing an organic and / or inorganic layer that is relatively thicker than other insulating layers, and then polishing and / or etching the organic and / or inorganic layers. Even after performing the aforementioned processes, an additional process of depositing conductive material can be performed to electrically connect the components to each other.

[0257] As an alternative to depositing and planarizing a passivation layer, the number of patterned masks required for the manufacturing process can be reduced by simultaneously achieving electrical connectivity and planarization using a third conductive material layer, CCM3. Therefore, embodiments of this disclosure can shorten the time required to perform the manufacturing process and reduce production costs.

[0258] Following this step, the third conductive material layer CCM3 will no longer be processed. Therefore, in Figures 19 to 25 In this process, the third conductive material layer, CCM3, will be referred to as the metal mesh MM.

[0259] Figure 19This is a cross-sectional view of the display panel DP during the step of forming multiple second contact holes CNT2 by removing portions of the protective material layer PTLM, the reflective material layer RFMM, the second insulating material layer INSM2, and the first insulating material layer INSM1.

[0260] refer to Figure 19 The second contact hole CNT2 can be formed by removing portions of the protective material layer PTLM, the reflective material layer RFMM, the second insulating material layer INSM2, and the first insulating material layer INSM1 on the light-emitting element LD, thus allowing a portion of the top surface of the second conductive connector CC2 of the light-emitting element LD to be exposed through the second contact hole CNT2. The second contact hole CNT2 can be formed by a dry etching process.

[0261] When the second contact hole CNT2 is formed, a second cross section CP2 can be formed in the protective material layer PTLM, the reflective material layer RFMM, the second insulating material layer INSM2, and the first insulating material layer INSM1 located in the display area AA. The second cross section CP2 can be aligned based on a direction substantially the same as that of the third direction DR3.

[0262] Figure 20 This is a cross-sectional view of the display panel DP during the step of forming a fourth conductive material layer CCM4 on the second conductive connector CC2 of the protective material layer PTLM and the light-emitting element LD.

[0263] refer to Figure 20 The fourth conductive material layer CCM4 can be formed across the entire surface of the display panel DP. Specifically, the fourth conductive material layer CCM4 can cover the second cross-section (see reference). Figure 19 The portion of the top surface of the second conductive connector CC2 of the light-emitting element LD exposed through the second contact hole CNT2, the top surface of the metal mesh MM, and the top surface of the protective material layer PTLM not covered by the metal mesh MM.

[0264] The fourth conductive material layer CCM4 can be configured to be formed as a reference by a manufacturing process described later. Figure 6 The cathode electrode CE is described. In other words, the fourth conductive material layer CCM4 may include the same material as the cathode electrode CE. Given the above, redundant descriptions will be omitted below.

[0265] The fourth conductive material layer CCM4 can be formed of a transparent or translucent material with conductivity, and can be formed by physical vapor deposition (PVD) (such as sputtering) or chemical vapor deposition (CVD), but this disclosure is not limited thereto. For example, the material layer can be deposited on a flexible substrate using a deposition method such as roll-to-roll.

[0266] Therefore, the fourth conductive material layer CCM4, which has conductivity, fills the second contact hole (reference). Figure 19 The second conductive connector CC2 of the light-emitting element LD can be electrically connected to the fourth conductive material layer CCM4.

[0267] Figure 21 This is a cross-sectional view of the display panel DP during the step of forming multiple third contact holes CNT3 by removing portions of the fourth conductive material layer CCM4, the protective material layer PTLM, the reflective material layer RFMM, the second insulating material layer INSM2, and the first insulating material layer INSM1.

[0268] refer to Figure 21 The third contact hole CNT3 can be formed by removing portions of the fourth conductive material layer CCM4, the protective material layer PTLM, the reflective material layer RFMM, the second insulating material layer INSM2, and the first insulating material layer INSM1 from the fourth dummy light-emitting element DLD4. This allows a portion of the top surface of the second conductive connector CC2 of the fourth dummy light-emitting element DLD4 to be exposed through the third contact hole CNT3. The third contact hole CNT3 can be formed using a dry etching process and can be aligned with a reference... Figure 6 The trench TR is described.

[0269] When the third contact hole CNT3 is formed, a third cross section CP3 can be formed in the fourth conductive material layer CCM4, the protective material layer PTLM, the reflective material layer RFMM, the second insulating material layer INSM2, and the first insulating material layer INSM1 located in the dam region DAM. The third cross section CP3 can be aligned based on a direction substantially the same as that of the third direction DR3.

[0270] Following this step, the first insulating material layer INSM1, the second insulating material layer INSM2, the reflective material layer RFMM, the protective material layer PTLM, and the fourth conductive material layer CCM4 will no longer be processed. Therefore, for ease of explanation, in Figures 22 to 25 In this context, the first insulating material layer INSM1, the second insulating material layer INSM2, the reflective material layer RFMM, the protective material layer PTLM, and the fourth conductive material layer CCM4 will be referred to as the first insulating layer INS1, the second insulating layer INS2, the reflective layer RFM, the protective layer PTL, and the cathode electrode CE, respectively.

[0271] Figure 22 This is a cross-sectional view showing the steps of forming a thin-film encapsulation material layer TFEM on the cathode electrode CE and the second conductive connector CC2 of the fourth dummy light-emitting element DLD4.

[0272] refer to Figure 22The thin-film encapsulation material layer TFEM can be formed across the entire surface of the display panel DP. Specifically, the thin-film encapsulation material layer TFEM can cover a third cross-section (see reference). Figure 21 The portion of the top surface of the second conductive connector CC2 exposed through the third contact hole CNT3, and the top surface of the fourth conductive material layer CCM4, which is CP3 in the middle, the fourth dummy light-emitting element DLD4.

[0273] The thin-film encapsulation material layer TFEM can be configured to be formed using a manufacturing process described later. Figure 6 The components of the thin-film encapsulation layer TFE are described. In other words, the thin-film encapsulation material layer TFEM may include the same material as the thin-film encapsulation layer TFE. Considering the above, redundant descriptions will be omitted below.

[0274] In the embodiments, the thin-film encapsulation material layer TFEM can be formed by atomic layer deposition (ALD), molecular layer deposition (MLD), sol-gel process, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), etc. However, the above is only illustrative and the embodiments are not limited thereto.

[0275] Figure 23 This is a cross-sectional view of the display panel DP during the step of forming a lens array LA on a light-emitting element LD.

[0276] refer to Figure 23 The lens array LA, including the first lens LS1 and the second lens LS2, is formed on the light-emitting element LD on the thin-film encapsulation material layer TFEM through the processing of the second contact hole (see reference). Figure 19 In the groove portion formed by CNT2). The lens array LA can be formed as many as the number of light-emitting elements LD, corresponding to each of all light-emitting elements LD formed in the display area AA.

[0277] Figure 23 The lens array LA shown can be the same as the reference. Figure 6 The lens array LA described is the same component. Redundant descriptions will be omitted below.

[0278] Figure 24 This is a cross-sectional view of the display panel DP during the step of forming the fourth contact hole CNT4 by removing a portion of the thin-film encapsulation material layer TFEM.

[0279] refer to Figure 24The fourth contact hole CNT4 is formed by removing a portion of the thin-film encapsulation material layer TFEM located in the pad region PAD. When the fourth contact hole CNT4 is formed, the top surface of the cathode electrode CE located in the pad region PAD can be exposed. Dry etching can be used as a method for removing a portion of the thin-film encapsulation material layer TFEM, but the implementation is not limited to this.

[0280] Following this step, the TFEM thin-film encapsulation material layer is no longer processed. Therefore, for ease of explanation, in Figure 25 In this context, the thin-film encapsulation material layer TFEM will be referred to as the thin-film encapsulation layer TFE.

[0281] Figure 25 This is a cross-sectional view of the display panel DP during the step of forming a pad electrode PE on a cathode electrode CE located in the pad area PAD.

[0282] refer to Figure 25 When a fourth contact hole is formed (refer to) Figure 24 When CNT4 is used, the pad electrode PE can be formed on the exposed portion of the cathode electrode CE.

[0283] Figure 25 The pad electrode PE shown can be the same as the reference. Figure 6 The pad electrode PE described is the same component. Redundant descriptions will be omitted below.

[0284] Figure 26 This is a block diagram illustrating an embodiment of the display system 1000.

[0285] refer to Figure 26 The display system 1000 may include a processor 1100 and a display device 1200.

[0286] The processor 1100 can perform various tasks and operations. In some embodiments, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 via a bus system to control these components.

[0287] The processor 1100 can transmit input image data IMG and control signal CTRL to the display device 1200. The display device 1200 can display an image based on the input image data IMG and control signal CTRL. The display device 1200 can also display an image with reference to... Figure 1 The display device DD described is configured in the same way. In this case, the input image data IMG and the control signal CTRL can be set to... Figure 1 The input image data is IMG and the control signal is CTRL.

[0288] Display system 1000 may include computing systems that provide image display capabilities, such as smartwatches, mobile phones, smartphones, portable computers, tablet PCs, watch phones, car displays, smart glasses, portable multimedia players (PMPs), navigation systems, and ultra-mobile personal computers (UMPCs). Furthermore, display system 1000 may include at least one of head-mounted displays (HMDs), virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices.

[0289] Figure 27 It is shown Figure 26 A 3D diagram illustrating an application example of the display system 1000.

[0290] refer to Figure 27 , Figure 26 The display system 1000 can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0291] The head-mounted display device 2000 may include a headband 2100 and a display device receiving housing 2200. The headband 2100 may be connected to the display device receiving housing 2200. The headband 2100 may include a horizontal strap and / or a vertical strap to secure the head-mounted display device 2000 to a user's head. The horizontal strap may wrap around the side of the user's head, and the vertical strap may wrap around the top of the user's head. However, the implementation is not limited to the examples mentioned above. For example, the headband 2100 may be implemented in the form of eyeglass frames, helmets, etc.

[0292] The display device receiving housing 2200 can accommodate Figure 26 The display device 1200. The display device receiving housing 2200 may also include Figure 26 The processor is 1100.

[0293] Figure 28 It is shown Figure 27 The image shows the head-mounted display device 2000 being worn by the user.

[0294] refer to Figure 28 The first display panel DP1 and the second display panel DP2 of the display device DD can be disposed in the head-mounted display device 2000. The head-mounted display device 2000 may also include one or more lenses LLNS and RLNS.

[0295] In the display device receiving housing 2200, the right eye lens RLNS can be located between the first display panel DP1 and the user's right eye. Furthermore, in the display device receiving housing 2200, the left eye lens LLNS can be located between the second display panel DP2 and the user's left eye.

[0296] The image output from the first display panel DP1 can be viewed by the user's right eye through the right eye lens RLNS. The right eye lens RLNS refracts the light emitted from the first display panel DP1 toward the user's right eye. The right eye lens RLNS performs the optical function of adjusting the viewing distance between the first display panel DP1 and the user's right eye.

[0297] The image output from the second display panel DP2 can be viewed by the user's left eye through the left-eye lens LLNS. The left-eye lens LLNS refracts light emitted from the second display panel DP2 toward the user's left eye. The left-eye lens LLNS performs the optical function of adjusting the viewing distance between the second display panel DP2 and the user's left eye.

[0298] In one embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens with a flat cross-section. In another embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens comprising sub-regions with different optical properties. In this case, each display panel can output an image corresponding to a sub-region of the multi-channel lens. The output image can be viewed by a user through the corresponding sub-region.

[0299] Based on the display device and method of manufacturing the display device according to embodiments of the present disclosure, the time required to perform the manufacturing process can be shortened, and production costs can be reduced. For example, light-emitting elements can be disposed not only in the display area but also in the non-display area, and a metal mesh serving as connecting electrodes can be disposed between the light-emitting elements. During the manufacturing process, the light-emitting elements and the metal mesh can serve a planarization function. Therefore, the processes of depositing and planarizing individual insulating layers can be omitted, thereby shortening the time required for manufacturing the display device and reducing production costs.

[0300] Based on the display device and method of manufacturing the display device according to embodiments of the present disclosure, the risk of electrical short circuits can be reduced. For example, the pad area in the display element component can be surrounded by a dam area in which at least one trench covered with insulating material is formed. Therefore, the risk of electrical short circuits can be reduced.

[0301] However, the effects of this disclosure are not limited to those described above, and various modifications are possible without departing from the spirit and scope of this disclosure.

[0302] While specific implementations and application examples have been described, it should be noted that other implementations and modifications can be derived from the provided disclosure. Therefore, the concept of this disclosure is not limited to the embodiments described above, but extends to the claims and various apparent modifications and equivalent arrangements.

Claims

1. A display device, comprising a display area and a non-display area formed around the display area, the display device comprising: Substrate; A pixel circuit layer is disposed on the substrate and includes a plurality of sub-pixel circuits disposed in the display area; A plurality of first conductive connectors are disposed on the pixel circuit layer, the plurality of first conductive connectors including a first conductive connector disposed in the display area and a first conductive connector disposed in the non-display area; as well as The display element layer is disposed on the plurality of first conductive connectors. The display element layer includes a plurality of light-emitting elements disposed in the display area and a plurality of dummy light-emitting elements disposed in the non-display area. The plurality of light-emitting elements are electrically connected to the sub-pixel circuit via a first conductive connector disposed in the display area and are configured to emit light in response to a signal applied from the sub-pixel circuit. The light-emitting element and the dummy light-emitting element are made of the same material.

2. The display device according to claim 1, wherein, Each of the light-emitting element and the dummy light-emitting element includes: A first semiconductor layer is disposed on the first conductive connector; An active layer is disposed on the first semiconductor layer; A second semiconductor layer is disposed on the active layer; and A second conductive connector is disposed on the second semiconductor layer. The first semiconductor layer, the active layer, the second semiconductor layer, and the second conductive connector are stacked sequentially in the thickness direction of the substrate. The first conductive connector, located in the display area, contacts the light-emitting element and is connected to the sub-pixel circuit. The first conductive connector, located in the non-display area, is in contact with the dummy light-emitting element and is separate from the sub-pixel circuit.

3. The display device according to claim 2, in, The non-display area includes a dummy area surrounding the display area, a cathode contact area surrounding the dummy area, a pad area spaced apart from the cathode contact area, and a dam area surrounding the pad area. The dummy light-emitting element includes: Multiple first dummy light-emitting elements are disposed in the dummy area; Multiple second dummy light-emitting elements are disposed in the cathode contact area; Multiple third dummy light-emitting elements are disposed in the pad area; and Multiple fourth dummy light-emitting elements are disposed in the dam area, and Wherein, along the thickness direction, the cross-section of the first dummy light-emitting element, the second dummy light-emitting element, the third dummy light-emitting element, or the fourth dummy light-emitting element is the same as the cross-section of the light-emitting element disposed in the display area.

4. The display device according to claim 3, wherein, The fourth dummy light-emitting element extends along the dam area in a closed-loop shape.

5. The display device according to claim 3, wherein, The display element layer further includes: An insulating layer covers at least a portion of the top surface of the first conductive connector, the light-emitting element, and the dummy light-emitting element, as well as at least a portion of the side surface of the first conductive connector, the light-emitting element, and the dummy light-emitting element. A reflective layer is disposed on the insulating layer and configured to guide light emitted from the light-emitting element in the thickness direction; A protective layer is disposed on the reflective layer; and A metal mesh is disposed on the protective layer in the spaces between adjacent light-emitting elements, between adjacent dummy light-emitting elements, and between any one of the adjacent light-emitting elements and any one of the dummy light-emitting elements. The top surface of the protective layer is not covered by the metal mesh.

6. The display device according to claim 5, wherein, The insulating layer, the reflective layer, and the protective layer comprise: A plurality of first contact holes extend to at least a portion of the top surface of the light-emitting element, and The groove extends to a portion of the top surface of the fourth dummy light-emitting element.

7. The display device according to claim 6, in, The display element layer also includes a cathode electrode disposed on the protective layer and the metal mesh. The cathode electrode is electrically connected to the top surface of the light-emitting element through the first contact hole, and The portion of the cathode electrode formed in the cathode contact region and the portion of the cathode electrode formed in the pad region are separated from each other by the trench provided in the dam region.

8. The display device according to claim 7, in, The display element layer further includes a thin-film encapsulation layer disposed on the cathode electrode, and The thin-film encapsulation layer contacts the top surface of each of the fourth dummy light-emitting elements through the trench.

9. The display device according to claim 8, wherein, The insulating layer, the reflective layer, and the protective layer further include: A plurality of second contact holes extend to at least a portion of the top surface of the first conductive connector that contacts the second dummy light-emitting element; and Multiple third contact holes extend to at least a portion of the top surface of the first conductive connector that contacts the third dummy light-emitting element. Wherein, the first end of the metal mesh disposed in the cathode contact area is electrically connected through the second contact hole to at least a portion of the top surface of the first conductive connector that contacts the second dummy light-emitting element. The second end of the metal mesh disposed in the cathode contact region is electrically connected to the cathode electrode. Wherein, the first end of the metal mesh disposed in the pad area is electrically connected through the third contact hole to at least a portion of the top surface of the first conductive connector that contacts the third dummy light-emitting element, and The second end of the metal mesh disposed in the pad area is electrically connected to the cathode electrode.

10. The display device according to claim 9, in, The thin-film encapsulation layer includes a fourth contact hole extending to the top surface of the cathode electrode disposed in the pad region, and The display element layer further includes a pad electrode disposed on the thin film encapsulation layer and electrically connected to the cathode electrode through the fourth contact hole.

11. A method of manufacturing a display device, the display device comprising a display area and a non-display area surrounding the display area, the method comprising: A pixel circuit layer in which multiple sub-pixel circuits are disposed is formed on a first substrate; A first conductive material layer is formed on the pixel circuit layer; A first semiconductor material layer, an active material layer, and a second semiconductor material layer are sequentially formed on the second substrate; The first conductive material layer and the second semiconductor material layer are joined together to make them in contact with each other, and the second substrate is separated from the first semiconductor material layer; A second conductive material layer is formed on the first semiconductor material layer; as well as By removing portions of the second conductive material layer, the first semiconductor material layer, the active material layer, and the second semiconductor material layer, a plurality of light-emitting elements disposed in the display area and a plurality of dummy light-emitting elements disposed in the non-display area are formed.

12. The method of claim 11, further comprising forming a first insulating material layer on the first conductive material layer, the light-emitting element, and the dummy light-emitting element.

13. The method of claim 12, further comprising: A portion of the first insulating material layer and a portion of the first conductive material layer are removed, wherein a portion of the top surface of the pixel circuit layer and a portion of the side surface of the first conductive material layer are exposed; A second insulating material layer is formed on the exposed side surfaces of the first insulating material layer and the first conductive material layer, and on the exposed portion of the top surface of the pixel circuit layer; A reflective material layer is formed on the second insulating material layer; and A protective material layer is formed on the reflective material layer.

14. The method of claim 13, further comprising: A third conductive material layer is formed on the protective material layer; as well as The third conductive material layer is planarized, wherein a portion of the protective material layer is exposed by planarizing the third conductive material layer.

15. The method of claim 14, further comprising: A plurality of first contact holes are formed by removing portions of the protective material layer, the reflective material layer, the second insulating material layer, and the first insulating material layer, wherein at least a portion of the top surface of the second conductive material layer disposed in the display area is exposed through the first contact holes; and A fourth conductive material layer is formed on the protective material layer and the third conductive material layer, wherein the fourth conductive material layer is electrically connected to the second conductive material layer disposed in the display area through the first contact hole.

16. The method of claim 14, further comprising: A fourth conductive material layer is formed on the exposed portion of the protective material layer and on the third conductive material layer; as well as A thin film encapsulation material layer is formed on the fourth conductive material layer.

17. The method of claim 12, further comprising: A second insulating material layer is formed on the first insulating material layer; A reflective material layer is formed on the second insulating material layer; as well as A protective material layer is formed on the reflective material layer.

18. The method of claim 17, further comprising: A plurality of second contact holes are formed by removing portions of the protective material layer, the reflective material layer, the second insulating material layer, and the first insulating layer, wherein a portion of the top surface of the first conductive material layer disposed in the non-display area is exposed through the second contact holes; A third conductive material layer is formed on the exposed portion of the top surface of the protective material layer and the first conductive material layer disposed in the non-display area, wherein the third conductive material layer is electrically connected to the first conductive material layer through the second contact hole; and A metal mesh is formed by planarizing the third conductive material layer, wherein a portion of the protective material layer is exposed by planarizing the third conductive material layer.

19. The method of claim 18, further comprising: A fourth conductive material layer is formed on the protective material layer and the metal mesh; as well as A thin film encapsulation material layer is formed on the fourth conductive material layer.

20. The method of claim 14, further comprising: A fourth conductive material layer is formed on the exposed portion of the protective material layer and on the third conductive material layer; The fourth contact hole is formed by removing portions of the fourth conductive material layer, the protective material layer, the reflective material layer, the second insulating material layer, and the first insulating material layer, wherein the top surface of the second conductive material layer disposed in the non-display area is exposed through the fourth contact hole; as well as A thin-film encapsulation material layer is formed on the top surface of the second conductive material layer exposed through the fourth contact hole, as well as on the side surfaces of the first insulating material layer, the second insulating layer, the reflective material layer, the protective material layer, and the fourth conductive material layer facing the fourth contact hole.

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