Method of manufacturing display device and electronic device including the same

Abstract

The invention relates to a method of manufacturing a display device and an electronic device including the same. A method of manufacturing a display device includes: forming a transistor on a substrate including a display area and a non-display area surrounding at least a portion of the display area; forming a first conductive layer in the non-display area on the substrate; forming a first insulating layer covering the first conductive layer and the transistor; forming a protective insulating layer on the first insulating layer that at least partially overlaps the first conductive layer in a plan view; forming a second insulating layer on the first insulating layer that at least partially overlaps the transistor in a plan view; removing the second portion of the protective insulating layer; forming a first electrode connected to the transistor on the second insulating layer; forming a pixel defining layer covering a side portion of the first electrode on the second insulating layer; forming a light emitting layer on the first electrode; and forming a second electrode on the light emitting layer.

Description

Technical Field

[0001] The embodiments relate to a method of manufacturing a display device that provides visual information and an electronic device including the display device. Background Technology

[0002] A display device is a device that displays images to provide visual information to a user. Among display devices, organic light-emitting diode (OLED) display devices have recently attracted attention.

[0003] Display devices may include drivers such as gate drivers and data drivers. A gate driver may include multiple wires to which clock signals, etc., are applied. When moisture or other substances penetrate the insulation layer covering the wires, clock signals, etc., may be applied to the wires with a delay. Summary of the Invention

[0004] The embodiments provide a method for manufacturing a display device with improved quality.

[0005] The embodiments provide an electronic device including a display device.

[0006] A method for manufacturing a display device according to an embodiment may include: forming a transistor on a substrate including a display area and a non-display area surrounding at least a portion of the display area; forming a first conductive layer on the substrate in the non-display area; forming a first insulating layer covering the first conductive layer and the transistor; forming a protective insulating layer on the first insulating layer that at least partially overlaps with the first conductive layer in a plan view; forming a second insulating layer on the first insulating layer that at least partially overlaps with the transistor in a plan view; removing a second portion of the protective insulating layer; forming a first electrode connected to the transistor on the second insulating layer; forming a pixel defining layer on the second insulating layer covering the side portion of the first electrode; forming a light-emitting layer on the first electrode; and forming a second electrode on the light-emitting layer.

[0007] In an embodiment, the protective insulating layer may include a first portion and a second portion having a thickness smaller than that of the first portion.

[0008] In this embodiment, the removal of the second portion of the protective insulating layer can be performed using a plasma ashing process.

[0009] In an embodiment, the method may further include: forming a preliminary dam in a non-display area on a first insulating layer.

[0010] In this embodiment, the formation of the protective insulation layer and the formation of the initial dam can be performed simultaneously.

[0011] In one embodiment, the first conductive layer may be disposed in the gate driver, which is disposed on the substrate in the non-display area.

[0012] In this embodiment, the clock signal can be applied through the first conductive layer.

[0013] In an embodiment, the method may further include: forming a second conductive layer spaced apart from the first conductive layer in a non-display area on a substrate, wherein the first conductive layer and the second conductive layer are disposed on the same layer, and a clock signal is applied to the second conductive layer.

[0014] In an embodiment, the method may further include performing plasma treatment on the first insulating layer after the removal of the second portion of the protective insulating layer.

[0015] In one embodiment, performing plasma treatment on the first insulating layer may be performing nitrogen (N2) plasma treatment on the first insulating layer.

[0016] In one embodiment, the thickness of the first portion of the protective insulating layer can be reduced by removing the second portion of the protective insulating layer.

[0017] In an embodiment, the method may further include: forming a third insulating layer on a first portion of the protective insulating layer having a reduced thickness, to form a support member including the first portion having a reduced thickness and the third insulating layer.

[0018] In this embodiment, the non-display area may include a pad area.

[0019] In an embodiment, the method may further include: forming a first auxiliary pad electrode in a pad area on a substrate; and forming a second auxiliary pad electrode on the first auxiliary pad electrode.

[0020] In an embodiment, the formation of the first insulating layer may include: forming a first preliminary insulating layer covering the second auxiliary pad electrode; and forming a first opening in the first preliminary insulating layer to expose the upper surface of the second auxiliary pad electrode.

[0021] In an embodiment, forming a first opening in a first preliminary insulating layer may include: forming a second preliminary insulating layer on the first preliminary insulating layer; forming a second opening in the second preliminary insulating layer that overlaps with a second auxiliary pad electrode in a plan view; and forming a first opening in the first preliminary insulating layer that overlaps with the second opening in a plan view.

[0022] In an embodiment, the method may further include: after the formation of the first opening, removing at least a portion of the second preliminary insulating layer.

[0023] A method for manufacturing a display device according to an embodiment may include: forming a transistor on a substrate including a display area and a non-display area surrounding at least a portion of the display area; forming a conductive layer on the substrate in the non-display area; forming a passivation layer covering the conductive layer and the transistor; forming a protective insulating layer on the passivation layer that at least partially overlaps with the conductive layer in a plan view; forming a via insulating layer on the passivation layer that at least partially overlaps with the transistor in a plan view; removing a second portion of the protective insulating layer; forming a pixel electrode connected to the transistor on the via insulating layer; forming a pixel defining layer on the via insulating layer covering the side portion of the pixel electrode; forming a light-emitting layer on the pixel electrode; and forming a common electrode on the light-emitting layer.

[0024] In an embodiment, the protective insulating layer may include a first portion and a second portion having a thickness smaller than that of the first portion.

[0025] In this embodiment, the removal of the second portion of the protective insulating layer can be performed using a plasma ashing process.

[0026] In an embodiment, the method may further include: forming a preliminary dam in a non-display area on a passivation layer.

[0027] In this embodiment, the formation of the protective insulation layer and the formation of the initial dam can be performed simultaneously.

[0028] In one embodiment, the conductive layer may be disposed in the gate driver, which is disposed on the substrate in the non-display area.

[0029] In this embodiment, the clock signal can be applied through a conductive layer.

[0030] In an embodiment, the method may further include performing plasma treatment on the passivation layer after the removal of the second portion of the protective insulating layer.

[0031] The electronic device according to the embodiments may include: a display device; and a memory device configured to store data.

[0032] In an embodiment, a method of manufacturing a display device may include: forming a transistor on a substrate including a display area and a non-display area surrounding at least a portion of the display area; forming a first conductive layer on the substrate in the non-display area; forming a first insulating layer covering the first conductive layer and the transistor; forming a protective insulating layer on the first insulating layer that at least partially overlaps with the first conductive layer in a plan view, the protective insulating layer including a first portion and a second portion having a thickness less than the thickness of the first portion; forming a second insulating layer on the first insulating layer that at least partially overlaps with the transistor in a plan view; removing the second portion of the protective insulating layer; forming a first electrode connected to the transistor on the second insulating layer; forming a pixel defining layer on the second insulating layer covering the side portion of the first electrode; forming a light-emitting layer on the first electrode; and forming a second electrode on the light-emitting layer.

[0033] A method for manufacturing a display device according to an embodiment may include: forming a first conductive layer on a substrate in a non-display area; forming a first insulating layer covering the first conductive layer and a transistor; forming a protective insulating layer on the first insulating layer that at least partially overlaps with the first conductive layer in a plan view; and removing a second portion of the protective insulating layer. The protective insulating layer may include a first portion and a second portion having a thickness less than that of the first portion. Removal of the second portion of the protective insulating layer may be performed by a plasma ashing process. The conductive layer may be disposed in a gate driver.

[0034] Because a protective insulating layer is formed on the first insulating layer, moisture and other contaminants cannot penetrate into the first insulating layer during the plasma ashing process. Correspondingly, parasitic capacitance can be prevented from forming near the first conductive layer. Consequently, the phenomenon of signals being applied to the first conductive layer with delay can be prevented, and the gate driver can output normal signals to the display area. Attached Figure Description

[0035] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0036] Figure 1 This is a plan view of a display device according to an embodiment.

[0037] Figure 2 It is a diagram. Figure 1 A schematic block diagram of a display device.

[0038] Figure 3 The illustration includes Figure 1 A schematic diagram of the equivalent circuit of the pixel circuit structure in a display device.

[0039] Figure 4 The illustration includes Figure 1 A schematic diagram of a gate driver in a display device.

[0040] Figure 5 It is intercepted along line I-I' Figure 1 A schematic cross-sectional view of the display device.

[0041] Figure 6 It is intercepted along line II-II'. Figure 1 A schematic cross-sectional view of the display device.

[0042] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 It is a diagram manufacturing process. Figure 1 A schematic cross-sectional view of a method for displaying a device.

[0043] Figure 25 This is a block diagram illustrating an electronic device according to an embodiment.

[0044] Figure 26 It is shown in the diagram. Figure 25 The diagram shows an example of an electronic device implemented as a smartphone. Detailed Implementation

[0045] In the following description, the display device according to the embodiment will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions of the same parts will be omitted.

[0046] When a component or layer is referred to as being "on," "connected to," or "attached to" another component or layer, it can be directly on, connected to, or attached to the other component or layer, or an intermediary component or layer may be present. However, when a component or layer is referred to as being "directly" on, "directly connected to," or "directly attached to" another component or layer, an intermediary component or layer is not present. Therefore, the term "connection" can refer to a physical, electrical, and / or fluid connection, with or without an intermediary component. Additionally, when a component is referred to as being "in contact" or "in phase contact" with another component, the component can be in "electrical contact" or "physical contact" with the other component, or in "indirect contact" or "direct contact" with the other component.

[0047] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0048] Spatial relative terms such as “below,” “under,” “below,” “lower,” “above,” “upper,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein for descriptive purposes and thus to describe the relationship of one element to another(s) as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to cover different orientations of the equipment in use, operation, and / or manufacture. For example, if the equipment in the drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the exemplary term “below” can cover both the above and below orientations. Furthermore, the equipment may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0049] In the specification and claims, for the purposes of their meaning and interpretation, "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in both combined and separate meanings and can be understood as equivalent to "and / or".

[0050] Unless otherwise defined or implied herein, all terms used (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined in the specification.

[0051] Figure 1 This is a plan view of a display device according to an embodiment.

[0052] refer to Figure 1 According to an embodiment, the display device DD may include a display area DA and a non-display area NDA. The display area DA may be an area used to display an image by generating light or adjusting the transmittance of light provided from an external light source.

[0053] The non-display area NDA can be disposed adjacent to the display area DA. For example, the non-display area NDA can surround at least a portion of the display area DA in a plan view. In an embodiment, the non-display area NDA can be an area where no image is displayed. However, this disclosure is not limited thereto, and in another embodiment, an image can be displayed in at least a portion of the non-display area NDA. For example, a light-emitting element can be disposed in at least a portion of the non-display area NDA.

[0054] In this embodiment, the non-display area NDA may include pad areas. For example, the non-display area NDA may include a first pad area PA1 and a second pad area PA2. The first pad area PA1 may be spaced apart from one side of the display area DA in the second direction DR2. The second pad area PA2 may be spaced apart from the first pad area PA1 in the second direction DR2.

[0055] The display device DD may include a substrate SUB. The substrate SUB may form the base of the display device DD. Since the display device DD includes a display area DA and a non-display area NDA including a first pad area PA1 and a second pad area PA2, the substrate SUB may also include a display area DA and a non-display area NDA including a first pad area PA1 and a second pad area PA2.

[0056] Multiple pixels (PX) can be disposed on the substrate SUB. Pixels (PX) can be disposed in the display area DA. Pixels (PX) can emit light based on a signal applied from the non-display area NDA. Pixels (PX) can be repeatedly arranged in a first direction DR1 and a second direction DR2 intersecting the first direction DR1. Accordingly, the display area DA can emit light throughout the entire area and display an image.

[0057] Multiple drivers for driving pixels PX can be disposed on the substrate SUB. The drivers can be disposed in the non-display area NDA. For example, gate driver 200, data driver (e.g., Figure 2 Data driver 400) and compensator (e.g., Figure 2 The compensator 500, etc., can be disposed on the substrate SUB in the non-display area NDA. For ease of description, only... Figure 1 The diagram shows the gate driver 200 in the driver.

[0058] Multiple first pad electrodes PEC1 can be disposed on the substrate SUB. The first pad electrodes PEC1 can be disposed in the first pad area PA1. The first pad electrodes PEC1 can be repeatedly arranged in the first direction DR1.

[0059] The driver chip IC can be disposed on the substrate SUB. In the plan view, the driver chip IC can at least partially overlap with the first pad area PA1. For example, the driver chip IC can be electrically connected to the first pad electrode PEC1. The driver chip IC can convert the digital data signal of the drive signal into an analog data signal. The driver chip IC can provide the data signal to the pixel PX through the first pad electrode PEC1.

[0060] Multiple second pad electrodes PEC2 can be disposed on the substrate SUB. The second pad electrodes PEC2 can be disposed within the second pad area PA2. The second pad electrodes PEC2 can be repeatedly arranged in the first direction DR1.

[0061] The circuit board (PCB) can be mounted on the substrate (SUB). In a plan view, the PCB can at least partially overlap with the second pad area (PA2). For example, the PCB can be electrically connected to the second pad electrode (PEC2). The PCB can apply drive signals and drive voltages to the driver chip (IC) and pixel (PX) via the second pad electrode (PEC2).

[0062] In an embodiment, a first direction DR1 and a second direction DR2 intersecting the first direction DR1 can be defined. For example, the second direction DR2 can be perpendicular to the first direction DR1. However, this disclosure is not limited thereto, and the second direction DR2 can form an acute or obtuse angle with the first direction DR1. A third direction DR3 intersecting the plane formed by the first direction DR1 and the second direction DR2 can be defined. For example, the third direction DR3 can be perpendicular to the plane formed by the first direction DR1 and the second direction DR2. However, this disclosure is not limited thereto, and the third direction DR3 can form an acute or obtuse angle with the plane formed by the first direction DR1 and the second direction DR2.

[0063] Figure 2 It is a diagram. Figure 1 A schematic block diagram of a display device.

[0064] refer to Figure 1 and Figure 2 As described above, the non-display area NDA may include a driver. The driver may include a drive controller 100, a gate driver 200, a gamma reference voltage generator 300, a data driver 400, and a compensator 500.

[0065] The display area DA may include multiple data lines DT1, ..., DTm, multiple first scan lines SCL1, ..., SCLn, multiple second scan lines SSL1, ..., SSLn, multiple sensing lines SL1, ..., SLm, and pixels PX. Each pixel PX can be electrically connected to a corresponding data line among the data lines DT1, ..., DTm, a corresponding first scan line among the first scan lines SCL1, ..., SCLn, a corresponding second scan line among the second scan lines SSL1, ..., SSLn, and a corresponding sensing line among the sensing lines SL1, ..., SLm. For ease of description, in... Figure 2 The diagram illustrates a pixel PX connected to the i-th data line DTi, the i-th first scan line SCLi, the i-th second scan line SSLi, and the i-th sensing line SLi. Here, m, n, and i are positive integers.

[0066] The first scan lines SCL1, ..., SCLn can extend along the first direction DR1 and can be repeated along the second direction DR2. The second scan lines SSL1, ..., SSLn can extend along the first direction DR1 and can be repeated along the second direction DR2. The first scan lines SCL1, ..., SCLn and the second scan lines SSL1, ..., SSLn can be alternately repeated. The data lines DT1, ..., DTm can extend along the second direction DR2 and can be repeated along the first direction DR1. The sensing lines SL1, ..., SLm can extend along the second direction DR2 and can be repeated along the first direction DR1.

[0067] The drive controller 100 can receive input image data IMG and input control signal CONT from an external device. In one embodiment, the input image data IMG may include red image data, green image data, and blue image data. In another embodiment, the input image data IMG may include white image data. In yet another embodiment, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0068] The drive controller 100 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0069] The drive controller 100 can generate a first control signal CONT1 for controlling the operation of the gate driver 200 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 200. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0070] The drive controller 100 can generate a second control signal CONT2 for controlling the operation of the data driver 400 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 400. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0071] The drive controller 100 can generate a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 300 based on the input control signal CONT, and output the third control signal CONT3 to the gamma reference voltage generator 300.

[0072] The drive controller 100 can generate a fourth control signal CONT4 for controlling the operation of the compensator 500 based on the input control signal CONT, and output the fourth control signal CONT4 to the compensator 500.

[0073] The drive controller 100 can generate a data signal DATA based on the input image data IMG. The drive controller 100 can output the data signal DATA to the data driver 400.

[0074] The gate driver 200 can generate scan signals for sending to the first scan lines SCL1, ..., SCLn and the second scan lines SSL1, ..., SSLn in response to a first control signal CONT1 input from the drive controller 100. The gate driver 200 can output the scan signals to the first scan lines SCL1, ..., SCLn and the second scan lines SSL1, ..., SSLn. For example, the gate driver 200 can output the first scan signal (e.g., ... Figure 3 The first scan signal SC) is output to the first scan lines SCL1, ..., SCLn, and the second scan signal (e.g., Figure 3 The second scan signal SS is output to the second scan lines SSL1, ..., SSLn.

[0075] The gamma reference voltage generator 300 can generate a gamma reference voltage VGREF in response to a third control signal CONT3 input from the drive controller 100. The gamma reference voltage generator 300 can provide the gamma reference voltage VGREF to the data driver 400. The gamma reference voltage VGREF can have a value corresponding to the data signal DATA.

[0076] In one embodiment, the gamma reference voltage generator 300 may be spaced apart from the data driver 400 in a direction opposite to the second direction DR2. However, this disclosure is not limited thereto, and in another embodiment, the gamma reference voltage generator 300 may be disposed in the drive controller 100 or in the data driver 400.

[0077] The data driver 400 can receive a second control signal CONT2 and a data signal DATA from the drive controller 100. The data driver 400 can receive a gamma reference voltage VGREF from the gamma reference voltage generator 300. The data driver 400 can use the gamma reference voltage VGREF to convert the data signal DATA into an analog data voltage. The data driver 400 can output the data voltage to data lines DT1, ..., DTm. For example, the data driver 400 can output the data voltage (e.g., ...) Figure 3 The data voltage VDATA is output to the data lines DT1, ..., DTm.

[0078] The compensator 500 can generate sensing signals for sending to sensing lines SL1, ..., SLm in response to a fourth control signal CONT4 input from the drive controller 100. For example, the compensator 500 can convert the sensing signals (e.g., ...) into sensing signals for sending to sensing lines SL1, ..., SLm. Figure 3 The sensing signal SV is output to the sensing lines SL1, ..., SLm.

[0079] In one embodiment, the gate driver 200 may be spaced apart from the display area DA in a direction opposite to the first direction DR1, and the compensator 500 may be spaced apart from the display area DA in a second direction DR2. However, this disclosure is not limited thereto. For example, both the gate driver 200 and the compensator 500 may be spaced apart from the display area DA in a direction opposite to the first direction DR1.

[0080] Figure 3 The illustration includes Figure 1 A schematic diagram of the equivalent circuit of the pixel circuit structure in a display device.

[0081] refer to Figure 3 A pixel PX may include a light-emitting element (LED) and a pixel driving circuit portion PXC electrically connected to the LED. In an embodiment, the pixel driving circuit portion PXC may include a first transistor T1, a second transistor T2, a third transistor T3, and a capacitor CST.

[0082] exist Figure 3In the diagram, each of the first transistor T1, the second transistor T2, and the third transistor T3 is illustrated as an n-type transistor. However, this disclosure is not limited thereto. For example, some of the first transistor T1, the second transistor T2, and the third transistor T3 may be n-type transistors, and the others may be p-type transistors.

[0083] The active pattern of the n-type transistor may include an oxide semiconductor material, and the active pattern of the p-type transistor may include a silicon semiconductor material. However, this disclosure is not limited thereto, and each of the active patterns of the n-type transistor and the p-type transistor may include a silicon semiconductor material.

[0084] The pixel driving circuit section PXC can be electrically connected to the sensing line SL, data line DT, first scan line SCL, second scan line SSL, first voltage line VL1, and second voltage line VL2.

[0085] The data line DT can apply the data voltage VDATA. The first voltage line VL1 can apply a first power supply voltage ELVDD with a relatively high voltage level. The second voltage line VL2 can apply a second power supply voltage ELVSS with a relatively low voltage level. The sensing line SL can apply the sensing signal SV. The first scan line SCL can apply the first scan signal SC. The second scan line SSL can apply the second scan signal SS.

[0086] The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to a first node N1. The first electrode of the first transistor T1 may be connected to a fifth node N5. The second electrode of the first transistor T1 may be connected to a first voltage line VL1.

[0087] The second transistor T2 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the second transistor T2 can be connected to the first scan line SCL. The first electrode of the second transistor T2 can be connected to the second node N2. The first electrode of the second transistor T2 can be connected to the data line DT through the second node N2. The second electrode of the second transistor T2 can be connected to the first node N1.

[0088] The second transistor T2 can be turned on or off in response to the first scan signal SC. For example, if the second transistor T2 is an n-type transistor, it can be turned off when the first scan signal SC has a negative voltage level and turned on when the first scan signal SC has a positive voltage level. If the second transistor T2 is a p-type transistor, it can be turned off when the first scan signal SC has a positive voltage level and turned on when the first scan signal SC has a negative voltage level. The second electrode of the second transistor T2 can provide the data voltage VDATA to the first node N1 during the period when the second transistor T2 is turned on. Accordingly, the second transistor T2 can drive the first transistor T1.

[0089] The third transistor T3 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the third transistor T3 can be connected to the second scan line SSL. The first electrode of the third transistor T3 can be connected to the fourth node N4. The second electrode of the third transistor T3 can be connected to the third node N3. The second electrode of the third transistor T3 can be connected to the sensing line SL through the third node N3.

[0090] The third transistor T3 can be turned on or off in response to the second scan signal SS. For example, if the third transistor T3 is an n-type transistor, it can be turned off when the second scan signal SS has a negative voltage level and turned on when the second scan signal SS has a positive voltage level. If the third transistor T3 is a p-type transistor, it can be turned off when the second scan signal SS has a positive voltage level and turned on when the second scan signal SS has a negative voltage level. During the period when the third transistor T3 is turned on, it can provide the sensing signal SV to the fourth node N4.

[0091] The capacitor CST may include a first electrode and a second electrode. The first electrode of the capacitor CST may be connected to a first node N1. The second electrode of the capacitor CST may be connected to a fourth node N4. The capacitor CST can be charged and discharged according to the data voltage VDATA transmitted to the first node N1.

[0092] A light-emitting element (LED) may include a first electrode and a second electrode. The first electrode of the LED may be connected to a fifth node N5. The second electrode of the LED may be connected to a second voltage line VL2. For example, the first electrode of the LED may be an anode electrode, and the second electrode may be a cathode electrode.

[0093] Figure 3An embodiment in which the pixel driving circuit section PXC includes a first transistor T1, a second transistor T2, a third transistor T3, and a capacitor CST can be illustrated. However, this disclosure is not limited thereto. For example, the pixel driving circuit section PXC may include four or more transistors and two or more capacitors.

[0094] Figure 4 The illustration includes Figure 1 A schematic diagram of a gate driver in a display device.

[0095] refer to Figure 4 The gate driver 200 may include multiple stages. For example, the gate driver 200 may include a first stage STG1, a second stage STG2, a third stage STG3, and a fourth stage STG4.

[0096] Each stage can be connected to a corresponding first scan line in the first scan line. Each stage can be connected to a corresponding second scan line in the second scan line. For example, the first stage STG1 can be connected to the first scan line SC1 and the second scan line SS1. The second stage STG2 can be connected to the first scan line SC2 and the second scan line SS2. The third stage STG3 can be connected to the first scan line SC3 and the second scan line SS3. The fourth stage STG4 can be connected to the first scan line SC4 and the second scan line SS4.

[0097] Each stage can be connected to a corresponding first clock line in the first clock line. Each stage can be connected to a corresponding second clock line in the second clock line. For example, the first stage STG1 can be connected to the first clock line CLK1_SC and the second clock line CLK1_SS. The second stage STG2 can be connected to the first clock line CLK2_SC and the second clock line CLK2_SS. The third stage STG3 can be connected to the first clock line CLK3_SC and the second clock line CLK3_SS. The fourth stage STG4 can be connected to the first clock line CLK4_SC and the second clock line CLK4_SS.

[0098] In one embodiment, the first clock lines may include four first clock lines: CLK1_SC, CLK2_SC, CLK3_SC, and CLK4_SC. However, this disclosure is not limited thereto, and the number of first clock lines may be varied depending on the embodiment. For example, the first clock lines may include six first clock lines.

[0099] In one embodiment, the second clock lines may include four second clock lines: CLK1_SS, CLK2_SS, CLK3_SS, and CLK4_SS. However, this disclosure is not limited thereto, and the number of second clock lines may be varied depending on the embodiment. For example, the second clock lines may include six second clock lines.

[0100] Each of the stages may include an input terminal IN, a first clock terminal CK_SC, a second clock terminal CK_SS, a first power supply terminal V1, a second power supply terminal V2, a carry terminal CR, a first output terminal OUT1, and a second output terminal OUT2.

[0101] The carry terminal CR can be electrically connected to the input terminal IN of the next stage. The carry terminal CR can output the carry signal of the corresponding stage. For example, the carry terminal CR of the first stage STG1 can output the first carry signal CR1, the carry terminal CR of the second stage STG2 can output the second carry signal CR2, and the carry terminal CR of the third stage STG3 can output the third carry signal CR3.

[0102] A scan start signal STV or a previous carry signal can be applied to the input terminal IN. In an embodiment, the scan start signal STV can be applied to the input terminal IN of the first stage STG1, and the carry signal from the previous stage can be applied to the input terminal IN of a stage other than the first stage STG1. For example, the first carry signal CR1 can be applied to the input terminal IN of the second stage STG2, the second carry signal CR2 can be applied to the input terminal IN of the third stage STG3, and the third carry signal CR3 can be applied to the input terminal IN of the fourth stage STG4. However, this disclosure is not limited thereto. For example, the scan start signal STV can be applied to the input terminal IN of each of the first stage STG1 and the second stage STG2.

[0103] The first clock terminal CK_SC can be connected to a first clock line. For example, the first clock terminal CK_SC can be connected to one of the four first clock lines CLK1_SC, CLK2_SC, CLK3_SC, and CLK4_SC. In an embodiment, the first clock terminal CK_SC of the first stage STG1 can be connected to the first clock line CLK1_SC. The first clock terminal CK_SC of the second stage STG2 can be connected to the first clock line CLK2_SC. The first clock terminal CK_SC of the third stage STG3 can be connected to the first clock line CLK3_SC. The first clock terminal CK_SC of the fourth stage STG4 can be connected to the first clock line CLK4_SC. A first clock signal can be applied from the first clock line to the first clock terminal CK_SC.

[0104] The second clock terminal CK_SS can be connected to a second clock line. For example, the second clock terminal CK_SS can be connected to one of the four second clock lines CLK1_SS, CLK2_SS, CLK3_SS, and CLK4_SS. In an embodiment, the second clock terminal CK_SS of the first stage STG1 can be connected to the second clock line CLK1_SS. The second clock terminal CK_SS of the second stage STG2 can be connected to the second clock line CLK2_SS. The second clock terminal CK_SS of the third stage STG3 can be connected to the second clock line CLK3_SS. The second clock terminal CK_SS of the fourth stage STG4 can be connected to the second clock line CLK4_SS. A second clock signal can be applied from the second clock line to the second clock terminal CK_SS.

[0105] A first power supply voltage VGH can be applied to the first power supply terminal V1 of the stage. A second power supply voltage VGL can be applied to the second power supply terminal V2 of the stage.

[0106] The first output terminal OUT1 can output the first scan signal. For example, the first output terminal OUT1 of the first stage STG1 can output the first scan signal SC (1). The first output terminal OUT1 of the second stage STG2 can output the first scan signal SC (2). The first output terminal OUT1 of the third stage STG3 can output the first scan signal SC (3). The first output terminal OUT1 of the fourth stage STG4 can output the first scan signal SC (4).

[0107] The second output terminal OUT2 can output a second scan signal. For example, the second output terminal OUT2 of the first stage STG1 can output the second scan signal SS (1). The second output terminal OUT2 of the second stage STG2 can output the second scan signal SS (2). The second output terminal OUT2 of the third stage STG3 can output the second scan signal SS (3). The second output terminal OUT2 of the fourth stage STG4 can output the second scan signal SS (4).

[0108] Figure 5 It is intercepted along line I-I' Figure 1 A schematic cross-sectional view of the display device.

[0109] refer to Figure 1 and Figure 5The display device DD may include a substrate SUB, a buffer layer BUF, a first lower metal pattern BLM1, a first transistor TR1, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer ILD, a passivation layer PVX, a second pad electrode PEC1, a through-hole insulating layer VIA, a first pixel electrode PE1, a first light-emitting layer EML1, a first common electrode CE1, a pixel defining layer PDL, a packaging layer TFE, a connection member ACF, and a driver chip IC.

[0110] The substrate SUB can include transparent or opaque materials. The substrate SUB can be a transparent resin substrate. Examples of transparent resin substrates include polyimide substrates. A polyimide substrate can include a first organic layer, a first barrier layer, and a second organic layer, etc.

[0111] In another embodiment, the substrate SUB may include quartz (e.g., synthetic quartz substrate, fluorine-doped quartz substrate), calcium fluoride, soda-lime glass, or alkali-free glass. These materials may be used alone or in combination with each other.

[0112] The first lower metal pattern BML1 can be disposed on the substrate SUB. The first lower metal pattern BML1 can be disposed in the display area DA. For example, the first lower metal pattern BML1 may include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides. These materials can be used alone or in combination with each other.

[0113] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0114] A buffer layer BUF can be disposed on the substrate SUB. The buffer layer BUF can cover the first lower metal pattern BML1. The buffer layer BUF can prevent metal atoms or impurities from diffusing from the substrate SUB into the first active pattern ACT1.

[0115] For example, the buffer layer BUF may include silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO)x N y ) or silicon oxide carbide (SiO) x C y Inorganic materials such as ) can be used alone or in combination with each other.

[0116] The first transistor TR1 may include a first active pattern ACT1, a first gate electrode GE1, a first contact electrode SE1, and a second contact electrode DE1. The first transistor TR1 may be disposed in the display area DA. For example, the first transistor TR1 may be disposed on the substrate SUB in the display area DA. In an embodiment, the first transistor TR1 may be disposed in the portion of the display area DA adjacent to the first pad area PA1.

[0117] A first active pattern ACT1 may be disposed on a buffer layer BUF. The first active pattern ACT1 may at least partially overlap with a first lower metal pattern BML1 in a planar view. For example, the first active pattern ACT1 may include an oxide semiconductor material, a silicon semiconductor material, and / or an organic semiconductor material. The first active pattern ACT1 may include a first contact region, a second contact region, and a channel region between the first and second contact regions. The first and second contact regions may have a higher conductivity than the channel region.

[0118] In one embodiment, the first active pattern ACT1 may include an oxide semiconductor material. However, this disclosure is not limited thereto, and in another embodiment, the first active pattern ACT1 may include a silicon semiconductor material. Examples of oxide semiconductor materials that can be used as the first active pattern ACT1 may include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), or indium tin zinc oxide (ITZO), etc. These materials may be used alone or in combination with each other.

[0119] A first gate insulating layer GI1 may be disposed on a first active pattern ACT1. The first gate insulating layer GI1 may cover at least a portion of the first active pattern ACT1. For example, the first gate insulating layer GI1 may cover the upper surface of the first active pattern ACT1.

[0120] For example, the first gate insulating layer GI1 may include silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) or silicon oxide carbide (SiO) x C y Inorganic materials such as ) can be used alone or in combination with each other.

[0121] The first gate electrode GE1 can be disposed on the first gate insulating layer GI1. In a planar view, the first gate electrode GE1 can overlap with the channel region of the first active pattern ACT1.

[0122] For example, the first gate electrode GE1 may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. These materials may be used alone or in combination with each other.

[0123] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0124] An interlayer insulating layer (ILD) can be disposed on the first gate electrode GE1. The ILD can fully cover the first gate electrode GE1. For example, the ILD can cover the first gate electrode GE1 and can be disposed along the contour of the first gate electrode GE1.

[0125] For example, the interlayer insulating layer (ILD) may include silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) or silicon oxide carbide (SiO) x C y Inorganic materials such as ) can be used alone or in combination with each other.

[0126] A first contact electrode SE1 and a second contact electrode DE1 can be disposed on an interlayer insulating layer (ILD). The first contact electrode SE1 can contact a first contact area of ​​a first active pattern ACT1. For example, the first contact electrode SE1 can contact the first contact area of ​​the first active pattern ACT1 through a contact hole defined by the interlayer insulating layer (ILD). The second contact electrode DE1 can contact a second contact area of ​​the first active pattern ACT1. For example, the second contact electrode DE1 can contact the second contact area of ​​the first active pattern ACT1 through a contact hole defined by the interlayer insulating layer (ILD).

[0127] For example, each of the first contact electrode SE1 and the second contact electrode DE1 may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. These materials may be used individually or in combination with each other.

[0128] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0129] In an embodiment, the first contact electrode SE1 may contact the first lower metal pattern BML1. For example, the first contact electrode SE1 may contact the first lower metal pattern BML1 through a contact hole defined by the interlayer insulating layer ILD and the buffer layer BUF. However, this disclosure is not limited thereto. For example, if the first gate electrode GE1 is in contact with the first lower metal pattern BML1, the first contact electrode SE1 may not be in contact with the first lower metal pattern BML1.

[0130] The second gate insulating layer GI2 can be disposed on the buffer layer BUF. The second gate insulating layer GI2 can be disposed in the non-display area NDA. For example, the second gate insulating layer GI2 can be disposed in the first pad area PA1.

[0131] For example, the second gate insulating layer GI2 may include silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) or silicon oxide carbide (SiO) x C y Inorganic materials such as ) can be used alone or in combination with each other.

[0132] The first auxiliary pad electrode PEA can be disposed on the second gate insulating layer GI2. For example, the first auxiliary pad electrode PEA can be disposed in the first pad area PA1.

[0133] For example, the first auxiliary pad electrode PEA may include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides. These materials may be used alone or in combination with each other.

[0134] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0135] In one embodiment, the first auxiliary pad electrode PEA and the first gate electrode GE1 may comprise substantially the same material. However, this disclosure is not limited thereto, and in another embodiment, the first auxiliary pad electrode PEA and the first gate electrode GE1 may comprise different materials.

[0136] The second auxiliary pad electrode PEB can be disposed on the interlayer insulating layer (ILD). For example, the second auxiliary pad electrode PEB can be disposed in the first pad region PA1. In a plan view, the second auxiliary pad electrode PEB can overlap with the first auxiliary pad electrode PEA. The second auxiliary pad electrode PEB can contact the first auxiliary pad electrode PEA. For example, the second auxiliary pad electrode PEB can contact the first auxiliary pad electrode PEA through a contact hole defined by the interlayer insulating layer (ILD).

[0137] For example, the second auxiliary pad electrode PEB can include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides. These materials can be used alone or in combination with each other.

[0138] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) xThese materials can be used individually or in combination with each other.

[0139] In one embodiment, the second auxiliary pad electrode PEB and the first contact electrode SE1 may comprise substantially the same material. However, this disclosure is not limited thereto, and in another embodiment, the second auxiliary pad electrode PEB and the first contact electrode SE1 may comprise different materials.

[0140] Accordingly, a first pad electrode PEC1 can be formed, including a first auxiliary pad electrode PEA and a second auxiliary pad electrode PEB.

[0141] The passivation layer PVX can be disposed on the interlayer insulating layer ILD. The passivation layer PVX can cover the first contact electrode SE1, the second contact electrode DE1, and the second auxiliary pad electrode PEB.

[0142] For example, the passivation layer PVX can include silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) or silicon oxide carbide (SiO) x C y Inorganic materials such as ) can be used alone or in combination with each other.

[0143] The via insulating layer (VIA) can be disposed on the passivation layer (PVX). The via insulating layer (VIA) can include organic materials. For example, the via insulating layer (VIA) can include organic materials such as phenolic resin, polyacrylate resin, polyimide resin, polyamide resin, silicone resin, or epoxy resin. These materials can be used alone or in combination with each other.

[0144] The first pixel electrode PE1 can be disposed on the via insulating layer VIA. The first pixel electrode PE1 can be disposed in the display area DA. The first pixel electrode PE1 can contact the first contact electrode SE1. For example, the first pixel electrode PE1 can contact the first contact electrode SE1 through a contact hole defined by the via insulating layer VIA and the passivation layer PVX.

[0145] For example, the first pixel electrode PE1 may include metals, alloys, metal nitrides, conductive metal oxides, or transparent conductive materials. These materials may be used individually or in combination. In an embodiment, the first pixel electrode PE1 may have a stacked structure including ITO / Ag / ITO. The first pixel electrode PE1 may function as an anode.

[0146] The pixel defining layer (PDL) can be disposed on the via insulating layer (VIA). The PDL can cover the side of the first pixel electrode (PE1). For example, a pixel opening can be defined in the PDL to expose at least a portion of the upper surface of the first pixel electrode (PE1).

[0147] For example, the pixel defining layer (PDL) may include inorganic or organic materials. In one embodiment, the PDL may include organic materials such as epoxy resin or silicone resin. These materials may be used alone or in combination with each other. In another embodiment, the PDL may further include a light-shielding material comprising a black pigment or black dye.

[0148] A first light-emitting layer EML1 can be disposed on the first pixel electrode PE1 and the pixel defining layer PDL. A portion of the first light-emitting layer EML1 can be disposed in a pixel opening of the pixel defining layer PDL. In an embodiment, the first light-emitting layer EML1 may include a first functional layer containing an organic material, a light-emitting layer containing a light-emitting material, and a second functional layer containing an organic material. For example, the first functional layer may include a hole injection layer and a hole transport layer, and the second functional layer may include an electron transport layer and an electron injection layer, etc.

[0149] The first common electrode CE1 can be disposed on the first light-emitting layer EML1. The first common electrode CE1 can include metals, alloys, metal nitrides, conductive metal oxides, or transparent conductive materials, etc. These materials can be used alone or in combination with each other. The first common electrode CE1 can operate as a cathode.

[0150] An encapsulation layer TFE can be disposed on the first common electrode CE1. The encapsulation layer TFE may include a first inorganic encapsulation layer L1, an organic encapsulation layer L2, and a second inorganic encapsulation layer L3. The first inorganic encapsulation layer L1 may cover the first common electrode CE1, the pixel defining layer PDL, and the via insulating layer VIA. For example, the first inorganic encapsulation layer L1 may include an inorganic insulating material. The organic encapsulation layer L2 can be disposed on the first inorganic encapsulation layer L1. For example, the organic encapsulation layer L2 may include an organic insulating material. The second inorganic encapsulation layer L3 can be disposed on the organic encapsulation layer L2. For example, the second inorganic encapsulation layer L3 may include an inorganic insulating material.

[0151] Although not in Figure 5 The illustration shows a touch sensing layer, but in an embodiment, the touch sensing layer may be disposed on the encapsulation layer TFE. For example, the touch sensing layer may include a plurality of touch electrode arrays for capacitively sensing user input, a touchpad portion, and a plurality of touch lines electrically connecting the touchpad portion to the touch electrode arrays. However, this disclosure is not limited thereto. In another embodiment, the touch sensing layer may be omitted.

[0152] In this embodiment, the passivation layer PVX may include an opening OP. The opening OP may be disposed in the first pad region PA1. The upper surface of the second auxiliary pad electrode PEB may be exposed through the opening OP.

[0153] The connecting component ACF can be disposed on the passivation layer PVX. The connecting component ACF can fill the opening OP. The driver chip IC and the first pad electrode PEC1 can be electrically connected to each other through the connecting component ACF. For example, the driver chip IC and the second auxiliary pad electrode PEB can be electrically connected to each other through the connecting component ACF.

[0154] In an embodiment, the connecting member ACF may include an anisotropic conductive film. For example, the connecting member ACF may include an adhesive layer and conductive particles. Each of the conductive particles may include a core comprising an insulating polymer material and a conductive layer surrounding the core comprising a conductive metallic material.

[0155] Figure 6 It is intercepted along line II-II'. Figure 1 A schematic cross-sectional view of the display device.

[0156] refer to Figure 1 and Figure 6 The display device DD may further include a second lower metal pattern BML2, a second transistor TR2, a second pixel electrode PE2, a second light-emitting layer EML2, a second common electrode CE2, a first barrier D1, a second barrier D2, a support member SP, a first conductive layer CL1, a second conductive layer CL2, a third conductive layer CL3, a fourth conductive layer CL4, a first lower auxiliary electrode BE1, a second lower auxiliary electrode BE2, a third lower auxiliary electrode BE3, a fourth lower auxiliary electrode BE4, and a third gate insulating layer GI3.

[0157] The second lower metal pattern BML2 can be disposed on the substrate SUB. The second lower metal pattern BML2 may include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides. These materials may be used alone or in combination with each other.

[0158] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) xThese materials can be used individually or in combination with each other.

[0159] In this embodiment, the first lower auxiliary electrode BE1, the second lower auxiliary electrode BE2, the third lower auxiliary electrode BE3, and the fourth lower auxiliary electrode BE4 can be disposed on the substrate SUB. Each of the first lower auxiliary electrode BE1, the second lower auxiliary electrode BE2, the third lower auxiliary electrode BE3, and the fourth lower auxiliary electrode BE4 can be disposed in the non-display area NDA. For example, each of the first lower auxiliary electrode BE1, the second lower auxiliary electrode BE2, the third lower auxiliary electrode BE3, and the fourth lower auxiliary electrode BE4 can be disposed in the gate driver 200.

[0160] Each of the first lower auxiliary electrode BE1, the second lower auxiliary electrode BE2, the third lower auxiliary electrode BE3, and the fourth lower auxiliary electrode BE4 may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. These materials may be used individually or in combination with each other.

[0161] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0162] In an embodiment, the first lower auxiliary electrode BE1, the second lower auxiliary electrode BE2, the third lower auxiliary electrode BE3, the fourth lower auxiliary electrode BE4, and the second lower metal pattern BML2 can be disposed on the same layer and can comprise substantially the same material.

[0163] A buffer layer BUF can be disposed on the substrate SUB. The buffer layer BUF can cover the second lower metal pattern BML2, the first lower auxiliary electrode BE1, the second lower auxiliary electrode BE2, the third lower auxiliary electrode BE3, and the fourth lower auxiliary electrode BE4. The buffer layer BUF can prevent metal atoms or impurities from diffusing from the substrate SUB into the second active pattern ACT2.

[0164] The second transistor TR2 may include a second active pattern ACT2, a second gate electrode GE2, a third contact electrode SE2, and a fourth contact electrode DE2. The second transistor TR2 may be disposed in the display area DA. For example, the second transistor TR2 may be disposed on the substrate SUB in the display area DA. In an embodiment, the second transistor TR2 may be disposed in the portion of the display area DA adjacent to the non-display area NDA.

[0165] The second active pattern ACT2 can be disposed on the buffer layer BUF. The second active pattern ACT2 can at least partially overlap with the second lower metal pattern BML2 in a planar view. For example, the second active pattern ACT2 can include an oxide semiconductor material, a silicon semiconductor material, and / or an organic semiconductor material. The second active pattern ACT2 can include a first contact region, a second contact region, and a channel region between the first and second contact regions. The first and second contact regions can have a higher conductivity than the channel region.

[0166] In one embodiment, the second active pattern ACT2 may include an oxide semiconductor material. However, this disclosure is not limited thereto, and in another embodiment, the second active pattern ACT2 may include a silicon semiconductor material. Examples of oxide semiconductor materials that can be used as the second active pattern ACT2 may include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), or indium tin zinc oxide (ITZO), etc. These materials may be used alone or in combination with each other.

[0167] A third gate insulating layer GI3 may be disposed on the second active pattern ACT2. The third gate insulating layer GI3 may cover at least a portion of the second active pattern ACT2. For example, the third gate insulating layer GI3 may cover the upper surface of the second active pattern ACT2.

[0168] For example, the third gate insulating layer GI3 may include silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) or silicon oxide carbide (SiO) x C y Inorganic materials such as ) can be used alone or in combination with each other.

[0169] The second gate electrode GE2 can be disposed on the third gate insulating layer GI3. In the planar view, the second gate electrode GE2 can overlap with the channel region of the second active pattern ACT2.

[0170] For example, the second gate electrode GE2 may include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides. These materials may be used alone or in combination with each other.

[0171] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0172] An interlayer insulating layer (ILD) can be disposed on the second gate electrode GE2. The ILD can fully cover the second gate electrode GE2. For example, the ILD can cover the second gate electrode GE2 and can be disposed along the contour of the second gate electrode GE2.

[0173] The third contact electrode SE2 and the fourth contact electrode DE2 can be disposed on the interlayer insulating layer (ILD). The third contact electrode SE2 can contact the first contact area of ​​the second active pattern ACT2. For example, the third contact electrode SE2 can contact the first contact area of ​​the second active pattern ACT2 through a contact hole defined by the interlayer insulating layer (ILD). The fourth contact electrode DE2 can contact the second contact area of ​​the second active pattern ACT2. For example, the fourth contact electrode DE2 can contact the second contact area of ​​the second active pattern ACT2 through a contact hole defined by the interlayer insulating layer (ILD).

[0174] For example, each of the third contact electrode SE2 and the fourth contact electrode DE2 may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. These materials may be used individually or in combination with each other.

[0175] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN)x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0176] In an embodiment, the third contact electrode SE2 may contact the second lower metal pattern BML2. For example, the third contact electrode SE2 may contact the second lower metal pattern BML2 through a contact hole defined by the interlayer insulating layer ILD and the buffer layer BUF. However, this disclosure is not limited thereto. For example, if the second gate electrode GE2 is in contact with the second lower metal pattern BML2, the third contact electrode SE2 may not be in contact with the second lower metal pattern BML2.

[0177] In this embodiment, the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 may be disposed on the interlayer insulating layer (ILD). Each of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 may be disposed in the non-display area (NDA). For example, each of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 may be disposed in the gate driver 200.

[0178] The second conductive layer CL2 can be spaced apart from the first conductive layer CL1 in a plan view. For example, in a cross-sectional view, the second conductive layer CL2 can be spaced apart from the first conductive layer CL1 in the first direction DR1. The third conductive layer CL3 can be spaced apart from the second conductive layer CL2 in a plan view. For example, in a cross-sectional view, the third conductive layer CL3 can be spaced apart from the second conductive layer CL2 in the first direction DR1. The fourth conductive layer CL4 can be spaced apart from the third conductive layer CL3 in a plan view. For example, in a cross-sectional view, the fourth conductive layer CL4 can be spaced apart from the third conductive layer CL3 in the first direction DR1.

[0179] In this embodiment, the clock signal can be applied through the first conductive layer CL1. For example, the first conductive layer CL1 can be... Figure 4 It is a portion of one of the first clock lines CLK1_SC, CLK2_SC, CLK3_SC, and CLK4_SC. In another embodiment, the first conductive layer CL1 may be... Figure 4 A portion of one of the second clock lines CLK1_SS, CLK2_SS, CLK3_SS, and CLK4_SS. However, this disclosure is not limited thereto, and signals other than the clock signal can be applied to the first conductive layer CL1. For example, Figure 4 The first power supply voltage VGH or the second power supply voltage VGL can be applied to the first conductive layer CL1.

[0180] In this embodiment, the clock signal can be applied through the second conductive layer CL2. For example, the second conductive layer CL2 can be... Figure 4 It is a portion of one of the first clock lines CLK1_SC, CLK2_SC, CLK3_SC, and CLK4_SC. In another embodiment, the second conductive layer CL2 may be... Figure 4 A portion of one of the second clock lines CLK1_SS, CLK2_SS, CLK3_SS, and CLK4_SS. However, this disclosure is not limited thereto, and signals other than the clock signal can be applied to the second conductive layer CL2. For example, Figure 4 The first power supply voltage VGH or the second power supply voltage VGL can be applied to the second conductive layer CL2.

[0181] In this embodiment, the clock signal can be applied through the third conductive layer CL3. For example, the third conductive layer CL3 can be... Figure 4 It is a portion of one of the first clock lines CLK1_SC, CLK2_SC, CLK3_SC, and CLK4_SC. In another embodiment, the third conductive layer CL3 may be... Figure 4 A portion of one of the second clock lines CLK1_SS, CLK2_SS, CLK3_SS, and CLK4_SS. However, this disclosure is not limited thereto, and signals other than the clock signal can be applied to the third conductive layer CL3. For example, Figure 4 The first power supply voltage VGH or the second power supply voltage VGL can be applied to the third conductive layer CL3.

[0182] In this embodiment, the clock signal can be applied through the fourth conductive layer CL4. For example, the fourth conductive layer CL4 can be... Figure 4 It is a portion of one of the first clock lines CLK1_SC, CLK2_SC, CLK3_SC, and CLK4_SC. In another embodiment, the fourth conductive layer CL4 may be... Figure 4 A portion of one of the second clock lines CLK1_SS, CLK2_SS, CLK3_SS, and CLK4_SS. However, this disclosure is not limited thereto, and signals other than the clock signal can be applied to the fourth conductive layer CL4. For example, Figure 4 The first power supply voltage VGH or the second power supply voltage VGL can be applied to the fourth conductive layer CL4.

[0183] The first conductive layer CL1 can contact the first lower auxiliary electrode BE1. For example, the first conductive layer CL1 can contact the first lower auxiliary electrode BE1 through a contact hole defined by the interlayer insulating layer ILD and the buffer layer BUF. The second conductive layer CL2 can contact the second lower auxiliary electrode BE2. For example, the second conductive layer CL2 can contact the second lower auxiliary electrode BE2 through a contact hole defined by the interlayer insulating layer ILD and the buffer layer BUF. The third conductive layer CL3 can contact the third lower auxiliary electrode BE3. For example, the third conductive layer CL3 can contact the third lower auxiliary electrode BE3 through a contact hole defined by the interlayer insulating layer ILD and the buffer layer BUF. The fourth conductive layer CL4 can contact the fourth lower auxiliary electrode BE4. For example, the fourth conductive layer CL4 can contact the fourth lower auxiliary electrode BE4 through a contact hole defined by the interlayer insulating layer ILD and the buffer layer BUF.

[0184] For example, each of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. These materials may be used individually or in combination with each other.

[0185] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0186] In an embodiment, the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the third contact electrode SE2 may be disposed in the same layer and may comprise substantially the same material. However, this disclosure is not limited thereto.

[0187] The passivation layer PVX can be disposed on the interlayer insulating layer ILD. The passivation layer PVX can cover the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, the third contact electrode SE2, and the fourth contact electrode DE2. For example, the passivation layer PVX can be referred to as the first insulating layer.

[0188] The through-hole insulating layer VIA can be disposed on the passivation layer PVX.

[0189] The second pixel electrode PE2 can be disposed on the via insulating layer VIA. The second pixel electrode PE2 can be disposed in the display area DA. The second pixel electrode PE2 can contact the third contact electrode SE2. For example, the second pixel electrode PE2 can contact the third contact electrode SE2 through a contact hole defined by the via insulating layer VIA and the passivation layer PVX.

[0190] For example, the second pixel electrode PE2 may include metals, alloys, metal nitrides, conductive metal oxides, or transparent conductive materials. These materials may be used individually or in combination. In an embodiment, the second pixel electrode PE2 may have a stacked structure including ITO / Ag / ITO. The second pixel electrode PE2 may operate as an anode. For example, the second pixel electrode PE2 may be referred to as the first electrode.

[0191] The pixel defining layer (PDL) can be disposed on the via insulating layer (VIA). The PDL can cover the side of the second pixel electrode (PE2). For example, a pixel opening can be defined in the PDL to expose at least a portion of the upper surface of the second pixel electrode (PE2).

[0192] The second light-emitting layer EML2 can be disposed on the second pixel electrode PE2 and the pixel defining layer PDL. A portion of the second light-emitting layer EML2 can be disposed in a pixel opening of the pixel defining layer PDL. In an embodiment, the second light-emitting layer EML2 may include a first functional layer containing organic material, a light-emitting layer containing light-emitting material, and a second functional layer containing organic material disposed on the light-emitting layer. For example, the first functional layer may include a hole injection layer and a hole transport layer, and the second functional layer may include an electron transport layer and an electron injection layer, etc.

[0193] In an embodiment, the second light-emitting layer EML2 can be connected to the first light-emitting layer (e.g., Figure 5 The first light-emitting layer (EML1). For example, the first light-emitting layer and the second light-emitting layer (EML2) can constitute a single light-emitting layer. However, this disclosure is not limited thereto, and the second light-emitting layer (EML2) can be separated from the first light-emitting layer.

[0194] The second common electrode CE2 can be disposed on the second light-emitting layer EML2. The second common electrode CE2 can include metals, alloys, metal nitrides, conductive metal oxides, or transparent conductive materials, etc. These materials can be used individually or in combination. The second common electrode CE2 can operate as a cathode. For example, the second common electrode CE2 can be referred to as the second electrode.

[0195] In an embodiment, the second common electrode CE2 can be connected to the first common electrode (e.g., Figure 5The first common electrode CE1). For example, the first common electrode and the second common electrode CE2 can constitute a common electrode. However, this disclosure is not limited thereto, and the second common electrode CE2 can be separated from the first common electrode.

[0196] The encapsulation layer TFE can be disposed on the second common electrode CE2. As described above, the encapsulation layer TFE may include a first inorganic encapsulation layer L1, an organic encapsulation layer L2, and a second inorganic encapsulation layer L3.

[0197] The encapsulation layer TFE can extend across the entire display area DA and the non-display area NDA. For example, the first inorganic encapsulation layer L1 and the second inorganic encapsulation layer L3 can cover the display area DA and extend beyond the second barrier D2. In an embodiment, the first inorganic encapsulation layer L1 and the second inorganic encapsulation layer L3 can extend to the upper surface of the support member SP.

[0198] The first dam D1 and the second dam D2 can be disposed in the non-display area NDA. For example, the first dam D1 and the second dam D2 can be disposed on the passivation layer PVX in the non-display area NDA. The first dam D1 and the second dam D2 can be spaced apart from each other in a plan view. In a cross-sectional view, the first dam D1 can be spaced apart from the via insulating layer VIA in a direction opposite to the first direction DR1. The second dam D2 can be disposed outside the first dam D1, and in a cross-sectional view, it can be spaced apart from the first dam D1 in a direction opposite to the first direction DR1.

[0199] When the encapsulation layer TFE is formed, the first dam D1 and the second dam D2 can prevent the encapsulation layer TFE from being in the edge direction of the substrate SUB (e.g., with). Figure 6 Overflow in the direction opposite to the first direction DR1. For example, the first dam D1 and the second dam D2 can prevent the organic encapsulation layer L2, which includes organic insulating material, from overflowing in the edge direction of the substrate SUB.

[0200] The first dam D1 may include a first layer D1-L1 and a second layer D1-L2. The first layer D1-L1 and the through-hole insulating layer VIA may include substantially the same material. The second layer D1-L2 may be disposed on the first layer D1-L1. The second layer D1-L2 and the pixel defining layer PDL may include substantially the same material.

[0201] The second dam D2 may include a first layer D2-L1 and a second layer D2-L2. The first layer D2-L1 and the through-hole insulating layer VIA may include substantially the same material. The second layer D2-L2 may be disposed on the first layer D2-L1. The second layer D2-L2 and the pixel defining layer PDL may include substantially the same material.

[0202] The support member SP can be disposed in the non-display area NDA. For example, the support member SP can be disposed on the passivation layer PVX in the non-display area NDA. The support member SP can be disposed outside the second dam D2, and in the cross-sectional view, it can be spaced apart from the second dam D2 in a direction opposite to the first direction DR1.

[0203] When the encapsulation layer TFE is formed, the support member SP can prevent the encapsulation layer TFE from overflowing in the edge direction of the substrate SUB. For example, the support member SP can prevent the organic encapsulation layer L2, which includes organic insulating material, from overflowing in the edge direction of the substrate SUB. The support member SP can also act as a support for the deposition mask used when depositing the second light-emitting layer EML2.

[0204] In one embodiment, the support member SP may overlap with some of the multiple conductive layers disposed on the interlayer insulating layer ILD in a plan view. In another embodiment, the support member SP may overlap with the third conductive layer CL3 and the fourth conductive layer CL4 in a plan view. However, this disclosure is not limited thereto, and in another embodiment, the support member SP may overlap with the fourth conductive layer CL4 in a plan view, and may not overlap with the third conductive layer CL3 in a plan view. In another embodiment, the support member SP may overlap with the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 in a plan view. In yet another embodiment, the support member SP may overlap with the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 in a plan view.

[0205] The support component SP may include a first layer SP-L1 and a second layer SP-L2. The first layer SP-L1 and the through-hole insulating layer VIA may include substantially the same material. The second layer SP-L2 may be disposed on the first layer SP-L1. The second layer SP-L2 and the pixel defining layer PDL may include substantially the same material.

[0206] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 It is a diagram manufacturing process. Figure 1 A schematic cross-sectional view of a method for displaying a device.

[0207] For example, Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 It is based on the illustration manufacturing Figure 5 A schematic cross-sectional view of a method for displaying a cross-sectional view of a device. Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 It is based on the illustration manufacturing Figure 6 A schematic cross-sectional view of a method for displaying a cross-sectional view of a device.

[0208] refer to Figure 7 The first lower metal pattern BML1 can be formed on the substrate SUB. The first lower metal pattern BML1 can be formed in the display area DA. For example, the first lower metal pattern BML1 can include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides. These materials can be used alone or in combination with each other.

[0209] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0210] A buffer layer BUF can be formed on the substrate SUB. The buffer layer BUF can be formed to cover the first lower metal pattern BML1. For example, the buffer layer BUF may include silicon oxide (SiO2) and other materials. x ), silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) or silicon oxide carbide (SiO) x Cy Inorganic materials such as ) can be used alone or in combination with each other.

[0211] The first transistor TR1 can be formed on the substrate SUB. For example, the first active pattern ACT1 can be formed on the buffer layer BUF, the first gate electrode GE1 can be formed on the first gate insulating layer GI1, and the first contact electrode SE1 and the second contact electrode DE1 can be formed on the interlayer insulating layer ILD.

[0212] The first active pattern ACT1 may be formed to at least partially overlap with the first lower metal pattern BML1 in a planar view. For example, the first active pattern ACT1 may include an oxide semiconductor material, a silicon semiconductor material, and / or an organic semiconductor material. The first active pattern ACT1 may include a first contact region, a second contact region, and a channel region between the first contact region and the second contact region. The first contact region and the second contact region may have a higher conductivity than the channel region.

[0213] In one embodiment, the first active pattern ACT1 may include an oxide semiconductor material. However, this disclosure is not limited thereto, and in another embodiment, the first active pattern ACT1 may include a silicon semiconductor material. Examples of oxide semiconductor materials that can be used as the first active pattern ACT1 may include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), or indium tin zinc oxide (ITZO), etc. These materials may be used alone or in combination with each other.

[0214] The second gate insulating layer GI2 can be formed on the buffer layer BUF. The second gate insulating layer GI2 can be formed in the non-display area NDA. For example, the second gate insulating layer GI2 can be formed in the first pad area PA1.

[0215] For example, the second gate insulating layer GI2 may include silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) or silicon oxide carbide (SiO) x C y Inorganic materials such as GI2 and GI1. These materials can be used alone or in combination with each other. The second gate insulating layer GI2 and the first gate insulating layer GI1 can comprise substantially the same material and can be formed by the same process.

[0216] A first gate insulating layer GI1 may be formed on a first active pattern ACT1. The first gate insulating layer GI1 may be formed to cover at least a portion of the first active pattern ACT1. For example, the first gate insulating layer GI1 may be formed to cover the upper surface of the first active pattern ACT1.

[0217] For example, the first gate insulating layer GI1 may include silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) or silicon oxide carbide (SiO) x C y Inorganic materials such as ) can be used alone or in combination with each other.

[0218] As described above, the first gate electrode GE1 can be formed on the first gate insulating layer GI1. The first gate electrode GE1 can overlap with the channel region of the first active pattern ACT1 in a planar view.

[0219] For example, the first gate electrode GE1 may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. These materials may be used alone or in combination with each other.

[0220] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0221] The first auxiliary pad electrode PEA can be formed on the second gate insulating layer GI2. For example, the first auxiliary pad electrode PEA can be formed in the first pad region PA1. For example, the first auxiliary pad electrode PEA can include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides. These materials can be used alone or in combination with each other.

[0222] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0223] In an embodiment, the first auxiliary pad electrode PEA and the first gate electrode GE1 may comprise substantially the same material and may be formed by the same process.

[0224] An interlayer insulating layer (ILD) can be formed on the first gate electrode GE1 and the first auxiliary pad electrode PEA. The ILD can be formed to fully cover the first gate electrode GE1 and the first auxiliary pad electrode PEA.

[0225] For example, the interlayer insulating layer (ILD) may include silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) or silicon oxide carbide (SiO) x C y Inorganic materials such as ) can be used alone or in combination with each other.

[0226] The first contact electrode SE1, the second contact electrode DE1, and the second auxiliary pad electrode PEB can be formed on the interlayer insulating layer ILD. The first contact electrode SE1 and the second contact electrode DE1 can be formed in the display area DA, and the second auxiliary pad electrode PEB can be formed in the first pad area PA1.

[0227] Contact holes for connecting the first contact area of ​​the first contact electrode SE1 and the first active pattern ACT1 can be formed in the interlayer insulating layer (ILD). Contact holes for connecting the second contact electrode DE1 and the second contact area of ​​the first active pattern ACT1 can be formed in the ILD. Contact holes for connecting the second auxiliary pad electrode PEB and the first auxiliary pad electrode PEA can be formed in the ILD.

[0228] For example, each of the first contact electrode SE1, the second contact electrode DE1, and the second auxiliary pad electrode PEB may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. These materials may be used individually or in combination with each other.

[0229] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0230] In an embodiment, the first contact electrode SE1, the second contact electrode DE1, and the second auxiliary pad electrode PEB may comprise substantially the same material and may be formed by the same process.

[0231] In an embodiment, a contact hole for connecting the first contact electrode SE1 and the first lower metal pattern BML1 can be formed in the interlayer insulating layer ILD and the buffer layer BUF.

[0232] The first auxiliary pad electrode PEA and the second auxiliary pad electrode PEB can constitute the first pad electrode PEC1.

[0233] refer to Figure 8 The initial passivation layer PPVX can be formed on the interlayer insulating layer (ILD). The initial passivation layer PPVX can be formed to cover the first contact electrode SE1, the second contact electrode DE1, and the second auxiliary pad electrode PEB. For example, the initial passivation layer PPVX can be referred to as the first initial insulating layer.

[0234] For example, the initial passivation layer PPVX can include silicon oxide (SiO2) and other similar materials. x ), silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) or silicon oxide carbide (SiO) x C y Inorganic materials such as ) can be used alone or in combination with each other.

[0235] refer to Figure 9A first preliminary via insulating layer PVA1 can be formed on the preliminary passivation layer PPVX. The first preliminary via insulating layer PVA1 can include a first portion PVA-S1 and a second portion PVA-S2. The first portion PVA-S1 can be a portion that at least partially overlaps with the first transistor TR1 in a planar view. The second portion PVA-S2 can be a portion that at least partially overlaps with the first pad electrode PEC1 in a planar view. The second portion PVA-S2 can contact the first portion PVA-S1 in the second direction DR2.

[0236] In this embodiment, the first portion PVIA-S1 and the second portion PVIA-S2 may have different thicknesses on the third-direction DR3. For example, the thickness H1 of the first portion PVIA-S1 may be greater than the thickness H2 of the second portion PVIA-S2.

[0237] For example, a first preliminary via insulating layer PVIA1, comprising a first portion PVIA-S1 and a second portion PVIA-S2, can be formed using a halftone mask comprising a light-transmitting region and a semi-light-transmitting region. For example, a semi-light-transmitting region can be a region through which light is transmitted through the halftone mask, and a semi-light-transmitting region can be a region through which less light than the light passing through the light-transmitting region is transmitted through the halftone mask. For example, the first preliminary via insulating layer PVIA1 can be referred to as a second preliminary insulating layer.

[0238] refer to Figure 10 The first opening VIA-OP can be formed in the first preliminary via insulating layer PVIA1. For example, the first opening VIA-OP can be formed in a second portion PVIA-S2 of the first preliminary via insulating layer PVIA1. For example, at least a portion of the first preliminary via insulating layer PVIA1 can be removed in the first pad area PA1 to form the first opening VIA-OP.

[0239] refer to Figure 11 The second opening OP can be formed in the initial passivation layer (e.g., Figure 10The initial passivation layer (PPVX) is formed in the first pad region PA1. Accordingly, a passivation layer (PVX) can be formed. For example, at least a portion of the initial passivation layer (PPVX) can be removed from the first pad region PA1 to form a second opening (OP). The second opening (OP) can at least partially overlap with the first opening (VIA-OP) in a plan view. For example, the second opening (OP) and the first opening (VIA-OP) can be connected to form an opening. The upper surface of the second auxiliary pad electrode (PEB) can be exposed through the second opening (OP). For example, the upper surface of the second auxiliary pad electrode (PEB) can be exposed through the second opening (OP) and the first opening (VIA-OP). The second opening (OP) can be connected with... Figure 5 The opening OP corresponds to this.

[0240] refer to Figure 12 This can remove the first preliminary through-hole insulation layer (e.g., Figure 10 At least a portion of the first preliminary via insulating layer (PVIA1). In an embodiment, a second portion of the first preliminary via insulating layer (e.g., Figure 11 The second part of PVIA-S2). The first part of the first preliminary through-hole insulation layer can be removed (e.g., Figure 11 A portion of the first part of the PVIA-S1. In an embodiment, this portion of the first preliminary via insulating layer and the second portion of the first preliminary via insulating layer can be removed by a plasma ashing process. For example, this portion of the first preliminary via insulating layer and the second portion of the first preliminary via insulating layer can be removed by an oxygen (O2) plasma ashing process. For example, by plasma ashing, the second portion of the first preliminary via insulating layer can be completely removed, and the thickness of the first portion of the first preliminary via insulating layer can be reduced (e.g., Figure 11 The thickness H1). Accordingly, a via insulating layer VIA can be formed. The thickness H3 of the via insulating layer VIA on the third-direction DR3 can be less than the thickness of the first portion of the first preliminary via insulating layer (e.g., Figure 11 Thickness H1).

[0241] In an embodiment, after removing at least a portion of the first preliminary via insulating layer, a plasma treatment can be performed on the passivation layer PVX. For example, a nitrogen (N2) plasma treatment can be performed on the passivation layer PVX. As described above, the first preliminary via insulating layer can be removed by an oxygen plasma ashing process. This includes materials such as silicon nitride (SiN2). x ), silicon oxynitride (SiO) x N yThe passivation layer PVX of the nitride may be oxidized to transform it into an oxygen-rich insulating layer. Accordingly, the passivation layer PVX can be an insulating layer susceptible to moisture, etc. Consequently, moisture, etc., can penetrate into the vicinity of the metal disposed beneath the passivation layer PVX. According to an embodiment, the passivation layer PVX, oxidized by an oxygen plasma ashing process, can be re-nitrided by performing nitrogen plasma treatment. Therefore, it is possible to prevent moisture, etc., from penetrating into the metal disposed beneath the passivation layer PVX.

[0242] refer to Figure 13 The first pixel electrode PE1 can be formed on the via insulating layer VIA. The first pixel electrode PE1 can be formed in the display area DA. A contact hole for connecting the first pixel electrode PE1 and the first contact electrode SE1 can be formed in the via insulating layer VIA and the passivation layer PVX.

[0243] For example, the first pixel electrode PE1 may include metals, alloys, metal nitrides, conductive metal oxides, or transparent conductive materials. These materials may be used individually or in combination. In an embodiment, the first pixel electrode PE1 may have a stacked structure including ITO / Ag / ITO. The first pixel electrode PE1 may function as an anode.

[0244] refer to Figure 14 The pixel defining layer (PDL) can be formed on the via insulating layer (VIA). The PDL can be formed to cover the side of the first pixel electrode (PE1). For example, a pixel opening exposing at least a portion of the upper surface of the first pixel electrode (PE1) can be formed in the PDL.

[0245] For example, the pixel defining layer (PDL) may include inorganic or organic materials. In one embodiment, the PDL may include organic materials such as epoxy resin or silicone resin. These materials may be used alone or in combination with each other. In another embodiment, the PDL may further include a light-shielding material comprising a black pigment or black dye, etc.

[0246] refer to Figure 15 A first light-emitting layer EML1 can be formed on the first pixel electrode PE1 and the pixel defining layer PDL. A portion of the first light-emitting layer EML1 can be formed in a pixel opening of the pixel defining layer PDL. In an embodiment, the first light-emitting layer EML1 may include a first functional layer containing an organic material, a light-emitting layer containing a light-emitting material, and a second functional layer containing an organic material. For example, the first functional layer may include a hole injection layer and a hole transport layer, and the second functional layer may include an electron transport layer and an electron injection layer, etc.

[0247] The first common electrode CE1 can be formed on the first light-emitting layer EML1. The first common electrode CE1 can include metals, alloys, metal nitrides, conductive metal oxides, or transparent conductive materials, etc. These materials can be used alone or in combination with each other. The first common electrode CE1 can operate as a cathode.

[0248] refer to Figure 16 The encapsulation layer TFE can be formed on the first common electrode CE1. For example, a first inorganic encapsulation layer L1 can be formed covering the first common electrode CE1, the pixel defining layer PDL, and the through-hole insulating layer VIA. An organic encapsulation layer L2 can be formed on the first inorganic encapsulation layer L1. A second inorganic encapsulation layer L3 can be formed on the organic encapsulation layer L2. Each of the first inorganic encapsulation layer L1 and the second inorganic encapsulation layer L3 may include inorganic materials, and the organic encapsulation layer L2 may include organic materials.

[0249] The driver chip IC can be attached to the first pad area PA1. For example, a connecting member ACF can be formed in the second opening OP, and the driver chip IC and the first pad electrode PEC1 can be electrically connected through the connecting member ACF. For example, the driver chip IC and the second auxiliary pad electrode PEB can be electrically connected through the connecting member ACF.

[0250] In an embodiment, the connecting member ACF may include an anisotropic conductive film. For example, the connecting member ACF may include an adhesive layer and conductive particles. Each of the conductive particles may include a core comprising an insulating polymer material and a conductive layer surrounding the core comprising a conductive metallic material.

[0251] refer to Figure 17 The second lower metal pattern BML2, the first lower auxiliary electrode BE1, the second lower auxiliary electrode BE2, the third lower auxiliary electrode BE3, and the fourth lower auxiliary electrode BE4 can be formed on the substrate SUB. The first lower auxiliary electrode BE1, the second lower auxiliary electrode BE2, the third lower auxiliary electrode BE3, and the fourth lower auxiliary electrode BE4 can be formed in the non-display area NDA. The second lower metal pattern BML2 can be formed in the display area DA, for example, in the portion of the display area DA adjacent to the non-display area NDA.

[0252] For example, each of the second lower metal pattern BML2, the first lower auxiliary electrode BE1, the second lower auxiliary electrode BE2, the third lower auxiliary electrode BE3, and the fourth lower auxiliary electrode BE4 may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. These materials may be used individually or in combination with each other.

[0253] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0254] In an embodiment, the second lower metal pattern BML2, the first lower auxiliary electrode BE1, the second lower auxiliary electrode BE2, the third lower auxiliary electrode BE3, and the fourth lower auxiliary electrode BE4 may comprise substantially the same material and may be formed by the same process.

[0255] The buffer layer BUF can be formed on the substrate SUB. The buffer layer BUF can cover the second lower metal pattern BML2, the first lower auxiliary electrode BE1, the second lower auxiliary electrode BE2, the third lower auxiliary electrode BE3, and the fourth lower auxiliary electrode BE4.

[0256] The second transistor TR2 can be formed on the substrate SUB. For example, the second active pattern ACT2 can be formed on the buffer layer BUF, the second gate electrode GE2 can be formed on the third gate insulating layer GI3, and the third contact electrode SE2 and the fourth contact electrode DE2 can be formed on the interlayer insulating layer ILD.

[0257] The second active pattern ACT2 can be formed on the buffer layer BUF. The second active pattern ACT2 can be formed to at least partially overlap with the second lower metal pattern BML2 in a planar view. For example, the second active pattern ACT2 can include an oxide semiconductor material, a silicon semiconductor material, and / or an organic semiconductor material. The second active pattern ACT2 can include a first contact region, a second contact region, and a channel region between the first and second contact regions. The first and second contact regions can have a higher conductivity than the channel region.

[0258] In one embodiment, the second active pattern ACT2 may include an oxide semiconductor material. However, this disclosure is not limited thereto, and in another embodiment, the second active pattern ACT2 may include a silicon semiconductor material. Examples of oxide semiconductor materials that can be used as the second active pattern ACT2 may include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), or indium tin zinc oxide (ITZO), etc. These materials may be used alone or in combination with each other.

[0259] A third gate insulating layer GI3 may be formed on the second active pattern ACT2. The third gate insulating layer GI3 may be formed to cover at least a portion of the second active pattern ACT2. For example, the third gate insulating layer GI3 may be formed to cover the upper surface of the second active pattern ACT2.

[0260] For example, the third gate insulating layer GI3 may include silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) or silicon oxide carbide (SiO) x C y Inorganic materials such as ) can be used alone or in combination with each other.

[0261] The second gate electrode GE2 can be formed on the third gate insulating layer GI3. In a planar view, the second gate electrode GE2 can overlap with the channel region of the second active pattern ACT2. For example, the second gate electrode GE2 can include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides. These materials can be used individually or in combination with each other.

[0262] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0263] An interlayer insulating layer (ILD) can be formed on the second gate electrode GE2. The ILD can be formed to fully cover the second gate electrode GE2.

[0264] The first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, the third contact electrode SE2, and the fourth contact electrode DE2 can be formed on the interlayer insulating layer ILD. The first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 can be formed in the non-display area NDA.

[0265] Contact holes for connecting the first conductive layer CL1 and the first lower auxiliary electrode BE1 can be formed in the interlayer insulating layer ILD and the buffer layer BUF. Contact holes for connecting the second conductive layer CL2 and the second lower auxiliary electrode BE2 can be formed in the interlayer insulating layer ILD and the buffer layer BUF. Contact holes for connecting the third conductive layer CL3 and the third lower auxiliary electrode BE3 can be formed in the interlayer insulating layer ILD and the buffer layer BUF. Contact holes for connecting the fourth conductive layer CL4 and the fourth lower auxiliary electrode BE4 can be formed in the interlayer insulating layer ILD and the buffer layer BUF.

[0266] The third contact electrode SE2 and the fourth contact electrode DE2 can be formed in the display area DA. A contact hole for connecting the third contact electrode SE2 and the first contact area of ​​the second active pattern ACT2 can be formed in the interlayer insulating layer (ILD). A contact hole for connecting the fourth contact electrode DE2 and the second contact area of ​​the second active pattern ACT2 can be formed in the interlayer insulating layer (ILD). A contact hole for connecting the third contact electrode SE2 and the second lower metal pattern BML2 can be formed in the interlayer insulating layer (ILD) and the buffer layer (BUF).

[0267] Each of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, the third contact electrode SE2, and the fourth contact electrode DE2 may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. These materials may be used individually or in combination with each other.

[0268] Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc). These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide. These materials can be used alone or in combination with each other. Examples of metal nitrides may include aluminum nitrides (AlN). x ), tungsten nitride (WN) x ) or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0269] In the embodiments, the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, the third contact electrode SE2, and the fourth contact electrode DE2 may comprise substantially the same material and may be formed by the same process.

[0270] refer to Figure 18The passivation layer PVX can be formed on the interlayer insulating layer ILD. The passivation layer PVX can be formed to cover the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, the third contact electrode SE2, and the fourth contact electrode DE2. As described above, the passivation layer PVX can be referred to as the first insulating layer.

[0271] refer to Figure 19 A second preliminary via insulating layer PVIA2, a first preliminary dam PD1, a second preliminary dam PD2, and a protective insulating layer PSP can be formed on the passivation layer PVX. The second preliminary via insulating layer PVIA2 can be formed throughout the display area DA and the non-display area NDA. The second preliminary via insulating layer PVIA2 can be formed to overlap with the second transistor TR2 in a plan view. The first preliminary dam PD1 can be formed outside the second preliminary via insulating layer PVIA2. For example, in a cross-sectional view, the first preliminary dam PD1 can be spaced apart from the second preliminary via insulating layer PVIA2 in a direction opposite to the first direction DR1. The second preliminary dam PD2 can be formed outside the first preliminary dam PD1. For example, in a cross-sectional view, the second preliminary dam PD2 can be spaced apart from the first preliminary dam PD1 in a direction opposite to the first direction DR1. The protective insulating layer PSP can be formed outside the second preliminary dam PD2. For example, in a cross-sectional view, the protective insulating layer PSP can be spaced apart from the second preliminary dam PD2 in a direction opposite to the first direction DR1.

[0272] In one embodiment, the protective insulating layer PSP may at least partially overlap with a plurality of conductive layers disposed on the interlayer insulating layer ILD in a plan view. For example, the protective insulating layer PSP may overlap with the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 in a plan view. However, this disclosure is not limited thereto, and in another embodiment, the protective insulating layer PSP may overlap with only some of the conductive layers in a plan view. For example, the protective insulating layer PSP may overlap with the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 in a plan view, and may not overlap with the first conductive layer CL1 in a plan view.

[0273] In an embodiment, the protective insulating layer PSP may include a first portion PSP1 and a second portion PSP2. In a cross-sectional view, the second portion PSP2 may contact the first portion PSP1 in a direction opposite to the first direction DR1. In an embodiment, the thickness H4 of the first portion PSP1 may be greater than the thickness H5 of the second portion PSP2. For example, the thickness H4 of the first portion PSP1 on the third direction DR3 may be greater than the thickness H5 of the second portion PSP2 on the third direction DR3. In an embodiment, the thickness H4 of the first portion PSP1 on the third direction DR3, the thickness of the second preliminary through-hole insulating layer PVIA2 on the third direction DR3, the thickness of the first preliminary dam PD1 on the third direction DR3, and the thickness of the second preliminary dam PD2 on the third direction DR3 may be substantially the same.

[0274] For example, the protective insulating layer PSP comprising a first part PSP1 and a second part PSP2 can be formed by a halftone mask comprising a light-transmitting area and a semi-light-transmitting area. For example, the semi-light-transmitting area can be an area through which light is transmitted through the halftone mask, and the semi-light-transmitting area can be an area through which less light than the light passing through the light-transmitting area is transmitted through the halftone mask.

[0275] For example, each of the second preliminary through-hole insulating layer PVA2, the first preliminary dam PD1, the second preliminary dam PD2, and the protective insulating layer PSP may include an organic material. For example, each of the second preliminary through-hole insulating layer PVA2, the first preliminary dam PD1, the second preliminary dam PD2, and the protective insulating layer PSP may include an organic material such as phenolic resin, polyacrylate resin, polyimide resin, polyamide resin, silicone resin, or epoxy resin. These materials may be used alone or in combination with each other.

[0276] In this embodiment, the second preliminary through-hole insulating layer PVA2, the first preliminary barrier PD1, the second preliminary barrier PD2, and the protective insulating layer PSP may comprise substantially the same material and can be formed by the same process. For example, the second preliminary through-hole insulating layer PVA2, the first preliminary barrier PD1, the second preliminary barrier PD2, and the protective insulating layer PSP can be formed simultaneously.

[0277] refer to Figure 19 and Figure 20At least a portion of the protective insulating layer PSP can be removed. In an embodiment, a second portion of the protective insulating layer PSP, PSP2, can be removed. The second portion of PSP2 can be completely removed. At least a portion of the first portion of PSP1 can be removed. A portion of the first preliminary dam PD1, the second preliminary dam PD2, and the second preliminary through-hole insulating layer PVIA2 can be removed. In an embodiment, a portion of the first portion of PSP1, a portion of the first preliminary dam PD1, a portion of the second preliminary dam PD2, a portion of the second preliminary through-hole insulating layer PVIA2, and the second portion of PSP2 can be removed by a plasma ashing process. For example, this portion of the first portion of PSP1, this portion of the first preliminary dam PD1, this portion of the second preliminary dam PD2, this portion of the second preliminary through-hole insulating layer PVIA2, and the second portion of PSP2 can be removed by an oxygen plasma ashing process. For example, by plasma ashing, the second portion of PSP2 can be completely removed, and the thickness H4 of the first portion of PSP1 can be reduced. By employing plasma ashing technology, the thicknesses of the first preliminary dam PD1, the second preliminary dam PD2, and the second preliminary through-hole insulating layer PVIA2 can be reduced. Accordingly, support components (e.g., Figure 6 The first layer SP-L1 of the supporting component SP), the first retaining dam (e.g., Figure 6 The first layer of the first retaining dam (D1) is D1-L1, and the second retaining dam (e.g., Figure 6 The second layer D2-L1 of the second retaining dam (D2) and the through-hole insulation layer VIA.

[0278] The thickness H6 of the first layer SP-L1 of the support component on the third direction DR3 can be less than the thickness H4 of the first part PSP1.

[0279] When performing plasma ashing processes, including those involving silicon nitrides (SiN) x ), silicon oxynitride (SiO) x N yThe passivation layer PVX of the nitride may be oxidized to transform it into an oxygen-rich insulating layer. Accordingly, the passivation layer PVX can be an insulating layer susceptible to moisture, etc., and insulating layers such as support members disposed on the passivation layer PVX may warp. Consequently, moisture, etc., can penetrate into the vicinity of the metal disposed beneath the passivation layer PVX. For example, moisture, etc., may penetrate into the vicinity of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4, and parasitic capacitance may form near the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4. As described above, a clock signal can be applied through the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4. In the case where moisture, etc., penetrates into the vicinity of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4, the clock signal may be applied to the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 with a delay. Accordingly, the gate driver (e.g., Figure 4 The gate driver 200 may output an abnormal signal. Accordingly, this may occur in the display area (e.g., Figure 1 The problem of visually identifying the horizontal line in the display area (DA).

[0280] According to an embodiment, the protective insulating layer PSP can be formed in the portion of the passivation layer PVX that overlaps with the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 in a planar view. For example, the first portion PSP1 can be formed to overlap with the third conductive layer CL3 and the fourth conductive layer CL4 in a planar view, and the second portion PSP2 can be formed to overlap with the first conductive layer CL1 and the second conductive layer CL2 in a planar view. Accordingly, the protective insulating layer PSP can prevent the portion of the passivation layer PVX covering the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 from being transformed into an oxygen-rich insulating layer during the plasma ashing process. Therefore, moisture and the like can not penetrate into the vicinity of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4. Accordingly, the generation of parasitic capacitances in the vicinity of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 can be prevented. Accordingly, it can prevent the clock signal from being applied to the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, and the fourth conductive layer CL4 with a delay, and the gate driver can output a normal signal to the display area. Accordingly, the horizontal line may not be visible to the display area.

[0281] Following the plasma ashing process, the passivation layer PVX can be subjected to plasma treatment. For example, nitrogen (N2) plasma treatment can be performed on the passivation layer PVX. In the portions where the protective insulating layer PSP, the first preliminary dam PD1, the second preliminary dam PD2, and the second preliminary via insulating layer PVIA2 are not provided, the passivation layer PVX can be oxidized by the plasma ashing process. Accordingly, the oxidized passivation layer PVX can be re-nitrided by performing nitrogen plasma treatment on it.

[0282] refer to Figure 21 The second pixel electrode PE2 can be formed on the via insulating layer VIA. The second pixel electrode PE2 can also be formed in the display area DA. A contact hole for connecting the second pixel electrode PE2 and the third contact electrode SE2 can be formed in the via insulating layer VIA and the passivation layer PVX.

[0283] For example, the second pixel electrode PE2 may include metals, alloys, metal nitrides, conductive metal oxides, or transparent conductive materials. These materials may be used individually or in combination. In an embodiment, the second pixel electrode PE2 may have a stacked structure including ITO / Ag / ITO. The second pixel electrode PE2 can operate as an anode.

[0284] refer to Figure 22 The pixel defining layer (PDL) can be formed on the via insulating layer (VIA). The PDL can be formed to cover the side of the second pixel electrode (PE2). For example, a pixel opening exposing at least a portion of the upper surface of the second pixel electrode (PE2) can be formed in the PDL.

[0285] For example, the pixel defining layer (PDL) may include inorganic or organic materials. In one embodiment, the PDL may include organic materials such as epoxy resin or silicone resin. These materials may be used alone or in combination with each other. In another embodiment, the PDL may further include a light-shielding material comprising a black pigment or black dye.

[0286] The second layer D1-L2 can be formed on the first layer D1-L1 of the first dam D1. The second layer D2-L2 can be formed on the first layer D2-L1 of the second dam D2. The second layer SP-L2 can be formed on the first layer SP-L1 of the support member SP. The second layers D1-L2 of the first dam D1, the second layers D2-L2 of the second dam D2, the second layers SP-L2 of the support member SP, and the pixel defining layer PDL can all be made of substantially the same material and can be formed by the same process.

[0287] For example, a second layer D1-L2 can be formed on the first layer D1-L1 to form a first dam D1. A second layer D2-L2 can be formed on the first layer D2-L1 to form a second dam D2. A second layer SP-L2 can be formed on the first layer SP-L1 to form a support member SP. For example, the second layer SP-L2 of the support member SP can be referred to as a third insulating layer.

[0288] refer to Figure 23 The second light-emitting layer EML2 can be formed on the second pixel electrode PE2 and the pixel defining layer PDL. A portion of the second light-emitting layer EML2 can be disposed in a pixel opening of the pixel defining layer PDL. In an embodiment, the second light-emitting layer EML2 may include a first functional layer containing an organic material, a light-emitting layer containing a light-emitting material, and a second functional layer containing an organic material and disposed on the light-emitting layer. For example, the first functional layer may include a hole injection layer and a hole transport layer, and the second functional layer may include an electron transport layer and an electron injection layer, etc.

[0289] The second common electrode CE2 can be formed on the second light-emitting layer EML2. The second common electrode CE2 can include metals, alloys, metal nitrides, conductive metal oxides, or transparent conductive materials, etc. These materials can be used individually or in combination. The second common electrode CE2 can operate as a cathode.

[0290] refer to Figure 24 The encapsulation layer TFE can be formed on the second common electrode CE2. For example, a first inorganic encapsulation layer L1 can be formed covering the second common electrode CE2, the pixel defining layer PDL, and the through-hole insulating layer VIA. An organic encapsulation layer L2 can be formed on the first inorganic encapsulation layer L1. A second inorganic encapsulation layer L3 can be formed on the organic encapsulation layer L2. Each of the first inorganic encapsulation layer L1 and the second inorganic encapsulation layer L3 may include inorganic materials, and the organic encapsulation layer L2 may include organic materials.

[0291] The encapsulation layer TFE can be formed throughout the entire display area DA and the non-display area NDA. For example, the first inorganic encapsulation layer L1 and the second inorganic encapsulation layer L3 can cover the display area DA and can extend outside the second barrier D2. In an embodiment, the first inorganic encapsulation layer L1 and the second inorganic encapsulation layer L3 can extend to the upper surface of the support member SP.

[0292] Figure 25 This is a block diagram illustrating an electronic device according to an embodiment. Figure 26 It is shown in the diagram. Figure 25 The diagram shows an example of an electronic device implemented as a smartphone.

[0293] refer to Figure 25 and Figure 26The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. In this case, the display device 1060 may be... Figure 1 The display device DD. Additionally, the electronic device 1000 may further include several ports capable of communicating with video cards, sound cards, memory cards, and / or USB devices.

[0294] According to the embodiments, such as Figure 26 As illustrated, the electronic device 1000 can be implemented as a smartphone. However, this is exemplary, and according to embodiments, the electronic device 1000 can be implemented as various devices. For example, the electronic device 1000 can be implemented as a mobile phone, video phone, smart tablet, smartwatch, tablet PC, vehicle navigation device, computer monitor, laptop computer, and / or head-mounted display device, etc.

[0295] Processor 1010 may be a microprocessor, a central processing unit, and / or an application processor, etc. Processor 1010 may be connected to other components via address buses, control buses, and / or data buses, etc. In embodiments, processor 1010 may also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0296] The memory device 1020 can store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include a non-volatile memory device and / or a volatile memory device. Examples of non-volatile memory devices may include erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, nano-floating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) devices, and / or ferroelectric random access memory (FRAM) devices, etc. Examples of volatile memory devices may include dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and / or mobile DRAM devices, etc.

[0297] Storage device 1030 may include solid-state drives (SSDs), hard disk drives (HDDs), and / or CD-ROMs, etc.

[0298] Input / output device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and / or mouse, and output devices such as speakers and printers. In an embodiment, display device 1060 may be included in input / output device 1040.

[0299] Power supply 1050 can supply the power required for the operation of electronic device 1000. For example, power supply 1050 can supply the power required for the operation of display device 1060.

[0300] The display device 1060 can be connected to other components via a bus or other communication link.

[0301] This disclosure can be applied to various display devices. For example, this disclosure can be applied to various display devices such as those in vehicles, ships and aircraft, portable communication devices, display devices for exhibition or information transmission, and medical display devices.

[0302] The above description is an example of the technical features of this disclosure, and those skilled in the art to which this disclosure pertains will be able to make various modifications and changes. Therefore, the embodiments of this disclosure described above can be implemented individually or in combination with each other.

[0303] Therefore, the embodiments disclosed herein are not intended to limit the technical spirit of this disclosure, but rather to describe it, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the claims, and should be construed as including all technical spirit within the equivalent scope within the scope of this disclosure.

Claims

1. A method for manufacturing a display device, the method comprising: Transistors are formed on a substrate including a display area and a non-display area surrounding at least a portion of the display area; A first conductive layer is formed on the substrate in the non-display area; A first insulating layer is formed covering the first conductive layer and the transistor; A protective insulating layer is formed on the first insulating layer in a plan view, which at least partially overlaps with the first conductive layer. The protective insulating layer includes a first portion and a second portion having a thickness smaller than that of the first portion. A second insulating layer is formed on the first insulating layer that at least partially overlaps with the transistor in the plan view; Remove the second portion of the protective insulation layer; A first electrode connected to the transistor is formed on the second insulating layer; A pixel defining layer covering the side portion of the first electrode is formed on the second insulating layer; A light-emitting layer is formed on the first electrode; as well as A second electrode is formed on the light-emitting layer.

2. The method according to claim 1, wherein, The removal of the second portion of the protective insulating layer is performed by a plasma ashing process.

3. The method according to claim 1, further comprising: A preliminary dam is formed on the first insulating layer in the non-display area. The formation of the protective insulation layer and the formation of the preliminary dam are performed simultaneously.

4. The method according to claim 1, wherein, The first conductive layer is disposed in the gate driver, and the gate driver is disposed on the substrate in the non-display area.

5. The method according to claim 4, wherein, The clock signal is applied through the first conductive layer.

6. The method of claim 1, further comprising: A second conductive layer is formed on the substrate in the non-display area, spaced apart from the first conductive layer in the plan view. The first conductive layer and the second conductive layer are disposed on the same layer, and a clock signal is applied to the second conductive layer.

7. The method of claim 1, further comprising: After the removal of the second portion of the protective insulating layer, plasma treatment is performed on the first insulating layer.

8. The method according to claim 7, wherein, Plasma treatment of the first insulating layer is nitrogen plasma treatment of the first insulating layer.

9. The method according to claim 1, wherein, The thickness of the first portion of the protective insulation layer is reduced by removing the second portion of the protective insulation layer.

10. The method of claim 9, further comprising: A third insulating layer is formed on the first portion of the protective insulating layer having a reduced thickness, to form a support member including the first portion having the reduced thickness and the third insulating layer.

11. The method according to claim 1, wherein, The non-display area includes the pad area, and The method further includes: forming a first auxiliary pad electrode in the pad area on the substrate; and forming a second auxiliary pad electrode on the first auxiliary pad electrode.

12. The method according to claim 11, wherein, The formation of the first insulating layer includes: Forming a first preliminary insulating layer covering the second auxiliary pad electrode; and A first opening is formed in the first preliminary insulating layer to expose the upper surface of the second auxiliary pad electrode.

13. The method according to claim 12, wherein, The formation of the first opening in the first preliminary insulating layer includes: A second preliminary insulating layer is formed on the first preliminary insulating layer; A second opening overlapping the second auxiliary pad electrode in the plan view is formed in the second preliminary insulating layer; and The first opening, which overlaps with the second opening in the plan view, is formed in the first preliminary insulating layer.

14. The method of claim 13, further comprising: After the formation of the first opening, at least a portion of the second preliminary insulating layer is removed.

15. A method of manufacturing a display device, the method comprising: Transistors are formed on a substrate including a display area and a non-display area surrounding at least a portion of the display area; A conductive layer is formed on the substrate in the non-display area; A passivation layer is formed covering the conductive layer and the transistor; A protective insulating layer is formed on the passivation layer in a plan view, at least partially overlapping the conductive layer. The protective insulating layer includes a first portion and a second portion having a thickness smaller than that of the first portion. An insulating layer with a via is formed on the passivation layer, which at least partially overlaps with the transistor in the plan view; Remove the second portion of the protective insulation layer; A pixel electrode connected to the transistor is formed on the through-hole insulating layer; A pixel defining layer covering the side portion of the pixel electrode is formed on the through-hole insulating layer; A light-emitting layer is formed on the pixel electrode; as well as A common electrode is formed on the light-emitting layer.

16. The method according to claim 15, wherein, The removal of the second portion of the protective insulating layer is performed by a plasma ashing process.

17. The method of claim 15, further comprising: A preliminary dam is formed on the passivation layer in the non-display area. The formation of the protective insulation layer and the formation of the preliminary dam are performed simultaneously.

18. The method according to claim 15, wherein, The conductive layer is disposed in the gate driver, and the gate driver is disposed on the substrate in the non-display area.

19. The method according to claim 18, wherein, The clock signal is applied through the conductive layer.

20. The method of claim 15, further comprising: After the removal of the second portion of the protective insulating layer, plasma treatment is performed on the passivation layer.

21. An electronic device comprising: The display device manufactured by the method according to any one of claims 1-20; as well as A memory device configured to store data.

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