Self-emitting display device and method for manufacturing self-emitting display device

Abstract

This self-emission type display device is provided with: a first pixel circuit including a first transistor (T1) having a first channel layer (C1) including an oxide semiconductor; and a second pixel circuit having the same circuit configuration as the first pixel circuit and including a second transistor (T2) corresponding to the first transistor (T1) and having a second channel layer (C2) including an oxide semiconductor, the gate length (L2) of the second transistor (T2) being larger than the gate length (L1) of the first transistor (T1), and the gate length (L2) of the second transistor (T2) being smaller than the gate length (L1) of the first transistor (T1). The oxide semiconductor contained in the second transistor (T2) is reduced more than the oxide semiconductor contained in the first transistor (T1).

Description

Technical Field

[0001] This disclosure relates to a self-emissive display device and a method for manufacturing a self-emissive display device. Background Technology

[0002] Patent document 1 discloses that the thickness of the gate insulating film affects the threshold of the transistor.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2015-060996 (March 30, 2015) Summary of the Invention

[0006] The problem the invention aims to solve

[0007] The threshold of a transistor is affected by the gate length and the carrier concentration in the channel layer. Therefore, the actual threshold of the transistor will deviate, which can easily degrade display quality.

[0008] Solution for solving the problem

[0009] One aspect of this disclosure is a self-emissive display device configured as follows: comprising: a first pixel circuit including a first transistor having a first channel layer comprising an oxide semiconductor; and a second pixel circuit having the same circuit configuration as the first pixel circuit, including a second transistor corresponding to the first transistor, having a second channel layer comprising an oxide semiconductor, the gate length of the second transistor being greater than the gate length of the first transistor, and the oxide semiconductor contained in the second channel layer being more reduced than the oxide semiconductor contained in the first channel layer.

[0010] One aspect of this disclosure is a method for manufacturing a self-emissive display device, comprising: a step of forming a channel layer comprising an oxide semiconductor of a transistor; a step of forming a first insulating layer in contact with the channel layer; a step of etching the first insulating layer using a first plasma to form a hole penetrating the first insulating layer, or a step of introducing oxygen into the first insulating layer; a step of annealing the channel layer and the first insulating layer after the step of using the first plasma; a step of forming a conductor layer of material that becomes the gate electrode of the transistor; and a step of etching the conductor layer using a second plasma to form the gate electrode of the transistor from the conductor layer.

[0011] Invention Effects

[0012] According to one aspect of this disclosure, the display quality of a display device can be improved. Attached Figure Description

[0013] Figure 1 This is a top view showing an example configuration of a self-emissive display device according to one embodiment of the present disclosure.

[0014] Figure 2 It is shown Figure 1 A top perspective view of an example configuration of the first and second transistors shown.

[0015] Figure 3 It is shown Figure 1 A cross-sectional view of the configuration example of the first transistor and the second transistor shown.

[0016] Figure 4 It is shown Figure 1 A cross-sectional view of the configuration example of the first transistor and the second transistor shown.

[0017] Figure 5 This is a cross-sectional view illustrating an example of a method for manufacturing a self-emissive display device according to one embodiment of the present disclosure.

[0018] Figure 6 It is shown Figure 5 A top view showing an example of the intensity distribution of the plasma.

[0019] Figure 7 This is a cross-sectional view showing an example configuration of a self-emissive display device according to one embodiment of the present disclosure.

[0020] Figure 8 This is a cross-sectional view illustrating an example of a method for manufacturing a self-emissive display device according to one embodiment of the present disclosure.

[0021] Figure 9 This is a cross-sectional view showing an example configuration of a self-emissive display device according to one embodiment of the present disclosure.

[0022] Figure 10 This is a cross-sectional view illustrating an example of a method for manufacturing a self-emissive display device according to one embodiment of the present disclosure.

[0023] Figure 11 This is a cross-sectional view illustrating an example of a method for manufacturing a self-emissive display device according to one embodiment of the present disclosure. Detailed Implementation

[0024] [Implementation Method 1]

[0025] (constitute)

[0026] Figure 1This is a top view illustrating an example configuration of a self-emissive display device according to one embodiment of the present disclosure. Figure 1 As shown, the self-emissive display device 1 of this disclosure includes a display section DA comprising a plurality of pixels PX and a driving circuit 10 for driving the display section DA. Each of the plurality of pixels PX has a light-emitting element 2 and a pixel circuit 3 for controlling the current or voltage applied to the light-emitting element 2. Each pixel circuit 3 includes a transistor TX, and each transistor TX has a channel layer comprising an oxide semiconductor.

[0027] The self-emissive display device 1 includes: a first pixel circuit 31, which includes a first transistor T1 having a first channel layer comprising an oxide semiconductor; and a second pixel circuit 32 having the same circuit configuration as the first pixel circuit 31, including a second transistor T2 corresponding to the first transistor T1, having a second channel layer comprising an oxide semiconductor. More specifically, the second pixel circuit 32 is designed with the same circuit element configuration and connection relationship as the first pixel circuit 31, and the characteristics of the corresponding circuit elements are the same. These characteristics include, for example, the threshold voltage of the transistor and the capacitance value of the capacitor element. As is well known, the threshold voltage of the gate voltage of an oxide semiconductor transistor depends on the gate length of the transistor and the degree of reduction of the oxide semiconductor in the transistor. Therefore, the first transistor T1 and the second transistor T2 are designed with the same threshold voltage, gate length, and degree of reduction. The first transistor T1 and the second transistor T2 can be driving transistors. Hereinafter, attention will be focused on the first transistor T1 and the second transistor T2.

[0028] Figure 2 , Figure 3 as well as Figure 4 It is shown Figure 1 Top perspective view, cross-sectional view and cross-sectional view of the configuration example of the first transistor and the second transistor shown. Figure 3 Show Figure 2 The ABCD section, Figure 4 Show Figure 2 The EFGHIJ section. For example... Figures 2-4 As shown, the first transistor T1 has a gate electrode G1, a source electrode S1, a drain electrode D1, and a first channel layer C1 comprising oxide semiconductor. The second transistor T2 has a gate electrode G2, a source electrode S2, a drain electrode D2, and a second channel layer C2 comprising oxide semiconductor.

[0029] The actual gate length L2 of transistor T2 is larger than the actual gate length L1 of transistor T1, and the oxide semiconductor contained in the actual second channel layer C2 is more reduced than the oxide semiconductor contained in the actual first channel layer C1. These actual differences are caused by the manufacturing process. Hereafter, unless otherwise specified as "designed" or "ideal," actual values ​​and differences will be described.

[0030] According to the above configuration, the difference in gate lengths L1 and L2 results in a threshold value for the second transistor T2 that is larger than that for the first transistor T1. On the other hand, the difference in the degree of reduction of the oxide semiconductor results in a threshold value for the second transistor T2 that is smaller than that for the first transistor T1. These effects (at least partially) cancel each other out, resulting in a reduction in the threshold value difference between the first transistor T1 and the second transistor T2.

[0031] As a comparative example, consider transistors with different gate lengths but the same degree of oxide semiconductor reduction. In this case, the difference in gate length directly relates to the difference in threshold value, and a large difference in threshold value can lead to uneven brightness in the multiple pixel circuits of a self-emissive display device, degrading display quality. Commercially, adjustments are typically made before shipment to make the uneven brightness invisible (so-called "demura processing"), but sometimes a degree of uneven brightness that is difficult to adjust remains. Furthermore, differences in threshold value can lead to variations over time, resulting in uneven brightness over years and further degrading display quality.

[0032] According to the configuration of this disclosure, the difference in threshold is small, and therefore the brightness unevenness of the pixels before the unevenness removal process is small. Therefore, the display quality of the self-emissive display device 1 can be improved, especially the display quality after years of variation.

[0033] The first transistor T1 and the second transistor T2 can also be thin-film transistors. The oxide semiconductor contained in the first channel layer C1 and the oxide semiconductor contained in the second channel layer C2 can also be made of the same material. Examples of oxide semiconductors include copper oxide, silver oxide, zinc oxide, gallium oxide, tin oxide, indium oxide, indium gallium zinc oxide, indium tin oxide, indium zinc oxide, titanium oxide, indium titanium oxide, and indium titanium zinc oxide. Gate electrodes G1 and G2 are formed from the same layer, as are the first channel layer C1 and the second channel layer C2. Source electrodes S1 and S2 and drain electrodes D1 and D2 can also be formed from the same layer.

[0034] The self-emissive display device 1 includes a first insulating layer I1, which has a first portion P1 that is in contact with the upper surface of the first channel layer C1 and a second portion P2 that is in contact with the upper surface of the second channel layer C2. The hydrogen density contained in the second portion P2 is greater than that contained in the first portion P1. Furthermore, the diameter of a second hole H2 penetrating near the second portion P2 is smaller than the diameter of the first hole H1 penetrating near the first portion P1. The first hole H1 is a through-hole for dehydrogenation from the first portion P1, and the second hole H2 is a through-hole for dehydrogenation from the second portion P2. The diameter of the second hole H2 can also be 0, in other words, there may be no dehydrogenation hole near the second portion P2. The first insulating layer I1 can be an inorganic insulating layer, for example, it can contain silicon nitride (SiN), silicon oxide (SiO), or silicon oxynitride (SiNO).

[0035] (Manufacturing method)

[0036] Figure 5 This is a cross-sectional view illustrating an example of a method for manufacturing a self-emissive display device according to an embodiment of the present disclosure. Figure 5 As shown, firstly, a first channel layer CX comprising an oxide semiconductor is formed into the transistor (step S10), and then a first insulating layer I1 is formed in contact with the channel layer CX (step S20). The channel layer CX comprises a first channel layer C1 and a second channel layer C2. The first insulating layer I1 is formed on the channel layer CX. The first insulating layer I1 already contains hydrogen at the time of its formation.

[0037] Next, a photoresist layer 21 with an opening OX is formed on the first insulating layer I1 (step S22). The opening OX includes a first opening O1 overlapping a predetermined formation position of the first hole H1 and a second opening O2 overlapping a predetermined formation position of the second hole H2. Ideally, the depth and diameter of the second opening O2 are the same as the depth and diameter of the first opening O1. It is advantageous that the opening OX is not through-hole. The photoresist layer 21 with the non-through-hole opening OX can be implemented using a halftone mask or a grayscale mask.

[0038] Then, using the first plasma 41, the photoresist layer 21 and the first insulating layer I1 are etched to form a hole HX penetrating the first insulating layer I1 (step S24), and the photoresist layer 21 is removed (step S26). The opening OX overlaps with the hole HX when viewed from above. The hole HX penetrating the first insulating layer I1 includes a first hole H1 and a second hole H2. In step S24, the stronger the first plasma 41, the larger the diameter of the opening OX and the hole HX. Specifically, the diameter of the first hole H1 formed in the region of strong first plasma 41 is larger than the diameter of the second hole H2 formed in the region of weak first plasma 41.

[0039] If the opening OX is not fully penetrated in step S22, in step S24, the photoresist layer 21 is etched using the first plasma 41 to make the opening OX penetrate the photoresist layer 21. Then, the first insulating layer I1 is etched to form the hole HX. Therefore, it is easy to assign a difference in diameter between the first hole H1 and the second hole H2. In particular, the diameter of the second hole H2 can be set to 0, in other words, a dehydrogenation hole can be prevented from forming in the region where the first plasma 41 is weak.

[0040] Following the process utilizing the first plasma 41, the channel layer CX and the first insulating layer I1 are annealed (step S30). During annealing, hydrogen is ionized from the first insulating layer I1. A portion of the ionized hydrogen reduces the oxide semiconductor contained in the channel layer CX, while the remainder escapes without reduction. The larger the diameter of the aperture HX, the easier it is for hydrogen to escape through it; therefore, the oxide semiconductor near the aperture HX is less likely to be reduced. Specifically, due to the difference in diameter between the first aperture H1 and the second aperture H2, hydrogen ionized from the first portion P1 towards the first channel layer C1 escapes more easily than hydrogen ionized from the second portion P2 towards the second channel layer C2. Therefore, the oxide semiconductor contained in the second channel layer C2 is more reduced than the oxide semiconductor contained in the first channel layer C1.

[0041] Next, a conductor layer 13, which forms the material of the gate electrode GX of the transistor, is formed (step S40), and a patterned template layer 51 is formed on the conductor layer 13 (step S42). Then, according to the template layer 51, the conductor layer 13 is etched using a second plasma 42 to form the gate electrode GX of the transistor from the conductor layer 13 (step S44), and the template layer 51 is removed. The gate electrode GX includes a gate electrode G1 and a gate electrode G2. In step S44, the stronger the second plasma 42, the smaller the gate length. Specifically, the gate length L1 of the first transistor T1 formed in the region where the second plasma 42 is strong is smaller than the gate length L2 of the second transistor T2 formed in the region where the second plasma 42 is weak.

[0042] According to this manufacturing method, the effects of gate length and the degree of reduction of the oxide semiconductor on the transistor threshold (at least partially) cancel each other out. As a result, the difference between the designed threshold and the actual threshold of the transistor can be reduced. Furthermore, the difference in threshold between the first transistor T1 formed in a region of strong plasma intensity and the second transistor T2 formed in a region of weak plasma intensity can be reduced.

[0043] Figure 6 It is shown Figure 5 A top view showing an example of the intensity distribution of the plasma. (See attached image.) Figure 6As shown, the first plasma 41 and the second plasma 42 can each have spatially non-uniform intensity distributions. Typically, within the plasma-generating chamber 40, the plasma is weak in the central region F1 and the outer peripheral region F2, and strong in the intermediate region F3. The shape of the intermediate region F3 corresponds to the shape of the plasma-generating electrode, and is usually annular. It is advantageous that the intensity distributions of the first plasma 41 and the second plasma 42 are approximately the same. Specifically, it is advantageous that the first plasma 41 and the second plasma 42 are strong in the region where the first transistor T1 is formed, and weak in the region where the second transistor T2 is formed. Even if the intensity distribution is measured, it can be inferred from the configuration of the plasma generating device. When the shape and configuration of the plasma-generating electrodes are the same, it can be determined that the intensity distributions of the first plasma 41 and the second plasma 42 are the same. Furthermore, the first plasma 41 and the second plasma 42 can be generated by the same device.

[0044] [Implementation Method 2]

[0045] Other embodiments of this disclosure are described below. Furthermore, for ease of explanation, components having the same function as those described in the above embodiments are labeled with the same reference numerals, and their descriptions are not repeated.

[0046] Figure 7 This is a cross-sectional view showing an example configuration of a self-emissive display device according to one embodiment of the present disclosure. Figure 7 As shown, the self-emissive display device 1 of this disclosure includes a second insulating layer I2. The second insulating layer I2 has a third portion P3 that is in contact with the lower surface of the first channel layer C1 and a fourth portion P4 that is in contact with the lower surface of the second channel layer C2. The hydrogen density contained in the fourth portion P4 is greater than the hydrogen density contained in the third portion P3. In addition, the diameter of the fourth hole H4 penetrating near the fourth portion P4 is smaller than the diameter of the third hole H3 penetrating near the third portion P3. The third hole H3 is a through hole for dehydrogenation from the third portion P3, and the fourth hole H4 is a through hole for dehydrogenation from the fourth portion P4. The diameter of the fourth hole H4 can also be 0, in other words, there may be no dehydrogenation hole near the fourth portion P4. The second insulating layer I2 can be an inorganic insulating layer, for example, it can contain silicon nitride (SiN), silicon oxide (SiO), or silicon oxynitride (SiNO). When viewed from above, hole H3 may or may not overlap with hole H1. Similarly, when viewed from above, hole H4 may or may not overlap with hole H2.

[0047] Figure 8 This is a cross-sectional view illustrating an example of a method for manufacturing a self-emissive display device according to an embodiment of the present disclosure. Figure 8As shown, a second insulating layer I2, which is in contact with the channel layer CX, is formed on the side opposite to the first insulating layer I1 (step S50). Figure 8 In the example shown, the channel layer CX is planned to be formed on the second insulating layer, and the first insulating layer I1 is planned to be formed on the channel layer CX. The second insulating layer I2 also contains hydrogen at the time of its formation. Next, a photoresist layer 22 with an opening OY is formed on the second insulating layer I2 (step S52). The opening OY includes a third opening O3 overlapping the predetermined formation position of the third hole H3 and a fourth opening O4 overlapping the predetermined formation position of the fourth hole H4. Ideally, the depth and diameter of the fourth opening O4 are the same as the depth and diameter of the third opening O3. It is also advantageous that the opening OY is not through-hole.

[0048] Then, using the third plasma 43, the photoresist layer 22 and the second insulating layer I2 are etched to form a hole HY penetrating the second insulating layer I2 (step S54), and the photoresist layer 22 is removed (step S56). In other words, using the third plasma 43, the photoresist layer 22 is etched so that an opening OY penetrates the photoresist layer 22, and then the second insulating layer I2 is etched to form the hole HY. The opening OY overlaps with the hole HY when viewed from above. The hole HY penetrating the second insulating layer I2 includes a third hole H3 and a fourth hole H4. The diameter of the third hole H3, formed in a region with a strong intensity of the third plasma 43, is larger than the diameter of the fourth hole H4, formed in a region with a weak intensity of the third plasma 43. The diameter of the fourth hole H4 can also be 0.

[0049] The third plasma 43 can have a spatially non-uniform intensity distribution. It is advantageous that the intensity distribution of the third plasma 43 is the same as that of the first plasma 41 and the second plasma 42. Alternatively, the first plasma 41 to the third plasma 43 can be generated by the same apparatus.

[0050] After the process utilizing the third plasma 43, the channel layer CX and the second insulating layer I2 are annealed (step S60). During annealing, hydrogen is ionized from the second insulating layer I2, and a portion of the ionized hydrogen reduces the oxide semiconductor contained in the channel layer CX. Then, steps S10 and subsequent steps are performed sequentially. The annealing processes in steps S60 and S30 can also be performed in the same process. In other words, the channel layer CX, the first insulating layer I1, and the second insulating layer I2 can be annealed after the process utilizing the first plasma 41 and after the process utilizing the third plasma 43.

[0051] [Implementation Method 3]

[0052] Figure 9This is a perspective top view showing an example of the configuration of a self-emissive display device according to one embodiment of the present disclosure. Figure 9 The ABCD section is with Figure 3 Same. For example... Figure 9 As shown, the self-emissive display device 1 of this disclosure does not have dehydrogenation pores near the first channel layer C1 and the second channel layer C2, and oxygen is doped in the first insulating layer I1. Figure 3 As shown, the self-emissive display device 1 includes a first insulating layer I1, which has a first portion P1 that is in contact with the upper surface of the first channel layer C1 and a second portion P2 that is in contact with the upper surface of the second channel layer C2. The oxygen density contained in the second portion P2 is smaller than the oxygen density contained in the first portion P1.

[0053] Figure 10 This is a cross-sectional view illustrating an example of a method for manufacturing a self-emissive display device according to an embodiment of the present disclosure. Figure 10 As shown, steps S10 and S20 are performed sequentially. Then, with the entire upper surface of the first insulating layer I1 exposed, oxygen is introduced into the first insulating layer I1 using the first plasma 41 (step S28). This is a so-called "oxygen plasma treatment" that can be achieved by using oxygen in the first plasma 41. In step S28, the stronger the first plasma 41, the more oxygen is introduced. Specifically, the first portion P1, located in the region of strong intensity of the first plasma 41, is introduced with more oxygen than the second portion P2, located in the region of weak intensity of the first plasma 41.

[0054] Then, step S30 is performed. Through annealing, oxygen is released from the first insulating layer I1, oxidizing the oxide semiconductor contained in the channel layer CX. The more oxygen contained in the first insulating layer I1, the more oxygen is released, and therefore, the oxide semiconductor is more oxidized. Specifically, due to the difference in oxygen content in the first portion P1 and the second portion P2, the oxide semiconductor contained in the first channel layer C1 is more oxidized than the oxide semiconductor contained in the second channel layer C2. Furthermore / or, oxygen reacts with hydrogen; the more oxygen present, the less likely hydrogen reduction of the oxide semiconductor will occur.

[0055] Next, steps S40, S42, and S44 are performed to remove the template layer 51.

[0056] This manufacturing method at least partially cancels out the effects of gate length and the degree of oxide semiconductor reduction on the transistor threshold, thus reducing the difference between the designed threshold and the actual threshold of the transistor. Furthermore, it reduces the threshold difference between the first transistor T1 formed in a region of high plasma intensity and the second transistor T2 formed in a region of low plasma intensity.

[0057] [Implementation Method 4]

[0058] Refer again Figure 9 and Figure 3 The self-emissive display device 1 disclosed herein may also have oxygen doped in the second insulating layer I2. The self-emissive display device 1 includes a second insulating layer I2, which has a third portion P3 that is in contact with the upper surface of the first channel layer C1 and a fourth portion P4 that is in contact with the upper surface of the second channel layer C2. The oxygen density contained in the fourth portion P4 is smaller than the oxygen density contained in the third portion P3.

[0059] Figure 11 This is a cross-sectional view illustrating an example of a method for manufacturing a self-emissive display device according to an embodiment of the present disclosure. Figure 11 As shown, a second insulating layer I2, which is in contact with the channel layer CX, is formed on the side opposite to the first insulating layer I1 (step S50). Figure 11 In the example shown, the channel layer CX is planned to be formed on the second insulating layer, and the first insulating layer I1 is planned to be formed on the channel layer CX. Next, with the entire upper surface of the second insulating layer I2 exposed, oxygen is introduced into the second insulating layer I2 using the third plasma 43 (step S58). This can be achieved by using oxygen in the third plasma 43. The third portion P3, located in the region of strong intensity of the third plasma 43, receives more oxygen than the fourth portion P4, located in the region of weak intensity of the third plasma 43.

[0060] Following the process utilizing the third plasma 43, the channel layer CX and the second insulating layer I2 are annealed (step S60). During annealing, oxygen is ionized from the second insulating layer I2, oxidizing the oxide semiconductor contained in the channel layer CX. Due to the difference in oxygen content in the third portion P3 and the fourth portion P4, the oxide semiconductor contained in the first channel layer C1 is more oxidized than the oxide semiconductor contained in the second channel layer C2. Furthermore / or, oxygen reacts with hydrogen; the more oxygen present, the less likely hydrogen reduction of the oxide semiconductor will occur. Then, steps S10 and subsequent steps are performed sequentially. The annealing processes in steps S60 and S30 can also be performed in the same process.

[0061] This disclosure is not limited to the embodiments described above, and various modifications can be made within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of this disclosure. Moreover, by combining the technical means disclosed in each embodiment, new technical features can be formed.

[0062] For example, dehydrogenation pores may be formed only in the insulating layer that is in contact with the lower surface of the channel layer. For example, oxygen may be doped only in the insulating layer that is in contact with the lower surface of the channel layer. For example, dehydrogenation pores may be formed in the insulating layer that is in contact with one side of the channel layer, and oxygen may be doped in the insulating layer that is in contact with the other side of the channel layer.

[0063] Explanation of reference numerals in the attached figures

[0064] 1 Self-emissive display device

[0065] 13 Conductor Layer

[0066] 21, 22 Photoresist layers

[0067] 31 First pixel circuit

[0068] 32 Second pixel circuit

[0069] 41 First Plasma

[0070] 42 Second Plasma

[0071] 43 Third Plasma

[0072] C1 First Channel Layer

[0073] C2 Second Channel Layer

[0074] CX channel layer

[0075] G1, G2, GX gate electrodes

[0076] H1 Hole 1

[0077] H2, second hole

[0078] H3, Hole 3

[0079] H4 hole 4

[0080] HX Hole

[0081] I1 First Insulation Layer

[0082] I2 Second Insulation Layer

[0083] L1, L2 gate lengths

[0084] OX and OY openings

[0085] T1, transistor number 1

[0086] T2, second transistor

[0087] Part 1, Page 1

[0088] Part 2, Page 2

[0089] Part 3, Page 3

[0090] Page 4, Part 4.

Claims

1. A self-emissive display device, characterized in that, have: A first pixel circuit, comprising a first transistor having a first channel layer comprising an oxide semiconductor; and The second pixel circuit has the same circuit configuration as the first pixel circuit, includes a second transistor corresponding to the first transistor, and has a second channel layer comprising an oxide semiconductor. The gate length of the second transistor is greater than that of the first transistor, and the oxide semiconductor contained in the second channel layer is more reduced than that contained in the first channel layer.

2. The self-emissive display device according to claim 1, wherein, The first transistor and the second transistor are both thin-film transistors.

3. The self-emissive display device according to claim 1 or 2, wherein, The oxide semiconductor contained in the first channel layer and the oxide semiconductor contained in the second channel layer are made of the same material.

4. The self-emissive display device according to any one of claims 1 to 3, wherein, The gate electrode of the first transistor and the gate electrode of the second transistor are formed from the same layer. The first channel layer and the second channel layer are formed of the same layer.

5. The self-emissive display device according to any one of claims 1 to 4, wherein, It includes a first insulating layer, the first insulating layer having a first portion that contacts the upper surface of the first channel layer and a second portion that contacts the upper surface of the second channel layer. The hydrogen contained in the second part has a greater density than the hydrogen contained in the first part.

6. The self-emissive display device according to any one of claims 1 to 5, wherein, It includes a first insulating layer, the first insulating layer having a first portion that contacts the upper surface of the first channel layer and a second portion that contacts the upper surface of the second channel layer. The diameter of the second hole penetrating near the second part is smaller than the diameter of the first hole penetrating near the first part.

7. The self-emissive display device according to any one of claims 1 to 4, wherein, It includes a first insulating layer, the first insulating layer having a first portion that contacts the upper surface of the first channel layer and a second portion that contacts the upper surface of the second channel layer. The oxygen contained in the second part has a lower density than the oxygen contained in the first part.

8. The self-emissive display device according to any one of claims 1 to 7, wherein, It includes a second insulating layer, the second insulating layer having a third portion that contacts the lower surface of the first channel layer and a fourth portion that contacts the lower surface of the second channel layer. The hydrogen contained in the fourth part has a greater density than the hydrogen contained in the third part.

9. The self-emissive display device according to any one of claims 1 to 8, wherein, It includes a second insulating layer, the second insulating layer having a third portion that contacts the lower surface of the first channel layer and a fourth portion that contacts the lower surface of the second channel layer. The diameter of the fourth hole, which penetrates the vicinity of the fourth part, is smaller than the diameter of the third hole, which penetrates the vicinity of the third part.

10. The self-emissive display device according to any one of claims 1 to 7, wherein, It includes a second insulating layer, the second insulating layer having a third portion that contacts the lower surface of the first channel layer and a fourth portion that contacts the lower surface of the second channel layer. The oxygen contained in the third part has a lower density than the oxygen contained in the fourth part.

11. A method for manufacturing a self-emissive display device, characterized in that, Include: The process of forming a channel layer containing an oxide semiconductor in a transistor; The process of forming a first insulating layer in contact with the channel layer; The process of etching the first insulating layer using a first plasma to form a hole penetrating the first insulating layer, or introducing oxygen into the first insulating layer; The process of annealing the channel layer and the first insulating layer after the process of utilizing the first plasma; The process of forming a conductive layer of material that becomes the gate electrode of the transistor; and The process of etching the conductor layer using a second plasma to form the gate electrode of the transistor from the conductor layer.

12. The method for manufacturing a self-emissive display device according to claim 11, wherein, The first plasma and the second plasma each have spatially non-uniform intensity distributions.

13. The method for manufacturing a self-emissive display device according to claim 11 or 12, wherein, The intensity distributions of the first plasma and the second plasma are identical.

14. A method for manufacturing a self-emissive display device according to any one of claims 11 to 13, wherein, The first plasma and the second plasma are generated by the same device.

15. A method for manufacturing a self-emissive display device according to any one of claims 11 to 14, wherein, It also includes the step of forming a photoresist layer with non-through openings on the first insulating layer. The photoresist layer and the first insulating layer are etched using the first plasma.

16. The method for manufacturing a self-emissive display device according to claim 15, wherein, The photoresist layer is etched using the first plasma to make the opening penetrate the photoresist layer. The opening overlaps with the hole when viewed from above.

17. A method for manufacturing a self-emissive display device according to any one of claims 11 to 16, wherein, With the upper surface of the first insulating layer fully exposed, oxygen is introduced into the first insulating layer using the first plasma.

18. A method for manufacturing a self-emissive display device according to any one of claims 17, wherein, The first plasma uses oxygen.

19. A method for manufacturing a self-emissive display device according to any one of claims 11 to 18, wherein, The first insulating layer is formed on top of the channel layer.

20. A method for manufacturing a self-emissive display device according to any one of claims 11 to 19, wherein, Also includes: The process of forming a second insulating layer that is in contact with the channel layer on the side opposite to the first insulating layer; The process of etching the second insulating layer using a third plasma to form a hole penetrating the second insulating layer, or introducing oxygen into the second insulating layer; as well as The process of annealing the channel layer and the second insulating layer after the process of utilizing the third plasma.

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